CCVGA7C5 [UTC]
VGA PORT COMPANION CIRCUIT;
| 型号： | CCVGA7C5 |
| 厂家： | 
Unisonic Technologies |
| 描述： | VGA PORT COMPANION CIRCUIT |
| 文件： | 总6页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
CCVGA7C5
Preliminary
TVS
VGA PORT COMPANION
CIRCUIT
DESCRIPTION
The UTC CCVGA7C5 is an ESD solution for the VGA port
connector. This device integrates ESD protection for all signals,
Two non-inverting drivers provide buffering for the HSYNC
and VSYNC signals from the video controller IC. These buffers
accept TTL input levels and convert them to CMOS output levels
that swing between Ground and VCC 。 These drivers have a
nominal 60Ω output impedance to match the characteristic
impedance of the HSYNC and VSYNC lines of the video cables
typically used. The inputs of these drivers also have high
impedance pull−ups (50kΩ nom.) pulling up to the VAUX rail.
In addition, the DDC_CLOCK and DDC_DATA channels have
1.8kΩ resistors pulling these inputs up to the main 5V (VCC) rail.
The upper ESD diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate
interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5
V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to
minimize crosstalk due to common ground impedance.
ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents
associated with the IEC−1000−4−2 Level−4 ESD Protection Standard (±8kV contact discharge). When the channels
are subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the
positive supply rails or ground where they may be safely dissipated.
FEATURES
* 7 Channels of ESD Protection Designed to Meet
IEC−1000−4−2 Level−4 ESD Requirements (±8kV Contact
Discharge)
* TTL to CMOS Level−Translating Buffers for the
HSYNC and VSYNC Lines
* High impedance Pull−Ups (50kΩ Nominal to
VAUX) for HSYNC and VSYNC Inputs
* Three Independent Supply Pins (VCC, VRGB and VAUX) to
Facilitate Operation with Sub−Micron Graphics Controller ICs * Pull−Up Resistors (1.8kΩ Nominal to VCC) for
* Very Low Loading Capacitance from ESD Protection Diodes
at Less than 5pF Typical
DDC_CLK and DDC_DATA Lines
ORDERING INFORMATION
Ordering Number
Lead Free
Package
Packing
Halogen Free
CCVGA7C5L-R16-T
CCVGA7C5L-R16-R
CCVGA7C5G-R16-T
CCVGA7C5G-R16-R
SSOP-16
SSOP-16
Tube
Tape Reel
CCVGA7C5L-R16-T
(1)Packing Type
(2)Package Type
(3)Lead Free
(1) T: Tube, R: Tape Reel
(2) R16: SSOP-16
(3) L: Lead Free, G: Halogen Free
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Copyright © 2013 Unisonic Technologies Co., Ltd
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CCVGA7C5
Preliminary
TVS
PIN CONFIGURATION
PIN DESCRIPTION
PIN NO.
PIN NAME
DESCRIPTION
Horizontal sync signal buffer output. Connects to the video connector side of the
horizontal sync line.
1
HSYNC_OUT
Horizontal sync signal buffer input. Connects to the VGA Controller side of the
horizontal sync line.
2
3, 11
4
HSYNC
GNDD
VRGB
Digital ground reference supply pin.
VRGB supply pin. This is an isolated supply pin for the R, G and B ESD protection
circuits.
Blue signal video protection channel. This pin is typically tied to the B video line
between the VGA controller device and the video connector.
5
6
B
Green signal video protection channel. This pin is typically tied to the G video line
between the VGA controller device and the video connector.
Red signal video protection channel. This pin is typically tied to the R video line
between the VGA controller device and the video connector.
Analog ground reference supply pin.
G
7
8
R
GNDA
VCC supply pin. This is the main supply input for the DDC_CLK and DDC_DATA pullup
resistors and ESD protection circuits. It is also connected to the sync buffers and to the
ESD protection diodes present on the HSYNC_OUT and VSYNC_OUT lines.
DDC data pin.
9, 16
VCC
10
12
DDC_DATA
DDC_CLK
DDC clock pin.
V
AUX supply pin. This is the supply input for the 50kΩ pullups connected to the HSYNC
13
14
15
VAUX
and VSYNC buffer inputs.
Vertical sync signal buffer input. Connects to the VGA Controller side of the vertical
sync line.
VSYNC
Vertical sync signal buffer output. Connects to the video connector side of the vertical
sync line.
VSYNC_OUT
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CCVGA7C5
Preliminary
TVS
BLOCK DIAGRAM
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CCVGA7C5
Preliminary
TVS
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage Inputs
Diode Forward Current
(One Diode Conducting at a Time)
R, G, B
VCC, VRGB, VAUX
GND-0.5 ~ +6.0
V
20
mA
GND-0.5 ~ VRGB +0.5
GND-0.5 ~ VAUX +0.5
GND-0.5 ~ VCC +0.5
750
V
V
DC Voltage at Inputs
HSYNC, VSYNC
DDC_CLK, DDC_DATA
V
Package Power Rating
mW
°C
°C
Operating Temperature Range
Storage Temperature Range
TOPR
TSTG
0 ~ +70
−40 ~ +150
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
STANDARD OPERATING CONDITIONS
PARAMETER
SYMBOL
VCC
TEST CONDITIONS
MIN
4.5
1.7
2.9
2.0
TYP
MAX UNIT
Main Supply Voltage
RGB Supply Voltage
Auxiliary Supply Voltage
Logic High Input Voltage (Note)
Logic Low Input Voltage (Note)
RGB
5.5
3.7
3.7
V
V
VRGB
VAUX
VIH
V
V
VIL
0.8
VRGB
VAUX
VCC
-8
V
0
0
0
V
Input Voltage
HSYNC, VSYNC
DDC_CLK, DDC_DATA
VI
V
V
High Level Output Current (Note 1)
Low Level Output Current (Note 1)
Free−Air Operating Temperature
IOH
IOL
TA
mA
mA
°C
8
0
+70
Note: These parameters apply only to the HSYNC and VSYNC signals.
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CCVGA7C5
Preliminary
TVS
ELECTRICAL CHARACTERISTICS (Note 1)
PARAMETER
SYMBOL
VF
TEST CONDITIONS
MIN
4.0
TYP
MAX UNIT
Diode Forward Voltage
Logic High Output Voltage
Logic Low Output Voltage
R, G and B Pins
IF=10mA
1.0
V
V
VOH
IOH=-4mA, VCC=4.5V
IOL=4mA, VCC=4.5V
VOL
0.4
±1
V
V
RGB=3.63V, VIN=VRGB or GND
μA
HSYNC, VSYNC
Pins
Input
Current
V
AUX=3.63V, VIN=VAUX
±1
μA
μA
μA
IIN
HSYNC, VSYNC
Pins
VAUX=3.63V, VIN=GND
-30.0 -72.5 -95.0
VCC=5.5V, VAUX=VRGB=2.97V, All Inputs
VCC upply Current
ICC
35
100
10
and Outputs Floating
R, G and B Pins at VCC r GND, All
Inputs and Outputs Floating
VRGB supply Current
R, G and B pins
IRGB
μA
pF
pF
5
HSYNC,
Input
10
VSYNC pins
Capacitance
DDC_DATA,
CIN
Note 2 Applies for All Cases
5
pF
DDC_CLK pins
Pull−up Resistance
DDC_DATA, DDC_CLK pins
ESD Withstand Voltage
SYNC Buffer L≥H Propagation
Delay
RPU
VESD
tPLH
1.52
±8
1.80
1.98
kΩ
kV
ns
VCC=5 V, VRGB=3.3V, VAUX=3.3 V
CL=50pF, VCC=5.0V, RL=500Ω (Note 3)
7.0
7.0
7.0
15.0
15.0
SYNC Buffer H≥L Propagation
Delay
tPHL
CL=50pF, VCC=5.0V, RL=500Ω (Note 3)
CL=50pF, VCC=5.0V, RL=500Ω (Note 3)
ns
ns
SYNC Buffer Output Rise &
Fall Times
tR, tF
Notes: 1. All parameters specified over standard operating conditions unless otherwise noted.
2. Measured at 1MHz. R/G/B inputs biased at 1.65V with VRGB=3.3V. DDC_CLK and DDC_DATA biased at
2.5V with VCC=5V. HSYNC and VSYNC inputs biased at VAUX or GND with VAUX=3.3V and VCC=5V.
3. Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times ≤5
ns. Guaranteed by correlation to buffer output drive currents.
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CCVGA7C5
Preliminary
TVS
TYPICAL APPLICATION CIRCUIT
To Video
DAC VDD
5V 3.3V
0.2µF 0.2µF
4
VRGB
9, 16
13
VCC VAUX
2
14
8
HSYNC
VSYNC
H-Sync
V-Sync
GNDA
GNDD
3, 11
10
12
DDC_DATA
DDC_CLK
DDC_Data
DDC_Clk
Digital Analog
GND GND
UTC
CCVGA7C5
Red
Green
Blue
1
15
HSYNC_OUT
VSYNC_OUT
VF**
VF**
VF**
SF**
SF**
7
6
5
R
G
B
H-Sync
V-Sync
DDC_Data
DDC_Clk
Red
Green
Blue
VF** − VIDEO EMI Filter
SF** − SYNC EMI Filter
GNDA, the negative voltage rail for the R, G and B diodes is not connected internally to GNDD. GNDA should
ideally be connected to the ground of the video DAC IC. This will prevent any ground bounce caused by digital
signals from injecting noise onto the R, G and B signals. Analog GND and digital GND are typically connected on the
printed circuit board.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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