4051L-P16-T [UTC]
8-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS; 8通道模拟多路复用器/多路解复用器型号: | 4051L-P16-T |
厂家: | Unisonic Technologies |
描述: | 8-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS |
文件: | 总6页 (文件大小:125K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
4051
CMOS IC
8-CHANNEL ANALOG
MULTIPLEXERS/DEMULTIPLEXERS
SOP-16
DIP-16
ꢀ
DESCRIPTION
UTC 4051 is single 8-channel analog multiplexers/demultiplexers
for application as digitally–controlled analog switches.
The device has three binary control inputs and an inhibit input. It
feature low ON impedance and very low OFF leakage current.
Control of analog signals up to the complete supply voltage range
can be achieved.
ꢀ
FEATURES
TSSOP-16
* Wide Analog Voltage Range: VDD–VEE = 3V~18V.
(Note: VEE must be≦VSS
)
*Pb-free plating product number: 4051L
* Break-Before-Make Switching Eliminates Channel Overlap.
* Linearized Transfer Characteristics
* Implement an SP8T solid state switch effectively.
* Pin–to–Pin Replacement for CD4051
ꢀ
ORDERING INFORMATION
Order Number
Package
Packing
Normal
Lead Free Plating
4051L-S16-R
4051L-S16-T
4051L-P16-R
4051L-P16-T
4051L-D16-T
4051-S16-R
4051-S16-T
4051-P16-R
4051-P16-T
4051-D16-T
SOP-16
SOP-16
Tape Reel
Tube
TSSOP-16
TSSOP-16
DIP-16
Tape Reel
Tube
Tube
www.unisonic.com.tw
Copyright © 2005 Unisonic Technologies Co., LTD
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CMOS IC
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PIN CONFIGURATION
X4
X6
X
16 VDD
1
2
3
4
5
6
7
8
15
X2
X1
14
13
X0
X3
X7
X5
UTC 4051
12
11
INH
VEE
VSS
A
10 B
9 C
ꢀ PIN DESCRIPTION
PIN No.
SYMBAL
NAME AND FUNCTION
3
X
INH
Common Input/Output
Inhibit Inputs
6
7
VEE
Supply Voltage
8
11,10,9
VSS
Ground
A,B,C
X0~X7
VDD
Binary Control Inputs
Independent Inputs/Outputs
Positive Supply Voltage
13,14,15,12,1,5,2,4
16
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ABSOLUTE MAXIMUM RATING
PARAMETER
DC Supply Voltage (Referenced to VEE, VSS≧VEE
SYMBOL
VDD
RATINGS
-0.5 ~ +18
UNIT
V
)
Input or Output Voltage (DC or Transient)
VIN, VOUT
-0.5 ~ VDD +0.5
V
(Referenced to VSS for Control Inputs and VEE for Switch I/O)
Input Current (DC or Transient), per Control Pin
Switch Through Current
IIN
±10
±25
mA
mA
ISW
Power Dissipation
Derating above 65℃
500
7
mW
mW/℃
PD
℃
℃
℃
Junction Temperature
TJ
125
Operating Temperature Range
Storage Temperature Range
TOPR
TSTG
-40 ~ +125
-40 ~ +150
Note: 1.Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2.The device is guaranteed to meet performance specification within 0℃~70℃ operating temperature range
and assured by design from –40℃~125℃.
ꢀ
ELECTRICAL CHARACTERISTICS (Ta=25℃, unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY REQUIREMENTS (Voltages Referenced to VEE
)
VDD – 3.0≧VSS≧VEE
Power Supply Voltage Range
VDD
IQ
3
18
5
V
VDD=5V
VDD=10V
DD=15V
0.005
0.010
0.015
Control Inputs: VIN = VSS or VDD
Quiescent Current per
Package
Switch I/O: VEE ≦VI/O ≦VDD
and ∆Vsw≦500mV(Note 2)
Ta=25℃ only (The channel
,
µA
10
20
V
VDD=5V
(0.07 µA/kHz) f + IQ
(0.20 µA/kHz) f + IQ
(0.36 µA/kHz) f + IQ
Total Supply Current
(Dynamic Plus Quiescent,
Per Package)
component, (VIN-Vout)/Ron, is
not included.)
ID(AV)
µA
VDD=10V
V
DD=15V
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to VEE
)
Recommended Peak–to–Peak
VI/O
Channel On or Off
0
0
VDD
600
VPP
Voltage Into or Out of the Switch
Recommended Static or Dynamic
Voltage Across the Switch
Output Offset Voltage
∆Vsw Channel On
mV
µV
VO(OFF) VIN = 0V, No Load
10
250
120
80
∆Vsw≦500mV
VDD=5V
VDD=10V
DD=15V
1050
500
280
70
ON Resistance
RON
∆RON
IOFF
VIN = VIL or VIH (Control), and
IN = 0 to VDD (Switch)
Ω
Ω
V
V
ΔON Resistance Between
Any Two Channels in the
Same Package
VDD=5V
25
VDD=10V
10
50
VDD=15V
10
45
VIN = VIL or VIH (Control)
Channel to Channel or Any
One Channel, VDD=15V
Inhibit = VDD
Off–Channel Leakage Current
±0.05
±100
nA
Capacitance, Switch I/O
Capacitance, Common O/I
Capacitance, Feedthrough
(Channel Off)
CI/O
CO/I
10
17
pF
pF
Inhibit = VDD
Pins Not Adjacent
Pins Adjacent
0.15
0.47
CI/O
pF
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ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.5
CONTROL INPUTS – INHIBIT A, B, C (Voltages Referenced to VSS
)
VDD=5V
2.25
4.50
4.0
Low Level Input Voltage
High Level Input Voltage
VIL
VIH
RON= per spec, IOFF = per spec
RON= per spec, IOFF = per spec
V
VDD=10V
VDD=15V
VDD=5V
3.0
6.75
3.5
7
2.75
5.5
V
VDD=10V
VDD=15V
11
8.25
Input Leakage Current
Input Capacitance
ILEAK VIN= 0 or VDD, VDD=15V
CIN
±0.00001 ±0.1
5.0 7.5
µA
pF
ꢀ
DYNAMIC ELECTRICAL CHARACTERISTICS
(CL = 50pF, Ta=25℃, VEE≦VSS, unless otherwise specified)
V
DD–VEE
Vdc
5
10
15
5
10
15
5
10
15
10
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
Propagation Delay Times
Switch Input to Switch
Output (RL = 10 kΩ)
t
t
t
PLH, tPHL =(0.17 ns/pF)CL + 26.5ns
PLH, tPHL =(0.08 ns/pF)CL + 11ns
PLH, tPHL =(0.06 ns/pF)CL + 9ns
35
15
12
90
40
30
tPLH, tPHL
ns
ns
ns
(RL=10kΩ, VEE=VSS
)
350
170
140
360
160
120
0.07
700
340
280
720
320
240
t
t
PHZ, tPLZ
PZH, tPZL
Inhibit to Output
Output “1” or “0” to High Impedance,
or High Impedance to “1” or “0” Level
Control Input to Output
tPLH, tPHL
RL = 10 kΩ, VEE = VSS
Total Harmonic Distortion
Bandwidth
THD
BW
RL = 10KΩ, f = 1 kHz, Vin = 5 VPP
RL = 1kΩ, VIN = 1/2 (VDD–VEE) p–p,
CL = 50pF, 20 Log (Vout/Vin) = -3dB)
RL=1KΩ, VIN = 1/2 (VDD–VEE) p–p
IN = 4.5 MHz
RL = 1kΩ, VIN = 1/2 (VDD–VEE) p–p
IN = 3MHz
R1 = 1kΩ, RL = 10kΩ Control
TLH = tTHL = 20ns, Inhibit = VSS
%
10
10
10
10
17
-50
-50
75
MHz
Off Channel Feedthrough
Attenuation
dB
dB
f
Channel Separation
f
Crosstalk, Control Input to
Common O/I
mV
t
Note 1. Data of “TYP” is intended as an indication of the IC’s potential performance.
2. For voltage drops across the switch(∆Vsw)>600mV (>300mV at high temperature), excessive VDD current
may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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CMOS IC
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TEST CIRCUIT
VDD
VDD
VDD
IN/OUT
OUT/IN
VEE
VDD
LEVEL
CONVERTED
OUT/IN
IN/OUT
CONTROL
CONTROL
VEE
Switch Circuit Schematic
ꢀ
TRUTH TABLE
16
VDD
Control Inputs
INH 6
A11
B 10
C 9
ON Switches
BINARY TO 1-
- 8
OF
LEVEL
INHIBIT
C
B
A
DECODER WITH
INHIBIT
CONVERTER
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
7
8
VEE
VSS
X0 13
X1 14
X2 15
X3 12
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
X4
X5
X6
X7
3X
X4
X5
X6
X7
1
5
2
4
1
x
x
x
None
x = Don’t Care
UTC 4051 Functional Diagram
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CMOS IC
ꢀ
TYPICAL CHARACTERISTICS
350
300
250
200
150
100
50
350
300
250
200
150
100
50
VDD = 7.5 V
VEE = - 7.5 V
Ta =25℃
VDD = 5.0 V
VEE = -5.0 V
Ta =25℃
0
0
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0 8.0 10
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0 8.0 10
Input Voltage, VIN (V)
Input Voltage , VIN (V )
350
300
250
200
150
100
50
VDD = 2.5 V
VEE = - 2.5 V
Ta =25℃
0
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0 8.0 10
Input Voltage, VIN (V)
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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