3510_15 [UTC]
PC POWER SUPPLY SUPERVISORS;
| 型号： | 3510_15 |
| 厂家： | 
Unisonic Technologies |
| 描述： | PC POWER SUPPLY SUPERVISORS PC |
| 文件： | 总8页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
3510
CMOS IC
PC POWER SUPPLY
SUPERVISORS
DESCRIPTION
The UTC 3510 is designed to provide protection circuits, power
good output (PGO) indicator, fault protection output (FPO) and a
PSON control for PC switching power supply systems.
DIP-8
The protection circuits include over voltage protection (OVP)
monitoring for 3.3V, 5V and 12V (12V via VDD pin) and under voltage
protection(UVP) monitoring for 3.3V and 5V. When an OV or UV event
arose and is detected, the power good output (PGO) goes low and the
FPO will be set to high. The protection latch can be reset by setting
PSON to high. UVP function is enabled 75ms after PSON is set low
and de-bounced. Besides, there is a 2.3ms delay with 38ms
de-bounce at turn off but no delay during turn on.
SOP-8
When OVP and UVP detected the right voltage level, a PGO signal
will be issued.
FEATURES
* Over Voltage Protection and Lock Out for 3V, 5V and 12V.
* Under Voltage Protection and Lock Out for 3.3V and 5V.
* Open Drain Output for PGO and FPO pin.
* 300ms delay for PGO.
* 75ms delay for 3.3V and 5V short-circuit turn-on protection.
* 2.3ms PSON control to FPO turn-off delay.
* 38ms PSON control de-bounce.
* 73us width noise deglitches.
* Wide supply voltage range from 4V ~15V.
■
ORDERING INFORMATION
Ordering Number
Package
Packing
Lead Free
3510L-D08-T
-
Halogen Free
3510G-D08-T
3510G-S08-R
DIP-8
Tube
SOP-8
Tape Reel
MARKING
DIP-8
SOP-8
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Copyright © 2015 Unisonic Technologies Co., Ltd
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3510
CMOS IC
PIN CONFIGURATION
PIN DESCRIPTION
PIN No.
PIN NAME
PGI
TYPE
I
DESCRIPTION
1
2
3
4
5
6
7
8
Power good input
Ground
GND
FPO
O
I
Fault protection output(invert), open drain output stage
ON/OFF control
PSON
VS33
I
3.3V over/under-voltage protection
VS5
I
5V over/under-voltage protection
VDD
I
Supply voltage/12V over-voltage protection input pin
Power good output, open drain output stage
PGO
O
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CMOS IC
BLOCK DIAGRAM
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CMOS IC
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VDD
RATINGS
16
UNIT
V
Supply Voltage
Output Voltage
All Other Pins
FPO
PGO
16
VOUT
V
V
8
-0.3 ~ 16
1092
DIP-8
Power Dissipation (TA≤25°C)
PD
mW
SOP-8
730
℃
℃
Operating Temperature
Storage Temperature
TOPR
TSTG
-20 ~ +85
-40 ~ +150
Note: 1. Absolute maximum ratings are stress ratings only and functional device operation is not implied. The device
could be damaged beyond Absolute maximum ratings.
2. The device is guaranteed to meet performance specifications within 0℃~+70℃ operating temperature range
and assured by design from -20℃~+85℃.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VDD
MIN
4
TYP
MAX
15
7
UNIT
V
Supply Voltage
Input Voltage
PSON, VS5, VS33
VIN
V
V
PGI
VDD+0.3V
7
FPO
PGO
FPO
PGO
15
7
Output Voltage
VOUT
20
10
Output Sink Current
IO(SINK)
mA
ms
Supply Voltage Rising Time (See Note)
Note: VDD rising and falling slew rate must be less than 14V/ms.
1
ELECTRICAL CHARACTERISTICS (TA=25°C, unless otherwise specified.)
PARAMETER
SYMBOL TEST CONDITIONS
MIN TYP MAX UNIT
OVER-VOLTAGE PROTECTION
VS33
VS5
3.7
5.7
3.9
6.1
4.1
6.5
Over Voltage Threshold
V
VDD
13.0 13.8 14.4
Low-level Output Voltage (FPO)
Leakage Current (FPO)
Noise Deglitch Time OVP
PGI AND PGO
VOL
VDD =5V, IO(SINK) =20mA
0.7
5
V
ILEAK V(FPO) =5V
VDD =5V
μA
μS
35
73
110
VPGI
1.1
0.9
2
1.15
0.95
2.2
1.2
1
Input threshold Voltage
Under Voltage Threshold
PGI
V
V
VPG2
VS33
VS5
2.4
3.7
0.4
5
VIT
3.3
3.5
Low-level Output Voltage (PGO)
Leakage Current (PGO)
VOL
VDD =4V, IO(SINK) =10mA
V
ILEAK PGO = 5 V
μA
ms
Short-Circuit Protection Delay
3.3V, 5V
49
200
3.2
88
75
114
450
7.2
225
445
220
PGI to PGO
PGI to FPO
PGI to PGO
PGI to FPO
UVP to FPO
300
4.8
Transient Delay time
Noise Deglitch Time
tDLY1
VDD = 5 V
VDD = 5 V
ms
150
296
146
μs
180
82
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3510
CMOS IC
ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
SYMBOL TEST CONDITIONS
MIN TYP MAX UNIT
PSON CONTROL
High-level
Low-level
VIH
VIL
2.4
V
Input Voltage
1.2
57
V
Input Pullup Current
IIN
tB
PSON = 0 V
VDD = 5 V
VDD = 5 V
120
38
μA
ms
ms
Debounce Time (PSON)
24
Transient Delay Time (PSON to FPO)
TOTAL DEVICE
tDLY2
tB+1.1 tB+2.3 tB+4
Supply Current
IDD
PSON =5V
1
mA
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CMOS IC
TIMING DIAGRAM
TYPICAL APPLICATION
5 VSB
PGI
PGO
12V
0.5 V
Drop
1
2
3
8
PGI
PGO
7
6
VSB
GND
VDD
VS5
5V
FPO
4
5
VS33
3.3V
PSON
PSON
(From Motherboard)
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CMOS IC
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE (FPO)
LOW-LEVEL OUTPUT VOLTAGE (FPO)
vs
vs
LOW-LEVEL OUTPUT CURRENT (FPO)
LOW-LEVEL OUTPUT CURRENT (FPO)
4
3
2
800
700
600
VDD=4V
PSON=GND
Exploded View
VDD=4V
PSON=GND
500
400
300
200
Ta = 85°C
Ta = 25°C
Ta = -20°C
Ta = 85°C
Ta = 25°C
Ta = -20°C
1
0
100
0
0
0
20
40
60
80
5
10
15
20
25
100
Low-Level Output Current, IOL (mA)
Low-Level Output Current, IOL (mA)
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3510
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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