CHK080A-SRA26 [UMS]
80W Power Packaged Transistor; 80W功率封装晶体管
| 型号： | CHK080A-SRA26 |
| 厂家： | 
UNITED MONOLITHIC SEMICONDUCTORS |
| 描述： | 80W Power Packaged Transistor |
| 文件： | 总14页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CHK080A-SRA
80W Power Packaged Transistor
GaN HEMT on SiC
Description
The CHK080A-SRA is an unmatched
Packaged Gallium Nitride High Electron
Mobility Transistor. It offers general purpose
and broadband solutions for a variety of RF
power applications. It is well suited for multi-
purpose applications such as radar and
telecommunication.
The CHK080A-SRA is developed on a 0.5µm
gate length GaN HEMT process. It requires
an external matching circuitry.
The CHK080A-SRA is available in
a
ceramic-metal flange power package
providing low parasitic and low thermal
resistance.
VDS = 50V, ID_Q = 600mA, Freq=3GHz
Pulsed mode
Main Features
■ Wide band capability: up to 3.5GHz
■ Pulsed and CW operating modes
■ High power : > 80W
65
60
55
50
45
40
35
30
25
20
15
10
5
6.5
6
Pulsed mode at 3GHz
PAE
5.5
5
Pout
Id
4.5
4
■ High Efficiency : up to 70%
■ DC bias: VDS =50V @ ID_Q =600mA
■ MTTF > 106 hours @ Tj=200°C
■ RoHS Flange Ceramic package
3.5
3
2.5
2
1.5
1
Gain
0.5
0
0
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
InputPower (dBm)
Intrinsic performances of the package device
Main Electrical Characteristics
Tcase= +25°C, Pulsed mode, F=3GHz, VDS=50V, ID_Q=600mA (ID_Q =300mA on each transistor)
Symbol
GSS
Parameter
Small Signal Gain
Min
Typ
17
Max
Unit
dB
W
-
-
-
-
PSAT
Saturated Output Power
80
50
100
65
PAE
Max Power Added Efficiency
%
GPAE_MAX Associated Gain at Max PAE
13
dB
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
1/14
Specifications subject to change without notice
United Monolithic Semiconductors S.A.S.
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK080A-SRA
80W Power Packaged Transistor
Recommended DC Operating Ratings
Tcase= +25°C
Symbol
VDS
Parameter
Min Typ Max Unit
Conditions
Drain to Source Voltage
Gate to Source Voltage
20
50
V
V
VGS_Q
-1.8
VD=50V, ID_Q=600mA
(ID_Q =300mA on each
transistor)
ID_Q
Quiescent Drain
Current
0.6
4
2
A
A
VD=50V
(1)
ID_MAX
IG_MAX
Tj_max
Drain Current
VD=50V,
Compressed mode
Gate Current
(forward mode)
0
48
mA Compressed mode
°C
Junction Temperature
200
(1) Limited by dissipated power
DC Characteristics
Tcase= +25°C
Symbol
VP
Parameter
Min
Typ
-2
16 (1)
Max Unit
Conditions
VD=50V, ID=IDSS/100
VD=7V, VG=2V
Pinch-Off Voltage
-3
-1
V
A
ID_SAT
IG_leak
Saturated Drain Current
Gate Leakage Current
(reverse mode)
-6
mA VD=50V, VG=-7V
VBDS
Drain-Source
Break-down Voltage
200
1.8
V
VG=-7V, ID=20mA
°C/W
RTH
Thermal Resistance
(1) For information, limited by ID_MAX , see on Absolute Maximum Ratings
CW Mode
RF Characteristics (CW)
Tcase= +25°C, CW mode, F=3GHz, VDS=50V, ID_Q=600mA (ID_Q =300mA on each transistor)
Symbol
GSS
Parameter
Small Signal Gain
Min
14
Typ
16
Max
Unit
dB
W
PSAT
Saturated Output Power
70
80
PAE
Max Power Added Efficiency
Associated Gain at Max PAE
45
50
%
GPAE_MAX
12
dB
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
2/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
80W Power Packaged Transistor
CHK080A-SRA
RF Characteristics (Pulsed)
Tcase= +25°C, Pulsed mode (1), F=3GHz, VD=50V, ID_Q=600mA (ID_Q =300mA on each transistor)
Symbol
GSS
Parameter
Small Signal Gain
Min
15
Typ
17
Max
Unit
dB
W
PSAT
Saturated Output Power
80
100
65
PAE
Max Power Added Efficiency
55
%
GPAE_MAX Associated Gain at Max PAE
13
dB
(1) Input RF and gate voltage are pulsed. Conditions are 25µs width, 10% duty cycle and 1µs
offset between DC and RF pulse.
These values are the intrinsic performance of the packaged device. They are deduced from
measurements and simulations. They are considered in the reference plane defined by the
leads of the package, at the connection interface with the PCB. The typical performance
achievable in more than 20% frequency band around 3GHz was demonstrated using the
reference board 61500192 presented hereafter.
Absolute Maximum Ratings
Tcase= +25°C(1), (2), (3)
Symbol
VDS
Parameter
Drain-Source Voltage
Rating
60
Unit
V
Note
(6)
VGS_Q
IG_MAX
IG_MIN
ID_MAX
PIN
Gate-Source Voltage
-10, +2
150
V
Maximum Gate Current in forward mode
Maximum Gate Current in reverse mode
Maximum Drain Current
mA
mA
A
-12
(4)
(5)
12
Maximum Input Power (typical)
Junction Temperature
41
dBm
°C
Tj
220
TSTG
TCase
Storage Temperature
-55 to +150
See note
°C
(4)
Case Operating Temperature
°C
(1) Operation of this device above anyone of these parameters may cause permanent
damage.
(2) Duration < 1s.
(3) The given values must not be exceeded at the same time even momentarily for any
parameter, since each parameter is independent from each other, otherwise deterioration or
destruction of the device may take place.
(4) Max junction temperature must be considered
(5) @3GHz - Linked to and limited by IG_MAX & IG_MIN values
(6)
V
GS_Q
max limited by ID_MAX and IG_MAX values
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
3/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK080A-SRA
80W Power Packaged Transistor
Simulated Source and Load Impedance
The device is composed of 2 independent transistors.
VDS=50V, ID_Q=600mA (300mA on each transistor)
Zload
Zload
Zsource
Zsource
Frequency (MHz)
Source
1 + j4.5
Load
21.6 + j7
15.3 + j14.3
5 + j7.9
500
1000
2000
3000
3500
1 + j1.9
1.3 - j1.9
1.4 - j4.8
0.8 - j6.7
2.8 + j2.3
2.3 + j0.2
These values are relative to each transistor and are given in the reference plane defined by
the connection between the package leads and the PCB. A gap of 200µm is considered
between the edge of the package and the PCB.
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
4/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
80W Power Packaged Transistor
CHK080A-SRA
Typical S-parameters
The device is composed of 2 independent transistors.
Each transistor has the following S-parameters.
Tcase=+25°C, CW mode, VDS=50V, ID_Q=600mA (300mA on each transistor), phase S(i,j) in °.
Freq
(GHz)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
6.75
7
Mag
S(1,1)
0.99
0.89
0.90
0.90
0.91
0.92
0.93
0.93
0.94
0.94
0.95
0.95
0.95
0.95
0.95
0.95
0.96
0.95
0.95
0.95
0.95
0.95
0.95
0.95
0.94
0.94
0.93
0.93
0.92
0.92
0.91
0.90
0.89
0.88
0.87
0.85
0.83
0.82
0.80
0.79
0.78
Phase
S(1,1)
0.00
Mag
S(2,1)
102.98
26.70
13.34
8.59
6.13
4.64
3.65
2.95
2.45
2.06
1.77
1.54
1.36
1.22
1.10
1.00
0.93
0.86
0.81
0.76
0.73
0.70
0.68
0.66
0.65
0.64
0.64
0.64
0.65
0.66
0.68
0.70
0.73
0.76
0.80
0.84
0.89
0.95
1.00
1.05
1.10
Phase
S(2,1)
-180.00
94.89
77.63
65.80
55.96
47.41
39.85
33.12
27.06
21.58
16.56
11.94
7.63
Mag
S(1,2)
Phase
S(1,2)
180.00
8.67
Mag
S(2,2)
0.53
0.37
0.42
0.50
0.57
0.63
0.69
0.73
0.77
0.80
0.82
0.84
0.86
0.87
0.88
0.89
0.90
0.90
0.91
0.91
0.92
0.92
0.92
0.92
0.92
0.92
0.92
0.92
0.92
0.91
0.91
0.91
0.90
0.90
0.89
0.89
0.88
0.87
0.87
0.86
0.85
Phase
S(2,2)
0.00
0.0000
0.0120
0.0120
0.0110
0.0090
0.0080
0.0060
0.0050
0.0050
0.0050
0.0060
0.0070
0.0080
0.0100
0.0120
0.0130
0.0150
0.0170
0.0190
0.0200
0.0220
0.0240
0.0270
0.0290
0.0310
0.0340
0.0370
0.0400
0.0430
0.0470
0.0510
0.0550
0.0610
0.0660
0.0730
0.0800
0.0880
0.0970
0.1060
0.1150
0.1230
-148.78
-165.08
-171.34
-175.14
-178.05
179.44
177.13
174.95
172.84
170.78
168.74
166.71
164.67
162.61
160.53
158.40
156.21
153.96
151.63
149.21
146.67
144.01
141.19
138.20
134.99
131.54
127.81
123.74
119.28
114.35
108.86
102.71
95.78
-127.84
-137.95
-141.46
-144.97
-148.80
-152.71
-156.53
-160.17
-163.60
-166.83
-169.87
-172.76
-175.50
-178.13
179.33
176.87
174.46
172.08
169.73
167.39
165.04
162.66
160.25
157.78
155.24
152.61
149.87
146.99
143.95
140.70
137.23
133.46
129.35
124.82
119.78
114.10
107.63
100.14
91.38
-4.55
-11.66
-15.55
-16.10
-12.17
-2.19
13.92
31.44
44.67
52.66
56.95
58.94
59.51
59.18
58.27
56.96
55.36
53.56
51.60
49.50
47.28
44.94
42.48
39.89
37.14
34.22
31.10
27.73
24.07
20.05
15.61
10.66
5.10
3.58
-0.26
-3.92
-7.46
-10.90
-14.26
-17.59
-20.90
-24.22
-27.57
-30.99
-34.51
-38.14
-41.93
-45.92
-50.14
-54.64
-59.48
-64.72
-70.44
-76.71
-83.64
-91.33
-99.89
-109.45
-120.09
-131.91
-144.94
7.25
7.5
7.75
8
8.25
8.5
8.75
9
9.25
9.5
9.75
10
87.92
78.95
68.71
57.03
43.79
28.98
12.80
-1.18
-8.30
-16.37
-25.51
-35.83
-47.36
81.00
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
5/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK080A-SRA
80W Power Packaged Transistor
Maximum Gain & Stability Characteristics
The device is composing by 2 independent transistors.
Each transistor has the following parameters.
Tcase= +25°C, CW mode, VDS=50V, ID_Q=600mA (300mA on each transistor)
40
35
4.0
3.0
2.0
1.0
0.0
Maximum Gain
30
25
20
15
10
K Factor
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
Frequency(GHz)
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
6/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
80W Power Packaged Transistor
CHK080A-SRA
Typical Performance on Demonstration Board (Ref. 61500192)
Calibration and measurements are done on the connector reference accesses of the
demonstration boards.
Tcase = +25°C, CW mode
Measured Id, Gain, Pout & PAE
F = 3GHz, VDS = 50V, ID_Q = 600mA
55
50
45
40
35
30
25
20
15
10
5
10
9
8
7
6
5
4
3
2
1
0
CW mode at 3GHz
Pout
PAE
Id
Gain
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
Input Power (dBm)
Measured Gain, Pout & PAE
Pin = 39dBm, VDS = 50V, ID_Q = 600mA
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
21
20
CW mode
19
18
17
16
15
14
13
12
11
10
9
Pout
PAE
Gain
2.8
8
7
2.7
2.9
3
3.1
3.2
3.3
3.4
Frequency(GHz)
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
7/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK080A-SRA
80W Power Packaged Transistor
Typical Performance on Demonstration Board (Ref. 61500192)
Calibration and measurements are done on the connector reference accesses of the
demonstration boards
Tcase = +25°C, Pulsed mode (1)
Measured Id, Gain, Pout & PAE
F = 3GHz, VDS = 50V, ID_Q = 600mA
55
50
45
40
35
30
25
20
15
10
5
10
9
8
7
6
5
4
3
2
1
0
Pulsed mode at 3GHz
Pout
PAE
Id
Gain
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
Input Power (dBm)
Measured Gain, Pout & PAE
Pin = 39dBm, VDS = 50V, ID_Q = 600mA
60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
20
19
18
17
16
15
14
13
12
11
10
9
Pulsed mode
PAE
Pout
Gain
8
7
6
5
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
Frequency(GHz)
(1) Input RF and gate voltage are pulsed. Conditions are 25µs width, 10% duty cycle and 1µs
offset between DC and RF pulse.
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
8/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
80W Power Packaged Transistor
CHK080A-SRA
Demonstration Amplifier Low Frequency Equivalent Schematic
+
Vd
+
Vg
J2
J1
C9
C8
R1
R1
C8
C7
C3
C4
C6
C5
C3
C7
C6
C4
C5
Q1
C1
C1
J3
C1
C1
J3
OUT
C2
R3
IN
R3
R2
C6
C7
C3
C4
C6
C5
R1
R1
C3
C7
C4
C5
C8
C8
C9
J2
J1
Vd
Vg
+
+
Demonstration Amplifier / Bill of Materials (Ref. 61500192)
Designator
Type
Value - Description
1pF, +/- 0.1pF, 0603
Qty
C1
C2
C3
C4
C5
C6
C7
C8
C9
R1
R2
R3
J1
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
4
1
4
4
4
4
4
4
2
4
1
2
2
2
2
1
-
3.3pF, +/- 0.1pF, 0603
5.6pF, +/- 0.25%, 0603
10pF, +/- 5%, 0603
120pF, +/- 5%, 0805
240pF, +/- 5%, 0805
10nF, +/- 10%, 0805
1µF, +/- 10%, 1204
68µF, +/- 10%, H13
49.9Ω, +/- 1%, 0603
220Ω +/- 1%, 0603
22Ω +/- 1%, MMA0204
CMS 3cts
Resistor
Resistor
Connector
Connector
Connector
Packaged Transistor
PCB
J2
CMS 5cts
J3
N
Q1
-
CHK080A-SRA
RO4003, Er=3.55, h=0.508mm
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
9/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK080A-SRA
80W Power Packaged Transistor
Demonstration Amplifier Circuit (Ref. 61500192)
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
10/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
80W Power Packaged Transistor
CHK080A-SRA
Package outline
All dimensions are in mm
Tcase (A) (°C)
Tcase (A) (°C)
(A)
Tcase locates the reference point used to monitor the device temperature. This point has
been taken at the device / system interface to ease system thermal design.
Chamfered lead indicates the gate access of the packaged transistor.
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
11/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK080A-SRA
80W Power Packaged Transistor
Recommended Assembly Procedure
CHK080A-SRA is available as a flange package to be bolt down onto a thermal heat sink
also used as main electrical ground. Use preferably screw M2 and flat washers.
Thermal and electrical resistance at the package to heat sink interface has to be as low as
possible. Thermal electrically conductive grease or conductive thin layer like indium sheets
are recommended between the package and the heat sink.
In case a thermal grease is selected, we recommend to use material offering thermal
conductivity >5W/m.K and electrical resistivity <0.01 ohm.cm. The grease layer thickness
should be about 25µm (1 mil).
Contact interface quality can be improved by cleaning process prior device mounting on the
heat-sink. Such operation will enhance the thermal and electrical contact by oxide removal at
each interface.
Package leads can be soldered on printed circuit board traces by using RoHS solder past.
Cavity depth and width to be performed into the heat-sink where the device will be mounted
are important to achieve the best performances. These dimensions have to be optimized in
order to minimize the distance between device and signal traces made on the printed circuit
board (PCB). But they also have to be calculated in order to accommodate device variations
in height. The following drawing gives the relationship between device dimensions (Hpack &
Wpack) and optimal cavity depth (Hcav) and width (Wcav) depending on the printed circuit-
board configuration (HPCB)
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
12/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
80W Power Packaged Transistor
CHK080A-SRA
Notes
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
13/14
Specifications subject to change without notice
Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34
CHK080A-SRA
80W Power Packaged Transistor
Recommended environmental management
UMS products are compliant with the regulation in particular with the directives RoHS
N°2011/65 and REACh N°1907/2006. More environmental data are available in the
application note AN0019 also available at http://www.ums-gaas.com.
Recommended ESD management
Refer to the application note AN0020 available at http://www.ums-gaas.com for ESD
sensitivity and handling recommendations for the UMS package products.
Ordering Information
Package :
CHK080A-SRA/XY
Tray: XY = 26
Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors
S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of
patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use
as critical components in life support devices or systems without express written approval from United
Monolithic Semiconductors S.A.S.
Ref. : DSCHK080A-SRA3148 - 28 Jun 13
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Specifications subject to change without notice
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