TTP259-EOBN [TTELEC]
Preliminary;
| 型号： | TTP259-EOBN |
| 厂家： | 
TT Electronics |
| 描述： | Preliminary |
| 文件： | 总81页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TTP259
TonTouchTM
Preliminary
§ PATENTEN
1. PATENT :『電流源控制及補償觸控電容感測方法及其裝置』
PAT NO. I339356 (Taiwan)
PAT NO. ZL 2007 1 0202087. 0 (CHINA)
2. PATENT :『具環境變化校正的電容式觸控感測裝置』
PAT NO. M383780 (Taiwan)
PAT NO. ZL 2010 2 0141537. 7 (CHINA)
3. PATENT :『省電型多鍵觸摸開關感測裝置』
PAT NO. M375250 (Taiwan)
PAT NO. ZL 2010 2 0302392. 4 (CHINA)
§ General Description:
TTP259 MCU is an easy-used 4-bit CPU base microcontroller. It
contains 4032-word ROM、384-nibble RAM、time base、timer/counter、
interrupt service、IO control hardware、PWM output、IIC function、LVR and
touch pad feature for specified applications. The device is also suitable for
diverse simple applications in control appliance and consumer product.
§ Features:
1. Tontek RISC 4-bit CPU core
2. Total 26 crucial instructions and two addressing mode
3. Most instructions need 1 word and 1 machine cycle(2 CPU clocks) except
read table instruction(RTB)
4. Advance CMOS process
5. Working memory with 4032*16 program ROM and 384*4 SRAM
6. 4-level stacks
7. Operating voltage: 2.4V~5.5V(LVR=2.2V); 3.3V~5.5V(LVR=3.0V);
2.2V~5.5V(LVR OFF)
8. System operating frequency: (at VDD=5V)
. High speed system oscillator (OSCH)
Built-in RC oscillator: 4MHz(typical)
. Low speed peripheral oscillator (OSCL)
Built-in RC oscillator: 16KHz(typical)
9. Provide 7 IO+16 touch pad or 23 general programmable IO
IO port built-in key wake-up feature enable by software setting
Provide external interrupt inputs
Provide internal signal outputs, like PWM
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TonTouchTM
Preliminary
10. TWO time base
Time base offers 2 various period interrupt request
11. One 8-bit TCP1 auto-reload timer/counter
4 timer clock sources selected by software
12. One 12-bit TCP2 auto-reload timer/counter, can improve PWM function
4 timer clock sources selected by software
13. Built-in 3 set 12-bit PWM output
14. MCU system protection and power saving controlled mode
Built-in watch dog timer (WDT) circuit
Built-in low voltage reset (LVR) function
Out of user program’s range detection
ROM code error detection
Provide high/low system operating speed, sleep and stop
mode for power saving control
15. Provide 16 pins with touch pad detection
16. LDO voltage can select 2.7V or 4.2V output by mask option
17. LVR voltage can select 2.2V or 3.0V by mask option
18. Provide two wire serial interface (IIC-BUS)
19. Provide 10 interrupt sources
External: INT0, INT1 shared with IO pad
Internal: two time base, two timer/counter
Two touch pad’s interrupt
Two IIC interrupt
20. Provide package types
28SSOP/20TSSOP/16SOP
§ Applications:
1. Household electric appliances
2. Consumer products
3. Measurement controller
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TonTouchTM
Preliminary
§ Package Description:
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TonTouchTM
Preliminary
§ Block Diagram:
OSCH and
OSCL
Time Base
PA2~PA0
8-bit Timer/Counter
12-bit Timer/Counter
PWM0,1,2
PB3~PB0
PC3~PC0
PD3~PD0
PE3~PE0
PF3~PF0
ROM
RAM
IO
IIC slave
System Control Unit
Interrupt
ST446DO5
MCU
RSTB
Touch Pad
Reset
Detection
VREG
CAP
LDO
WDT
LVR
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TonTouchTM
Preliminary
§ Pad Description:
Mask
Pad
Pad Name
Share Pad
IO
Pad Description
Option
VDD
VSS
RSTB
PA0
PA1
PA2
-
-
-
Power
Power
I
+2
+4
+1
-
-
Positive power supply.
Negative power supply, ground.
External reset input, active low.
IO port with external interrupt
input, external clock input and
PWM output. PA0 is shared with
external interrupt input, PA1 is
shared with external clock input,
PA0,PA1,PA2 is shared with PWM
output.
-
INT0/PWM2/VPP IO/I/O +3
Yes
TCP1I/PWM1
PWM0
IO/I/O
IO/O
PB0
PB1
PB2
PB3
SCL/INT1/PWM0 IO/I/O +4
Yes
IO port with internal IICBUS,
external interrupt input and PWM
output. PB0,PB1 is shared with
internal IICBUS, PB0,PB2,PB3 is
shared with external interrupt
input, PB0,PB1,PB3 is shared with
PWM output.
SDA/PWM1
INT1
IO/O
IO/I
INT0/PWM2
IO/I/O
PC0
PC1
PC2
PC3
PD0
PD1
PD2
PD3
PE0
PE1
PE2
PE3
PF0
PF1
PF2
PF3
TP0
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
+4
+4
+4
+4
-
-
-
-
IO port or touch pad input.
TP1
TP2
TP3
TP4
IO port or touch pad input.
IO port or touch pad input.
IO port or touch pad input.
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
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Preliminary
TonTouchTM
CAP
-
-
O
Power
-
+1
+1
32
-
-
-
Touch signal output.
VREG
LDO voltage output.
-
Total pad -
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TonTouchTM
Preliminary
§ IO Cell Type Description:
Pin Name
IO Type
Description
PA0
PA1
Figure IO-G
STD IO with internal PWM output and
external interrupt trigger input.
STD IO with internal PWM output and
external TCP1 clock input.
Figure IO-C
PA2
PB0
Figure IO-B
Figure IO-E
STD IO with internal PWM output.
STD IO with internal PWM output and
external interrupt trigger input and IIC.
STD IO with internal PWM output and
IIC.
PB1
PB2
PB3
Figure IO-F
Figure IO-D
Figure IO-H
STD IO with internal PWM output and
external interrupt trigger input.
STD IO with external interrupt trigger
input.
PC0~PC3
PD0~PD3
PE0~PE3
PF0~PF3
Figure IO-A
Figure IO-A
Figure IO-A
Figure IO-A
STD IO with touch pad input.
STD IO with touch pad input.
STD IO with touch pad input.
STD IO with touch pad input.
§ Absolute Maximum ratings:
ITEM
SYMBOL
Top
RATING
-20~+70
UNIT
℃
Operating Temperature
Storage Temperature
Supply Voltage
-50~+125
℃
Tst
VSS-0.3~VSS+6.0
VSS-0.3~VSS+12.5
VSS-0.3~VDD+0.3
>5
V
VDD
VPP
V
OTP Supply Voltage
Input Voltage
V
Vin
KV
Human Body Mode ESD
Note: VSS symbolizes for system ground.
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TonTouchTM
Preliminary
§ DC and AC Characteristics
§ DC Characteristics: (Test condition at room temperature=25oC)
Parameter
Symbol Test Condition
Min. Typ. Max. Unit
Operating Voltage
VDD
2.4
3.3
2.2
-
-
-
5.5
5.5
5.5
4.0
V
FOSCH=4MHz, LVR on 2.2V
FOSCH=4MHz, LVR on 3.0V
FOSCH=4MHz, LVR off
-
Operating Current
(Normal Mode, CPU
working, IO no load)
Ind1
Ind2
Isd1
Isd2
Isd3
VDD=5.0V, no load, FOSCL on,
3.5
mA
uA
mA
uA
uA
F
OSCH=4MHz, LVR off, LDO off
VDD=5.0V, no load, FOSCL on,
OSCH off, LVR off, LDO off
VDD=5.0V, no load, FOSCL on,
OSCH=4MHz, LVR off, LDO off
VDD=3.0V, no load, FOSCL on,
OSCH off, LVR off, LDO off
VDD=5.0V, no load, FOSCL off,
-
-
-
-
30
0.6
5
50
0.8
10
1
F
Operating Current
(Sleep Mode, CPU stop,
IO no load)
F
F
Standby Current
(Stop Mode, CPU stop,
IO no load)
-
FOSCH off, LVR off, LDO off
LVR Current
ILVR
ILDO
VIL
VDD=5.0V
VDD=5.0V
55
uA
uA
LDO Current
100
Input Ports
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
VDD=5.0V, VOL=0.6V
0
0.8
0
-
-
0.2 VDD
1.0 VDD
0.3 VDD
1.0 VDD
Input Ports
VIH
VIL
RSTB and INT
RSTB and INT
PA0 Sink Current
-
VIH
IOL
0.7
-
-
2
-
mA
PA0 Source Current
Output port Sink Current
(PA, PB exclude PA0)
Output Port Source
Current (PA, PB exclude
PA0)
IOH
IOL
VDD=5.0V, VOH=4.3V
VDD=5.0V, VOL=0.6V
-
-
-1
-
-
mA
mA
32
IOH
VDD=5.0V, VOH=4.3V
-
-8
-
mA
Output port Sink Current
(PC, PD, PE, PF)
IOL
IOH
RPH
VDD=5.0V, VOL=0.6V
VDD=5.0V, VOH=4.3V
VDD=5.0V
-
-
16
-8
-
-
mA
mA
KΩ
Output Port Source
Current (PC, PD, PE, PF)
IO Port Pull-up Resistor
100 150 200
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Preliminary
TonTouchTM
RSTB Pull-up Resistor
RPH
VDD=5.0V
30
50
80
3.3
2.4
4.6
3.0
KΩ
Low Voltage Reset (LVR) VLVR1
VLVR2
For AC application
2.7 3.0
2.0 2.2
3.8 4.2
2.4 2.7
V
V
LDO Voltage
VLDO1
VLDO2
VBGAP
V
V
Bandgap Voltage
1.0 1.12 1.23
V
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TonTouchTM
Preliminary
§ AC Characteristics: (Test condition at room temperature=25oC)
Parameter
Test Condition
Min. Typ. Max. Unit
External Reset
Low active pulse width tRES
2
-
-
CPU
clock
CPU
Interrupt input
Wake up input
Low active pulse width tINT
2
-
-
clock
Low active pulse width tWKUP,
Application de-bounce should be
manipulated by user’ software
2
-
-
-
-
OSCL
Hz
System Oscillator
Frequency
FOSCH (Built-in RC)
FOSCL (Built-in RC)
VDD=5.0V
VDD=5.0V
4M
Peripheral
Oscillator
Frequency
Hz
-
16K
-
wake-up from
off mode
TOSCH (Built-in RC)
TOSCL (Built-in RC)
8
8
-
-
-
-
TOSCH
TOSCL
Startup Period of
Oscillators
Wake-up from
off mode
OSCLÆOSCH
TOSCH (Built-in RC)
TOSCL (Built-in RC)
8
-
-
TOSCL
and OSCH off
Stable Time
Of System Clock
Switching
(If H/L=0 then OSCH stop)
OSCHÆOSCL
-
-
-
-
TOSCL
and OSCL on
Timer/Counter Input frequency rating, no de-bounce
input clock
frequency
circuit built-in,
VDD=5V
DC
-
4M
Hz
System Stable After power up, the system needs to
Time after
Power up
initialize the configured state and
OST
-
40
ms
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TonTouchTM
Preliminary
§ Memory Map:
ROM ADDRESS
RAM ADDRESS
Function Block
-
000H~FBFH
Program ROM [4032*16]
File Registers
-
-
-
-
000H~007H
008H~01FH
020H~19FH
200H~304H
Peripheral registers (I)
Working RAM [384*4]
Peripheral registers (II)
§ Interrupt Vectors:
Interrupt Vectors
Function Description
Hardware reset
$000
$001
Hardware interrupt
§ File registers:
Address Symbol R/W Default
Description
----
000H
001H
002H
003H
004H
005H
006H
007H
(DP1) R/W
Indirect addressing register
Accumulator and read table 1st data
Read table 2nd data
ACC
TB1
TB2
TB3
DPL
DPM
DPH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
Read table 3rd data
Read table 4th data
Data pointer low nibble data
Data pointer middle nibble data
Data pointer high nibble data
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TonTouchTM
Preliminary
§ Peripheral registers:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address Symbol
Default
-100 CPU power saving control register
0--- Peripheral power saving control register
Description
008H
009H
00AH
00BH
00CH
00DH
00EH
00FH
010H
011H
012H
013H
014H
015H
016H
017H
018H
019H
01AH
01BH
01CH
01DH
01EH
01FH
PS
PSP
INTC
INTF
INTC1
INTF1
PWMC
PWM0L
PWM0M
PWM0H
PAC
0000 Interrupt enable control register
0000 Interrupt request flag register
0000 Extended interrupt enable control register
0000 Extended interrupt request flag register
-000 PWM control register
xxxx PWM0 duty low nibble data register
xxxx PWM0 duty middle nibble data register
xxxx PWM0 duty high nibble data register
-111 IO port A control register
PA
-111 IO port A output data register
1111 IO port B control register
PBC
PB
1111 IO port B output data register
1111 IO port C control register
PCC
PC
1111 IO port C output data register
1111 IO port D control register
PDC
PD
1111 IO port D output data register
1111 IO port E control register
PEC
1111 IO port E output data register
PE
PFC
R/W
R/W
R/W
R/W
1111 IO port F control register
PF
1111 IO port F output data register
TPINTC
TPINTF
00--
00--
Touch pad interrupt enable control register
Touch pad interrupt request flag register
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TonTouchTM
Preliminary
200H
201H
202H
203H
204H
205H
206H
207H
208H
209H
20AH
20BH
20CH
20DH
20EH
20FH
210H
211H
212H
213H
214H
215H
216H
217H
218H
219H
21AH
21BH
21CH
21DH
21EH
21FH
220H
TCP1C
TCP1L
TCP1H
TCP2C
TCP2L
TCP2M
TCP2H
PAI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0000 TCP1 Timer/counter control register
xxxx TCP1 Timer/counter data low register
xxxx TCP1 Timer/counter data high register
0000 TCP2 Timer/counter control register
xxxx TCP2 Timer/counter data low register
xxxx TCP2 Timer/counter data middle register
xxxx TCP2 Timer/counter data high register
----
----
----
----
----
----
Port A pad data reading address
Port B pad data reading address
Port C pad data reading address
Port D pad data reading address
Port E pad data reading address
Port F pad data reading address
PBI
R
PCI
R
PDI
R
PEI
R
PFI
R
TCPFS
TBC
R/W
R/W
-
-000 TCP clock source FS pre-scale register
1111 Time base control register
-
----
-
TPCHS0
TPCHS1
TPCHS2
TPCHS3
TPCTL
TPCT0
TPCT1
TPCT2
CSAL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000 Touch pad channel selector register 0
0000 Touch pad channel selector register 1
0000 Touch pad channel selector register 2
0000 Touch pad channel selector register 3
-000 Touch pad control register
1111 Touch pad Duty counter 1st nibble
1111 Touch pad Duty counter 2nd nibble
1111 Touch pad Duty counter 3rd nibble
0000 Touch pad C load low nibble
CSAH
MCKS
SPCON0
SPCON1
--00
Touch pad C load high nibble
-111 Modulation clock selector register
0000 Special control register 0
0000 Special control register 1
SPCON2 R/W
LDOFLAG R/W
--00
---0
Special control register 2
LDO fail flag
R/W
R/W
0000 Touch pad output register for special function
0001 OSCH frequency adjustment register
ODATA
OSCHADJ
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Preliminary
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
---1
IIC control register 0
221H
222H
223H
224H
225H
226H
227H
228H
229H
22AH
22BH
22CH
22DH
22EH
22FH
230H
231H
232H
300H
301H
302H
303H
304H
IICCON0
IICCON1
IICSTS
0000 IIC control register 1
0001 IIC status register
xxxx IIC data low nibble register
IICDATL
IICDATH
IICRDATL0
IICRDATH0
IICRDATL1
IICRDATH1
PWM1L
xxxx IIC data high nibble registe
0000 IIC fast read data low nibble register 0
0000 IIC fast read data high nibble register 0
0000 IIC fast read data low nibble register 1
0000 IIC fast read data high nibble register 1
xxxx PWM1 duty low nibble data register
xxxx PWM1 duty middle nibble data register
xxxx PWM1 duty high nibble data register
xxxx PWM2 duty low nibble data register
xxxx PWM2 duty middle nibble data register
xxxx PWM2 duty high nibble data register
PWM1M
PWM1H
PWM2L
PWM2M
PWM2H
ADJSTAT
TBLDRL
TBLDRH
RESETF
TBRB
--11
Frequency Adjustment Status flag register
R
0000 Time base preload register low nibble
1000 Time base preload register high nibble
0000 Reset flag
R
R/W
W
----
----
Time base clear address
W
Mask option register enable address
MRO
W
----
Clear WDT 2nd instruction
LVR enable control register
CLRWDT
LVREN
R/W
---0
Note: a. Default means initial value after power on or reset.
b. R is “read” only, W is “write” only, R/W is both of “read” and “write”.
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Preliminary
§ System function description:
S-1: System Oscillator
The high speed oscillator is operated in built-in RC mode. It is fixed
4MHz (typical at VDD=5V).
S-2: Peripheral Oscillator
The low speed oscillator was built-in an internal RC oscillator that is for
low power consumption consideration and fixed peripheral device timing
control. Built-in RC oscillator and the frequency range between 11 KHz~21
KHz.
S-3: CPU clock
The CPU clock comes from system/peripheral oscillator which was
controlled by H/L bit in PS register. The high speed operation frequency
comes from system oscillator. The low speed operation frequency comes
from peripheral oscillator.
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Preliminary
OSCHEN
System clock
OSCH (4MHz)
1
M
U
CPU clock
X
0
4MHz (Built-in RC)
H/L
Peripheral clock
OSCL (16KHz)
TBCK
16KHz (Built-in RC)
Figure: System/Peripheral Oscillator and CPU Clock
Sources
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Preliminary
S-4: Power saving mode (Stop mode and Sleep mode)
The CPU enters stop or sleep mode is operated by writing CPU power
saving control register (PS). During the power saving mode, CPU holds the
internal status of the system. In stop mode, the oscillator clocks will be
stopped and system need a warm-up time for the stability of system clock
running after wake up.
S-5: MCU System Operating Mode
The MCU has 4 operating modes, including high speed operation, low
speed operation, sleep and stop modes. After power on reset, the MCU will
go into high speed operation mode automatically. After wake up from
sleep mode, the MCU will resume the last operation mode.
STOP mode
OSCH off & OSCL off
STOP/
STOP/
wake up
wake up
Reset
High speed operating
mode
OSCH on & OSCL on
Reset release
H/L
Reset
Low speed operating
Reset
mode
RESET
OSCH off & OSCL on
SLEEP/
wake up
Reset
SLEEP/
wake up
SLEEP mode
CPU stop
Figure: System Operation State Diagram
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Preliminary
* Power saving mode condition and release
Modes
Stop mode
Sleep mode
Stopped as H/L=0
Keep operating as H/L=1
Keep operating
High speed oscillator
Stopped
Low speed oscillator
CPU clock
Stopped
Stopped
Stopped
CPU internal status
Memory, Flag, Register, IO
Program counter
Stop and Retain the status
Retain the status
Hold the next executed address
Peripherals: Time bases,
Timers, Interrupts
Watch Dog Timer
Stopped and Retain
Keep operating
Disable and cleared
Release Condition
Reset, external INT
sources, Input wake-up
Reset, internal and external
INT sources, Input wake-up
S-6: Watch Dog Timer (WDT)
The clock of watch dog timer comes from time base 1st overflow output
(TB1OV).User can use the time up signal to prevent a software malfunction or
abnormal sequence from jumping to an unknown memory location causing a
system fatal failure. Normally, if the watch dog timer time up signal active that
will reset the chip. At the same time, program and hardware can be initialized
and resume system under normal operation. The chip also provides 2 steps
clear watch dog command as the programmer writes INTF with $F data first
that will enable the WDT clear, and then writes CLRWDT register after.
Completely finishes the two write steps will clear the watch dog timer. User
should well arrange the two command steps for avoiding the dead lock loop.
User should keep in minds that always clear the WDT at main
program and never clear the WDT in the interrupt routine.
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Preliminary
The maximum period of WDT =(TB1OV cycle time) * 8
Q
WDT
TB1OV
QB
TFF
TFF
TFF
DFF
Overflow
POR+RESET
SLEEP, STOP
INTF write $F first then
write CLRWDT after
Figure: Watch Dog Timer circuit
S-7: Low Voltage Reset (LVR)
The low voltage reset (LVR) forces the MCU in reset state during power
failure, especially as MCU working in AC power application, preventing from
abnormal state is the key issue. The LVR voltage can be select 2.2V, 3.0V by
mask option.
S-8: Reset
The chip has six kinds of reset sources: POR (power on reset), External
reset, Watch dog timer reset, LVR (low voltage reset), Burn out reset and
ROM fail reset. The reset feature can be divided into 2 kind groups that one
is system reset and the other is CPU reset. The system reset will initialize
the CPU and peripheral device with default state. The CPU reset only
initializes the CPU state and keeps the peripheral state no change.
.POR (power on reset)
The chip provides automatically reset function when the power is
turned on. The VDD should be below 0.5V and its rising slope (from
0.1VDD up to 0.9VDD) needs less than 10ms.
.External reset (RSTB)
This is one kind of system reset signal, but only forced externally.
When the chip acknowledged the low level from the pin RSTB exceed 1 us,
it will generate the reset procedure to reset CPU and all the peripheral back
to their initial state (default values).
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.Watch Dog Timer reset
The reset signal will generate automatically when the watch dog timer
runs overflow. If the watch dog timer is cleared regularly by users’ program,
no watch dog timer reset will occur. Unless the MCU is forced into abnormal
state, the software controlled procedure is disrupted and causing watch
dog timer overflow, then it will generate reset signal to initializes the chip
returning to normal operation.
.Low voltage reset (LVR)
The LVR function is used to monitor the supply voltage of MCU, it will
generate a reset signal (with 4 OSCL de-bounce time) to reset the
microcontroller as the VDD power falls below the default setting level VLVR.
It can also be enabled or disabled by programming LVREN bit in LVREN
register. User writes $5 to LVREN register, LVREN bit is set to 1 and enable
LVR function. User writes $A to LVREN register, LVREN bit is clear to 0 and
disable LVR function. If user writes other value to LVREN register, it can’t
change LVREN bit.
.Burn out reset (Program sequence abnormal)
As CPU out of program area, the CPU can detect the abnormal
condition and generate a system reset request.
.ROM fail reset
As ROM fail, the CPU can detect the abnormal condition and generate
a system reset request.
RESETF[300H]: Reset source flag register [R/W], power on value [0000]
Register
Bit Name
Read/Write
Bit3
ROMF
R/W
Bit2
BOF
R/W
Bit1
LVRF
R/W
Bit0
WDTF
R/W
WDTF: Watch dog timer overflow reset flag. (0: no active; 1: active)
LVRF: Low voltage reset flag. (0: no active; 1: active)
BOF: Burn out flag. (0: no active; 1: active)
ROMF: ROM fail flag. (0: no active; 1: active)
Note: The RESETF is only cleared by power on reset and external reset.
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S-9. Power saving control register
PS[008H]: Power saving control register [R/W], default value [-100]
Register
Bit Name
Read/write
Bit3
Bit2
H/L
Bit1
SLEEP
R/W
Bit0
STOP
R/W
-
-
R/W
STOP: Into stop mode. (0: disable; 1: enable)
SLEEP: Into sleep mode. (0: disable; 1: enable)
H/L: CPU clock source selector. (1: system clock; 0: peripheral clock)
When H/L=0, system clock oscillator is stopped.
When STOP bit is set to 1, system and peripheral clock oscillator are
stopped. When H/L bit is set to 1, system clock oscillator is stopped. The SLEEP
bit and STOP bit will be cleared to 0 automatically, when the release conditions
occur from reset, interrupt or input wake up.
S-10. Special control register
SPCON0 [21BH]: Special control register 0 [R/W], default value [0000]
Register
Bit3
CDSC2
R/W
Bit2
CDSC1
R/W
Bit1
CDSC0
R/W
Bit0
VREFS
R/W
Bit Name
Read/write
VREFS: Voltage reference selector for touch sensor detection. (0: 1/2 VDD; 1:
2/3 VDD)
CDSC2~CDSC0: Charge and discharge sequence control for touch sensor
function.
CDSC2~CDSC0
Sequence change clock
000
001
010
011
100
101
110
111
OFF
8
12
16
24
32
Reserve
Reserve
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SPCON1 [21CH]: Special control register 1 [R/W], default value [0000]
Register
Bit3
INTTS
R/W
Bit2
FST2
R/W
Bit1
FST1
R/W
Bit0
FST0
R/W
Bit Name
Read/write
FST2~FST0: Frequency Shift Time selector.
INTTS: INT0 Interrupt input type selector. (0: Schmitt; 1: comparator)
Compare reference voltage use bandgap voltage 1.12V.
FST2~FST0
000
Frequency Shift Time (us)
OFF
4
001
010
8
011
16
32
64
128
256
100
101
110
111
SPCON2 [21DH]: Special control register 2 [R/W], default value [--00]
Register
Bit3
Bit2
Bit1
TPNIS
R/W
Bit0
CSAMODE
R/W
Bit Name
Read/write
-
-
-
-
CSAMODE: CSA mode selector for touch pad scan.
0: C array as a touch pad capacitance compensation.
1: C array as a touch pad current compensation.
TPNIS: Touch detect circuit type selector.
0: TPNI use Schmitt trigger output signal.
1: TPNI use comparator output signal.
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S-11. OST time
The system oscillator generates the system control timing for CPU core or
peripheral devices with fixed control phase, so the waveform of oscillator
becomes sensitive to noise, abnormal duty especially fatal for CPU. Any
switching of clock source needs oscillation stable time (OST) to make sure the
oscillation is stable and synchronized with CPU timing phase. The relative OST
for different oscillator with reference value as below table:
OST
System clock(OSCH) Peripheral clock(OSCL)
High speed STOP wakeup
Low speed STOP wakeup
High speed SLEEP wakeup
Low speed SLEEP wakeup
Low speed to High speed
-
-
8
8
-
8
-
8
8
-
PSP[009H]: Peripheral power saving control register [R/W], default value [0---]
Register
Bit Name
Read/write
Bit3
LDOEN
R/W
Bit2
Bit1
Bit0
-
-
-
-
-
-
LDOEN: LDO enable. (0:disable; 1:enable)
The LDO voltage can be select 2.7V, 4.2V by mask option.
LVREN[304H]: LVR enable control register [R/W], default value [---0]
Register
Bit Name
Read/write
Bit3
Bit2
Bit1
Bit0
LVREN
R/W
-
-
-
-
-
-
LVREN: Low voltage reset enable. (0:disable, 1:enable)
When write $5 to this address, LVREN is set to 1; write $A, LVREN is clear to 0.
LDOFLAG[21EH]: LDO flag register [R/W], default value [---0]
Register
Bit Name
Read/write
Bit3
Bit2
Bit1
Bit0
LDOFAIL
R/W
-
-
-
-
-
-
LDOFAIL: When VDD voltage is smaller than LDO voltage, LDOFAIL will be set.
This bit can be clear by write 0.
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S-12. Interrupts
The CPU provides only 1 interrupt vector ($001H) and no priority, but can
expand to multi-sources. Interrupt source includes external interrupts
(INT0,INT1), timer/counter interrupts (TCP1,TCP2), Time base timer interrupt
(TBxINT) or other peripheral device interrupt request (PERINT). The interrupt
control registers (INTC or INTC1) contain the interrupt control bit to enable and
disable corresponding interrupt request and the corresponding interrupt
request flags in the (INTF or INTF1) registers. Before finishing the INT service
routine, another INT request will keep waiting until program return from
interrupt routine.
If the interrupt request needs service, the programmer may set the
corresponding INT enable bit to allow interrupt active. External interrupts are
triggered by both falling and rising edge trigger and set the related interrupt
request flag (INTFx). The internal timer/counter interrupt is setting the TCPxF
to 1, resulting from the timer/counter overflow. The time base interrupt TBxINT
was provided 2 periodic interrupt request cycles for user operating a periodic
routine.
When the corresponding interrupt enable and flag bit is set to 1, the CPU
will active the interrupt service routine. Then CPU reads the service flag and
check the request priority then proceeds with the relative interrupt service.
After CPU writes the corresponding bit to 0 in the INTFx register, the service
flag will be cleared to 0(using STX #n,$m instruction). The INTF and INTF1
registers’ bit can only write 0 to clear the flag. User writes 1 to flag bit with no
effect.
INT0 input type can select Schmitt or comparator by SPCON1 register, if
comparator select then the comparator reference voltage is the bandgap
voltage(1.12+-10%), it will consumption more current than Schmitt because
bandgap turn on. It can be used to detect VDD voltage for battery low and so
on.
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INTC[00AH]: Interrupt control register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TB2IE
R/W
Bit2
TCP2IE
R/W
Bit1
TCP1IE
R/W
Bit0
TB1IE
R/W
TB1IE: Enable time base 1st interrupt. (0: disable; 1: enable)
TCP1IE: Enable interrupt of TCP1 timer/counter. (0: disable; 1: enable)
TCP2IE: Enable interrupt of TCP2 timer/counter. (0: disable; 1: enable)
TB2IE: Enable time base 2nd interrupt. (0: disable; 1: enable)
INTF[00BH]: Interrupt request flag register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TB2F
R/W
Bit2
TCP2F
R/W
Bit1
TCP1F
R/W
Bit0
TB1F
R/W
TB1F: Time base 1st interrupt request flag. (0: inactive; 1: active)
TCP1F: TCP1 Timer/counter interrupt request flag. (0: inactive; 1: active)
TCP2F: TCP2 Timer/counter interrupt request flag. (0: inactive; 1: active)
TB2F: Time base 2nd interrupt request flag. (0: inactive; 1: active)
INTC1[00CH]: Extended interrupt control register [R/W], default value [0000]
Register
Bit3
STIE
R/W
Bit2
IICIE
R/W
Bit1
INT1IE
R/W
Bit0
INT0IE
R/W
Bit Name
Read/Write
INT0IE: Enable INT0 external interrupt. (0: disable; 1: enable)
INT1IE: Enable INT1 external interrupt. (0: disable; 1: enable)
IICIE: Enable IIC interrupt. (0: disable; 1: enable)
STIE: Enable IIC start signal interrupt. (0: disable; 1: enable)
INTF1[00DH]: Extended interrupt request flag register [R/W], default value [0000]
Register
Bit3
STIF
R/W
Bit2
IICF
R/W
Bit1
INT1F
R/W
Bit0
INT0F
R/W
Bit Name
Read/Write
INT0F: INT0 external interrupt request flag. (0: inactive; 1: active)
INT1F: INT1 external interrupt request flag. (0: inactive; 1: active)
IICF: IIC interrupt request flag. (0: inactive; 1: active)
STIF: IIC start signal interrupt request flag. (0: inactive; 1: active)
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INTxS1~INTxS0
Trigger type
00
01
10
11
Low active
Falling edge
Rising edge
Dual edge trigger
Note: INTx Trigger type are selected by mask option.
TPINTC[01EH]: Touch pad interrupt control register [R/W], default value [00--]
Register
Bit3
TPCTIE
R/W
Bit2
TPCMPIE
R/W
Bit1
Bit0
Bit Name
-
-
-
-
Read/Write
TPCMPIE: Capacitor overcharge interrupt enable. (0: disable; 1: enable)
TPCTIE: Duty counter overflow interrupt enable. (0: disable; 1: enable)
TPINTF[01FH]: Touch pad request flag register [R/W], default value [00--]
Register
Bit3
TPCTF
R/W
Bit2
TPCMPF
R/W
Bit1
Bit0
Bit Name
-
-
-
-
Read/Write
TPCMPF: Capacitor overcharge flag. (0: inactive; 1: active)
TPCTF: Duty counter overflow flag. (0: inactive; 1: active)
§ Peripheral function description:
P-1: System clock pre-scale
The system clock is the most high frequency of MCU. For various peripherals,
application needs different clock source divided from system clock. TCPFS register
is a selector for choosing suitable frequency (FS).
TCPFS[20DH]: System clock pre-scale register [R/W], default value [-000]
Register
Bit Name
Read/Write
Bit3
Bit2
FS2
R/W
Bit1
FS1
R/W
Bit0
FS0
R/W
-
-
FS2~FS0: The selector of TCPFS.
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FS2~FS0
FS
FS2~FS0
FS
0
1
2
3
OSCH/1
OSCH/2
OSCH/4
OSCH/8
4
5
6
7
OSCH/16
OSCH/32
OSCH/64
OSCH/128
P-1-1: OSC Frequency Adjustment
ADJSTAT[230H]: Frequency Adjustment Status flag register [R], default value [--11]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
Bit0
-
-
-
-
OSCHADJF TBADJF
R
R
TBADJF: Time base adjustment status flag. (0: busy, 1: idle)
OSCHADJF: OSCH frequency adjustment status flag. (0: busy, 1: idle)
SPCON1 [21CH]: Special control register 1 [R/W], default value [0000]
Register
Bit3
INTTS
R/W
Bit2
FST2
R/W
Bit1
FST1
R/W
Bit0
FST0
R/W
Bit Name
Read/write
FST2~FST0: Frequency Shift Time selector.
FST2~FST0
000
Frequency Shift Time (us)
OFF
4
001
010
8
011
16
32
64
128
256
100
101
110
111
OSCHADJ [220H]: OSCH frequency adjustment register [R/W], default value [0001]
Register
Bit3
ADJ3
R/W
Bit2
ADJ2
R/W
Bit1
ADJ1
R/W
Bit0
ADJ0
R/W
Bit Name
Read/write
ADJ3~ADJ0: OSCH frequency adjustment data.
OSCHADJ set the frequency swing range, when the change time in register
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FST is set, frequency shift function will be activated. Swing shift back and forth
from the center frequency. Set FST=0 to off frequency shift function. When
frequency shift function is executing, OSCHADJF will be set 0. Then user can
not change OSCHADJ and FST, but only can be set 0 to off function. Frequency
shift function will not immediately stop, when FST is set to 0, the need to wait
until the frequency back to the original frequency, while OSCHADJF will be set
to 1.
OSCHADJ use ranges from 1 to 8, do not use the value out of range.
P-2: Time Base
The time base has 2 interrupt sources and both of them come from
the peripheral internal RC oscillator. The time base 1st overflow output
(TB1OV) can cause interrupt and the period is selected by TB1S2~TB1S0
in TBC register. The time base 2nd overflow output (TB2OV) also offers
two sample frequency options by TB2S bit in the TBC register.
TBCK/128
128Hz
TBCK/256
64Hz
TBCK/512
32Hz
16Hz
8Hz
4Hz
2Hz
1Hz
TB1OV
TB2OV
TBCK/1024
TBCK/2048
TBCK/4096
TBCK/8192
TBCK/16384
TBCK
8-bit
7-bit
Counter
Counter
clear
TBLDR
reload
Write TBRB to
TB2S
TB1S2~TB1S0
reload 8-bit counter
and clear 7-bit counter
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TBC[20EH]: Time base control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
TB2S
R/W
Bit2
TB1S2
R/W
Bit1
TB1S1
R/W
Bit0
TB1S0
R/W
TB1S2~TB1S0: Time base 1st overflow frequency selector.
TB2S: Time base 2nd overflow frequency selector.
Note: Every time writing the TBRB will clear the time base.
TB1S2 TB1S1 TB1S0 Time Base overflow
frequency (TB1OV)
TB1OV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TBCK/128
TBCK/256
128HZ
64HZ
32HZ
16HZ
8HZ
TBCK/512
TBCK/1024
TBCK/2048
TBCK/4096
TBCK/8192
TBCK/16384
4HZ
2HZ
1HZ
TB2S
Time Base overflow
frequency (TB2OV)
TBCK/512
TB2OV
0
1
32Hz
16Hz
TBCK/1024
Note: TB1OV select 128Hz can not be use for TCP1 clock source, the TCP1 will not
work. Please use other time base select option.
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P-2-1: Adjustment Time base
ADJSTAT[230H]: Frequency Adjustment Status flag register [R], default value [--11]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
Bit0
-
-
-
-
OSCHADJF TBADJF
R
R
TBADJF: Time base adjustment status flag. (0: busy, 1: idle)
OSCHADJF: OSCH frequency adjustment status flag. (0: busy, 1: idle)
TBLDRL[231H]: Time base preload register low nibble [R], default value [0000]
Register
Bit Name
Read/Write
Bit3
TBLDR3
R
Bit2
TBLDR2
R
Bit1
TBLDR1
R
Bit0
TBLDR0
R
TBLDR3~TBLDR0: Time base preload register low nibble data.
TBLDRH[232H]: Time base preload register low nibble [R], default value [1000]
Register
Bit Name
Read/Write
Bit3
TBLDR7
R
Bit2
TBLDR6
R
Bit1
TBLDR5
R
Bit0
TBLDR4
R
TBLDR7~TBLDR4: Time base preload register high nibble data.
User can adjustment the time base for accurate 128Hz by modify first
8-bit counter preload value, the time base preload counter initial value is
80H in power on, the adjustment procedure will modify the preload counter
value to approach 128Hz, there is using TCP1 and TCP2 cascaded to form a
20-bit timer/counter, chooses clock source FS and set TCPFS=0 for TCP1,
then load 07A12H(4MHz/31250=128Hz) to the 20-bit counter and write 1H
to ADJSTAT register to start adjustment, then check TBADJF flag. It is
finished when TBADJF=1. The adjustment procedure flow chart as follow:
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START
ADJUSTMENT
CLEAR WDT
TCPFS=0
TCP1C=8
TCP2C=F
TCP1L=2
TCP1H=1
TCP2L=A
TCP2M=7
TCP2H=0
SET 20 BITS COUNTER
INITIAL VALUE
07A12H FOR 128Hz
WRITE ADJSTAT
TO START
ADJUSTMENT
STX #$1,ACC
STX ADJSTAT
YES
TBADJF=0
NO
END
P-3: 8-bit Timer/Counter for TCP1
One 8-bit timer/counter (TCP1) with 4 kind clock sources and preload
data buffer can implement as a timer or counter feature. The clock sources
of TCP1 are selected by TCP1S1~TCP1S0 of TCP1 control register (TCP1C).
TCP1OV is the timer or counter overflow signal and the rising edge will set
the relative INT flag.
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TonTouchTM
TCP1C[200H]: TCP1 Timer/counter control register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TCP1LD
R/W
Bit2
TCP1S1
R/W
Bit1
TCP1S0
R/W
Bit0
TCP1EN
R/W
TCP1EN: TCP1 counting enable. (0: disable; 1: enable)
TCP1LD: TCP1 auto-reload enable. (0: disable; 1: enable)
TCP1S1~TCP1S0: TCP1 clock source selector.
TCP1S1
TCP1S0
Selected Clock source
0
0
1
1
0
1
0
1
FS
TCP1I
TBCK
TB1OV
Note: TB1OV select 128Hz can not be use for TCP1 clock source, the TCP1 will not
work. Please use other time base select option.
TCP1L[201H]: TCP1 low nibble data register [R/W], default value [0000]
Register
Bit Name TCP1_3/TCP1D3 TCP1_2/TCP1D2 TCP1_1/TCP1D1 TCP1_0/TCP1D0
Read/Write R/W R/W R/W R/W
Bit3
Bit2
Bit1
Bit0
TCP1_3~TCP1_0: Reading TCP1 counter low nibble data.
TCP1D3~TCP1D0: Writing TCP1D low nibble of data buffer.
TCP1H[202H]: TCP1 high nibble data register [R/W], default value [0000]
Register Bit3 Bit2 Bit1 Bit0
Bit Name TCP1_7/TCP1D7 TCP1_6/TCP1D6 TCP1_5/TCP1D5 TCP1_4/TCP1D4
Read/Write R/W R/W R/W R/W
TCP1_7~TCP1_4: Reading TCP1 counter high nibble data.
TCP1D7~TCP1D4: Writing TCP1D high nibble of data buffer.
* TCP1D: Like a 8-bit TCP1 data register [R/W], default value [00H]
TCP1D Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit0
Bit Name TCP1D7 TCP1D6 TCP1D5 TCP1D4 TCP1D3 TCP1D2 TCP1D1 TCP1D0
The special R/W function for TCP1 has different Target, AS writing TCP1H/L
registers that are updating preload data of the TCP1D. As read TCP1H/L
registers that are the brand new TCP1 counter value.
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P-4: 12-bit Timer/Counter/PWM for TCP2
One 12-bit timer/counter (TCP2) with 4 kind clock sources and preload
data buffer can implement as a timer or counter feature. The clock sources of
TCP2 are selected by TCP2S1~TCP2S0 of TCP2 control register (TCP2C).
TCP2OV is the timer or counter overflow signal and the rising edge will set the
relative INT flag.
TCP2C[203H]: TCP2 Timer/counter/PWM control register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TCP2LD
R/W
Bit2
TCP2S1
R/W
Bit1
TCP2S0
R/W
Bit0
TCP2EN
R/W
TCP2EN: TCP2 counting enable. (0: disable; 1: enable)
TCP2LD: TCP2 auto-reload enable. (0: disable; 1: enable)
TCP2S1~TCP2S0: TCP2 clock source selector.
TCP2S1
TCP2S0
Selected Clock source
0
0
1
1
0
1
0
1
FS
OSCH
TBCK
TCP1OV
TCP2L[204H]: TCP2 low nibble data register [R/W], default value [0000]
Register Bit3 Bit2 Bit1 Bit0
Bit Name TCP2_3/TCP2D3 TCP2_2/TCP2D2 TCP2_1/TCP2D1 TCP2_0/TCP2D0
Read/Write R/W R/W R/W R/W
TCP2_3~TCP2_0: Reading TCP2 counter low nibble data.
TCP2D3~TCP2D0: Writing TCP2D low nibble of data buffer.
TCP2M[205H]:TCP2 middle nibble data register [R/W], default value [0000]
Register
Bit Name TCP2_7/TCP2D7 TCP2_6/TCP2D6 TCP2_5/TCP2D5 TCP2_4/TCP2D4
Read/Write R/W R/W R/W R/W
Bit3
Bit2
Bit1
Bit0
TCP2_7~TCP2_4: Reading TCP2 counter middle nibble data.
TCP2D7~TCP2D4: Writing TCP2D middle nibble of data buffer.
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TCP2H[206H]: TCP2 high nibble data register [R/W], default value [0000]
Register Bit3 Bit2 Bit1 Bit0
Bit Name TCP2_11/TCP2D11 TCP2_10/TCP2D10 TCP2_9/TCP2D9 TCP2_8/TCP2D8
Read/Write R/W R/W R/W R/W
TCP2_11~TCP2_8: Reading TCP2 counter high nibble data.
TCP2D11~TCP2D8: Writing TCP2D high nibble of data buffer.
* TCP2D: Like a 12-bit TCP2 data register [R/W], default value [000H]
TCP2D
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit Name TCP2D11 TCP2D10 TCP2D9 TCP2D8 TCP2D7 TCP2D6 TCP2D5 TCP2D4 TCP2D3 TCP2D2 TCP2D1 TCP2D0
The special R/W function for TCP2 has different Target, AS writing
TCP2H/M/L registers that are updating preload data of the TCP2D. As read
TCP2H/M/L registers that are the brand new TCP2 counter value.
.Timer
When TCPx works as a Timer, user needs give the preload data TCPxD for
periodic interrupt. After initial setting, user starts the TCPx counting by setting.
When 8-bit TCP1 timer/counter:
TCP1EN=1, the TCP1 cycle period is:
Tc = (selected clock cycle) * (256) if TCP1D=00H
Tc = (selected clock cycle) * (TCP1D) otherwise
When 12-bit TCP2 timer/counter:
TCP2EN=1, the TCP2 cycle period is:
Tc = (selected clock cycle) * (4096) if TCP2D=000H
Tc = (selected clock cycle) * (TCP2D) otherwise
When 20-bit timer/counter:
Tc = (selected clock cycle) * (1048576) if TCP1D=00H and TCP2D=000H
Tc = (selected clock cycle) * (TCP2D*256+TCP1D) otherwise
When user writes data to the TCPxH/M/L, the data just keep in TCPxH/M/L
latch. During the TCPxEN=1 command executed, the TCPxH/M/L latch’s
complement value will load into counter TCPxH/M/L as initial value and start the
timer function. Necessary TCPxLD=1, timer run with reload feature as TCPx up
counts and reaches the value of FFH or 255 for TCP1 or value of FFFH or 4095
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Preliminary
for TCP2. At the same time, interrupt request flag TCPxF will set activated, if
software enables the corresponding interrupt enable bit, INT hardware will
cause MCU interrupt service routine.
.Counter
Counter feature is implemented only by TCPxLD=0, the TCPxD can be zero
or not that depends on software needs. User starts and stops the counter by
changing the TCPxEN bit value. On the save side, reading the counter value
after stopping the count by disable TCPxEN=0, if reading the counter value
during value changing that means clock in happening at the same time. The
reading of counter value may disrupt for transient state. If 8-bit counter is not
enough for counting, user can enable the interrupt and using the data RAM as
software counter for extending the counter stage.
FS
Data Bus
Timer/Counter
M
U
X
TCP1I
TBCK
TB1OV
TCP1S1
TCP1S0
TCP1LD
TCP1EN
TCP1OV
Preload Data
Data Bus
Figure: 8-bit Timer/Counter (TCP1)
FS
OSCH
Data Bus
M
U
X
PWMx Circuit
Timer/Counter
TBCK
TCP1OV
TCP2S1
TCP2S0
TCP2LD
TCP2EN
TCP2OV
Preload Data
Data Bus
Figure: 12-bit Timer/Counter/PWM (TCP2)
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PWM Output
TCP1S1 TCP1S0 TCP1
0
0
1
1
0
1
0
1
FS
TCP2
PWM0,1,2
TCP1I
TBCK
TB1OV
TCP2S1 TCP2S0 TCP2
0
0
1
1
0
1
0
1
FS
OSCH
TBCK
TCP1OV
FS: System scaled frequency.
TCP1I: External clock input (falling edge).
TBCK: Peripheral clock source, 16KHz in the RC mode.
TB1OV: Time base 1st overflow output.
OSCH: System clock source, 4MHz in the RC mode.
TCP1OV: TCP1 overflow output.
PWM0,1,2: TCP2 cycle time with PWMxD duty output signal.
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P-5: 20-bit Timer/Counter (TCP1 and TCP2 cascade)
Two sets TCP can be cascaded to form a 20-bit timer/counter when TCP2
chooses TCP1OV as clock source (TCP2S1=1 and TCP2S0=1). In the 20-bit
timer application, user should use TCP1EN to control the starting or stopping
counting of 20-bit timer/counter, data load is controlled by writing TCP1EN=1.
The rising TCP2OV will reload the contents in the pre-load register into
timer/counter, if TCP2LD in TCP2C are enabled. The interrupt feature is
different, in this case, the TCP1 INT will be inhibit when TCP1OV occur, the
TCP2 INT is normally.
Data Bus
TCP1OV
Data Bus
TCP2OV
FS
TCP1I
M
U
X
TCP1
TCP2
TBCK
Timer/Counter
Timer/Counter
TB1OV
TCP1S1
TCP1S0
Preload data
Preload data
Data Bus
Data Bus
TCP2LD
TCP1EN
Figure: 20-bit Timer/Counter (TCP1 and TCP2 cascade)
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.PWM
The PWM period generated from TCP2. When PWMxEN (PWMC<0~2>)
enable, and PWMOUT pin (PA0~PA2,PB0~PB2 must be output mode and
select PWM function pin and normal IO by mask option) change to output
mode, PWMx signal will output to PWMOUT pin. If TCP2 is running, set
PWMxEN=1 will not execute until TCP2OV occur.
The duty of PWMx value is store in PWMxL, PWMxM and PWMxH, user
write PWMxH and PWMxM first, last write PWMxL. When write the PWMxL the
12-bit duty value will be load to PWMxD at the same time. PWM’s duty value
cannot bigger than TCP2 pre-load data. If not, PWMOUT is an unexpected
signal.
User can select PWMOUT pin start with 1 or start with 0 by mask option.
When TCP2 enable, timer start increment, if timer/counter value bigger than
PWM’s duty value, PWMOUT will change state. The PWMOUT back to start
state, When TCP2 is overflow.
User does not use PWM in 20-bit timer/counter mode. If not, PWMOUT is
an unexpected signal.
User does not use TCP2D=000H. If not, PWMOUT is an unexpected signal.
PWMC[00EH]: PWM control register [R/W], default value [-000]
Register
Bit Name
Read/Write
Bit3
Bit2
PWM2EN
R/W
Bit1
PWM1EN
R/W
Bit0
PWM0EN
R/W
-
-
PWM0EN: PWM0 output enable. (0: disable; 1: enable)
PWM1EN: PWM1 output enable. (0: disable; 1: enable)
PWM2EN: PWM2 output enable. (0: disable; 1: enable)
PWM0L[00FH]: PWM0 duty low nibble data register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
PWM0D3
R/W
Bit2
PWM0D2
R/W
Bit1
PWM0D1
R/W
Bit0
PWM0D0
R/W
PWM0D3~PWM0D0: PWM0 duty low nibble data.
PWM0M[010H]: PWM0 duty middle nibble data register [R/W], default value [xxxx]
Register
Bit3
Bit2
Bit1
Bit0
Bit Name
PWM0D7
PWM0D6
PWM0D5
PWM0D4
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Read/Write
R/W
R/W
R/W
R/W
PWM0D7~PWM0D4: PWM0 duty middle nibble data.
PWM0H[011H]: PWM0 duty high nibble data register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
PWM0D11 PWM0D10
R/W R/W
Bit2
Bit1
PWM0D9
R/W
Bit0
PWM0D8
R/W
PWM0D11~PWM0D8: PWM0 duty high nibble data.
PWM1L[22AH]: PWM1 duty low nibble data register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
PWM1D3
R/W
Bit2
PWM1D2
R/W
Bit1
PWM1D1
R/W
Bit0
PWM1D0
R/W
PWM1D3~PWM1D0: PWM1 duty low nibble data.
PWM1M[22BH]: PWM1 duty middle nibble data register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
PWM1D7
R/W
Bit2
PWM1D6
R/W
Bit1
PWM1D5
R/W
Bit0
PWM1D4
R/W
PWM1D7~PWM1D4: PWM1 duty middle nibble data.
PWM1H[22CH]: PWM1 duty high nibble data register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
PWM1D11 PWM1D10
R/W R/W
Bit2
Bit1
PWM1D9
R/W
Bit0
PWM1D8
R/W
PWM1D11~PWM1D8: PWM1 duty high nibble data.
PWM2L[22DH]: PWM2 duty low nibble data register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
PWM2D3
R/W
Bit2
PWM2D2
R/W
Bit1
PWM2D1
R/W
Bit0
PWM2D0
R/W
PWM2D3~PWM2D0: PWM2 duty low nibble data.
PWM2M[22EH]: PWM2 duty middle nibble data register [R/W], default value [xxxx]
Register
Bit3
Bit2
Bit1
Bit0
Bit Name
PWM2D7
PWM2D6
PWM2D5
PWM2D4
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Read/Write
R/W
R/W
R/W
R/W
PWM2D7~PWM2D4: PWM2 duty middle nibble data.
PWM2H[22FH]: PWM2 duty high nibble data register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
PWM2D11 PWM2D10
R/W R/W
Bit2
Bit1
PWM2D9
R/W
Bit0
PWM2D8
R/W
PWM2D11~PWM2D8: PWM2 duty high nibble data.
PW M xEN
Duty
PW M xO
TCP2CNT
CM P
PW M x
TCP2OV
12-bit duty
W R
PW M xL
4-bit duty L
8-bit duty M and H
TM P duty M and H
W R
PW M xH
and
PW M xM
Figure: PWM (TCP2)
PWMxD
PWM duty
Note
All off
0
1
(0 * clock cycle) / TCP2 timer’s period
(1 * clock cycle) / TCP2 timer’s period
(2 * clock cycle) / TCP2 timer’s period
……
2
……
n
((n) * clock cycle) / TCP2 timer’s period
……
……
TCP2D
((TCP2D) * clock cycle) / TCP2 timer’s period
All on
Note: 1. PWMxD can not bigger than TCP2D
2. TCP2 timer’s period = (TCP2D) * clock cycle.
3. PWM can start 0 or start 1 by mask option.
Table: PWM duty
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P-6: IIC Module
IIC is a 2-wire, bi-directional serial bus, which provides a simple, efficient
way for data exchange between devices. This two-wire bus minimizes the
interconnection between devices and eliminates the need for address
decoders.
IIC CONTROL
Every IIC device must have independent slave address. User can use
IICCON1<3:1> (ADR<2:0>) to select one independent slave address, the
map address reference follow table.
MODE
ADR2
ADR1
ADR0
IIC device address 7-bit
101 0000 (50H)
101 0001 (51H)
101 0010 (52H)
101 0011 (53H)
101 0100 (54H)
101 0101 (55H)
101 0110 (56H)
101 0111 (57H)
IIC device address 8-bit
1010 0001 (A1H)
1010 0011 (A3H)
1010 0101 (A5H)
1010 0111 (A7H)
1010 1001 (A9H)
1010 1011 (ABH)
1010 1101 (ADH)
1010 1111 (AFH)
Normal
mode
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MODE
ADR2
ADR1
ADR0
Fast read
mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table: IIC address mapping table
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Set IICCON1<0> (IICEN) can enable all IIC block, IICCON0<0> (IICMOD)
can select IIC operation in normal mode or fast read mode. The first byte of
data transfer immediately following the START signal is the slave address
transmitted by the master. This is a seven bit long calling address followed by
a R/W bit in Normal mode. Fast read mode only have transmit mode, so R/W
bit must be 1.
When START signal is detected, IICSTS<2> (MBB) is set. When STOP
signal is detected, MBB is cleared. IICSTS<3> (MAASF) is set, when IIC
device match the calling address. When MAASF is set, and INTF1<2> (IICF)
is also set. An interrupt is generated if the INTC1<2> (IICIE) be set. User can
check IICSTS<1> (SRWB) to know IIC device operate in transmit or receive
mode. When IICF is set, an interrupt is generated to the CPU. IICF is set when
one of the following event occurs:
1) IIC device address match in normal mode.
2) Completion of one byte of data transfer. It is set at the falling edge of
the 9th clock in normal mode.
3) Completion of IICRDAT(L/H)0 data transfer and IICRDAT(L/H)1 load
on IICDAT(L/H) in fast read mode.
When IIC device operate in transmit mode, master’s acknowledge store in
IICSTS<0> (TXACK). If detect acknowledge, this bit set, if not, this bit clear.
IICDAT(L/H) only use in normal mode. In transmit mode, data written into
the register to send to the bus automatically, with the most significant bit out
first. In receive mode, reading of this register initiates receiving of the next
byte data. IICRDAT(L/H)0 and IICRDAT(L/H)1 only use in fast mode. IIC
device transmit IICRDAT(L/H)0 first, completion of transfer, IICRDAT(L/H)1
continue transmit to bus automatically.
Whenever IICRDAT(L/H)0 transfer is complete, IICRDAT(L/H)1 will
automatically load transfer buffer, and generates an interrupt flag notify
updatable. If the data transfer will be more than two bytes, you can create a
data counter, interrupt flag is generated every time, data will be placed in
IICRDAT(L/H)0 and IICRDAT(L/H)1 by order by software, however, if the
master halfway want to re-read the beginning of the data, when the data
counter is not starting from scratch, data can not be read correctly, this
situation can be set STIE be 1, when receiving the START signal from IIC BUS,
an interrupt is generated, by receiving this start signal, the data counter is reset
by the software, so you can re-read the data correctly. STIF can only be actived
in fast read mode.
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INTC1[00CH]: Extended interrupt control register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
STIE
R/W
Bit2
IICIE
R/W
Bit1
INT1IE
R/W
Bit0
INT0IE
R/W
INT0IE: enable INT0 external interrupt. (0: disable; 1: enable)
INT1IE: enable INT1 external interrupt. (0: disable; 1: enable)
IICIE: enable IIC interrupt. (0: disable; 1: enable)
STIE: enable IIC start signal interrupt. (0: disable; 1: enable)
INTF1[00DH]: Extended interrupt request flag register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
STIF
R/W
Bit2
IICF
R/W
Bit1
INT1F
R/W
Bit0
INT0F
R/W
INT0F: INT0 external interrupt request flag. (0: inactive; 1: active)
INT1F: INT1 external interrupt request flag. (0: inactive; 1: active)
IICF: IIC interrupt request flag. (0: inactive; 1: active)
STIF: IIC start signal interrupt request flag. (0: inactive; 1: active)
IICCON0[221H]: IIC control register 0 [R/W], default value [---1]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
Bit0
IICMOD
R/W
-
-
-
-
-
-
IICMOD: IIC Operation mode. (0: normal; 1: fast read)
IICCON1[222H]: IIC control register 1 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
ADR2
R/W
Bit2
ADR1
R/W
Bit1
ADR0
R/W
Bit0
IICEN
R/W
IICEN: IIC function enable. (0: disable; 1: enable)
ADR2~ADR0: IIC slave address.
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IICSTS[223H]: IIC status register [R/W], default value [0001]
Register
Bit Name
Read/Write
Bit3
MAASF
R/W
Bit2
MBB
R
Bit1
Bit0
TXACK
R
SRWB
R
TXACK: receive master acknowledge. (0: master don’t send acknowledge;
1: master send acknowledge)
SRWB: IIC slave read or write select. (0: write data to slave; 1: read data
from slave)
MBB: IIC bus busy flag. (0: IIC bus idle; 1: IIC bus busy)
MAASF: IIC slave address match flag. (0: not match; 1: match(must clear
by software))
IICDATL[224H]: IIC data low nibble register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
DAT3
R/W
Bit2
DAT2
R/W
Bit1
DAT1
R/W
Bit0
DAT0
R/W
DAT3~DAT0: IIC low nibble data.
IICDATH[225H]: IIC data high nibble register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
DAT7
R/W
Bit2
DAT6
R/W
Bit1
DAT5
R/W
Bit0
DAT4
R/W
DAT7~DAT4: IIC high nibble data.
IICRDATL0[226H]: IIC fast read data low nibble register 0 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
RDAT03
R/W
Bit2
RDAT02
R/W
Bit1
RDAT01
R/W
Bit0
RDAT00
R/W
RDAT03~RDAT00: IIC fast read low nibble data 0.
IICRDATH0[227H]: IIC fast read data high nibble register 0 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
RDAT07
R/W
Bit2
RDAT06
R/W
Bit1
RDAT05
R/W
Bit0
RDAT04
R/W
RDAT07~RDAT04: IIC fast read high nibble data 0.
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TonTouchTM
IICRDATL1[228H]: IIC fast read data low nibble register 1 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
RDAT13
R/W
Bit2
RDAT12
R/W
Bit1
RDAT11
R/W
Bit0
RDAT10
R/W
RDAT13~RDAT10: IIC fast read low nibble data 1.
IICRDATH1[229H]: IIC fast read data high nibble register 1 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
RDAT17
R/W
Bit2
RDAT16
R/W
Bit1
RDAT15
R/W
Bit0
RDAT14
R/W
RDAT17~RDAT14: IIC fast read high nibble data 1.
.IIC operation
IIC support normal mode and fast read mode. Normal mode is
compatible to standard IIC bus. Fast read mode is support fast read data, for
reduce CPU wait time.
In normal mode, IIC device address match and completion of one byte of
data transfer, interrupt will occur. It is set at the falling edge of the 9th clock in
normal mode. if master read last data, master does not send acknowledge to
IIC device, it can let IIC device know don’t need to send data, and do dummy
write for release data bus to avoid bus error.
When an interrupt occurs, MCU must first determine the current mode
will be receive or transmit, and then determine whether the command mode
by MAASF flag. Due to the process by software, so before entering the
interrupt will pull low the SCL, to notify the Master waits. In receive mode
when reading IICDATL and the transfer mode when writing IICDATL, the SCL
pull low will be release. The timing as follow:
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Preliminary
1) Normal mode
Follow show a flowchart of IIC device program state machine in normal
mode.
IIC INITIAL
CLEAR IICF
SET IICIE=1
SET IICMOD=0
SET ADR[0..2]
SET IICEN=1
RTS
INT
PROGRAM
NO
Check
IICF=1
YE
S
Clear IICF
NO (RX)
Check
YES (TX)
SRWB=1
YES
(first INT)
YES
(first INT)
Check
Check
MAASF=1
MAASF=1
Clear
MAASF
Clear
MAASF
NO
NO
NO
(last data)
Read
IICDATH
Check
TXACK=1
Read
IICDATL
(dummy
read release
SCL)
Write IICDATL
(dummy write
release SCL)
Write
IICDATH
YES
Read
IICDATL
(release
SCL)
Write
IICDATH
Write
IICDATL
(release
SCL)
Write
IICDATL
(release
SCL)
RTI
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Preliminary
2) Fast read mode
Master read data fast in fast read mode, to reduce CPU process time.
Follow shows a flowchart of IIC device program state machine in fast read
mode. When master read the first data, IIC device automatically load next
data to the sent buffer and generates an interrupt allows users to update
new IICRDAT(L/H)0 and IICRDAT(L/H)1 data.
1. For two byte data:
IIC INITIAL
SET IICMOD=1
NEW DATA
SET ADR[0..2]
UPDTAE
WRITE
IICRDAT(L/H)0
and
NO
CHECK
MBB=0
IICRDAT(L/H)1
YES
WRITE
IICRDAT(L/H)0~1
(TWO BYTE NEW
DATA)
SET IICEN=1
RTS
RTS
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2. For more than two byte data:
IIC INITIAL
INT PROGRAM
CLEAR IICF
CLEAR STIF
NO
CHECK
STIF=1
YES
NO
SET IICIE=1
SET STIE=1
CHECK IICF=1
CLEAR STIF
YES
SET IICMOD=1
CLEAR IICF
SET DATACNT=0
WRITE FIRST
TWO BYTE DATA
TO
DATACNT+1
SET ADR[0..2]
IICRDAT(L/H)0~1
YES
LAST DATA?
SET DATACNT=0
NO
WRITE FIRST
TWO BYTE DATA
TO
SET DATACNT=0
WRITE NEXT
TWO BYTE DATA
TO
IICRDAT(L/H)0 ~1
IICRDAT(L/H)0~1
WRITE FIRST
TWO BYTE DATA
TO
IICRDAT(L/H)0~1
SET IICEN=1
RTS
RTI
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Preliminary
. IO Pad Cell Structure and Function Description
.. IO port with touch pad input
The input/output port has the IO control register for switching input or
output mode and data register stores the output data in output mode. If IO
control register=1 and output data=1, the IO port is programmed as input
with pull-up resistor and also actives the wake-up function. User intends to
read the port data with differed read instruction. The read PxI is reading data
comes from IO pad data. The data register reading result will have the same
value with output register data. Software can performs a configuration
(output data register=0, changing the IO control register 0 or 1) for open
drain type that specifies suitable for key scan application. An additional
feature supports the touch pad input.
Extern input
IO control data Output data
Pull-up
R
Wake-up
feature
No
Disable
Disable
0
1
1
X
X
0
1
X
No
No
No
Disable
Enable
No
Enable
No
Enable and touch
pad scan
X: don’t care the value
IO control data
IO pad
0
1
Output register data
IO pad input data
Read PxI
1
Read input data
IO pad data
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Preliminary
Pull-up
R
S
Data Bus
P
D
Q
IO control
TPEN & touch pad scan
CK QB
Register Write
PR
Read PxC
S
P
D
Q
TPEN & touch pad scan
Data Register
Write
CK QB
N
IO pad
TPEN & touch pad scan
Read PxI
0
1
M
U
X
Wake-up
Read PxI
or Px
N
N
Analog
switch
touch pad
TPEN & touch pad scan
Figure IO-A: Standard IO port with touch pad input
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Preliminary
.. IO port with internal PWM output
The standard input/output port has the IO control register for switching
input or output mode and data register stores the output data in output mode.
If IO control data=1 and output data=1, the IO port is programmed as input
with pull-up resistor and also actives the wake-up function. User intends to read
the port data with differed read instruction. The read PxI is reading data comes
from IO pad data. The data register reading result will have the same value
with output register data. If enable internal output, the IO port must set as
output (IO control data=0). An additional feature supports the internal PWM
output.
IO control data
Output data
Pull-up
R
Wake-up
feature
No
0
X
0
1
No
1
No
No
1
Enable
Enable
X: don’t care the value
IO control data
Internal output
Enable
IO pad
0
0
1
Output internal data
Output register data
IO pad input data
Disable
X
X: don’t care the value
Read PxI
1
Read input data
IO pad data
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Ver: 1.1
TTP259
TonTouchTM
Preliminary
S
Pull-up
Data Bus
R
D
Q
R
IO control
CK QB
Register Write
PR
Read PxC
S
P
D
Q
Data Register
Write
CK QB
N
IO pad
Read PxI
0
1
M
U
X
Read PxI
or Px
Wake-up
N
N
Internal output signal
(PWM)
0
1
MUX
Output enable
(PWMEN)
Figure IO-B: Standard IO port with internal PWM output
2015/05/25
Page 52 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
.. IO port with internal PWM output and external TCP1
clock input
The standard input/output port has the IO control register for switching
input or output mode and data register stores the output data in output mode.
If IO control data=1 and output data=1, the IO port is programmed as input
with pull-up resistor and also actives the wake-up function. User intends to read
the port data with differed read instruction. The read PxI is reading data comes
from IO pad data. The data register reading result will have the same value
with output register data. If enable internal output, the IO port must set as
output (IO control data=0). An additional feature supports the internal PWM
output and external TCP1 clock input.
IO control data
Output data
Pull-up
R
Wake-up
feature
No
External
input
0
X
0
1
No
No
1
No
No
Enable
Enable
1
Enable
Enable
X: don’t care the value
IO control data
Internal output
Enable
IO pad
0
0
1
Output internal data
Output register data
IO pad input data
Disable
X
X: don’t care the value
Read PxI
1
Read input data
IO pad data
2015/05/25
Page 53 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
S
Pull-up
Data Bus
D
Q
R
R
IO control
CK QB
Register Write
PR
Read PxC
S
P
D
Q
Data Register
Write
CK QB
N
IO pad
Read PxI
0
1
M
U
X
Read PxI
or Px
Wake-up
N
N
TCP1 clock input
(TCP1I)
Internal output signal
(PWM)
0
1
MUX
Output enable
(PWMEN)
Figure IO-C: Standard IO port with internal PWM output and external
TCP1 clock input
2015/05/25
Page 54 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
.. IO port with internal PWM output and external
interrupt trigger input
The standard input/output port has the IO control register for switching
input or output mode and data register stores the output data in output mode.
If IO control data=1 and output data=1, the IO port is programmed as input
with pull-up resistor and also actives the wake-up function. User intends to read
the port data with differed read instruction. The read PxI is reading data comes
from IO pad data. The data register reading result will have the same value
with output register data. If enable internal output, the IO port must set as
output (IO control data=0). An additional feature supports the internal PWM
output and external interrupt trigger input.
IO control data
Output data
Pull-up
R
Wake-up
feature
No
External
input
0
X
0
1
No
No
1
No
No
Enable
Enable
1
Enable
Enable
X: don’t care the value
IO control data
Internal output
Enable
IO pad
0
0
1
Output internal data
Output register data
IO pad input data
Disable
X
X: don’t care the value
Read PxI
1
Read input data
IO pad data
2015/05/25
Page 55 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
S
Pull-up
Data Bus
R
D
Q
R
IO control
CK QB
Register Write
PR
Read PxC
S
P
D
Q
Data Register
Write
CK QB
N
IO pad
Read PxI
0
1
M
U
X
Read PxI
or Px
Wake-up
N
N
External interrupt trigger
Internal output signal
(PWM)
0
1
MUX
Output enable
(PWMEN)
Figure IO-D: Standard IO port with internal PWM output and
external interrupt trigger input
2015/05/25
Page 56 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
.. IO port with internal PWM output and external
interrupt trigger input and IIC
The standard input/output port has the IO control register for
switching input or output mode and data register stores the output data in
output mode. If IO control data=1 and output data=1, the IO port is
programmed as input with pull-up resistor and also actives the wake-up
function. User intends to read the port data with differed read instruction.
The read PxI is reading data comes from IO pad data. The data register
reading result will have the same value with output register data. If enable
internal output, the IO port must set as output (IO control data=0). An
additional feature supports the internal PWM output and external interrupt
trigger input and IIC.
IO control data
Output data
Pull-up
R
Wake-up
feature
No
External
input
0
X
0
1
No
No
1
No
No
Enable
Enable
1
Enable
Enable
X: don’t care the value
IO control data
Internal output
Enable
IO pad
0
0
1
Output internal data
Output register data
IO pad input data
Disable
X
X: don’t care the value
Read PxI
1
Read input data
IO pad data
2015/05/25
Page 57 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
Pull-up
S
R
Data Bus
R
D
Q
IO control
CK QB
Register Write
IICEN
PR
IICEN
Read PxC
S
P
D
Q
Data Register
Write
IICEN
CK QB
0
N
MUX
IO pad
1
IIC control data
Read PxI
0
1
M
U
X
Read PxI
or Px
Wake-up
N
N
External interrupt trigger
Internal output signal
(PWM)
0
1
MUX
Output enable
(PWMEN)
Figure IO-E: Standard IO port with internal PWM output and
external interrupt trigger input and IIC
2015/05/25
Page 58 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
.. IO port with internal PWM output and IIC
The standard input/output port has the IO control register for
switching input or output mode and data register stores the output data in
output mode. If IO control data=1 and output data=1, the IO port is
programmed as input with pull-up resistor and also actives the wake-up
function. User intends to read the port data with differed read instruction.
The read PxI is reading data comes from IO pad data. The data register
reading result will have the same value with output register data. If enable
internal output, the IO port must set as output (IO control data=0). An
additional feature supports the internal PWM output and IIC.
IO control data
Output data
Pull-up
R
Wake-up
feature
No
0
X
0
1
No
1
No
No
1
Enable
Enable
X: don’t care the value
IO control data
Internal output
Enable
IO pad
0
0
1
Output internal data
Output register data
IO pad input data
Disable
X
X: don’t care the value
Read PxI
1
Read input data
IO pad data
2015/05/25
Page 59 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
Pull-up
S
R
Data Bus
R
D
Q
IO control
Register Write
PR
CK QB
IICEN
IICEN
Read PxC
S
P
D
Q
Data Register
Write
IICEN
CK QB
0
N
MUX
IO pad
1
IIC control data
Read PxI
0
1
M
U
X
Read PxI
or Px
Wake-up
N
N
Internal output signal
(PWM)
0
1
MUX
Output enable
(PWMEN)
Figure IO-F: Standard IO port with internal PWM output and IIC
2015/05/25
Page 60 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
.. IO port with internal PWM output and external
interrupt trigger input
The standard input/output port has the IO control register for
switching input or output mode and data register stores the output data in
output mode. If IO control data=1 and output data=1, the IO port is
programmed as input with pull-up resistor and also actives the wake-up
function. User intends to read the port data with differed read instruction.
The read PxI is reading data comes from IO pad data. The data register
reading result will have the same value with output register data. If enable
internal output, the IO port must set as output (IO control data=0). An
additional feature supports the internal PWM output and external interrupt
trigger input.
IO control data
Output data
Pull-up
R
Wake-up
feature
No
External
input
0
X
0
1
No
No
1
No
No
Enable
Enable
1
Enable
Enable
X: don’t care the value
IO control data
Internal output
Enable
IO pad
0
0
1
Output internal data
Output register data
IO pad input data
Disable
X
X: don’t care the value
Read PxI
1
Read input data
IO pad data
2015/05/25
Page 61 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
S
Pull-up
Data Bus
R
D
Q
R
IO control
CK QB
Register Write
PR
Read PxC
S
P
D
Q
Data Register
Write
CK QB
N
IO pad
Read PxI
0
M
U
X
Read PxI
or Px
1
Wake-up
N
N
External interrupt trigger
0
1
MUX
Internal output signal
(PWM)
0
1
MUX
INTTS
Output enable
(PWMEN)
VBGAP
Figure IO-G: Standard IO port with internal PWM output and
external interrupt trigger input
2015/05/25
Page 62 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
.. IO port with external interrupt trigger input
The standard input/output port has the IO control register for
switching input or output mode and data register stores the output data in
output mode. If IO control data=1 and output data=1, the IO port is
programmed as input with pull-up resistor and also actives the wake-up
function. User intends to read the port data with differed read instruction.
The read PxI is reading data comes from IO pad data. The data register
reading result will have the same value with output register data. If enable
internal output, the IO port must set as output (IO control data=0). An
additional feature supports the external interrupt trigger input.
IO control data
Output data
Pull-up
R
Wake-up
feature
No
External
input
0
X
0
1
No
No
1
No
No
Enable
Enable
1
Enable
Enable
X: don’t care the value
IO control data
IO pad
0
1
Output internal data
IO pad input data
Read PxI
1
Read input data
IO pad data
2015/05/25
Page 63 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
S
Pull-up
Data Bus
IO ctrl
R
D
Q
R
CK QB
Register Write
PR
Read PxC
S
P
D
Q
Data Register
Write
CK QB
N
IO pad
Read PxI
M
U
X
0
1
Read PxI
or Px
Wake-up
N
N
External interrupt trigger
0
1
MUX
INTTS
VBGAP
Figure IO-H: Standard IO port with external interrupt trigger
input
2015/05/25
Page 64 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
3. IO Pad Cells
The main features of IO pad cell are including ESD/EFT protection and
general IO access. A general IO pad cell can be configured as input with or
without pull-up resistor, or working as a CMOS or NMOS output driver. The
input pad cell must have pull-up resistor for avoiding a floating state when
user doesn’t care or not be used. For concerning the standby current, user can
use data register or IO control register to fit the application.
. IO File Register
PAC[012H]: Port A IO control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
PAC2
R/W
Bit1
PAC1
R/W
Bit0
PAC0
R/W
-
-
PAC2~PAC0: Port A IO control data.
PA[013H]: Port A output data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
PA2
R/W
Bit1
PA1
R/W
Bit0
PA0
R/W
-
-
PA2~PA0: Port A output data.
PBC[014H]: Port B IO control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PBC3
R/W
Bit2
PBC2
R/W
Bit1
PBC1
R/W
Bit0
PBC0
R/W
PBC3~PBC0: Port B IO control data.
PB[015H]: Port B output data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PB3
R/W
Bit2
PB2
R/W
Bit1
PB1
R/W
Bit0
PB0
R/W
PB3~PB0: Port B output data.
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Preliminary
PCC[016H]: Port C IO control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PCC3
R/W
Bit2
PCC2
R/W
Bit1
PCC1
R/W
Bit0
PCC0
R/W
PCC3~PCC0: Port C IO control data.
PC[017H]: Port C output data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PC3
Bit2
PC2
Bit1
PC1
Bit0
PC0
R/W
R/W
R/W
R/W
PC3~PC0: Port C output data.
PDC[018H]: Port D IO control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PDC3
R/W
Bit2
PDC2
R/W
Bit1
PDC1
R/W
Bit0
PDC0
R/W
PDC3~PDC0: Port D IO control data.
PD[019H]: Port D output data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PD3
R/W
Bit2
PD2
R/W
Bit1
PD1
R/W
Bit0
PD0
R/W
PD3~PD0: Port D output data.
PEC[01AH]: Port E IO control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PEC3
R/W
Bit2
PEC2
R/W
Bit1
PEC1
R/W
Bit0
PEC0
R/W
PEC3~PEC0: Port E IO control data.
PE[01BH]: Port E output data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PE3
Bit2
PE2
Bit1
PE1
Bit0
PE0
R/W
R/W
R/W
R/W
PE3~PE0: Port E output data.
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Preliminary
TonTouchTM
PFC[01CH]: Port F IO control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PFC3
R/W
Bit2
PFC2
R/W
Bit1
PFC1
R/W
Bit0
PFC0
R/W
PFC3~PFC0: Port F IO control data.
PF[01DH]: Port F output data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PF3
R/W
Bit2
PF2
R/W
Bit1
PF1
R/W
Bit0
PF0
R/W
PF3~PF0: Port F output data.
PAI[207H]: Port A pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
Bit2
PAI2
R
Bit1
PAI1
R
Bit0
PAI0
R
-
-
PAI3~PAI0: Port A pad data.
PBI[208H]: Port B pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
PBI3
R
Bit2
PBI2
R
Bit1
PBI1
R
Bit0
PBI0
R
PBI3~PBI0: Port B pad data.
PCI[209H]: Port C pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
PCI3
R
Bit2
PCI2
R
Bit1
PCI1
R
Bit0
PCI0
R
PCI3~PCI0: Port C pad data.
PDI[20AH]: Port D pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
PDI3
R
Bit2
PDI2
R
Bit1
PDI1
R
Bit0
PDI0
R
PDI3~PDI0: Port D pad data.
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Preliminary
PEI[20BH]: Port E pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
PEI3
R
Bit2
PEI2
R
Bit1
PEI1
R
Bit0
PEI0
R
PEI3~PEI0: Port E pad data.
PFI[20CH]: Port F pad data reading address [R], default value [----]
Register
Bit Name
Read/Write
Bit3
PFI3
R
Bit2
PFI2
R
Bit1
PFI1
R
Bit0
PFI0
R
PFI3~PFI0: Port F pad data.
. IO Port’s Special function
When SpecIO is selected by mask option, PA0, PB0 and PB1 is special IO
function. It can output ODATA register to user. ODATA can be store Key touch
information by software. User set PA0 for input, PB0,PB1 for output. User can
use this function to get Key touch information.
When using special IO function, do not use IIC function. If not, PB0,PB1
are unexpected signal.
ODATA[21FH]: Touch pad output register for special function [R/W], default value [0000]
Register
Bit3
ODATA3
R/W
Bit2
ODATA2
R/W
Bit1
ODATA1
R/W
Bit0
ODATA0
R/W
Bit Name
Read/Write
ODATA3~ODATA0: Touch pad information.
PA0 (input)
PB0 (output)
ODATA0
PB1(output)
1
0
ODATA1
ODATA3
ODATA2
2015/05/25
Page 68 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
16 non-contact inputs touch pad detector
The touch pad detector applies the charge sharing conception. The
inputs share the pad with IO ports. Built-in charge sharing control, duty
detector and de-bounce feature can response the input with varied output
refresh rate that dependant on the system request. For power saving
concern, auto power off function and wake up de-bounce capability can
support a lower average operating current.
OSCH/
OSCL
Modulation
clock selector
Data Bus
CS
Edge
Clock
CH0
Detector
Gating
CH1
:
12-bit Duty counter &
Reload data latch
TPCTF
:
:
:
Touch pad scan & Timing control
TPCMPF
CH14
CH15
Touch pad selector
Figure: 16 pads Touch pad detector
2015/05/25
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Ver: 1.1
TTP259
TonTouchTM
Preliminary
Parameters
Target value
Remark
4MHz or 16KHz
OSCH/N or OSCL
12-bit
Touch pad OSC
Modulation clock
Duty counter
Reload data latch
Touch pads
Using OSCH or OSCL
N=1,2,4,8,16,32,64
With INT
12-bit
Write only
1~16 pads
-
Key de-bounce time s/w implements
By application or cover thickness
Resolution=1 modulation clock
Sensitivity level
Offset value by s/w
The flowchart as follow:
TOUCH
PROGRAM
SET MCKS
WRITE FFFH TO
TPCT0~2
FOR
TPCT0~2=000H
SET TPCHS3~0
WHEN SET
TPCHS0 WILL
START SCAN
AND CLEAR
TPCTF, TPCMPF
TPCTL=3
CHARGE TIME
(ABOUT 100uS)
SET TPCTL=1
START SCAN
NO
CHECK
TPCTF=1
YES
NO
CHECK
TPCMPF=1
COUNT
OVERFLOW
ERROR
YES
SAVE TPCT0~2
THEN TPCTL=0
RTS
2015/05/25
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Ver: 1.1
TTP259
TonTouchTM
Preliminary
TPINTC[01EH]: Touch pad interrupt control register [R/W], default value [0000]
TPINTC
Bit Name
Read/Write
Bit3
TPCTIE
R/W
Bit2
TPCMPIE
R/W
Bit1
Bit0
-
-
-
-
TPCMPIE: Capacitor overcharge interrupt enable. (0: disable; 1: enable)
TPCTIE: Duty counter overflow interrupt enable. (0: disable; 1: enable)
TPINTF[01FH]: Touch pad request flag register [R/W], default value [0000]
TPINTF
Bit3
TPCTF
R/W
Bit2
TPCMF
R/W
Bit1
Bit0
Bit Name
-
-
-
-
Read/Write
TPCMPF: Capacitor overcharge flag. (0: inactive; 1: active)
TPCTF: Duty counter overflow flag. (0: inactive; 1: active)
TPCT0[215H]: Touch pad duty counter and latch data register 0 [R], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
TPCT3/CT3 TPCT2/CT2 TPCT1/CT1 TPCT0/CT0
R/W R/W R/W R/W
Bit2
Bit1
Bit0
TPCT3~TPCT0: Duty counter 1st nibble data for counter read.
CT3~CT0: 1st nibble of reload latch data.
TPCT1[216H]: Touch pad duty counter and latch data register 1 [R], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
TPCT7/CT7 TPCT6/CT6 TPCT5/CT5 TPCT4/CT4
R/W R/W R/W R/W
Bit2
Bit1
Bit0
TPCT7~TPCT4: Duty counter 2nd nibble data for counter read.
CT7~CT4: 2nd nibble of reload latch data.
TPCT2[217H]: Touch pad duty counter and latch data register 2 [R], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
TPCT11/CT11 TPCT10/CT10 TPCT9/CT9 TPCT8/CT8
R/W R/W R/W R/W
Bit2
Bit1
Bit0
TPCT11~TPCT8: Duty counter 3rd nibble data for counter read.
CT11~CT8: 3rd nibble of reload latch data.
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Ver: 1.1
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Preliminary
Duty counter value= TPCT2*256 +TPCT1*16+TPCT0
When user writes data to the TPCT2~TPCT0, the data just keep in
TPCT2~TPCT0 latch register. When TPCHS0 is writing, the TPCT2~TPCT0 latch
register’s complement value will load into TPCT2~TPCT0 duty counter as initial
value and start the scan function.
The duty counter will be enabled by writing the TPCHS0 register and will
set the TPCTF flag if duty counter overflow. As writing the TPCHS0 register will
reload the 12-bit duty counter and clear the TPCTF and TPCMPF.
MCKS[21AH]: Modulation clock selector register [R/W], default value [0111]
Register
Bit Name
Read/Write
Bit3
Bit2
MCKS2
R/W
Bit1
MCKS1
R/W
Bit0
MCKS0
R/W
-
-
MCKS2~MCKS0: Modulation clock selector.
MCKS2~MCKS0
Sample time MCKS2~MCKS0 Sample time
000
001
010
011
OSCH/1
OSCH/2
OSCH/4
OSCH/8
100
101
110
111
OSCH/16
OSCH/32
OSCH/64
OSCL
The TPCMPF will be set as no modulation clock going into duty counter
with de-bounce feature and will also call the interrupt as TPCMPIE=1.
TPCHS0[210H]: Touch pad channel selector register0 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TPEN3
R/W
Bit2
TPEN2
R/W
Bit1
TPEN1
R/W
Bit0
TPEN0
R/W
TPEN3~TPEN0: Touch pad channel selector 1st nibble.
TPCHS1[211H]: Touch pad channel selector register1 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
TPEN7
R/W
Bit2
TPEN6
R/W
Bit1
TPEN5
R/W
Bit0
TPEN4
R/W
TPEN7~TPEN4: Touch pad channel selector 2nd nibble.
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Preliminary
TPCHS2[212H]: Touch pad channel selector register2 [R/W], default value [0000]
Register
Bit3
Bit2
Bit1
Bit0
Bit Name
TPEN11
R/W
TPEN10
R/W
TPEN9
R/W
TPEN8
R/W
Read/Write
TPEN11~TPEN8: Touch pad channel selector 3rd nibble.
TPCHS3[213H]: Touch pad channel selector register3 [R/W], default value [0000]
Register
Bit3
Bit2
Bit1
Bit0
Bit Name
TPEN15
R/W
TPEN14
R/W
TPEN13
R/W
TPEN12
R/W
Read/Write
TPEN15~TPEN12: Touch pad channel selector 4th nibble.
As program writes the TPCHS0 register, hardware automatically discharges
the external capacitor and enable the sensor clock input until period end.
Channel
Enable
State
TP0
TPCHS0
TPEN3~
TPEN0
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
TPCHS1
TPEN7~
TPEN4
0000
0000
0000
0000
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
TPCHS2
TPCHS3
TPEN11~ TPEN15~
TPEN8
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
0000
0000
0000
0000
TPEN12
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0100
1000
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
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TTP259
TonTouchTM
Preliminary
When TPCHS0 is writing, TPCTL will be set TP RUN mode, and begin to
scan the channel by TPCHS3~TPCHS0 select.
Users can enable multi-channel by setting corresponding bit 1, that will
turn on all enable channel at the same time.
TPCTL[214H]: Touch pad control register [R/W], default value [-000]
Register
Bit Name
Read/Write
Bit3
Bit2
TPCTL2
R/W
Bit1
TPCTL1
R/W
Bit0
TPCTL0
R/W
-
-
TPCTL2~TPCTL0: Touch pad control selector.
As program writes the TPCTL register, hardware automatically charges the
external capacitor and reload TPCTx and enable the sensor clock input until
period end.
TPCTL2~TPCTL0
Channel Enable State
000
001
010
011
100
101
110
111
TP STOP
TP RUN
-
Charge
Inner pad
-
-
-
TP STOP: STOP the touch pad feature and release pad for IO port.
TP RUN: TP RUN is touch pad scan start signal, it’s scan the channel by
TPCHS3~TPCHS0 select.
Charge: Charge can hold touch pad in charge state, to avoid charge time
too short.
Inner pad: Select switch select Inner pad. Inner pad is reference pad, this
pad is no bounding to package.
When user writes data to the TPCT2~TPCT0, the data just keep in
TPCT2~TPCT0 latch register. When writing the TPCTL register (exclude select
TP STOP), the TPCT2~TPCT0 latch register’s complement value will load into
2015/05/25
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Ver: 1.1
TTP259
Preliminary
TonTouchTM
TPCT2~TPCT0 duty counter as initial value and start the scan function.
As writing the TPCTL register (exclude select TP STOP) will reload the
12-bit duty counter and clear the TPCTF and TPCMPF.
As touch pad analog switch keeps on, the relative IO port is disabled as
tri-state by hardware.
CSAL[218H]: Select Capacity load low nibble register [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
CSA3
R/W
Bit2
CSA2
R/W
Bit1
CSA1
R/W
Bit0
CSA0
R/W
CSA3~CSA0: Select Capacity load low nibble data for touch pad.
CSAH[219H]: Select Capacity load high nibble register [R/W], default value [--00]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
CSA5
R/W
Bit0
CSA4
R/W
-
-
-
-
CSA5~CSA4: Select Capacity load high nibble data for touch pad.
CSA5~CSA0
00 0000
00 0001
……
Extra capacity load
0 * C array unit
1 * C array unit
……
11 1110
11 1111
62 * C array unit
63 * C array unit
Note: C array unit = 0.25pf
2015/05/25
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Ver: 1.1
TTP259
TonTouchTM
Preliminary
§ Mask Option Table:
All the OTP mask option register can open for user to reset the initial value,
but should enable the MRO. User writes MRO address first then changes the
target mask option register data. The MRO enable will be cleared with other
writing address. Bit 3 of MOP0 must always set to 1.
MOP0: LVR voltage select option register [R/W], default value [1-0-]
Mask option
Bit Name
Bit3
1
Bit2
Bit1
LVRVS
R/W
Bit0
-
-
-
-
Read/Write
R/W
MOP1: PWM start level option register [R/W], default value [-000]
Mask option
Bit Name
Bit3
Bit2
PWM2S
R/W
Bit1
PWM1S
R/W
Bit0
PWM0S
R/W
-
-
Read/Write
MOP2: INT trigger option register [R/W], default value [0000]
Mask option
Bit Name
Bit3
INT1S1
R/W
Bit2
INT1S0
R/W
Bit1
INT0S1
R/W
Bit0
INT0S0
R/W
Read/Write
MOP3: Function pin select 1st option register [R/W], default value [0000]
Mask option
Bit Name
Bit3
PWM1PS
R/W
Bit2
PWM0PS
R/W
Bit1
INT1PS
R/W
Bit0
INT0PS
R/W
Read/Write
MOP4: Function select option register [R/W], default value [0--0]
Mask option
Bit Name
Bit3
LVREN
R/W
Bit2
Bit1
Bit0
LDOVS
R/W
-
-
-
-
Read/Write
MOP5: Function pin select 2nd option register [R/W], default value [000-]
Mask option
Bit Name
Bit3
Bit2
Bit1
SpecIO
R/W
Bit0
PWM2PS1 PWM2PS0
-
-
Read/Write
R/W
R/W
2015/05/25
Page 76 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
The following table shows the mask option in this chip. All the mask options must be
defined clearly and ensure to meet user’s proper function.
No.
Mask Option
Function Descriptions
+1 LVR output Voltage select
0
1
2.2V
3.0V
+1 PWM0S
0
Start 0(active high)
Start 1(active low)
Start 0(active high)
Start 1(active low)
Start 0(active high)
Start 1(active low)
Low level trigger
Falling edge trigger
Rising edge trigger
Dual edge trigger
Low level trigger
Falling edge trigger
Rising edge trigger
Dual edge trigger
INT0 select PB3
1
+1 PWM1S
0
1
+1 PWM2S
0
1
+2 INT0F trigger type
INT0S1,INT0S0
00
01
10
11
00
01
10
11
0
+2 INT1F trigger type
INT1S1,INT1S0
+1 INT0 function pin select
+1 INT1 function pin select
+1 PWM0 function pin select
+1 PWM1 function pin select
+1 LDO output Voltage select
+1 LVREN select
1
INT0 select PA0
0
INT1 select PB2
1
INT1 select PB0
0
PWM0 select PA2
PWM0 select PB0
PWM1 select PA1
PWM1 select PB1
2.7V
1
0
1
0
1
4.2V
0
LVREN disable
1
LVREN enable
+1 SpecIO
0
PA0,PB0,PB1 is normal IO port
PA0,PB0,PB1 is special function
1
2015/05/25
Page 77 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
+2 PWM2 function pin select
00
01
10
11
PA0
PA0
PB2
Both PA0 and PB2
§ Application Circuit
2015/05/25
Page 78 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
§ Package and Pad Information:
z
SSOP 28
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Page 79 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
z
TSSOP 20
z
SOP 16
2015/05/25
Page 80 of 81
Ver: 1.1
TTP259
TonTouchTM
Preliminary
§ Ordering Form:
Package type
TTP259-ASFN
TTP259-DTDN
TTP259 -EOBN
SSOP28-A
TSSOP20-B
SOP16-B
Modified Record:
Body:
2015/05/08:
¾ 1st version
2015/05/25:
¾ Modify package type TSSOP20-B and SOP16-B
2015/05/25
Page 81 of 81
Ver: 1.1
相关型号：
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