TC94A48FG_技术文档

TC94A48FG

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC94A48FG

Single-chip Audio Digital Signal Processor

The TC94A48FG is a single-chip audio Digital Signal

Processor, incorporating two channels AD converter and

six channels DA converter.

It can realize many applications, including sound field

control, such as hall simulation, digital filters, such as

equalizers, surround sound, base boost and more.

Features

P-LQFP64-1010-0.50E

Weight: 0.4 g (typ.)

•

Incorporates a 1-bit Σ-∆ AD converter (2 channels).

THD+N: -78 dB (typ.), S/N ratio: 92 dB (typ.)

Incorporates a multi-bit Σ-∆ DA converter (6 channels).

THD+N: -88 dB (typ.), S/N ratio: 98 dB (typ.)

Digital input/output ports

Four input ports (8 channels)

Four output ports (8 channels)

•

The DSP block specifications are as follows:

Data bus

: 24 bits

Multiplier/adder

Accumulator

Program ROM

Program RAM

XRAM

: 24 bits × 24 bits + 51 bits → 51 bits

: 51 bits (sign extension: 4 bits)

: 3072 words × 16 bits

: 1024 words × 16 bits

: 4096 words × 24 bits

: 1024 words × 24 bits

YRAM

CROM

•

The microcontroller interface can be selected between serial mode and I²C bus mode.

Operating supply voltage: 3.3 V (some pins accept 5 V)

CMOS silicon structure supports high speed.

The package is a 64-pin LQFP (0.5-mm pitch) package.

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TC94A48FG

Block Diagram

11.2896MHz(256fs)

PLLC

/RST

Microcontroller

interface

General-

perpose port

ＰＬＬ

Timing

BTMD

LRCKI0

LRCKI1

BCKI0

BCKI1

SDI0

SDO0

SDO1

SDO2

SDO3

ＳＯ

(8ch)

ＳＩ

(8ch)

SDI1

16bit Instruction

DSP

SDI2

SDI3

ＤＡＣ

１ｃｈ

ΣΔ

DAO1

DAO2

ＤＡＣ

２ｃｈ

ＡＤＣ

Ｌｃｈ

(4fs rate

×6ch)

(4fs rate

×2ch)

LIN

ADVL

ADVR

ＤＡＣ

３ｃｈ

DAO3

VRI

REG Buffer

(64w×21b)

VREF

ＤＡＣ

４ｃｈ

ΣΔ

DAO4

DAO5

DAO6

(4fs rate

×2ch)

(4fs rate

×6ch)

ＤＡＣ

５ｃｈ

ＡＤＣ

Ｒｃｈ

RIN

ＤＡＣ

６ｃｈ

Pin Layout

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

BTMD

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

LRCKO

SDO0

SDO1

SDO2

SDO3

BCKI0

BCKI1

LRCKI0

LRCKI1

SDI0

MIMD

/RST

VDD

GND

TEST1

TEST0

GNDL

LIN

TC94A48FG

ADVL

VDDA

ADVR

RIN

SDI1

SDI2

SDI3

GNDR

GNDX

XI

GND

VDD

VDD6

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

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TC94A48FG

Pin Function

Symbol

XO

I/O

Function

Remarks

No.

1

O

－

O

Crystal oscillator connecting or clock output pin

Power pin for oscillator circuit

Analog power pin for DAC1

DAC1 signal output pin

2

3

V

DDX

V

DD1

4

DAO1

5

GND12

DAO2

－

O

－

O

－

I

Analog ground pin for DAC1/2

DAC2 signal output pin

6

7

V

DD23

Analog power pin for DAC2/3

DAC3 signal output pin

8

DAO3

GND3

VRI

9

Analog power pin for DAC3

Reference voltage pin for DAC

Analog ground pin for DAC4

DAC4 signal output pin

10

11

12

13

14

15

16

17

18

19

GND4

DAO4

－

O

－

O

－

O

V

DD45

Analog power pin for DAC4/5

DAC5 signal output pin

DAO5

GND56

DAO6

Analog ground pin for DAC5/6

DAC6 signal output pin

V

DD6

－

Analog power pin for DAC6

Digital power pin

V

DD

GND

SDI3

－

Digital ground pin

Audio serial data input pin 3

Schmitt input

20

21

22

23

24

25

26

27

28

29

30

31

32

33

I

It connects to GND or V

pins when if it is unused this pin.

5V tolerant

Schmitt input

5V tolerant

Schmitt input

5V tolerant

Schmitt input

5V tolerant

Schmitt input

5V tolerant

Schmitt input

5V tolerant

Schmitt input

5V tolerant

Schmitt input

5V tolerant

DD

Audio serial data input pin 2

It connects to GND or V

SDI2

SDI1

I

DD

Audio serial data input pin 1

It connects to GND or V

DD

Audio serial data input pin 0

SDI0

I

It connects to GND or V

LR clock input pin 1

DD

LRCKI1

LRCKI0

BCKI1

BCKI0

SDO3

SDO2

SDO1

SDO0

LRCKO

BCKO

I

It connects to GND or V

LR clock input pin 0

I

It connects to GND or V

Bit clock input pin 1

I

It connects to GND or V

Bit clock input pin 0

I

It connects to GND or V

Audio serial data output pin 3

It leaves to open when if it is unused.

Audio serial data output pin 2

It leaves to open when if it is unused.

Audio serial data output pin 1

It leaves to open when if it is unused.

Audio serial data output pin 0

It leaves to open when if it is unused.

LR clock output pin

O

Push-pull output

It leaves to open when if it is unused.

Bit clock output pin

It leaves to open when if it is unused.

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2005-09-28

TC94A48FG

No.

Symbol

MCKO

GPO1

I/O

O

Function

Remarks

System clock output pin

34

35

36

Push-pull output

It leaves to open when if it is unused.

General-purpose output pin 1

Open-drain output

5V tolerant

O

It leaves to open when if it is unused.

General-purpose output pin 0

Open-drain output

5V tolerant

GPO0

GND

O

It leaves to open when if it is unused.

37

38

－

Digital ground pin

V

DD

Digital power pin

General-purpose input pin 1

Schmitt input

5V tolerant

39

40

41

42

43

44

45

GPI1

GPI0

I

It connects to GND or V

pins when if it is unused this pin.

DD

General-purpose input pin 0

It connects to GND or V

Schmitt input

5V tolerant

pins when if it is unused this pin.

DD

Schmitt input

5V tolerant

/MICS

/MICK

/MIDIO

/MIACK

MILP

Microcontroller interface: Chip select signal input pin

Microcontroller interface: Clock input pin

Schmitt input

5V tolerant

I

Schmitt input / Open-drain

output, 5V tolerant

Open-drain output

5V tolerant

I/O Microcontroller interface: Data input/output pin

O

I

Microcontroller interface: Acknowledge signal output pin

Microcontroller interface: Latch pulse input pin

Schmitt input

5V tolerant

46

47

48

GNDP

PLLC

－

I

Ground pin for PLL

Charge pump for PLL

V

DDP

－

Power pin for PLL

Boot mode setting pin

Schmitt input

49

BTMD

I

It is set to “L” when if software specification does not indicate 5V tolerant

since there is deference by each program ROMs.

Schmitt input

Microcontroller interface: Mode select input pin

5V tolerant

50

51

MIMD

/RST

I

Schmitt input

Reset input pin

5V tolerant

52

53

V

－

Digital power pin

Digital ground pin

DD

GND

Test setting pin 1

Schmitt input

5V intolerant

Schmitt input

5V intolerant

54

55

TEST1

I

Usually it connects to GND pins.

Test setting pin 0

TEST0

Usually it connects to GND pins.

56

57

58

59

GNDL

LIN

－

Ground pin for ADC-Lch

I

ADC-Lch signal input pin

AVDL

Reference voltage pin for ADC-Lch

Analog power pin for ADC

V

DDA

－

I

60

61

62

ADVR

RIN

Reference voltage pin for ADC-Rch

ADC-Rch signal input pin

I

GNDR

－

Ground pin for ADC-Rch

63

64

GNDX

XI

－

Ground pin for oscillator circuit

I

Crystal oscillator connecting or clock input pin

5V intolerant

Note 1: 5V tolerant pins can have voltage applied even when the power to the device is turned off.

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TC94A48FG

Description of Operation

1. Timing System

The TC94A48FG uses pulses from the XI-XO pins as the reference clock. The system is divided into blocks

that use the reference clock directly or by dividing its frequency and blocks that operate on a clock the PLL

generates based on the crystal resonation clock. The analog and microcontroller interface blocks operate on

the crystal resonation clock while the DSP block operates on the PLL-generated clock.

Dividing

PLL

Clock for DSP

Crystal

PLL-generated

Clock for Analog Block (256fs)

Input=

256fs

Clock for Analog Block (256fs or 512fs)

Timing output to pins

(LRCKO,BCKO,MCKO)

Divider

Crystal precision

Figure 1 Timing System

The system can divide the clock from the crystal and provide three types of clock from output pins.

MCKO Clock

fs256

LRCKO, BCKO Clock

ADC, DAC

MAF, ΣΔ

Audio I/F

MCU I/F

Xi

×1/2 ～×1/512

fs128～fs0.5

Xo

ｆxi = 11.2896MHz

(44.1kHz×256)

REFCK

VARCK

×1/M

Phase

Comp.

VCO

×1/Ｊ

DSP

×1/Ｎ

PLL

Figure 2 Block diagram of clock generator circuit

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2005-09-28

TC94A48FG

1.1 Timing register setting

[AIFA]

Bit

Default

Contents

15-14

BCKi-1 clock frequency

＊

00

01

10

11

32fs

48fs

64fs

13-12

BCKi-0 clock frequency

＊

00

01

10

11

32fs

48fs

64fs

11

10

9

LRCKi-1 polarity

＊

0

1

Lch=Low (interrupt by fall edge)

Lch=High (interrupt by rise edge)

LRCKi-0 polarity

0

1

Lch=Low (interrupt by fall edge)

Lch=High (interrupt by rise edge)

SDi clock select

0

1

LRCKi-0/BCKi-0

LRCKi-1/BCKi-1

8

SDo clock select

0

1

LRCKi-0/BCKi-0

LRCKi-1/BCKi-1

7-6

SDi input format

00

01

10

11

LSB justified

MSB justified

I²S

5-4

3-2

1-0

SDi input bit clock

＊

00

01

10

11

16bit

18bit

20bit

24bit

SDo output format

00

01

10

11

LSB justified

MSB justified

I²S

SDo output bit clock

00

01

10

11

16bit

18bit

20bit

24bit

Note 2: In 48fs frequency setup of BCKi-1 and BCKi-0, LRCKi/BCKi coresponds only an input, and LRCKo / BCKo

does not correspond.

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TC94A48FG

[MOD_O]

Bit

Default

Contents

15-12

Reserved

Fixed to “0”

11

10

9

SDo3 is used as a general-purpose output Po5.

＊

0

1

Disable

Enable

SDo2 is used as a general-purpose output Po4.

0

1

Disable

Enable

SDo1 is used as a general-purpose output Po3.

0

1

Disable

Enable

8

SDo0 is used as a general-purpose output Po2.

0

1

Disable

Enable

7

6

5

Reserved

Fixed to “0”

Reserved

Fixed to “1”

Synchronization of LRCKi and LRCKo

＊

0

1

Disable

Enable

4

3

2

1

0

BCCMP/BCJMP Enable

0

1

Disable

Enable

DAC Enable

0

1

Disable

Enable

ADC Enable

0

1

Disable

Enable

LRCKo is connected to LRCKi1.

0

1

It does not connect.

It connects.

LRCKo is connected to LRCKi0.

0

1

It does not connect.

It connects.

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2005-09-28

TC94A48FG

[TMGA]

Bit

Default

Contents

15-14

Reserved

Fixed to “0”

13

DSP clock output select

＊

0

1

Disable

Enable

12-7

6

Reserved

Fixed to “0”

MCKO clock output select

＊

0

1

1/1 Xi clock

1/2 Xi clock

5-3

2-0

Reserved

Fixed to “0”

DSP clock divider setting (1/J)

000

001

010

011

100

101

110

111

1/1

1/2

1/4

1/8

1/16

1/3

1/6

＊

Prohibit

[TMGB]

Bit

Default

Contents

15-14

LRCKo/BCKo clock select

＊

00

01

10

11

FS1/FS32(BCK=fs32)

FS1/FS64(BCK=fs64)

FS2/FS64(BCK=fs32)

FS2/FS128(BCK=fs64)

13

LRCKo/BCKo output clock select

＊

0

1

Disable

Enable

12-8

Reference clock divider setting (1/M)

00h

01h

・

1/1

1/2

・

09h

・

1/10

1/32

1Fh

7-0

Variable clock divider setting (1/N)

00h

01h

・

1/1

1/2

・

＊

3Fh

・

1/64

FFh

1/256

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2005-09-28

TC94A48FG

1.2 Timing Output

LRCKO / BCKO Pin Output Settings

Mode

LRCKO Pin Output

BCKO Pin Output

Fixed to ground

Remarks

Initial Value

0

1

2

3

4

Fixed to GND

1fs

2fs

32fs

64fs

128fs

MCKO Pin Output Settings

Mode

MCKO Pin Output

Fixed to GND

XCKI (=XI)

Remarks

It can be initialized by reset.

Undefined until set by microcontroller or

built-in DSP program

0

1

2

0.5 × XCKI

Note 3:

A setup of a timing output is performed by the built-in firmware.

1.3 Example of oscillator circuit

The example of a circuit at the time of the crystal oscillator use in an oscillation part is shown in

figure 3.

Crystal oscillator connection

XI

64

XO

1

11.2896MHz

1MΩ

22pF

Figure 3 Example of oscillator circuit

1.4 Example of PLL circuit

A PLL circuit can consist of connecting LPF to a PLLC terminal easily. The example of a circuit is

shown in figure 4.

Phaseꢀ

VCO

Comp.

46 47 48

0.1uF

220Ω

47uF

0.01uF

VDD

Figure 4 Example of PLL circuit

The above-mentioned external constant is a reference value. It may change with application.

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TC94A48FG

1.5

Audio Input/Output Format

1.5.1

Audio Serial Data Input Format

The TC94A48FG supports MSB-first input only. In slave mode, it supports all setting formats for

the number of bit clock slots. In master mode, it does not support 24 slots.

don't care(invalid data, padded with "0" when read by DSP

M

L

= MSB

= LSB

internal firmware)

Data Word

Length

(bit)

Number

of

Slots

MO

DE

Timing Chart

Remarks

Format

MSB-

justified

(LSB-

Initial

Value

0

M

15

L

0

justified)

14

13

14

12

13

11

12

10

11

9

8

9

7

8

6

7

5

6

4

5

3

4

2

3

1

2

16

24

16

1

2

I²S

M

15

L

0

10

1

MSB-

justified

M

1

5

L

0

1

4

1

3

1

2

1

0

9

8

7

6

5

4

3

2

1

LSB-

justified

3

M

15

L

0

Unavailable

in master

mode(Note)

4

24

I²S

M

15

L

0

MSB-

justified

(LSB-

5

M

23

L

0

justified)

6

I²S

M

23

L

0

MSB-

justified

7

M

15

L

0

LSB-

justified

8

M

L

15

0

9

I²S

M

15

L

0

32

MSB-

justified

10

11

12

M

23

L

0

LSB-

justified

24

M

23

L

0

I²S

M

23

L

0

Note 4: These formats cannot be used in master mode (when LRCK and BCK are supplied to external devices).

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2005-09-28

TC94A48FG

1.5.2 Audio Serial Data Output Format

The valid part of data is the same as that for the input format. The TC94A48FG supports MSB-first

output only. In slave mode, it supports all setting formats for the number of bit clock slots. In master

mode, it does not support 24 slots.

M

L

＝MSB

＝LSB

＝fixed to “0” (data sent from DSP is ignored)

Number Data Word

MO

DE

of

Length

(bits)

Format

Timing Chart

Remarks

SLOT

Initial

value

0

M

L

15

14

13

14

12

13

11

12

10

11

9

8

9

7

8

6

7

5

6

4

5

3

4

2

3

1

2

0

16

24

16

1

2

I²S

M

15

L

0

10

1

M

1

5

L

0

1

4

1

3

1

2

1

0

9

8

7

6

5

4

3

2

1

3

M

15

L

0

Unavailable

in master

4

24

I²S

mode(Note)

M

15

L

0

5

M

23

L

0

6

I²S

M

23

L

0

7

M

15

L

0

8

M

L

15

0

9

I²S

M

15

L

0

32

10

11

12

M

23

L

0

24

M

23

L

0

I²S

M

23

L

0

Note 5: These formats cannot be used in master mode (when LRCK and BCK are supplied to external devices).

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2005-09-28

TC94A48FG

The audio input block and output block support different clock settings. Input and output port

settings are, however, shared as follows:

LR Clock Setting for Input Block

Mode

Signal

Signal delivered to LRCKO pin (crystal resonation clock divided)

LRCKI0 pin input

Master Mode

Slave Mode

LRCKI1 pin input

Bit Clock Setting for Input Block

Mode

Signal

Master Mode

Slave Mode

Signal delivered to BCKO pin (crystal resonation clock divided)

BCKI0 pin input

BCKI1 pin input

LR Clock Setting for Output Block

Mode

Signal

Master Mode

Slave Mode

Signal delivered to LRCKO pin (crystal resonation clock divided)

LRCKI0 pin input

LRCKI1 pin input

Bit Clock Setting for Input Block

Mode

Signal

Master Mode

Slave Mode

Signal delivered to BCKO pin (crystal resonation clock divided)

BCKI0 pin input

BCKI1 pin input

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TC94A48FG

2. Microcontroller Interface

The TC94A48FG can exchange data with a microcontroller in either normal transmission mode or I²C

mode. It uses the MIMD pin to select the mode and inputs/outputs data in MSB-first format.

Table 1 shows the features supported and the pins used in each mode.

Table 2 shows the bit composition of a 24-bit command.

Note 6: This data sheet shows general control methods. Refer to the separate program explanation data sheet for a

complete command list or detailed description of control methods.

Table 1 Pins Used and Features Supported in Normal Transmission Mode and I²C Mode

Transmission Mode

Input/Output

Normal Transmission Mode (MIMD=L)

Function

I²C Mode (MIMD=H)

Function

/MICS

MILP

Input

Chip select Input

Not used (fixed to “L”)

Input

Latch pulse input

Input

/MIDIO

Data input / output

Data input / output (SDA)

Output (open-drain)

/MICK

Input, Input / Output (I²C mode) Clock input

Clock input (SCL)

Not used

/MIACK

Output (open-drain) Acknowledge output

Note 7: The input High voltage for these pins should be V_DD-0.2 V to 5.5V.

Note 8: The open-drain /MIDIO and /MIACK pins require external pull-up resistors.

In I²C mode, the /MICK pin also requires a pull-up resistor.

The pulled-up voltage for these pins should be V_DD-0.2V to 5.5V.

Note9: The I²C bus write address is 30 h and read address is 31h.

Table 2 Bit Composition of a 24-bit Command

Bit

Function

Remarks

Refer to the command list in the

program explanation data sheet.

23-8

16-bit address

Not used

7

6

5

4

―

"1" starts program RAM boot.

"1" triggers a soft reset.

"1" specifies a read.

0h” ; 1word

Start program RAM boot

Specify soft reset

Specify read or write (R/W)

Set the number of words to be

transmitted

3-0

↓

“7h” ; 8words

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2005-09-28

TC94A48FG

2.1

Normal Transmission Mode

2.1.1 Data Transfer Format in Normal Transmission Mode

Figure 1 shows the data transfer format in normal transmission mode.

In normal transmission mode, the system first drives /MICS low and then checks that /MIACK is low

before transferring a 24-bit command MSB first. It cannot transfer data if /MIACK is high.

The system then reads or writes as many 24-bit data words (one to eight) as specified with the 24-bit

command and finally drives /MICS high. For a read, it should also make sure that /MIACK is low

after transferring a 24-bit command because /MIACK becomes high temporarily after the command is

transferred.

24bit DATA(1～8word)

/MICS

/MIACK

/MILP

/MICK

/MIDIO

COMMAND(24bit)

DATA(24bit)

Figure 5(a) Data Transfer Format in Normal Transmission Mode

2.1.2

Data Transfer Method in Normal Transmission Mode

(1) Program boot and program start

The TC94A48FG has 1k-word RAM assigned to program addresses 000h to 3FFh, in which 000h to

003h are interrupt vector addresses. To enable the TC94A48FG to operate, a program must be booted

to an interrupt vector address. If you want to store a program in the area from 004h to 3FFh, a

program loading process must follow the interrupt vector address. For a program boot, the 24-bit

command transferred upon a reset must have the program RAM boot start bit and soft reset bit set to

"1" (command = xxxx60h).

The command must be followed by 16-bit program data, set in lower bits in 24-bit data.

The write address is automatically incremented (by one) from the command (000h). The program boot

completes once /MICS is driven high upon transferring the required number of words.

The write address for a program boot always starts from the command (000h). To start the program,

transfer a 24-bit command with the soft reset bit cleared and then drive /MICS high without

transferring data.

Figure 6 shows the program boot and program start procedure.

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2005-09-28

TC94A48FG

Hard reset

(or soft reset)

／ＭＩＣＳ＝”Ｌ”

Check ＭＩＡＣＫ＝=”Ｌ”

If ＭＩＡＣＫ＝”Ｈ” , wait until ＭＩＡＣＫ＝”Ｌ”

Write 24-bit command

(program boot = 000060h)

Set the program boot and soft reset

bits to “H”

Write program data

(16bits at address 000h)

Program data stored in lower 16bits

Bootable for address of up to 3FFh

Write program data

(16bits at address 001h)

Write program data

(Address 3FEh)

Write program data

(Address 3FFh)

／ＭＩＣＳ＝”Ｈ”

／ＭＩＣＳ＝”Ｌ”

Program boot finished

Check ＭＩＡＣＫ＝=”Ｌ”

If ＭＩＡＣＫ＝”Ｈ” , wait until ＭＩＡＣＫ＝”Ｌ”

Write 24-bit command

(soft reset off = 000000h)

／ＭＩＣＳ＝”Ｈ”

Start program

Figure 6

Program Boot and Program Start Procedure

15

2005-09-28

TC94A48FG

(2) Writing 24-bit data

When the host microcontroller writes data to the TC94A48FG during the execution of a program, it

sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "0" and sets the number of

words to be written. Then, it transfers the 24-bit command, followed by a required number of 24-bit

data words.

Figure 7 shows the 24 bit data write procedure.

／ＭＩＣＳ＝“Ｌ”

Check MＩＡＣＫ = “Ｌ”

(If MIACK = “H” , wait until MIACK = “L”)

Write 24-bit command

(data write = xxxx0xh)

Set 16-bit address and the number of

words to be transferred.

Write 24-bit data (1)

Write 24-bit data (2)

Can write up to eight 24-bit data words

Write 24-bit data (n)

／ＭＩＣＳ＝“Ｈ”

Data write finished

Figure 7 shows the 24-bit data write procedure.

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2005-09-28

TC94A48FG

(3) Reading 24-bit data

When the host microcontroller reads data from the TC94A48FG during the execution of a program, it

sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "1" and sets the number of

words to be read. Then, it transfers the 24-bit command, check that /MIACK = "L", and read a

required number of 24-bit data words.

The host microcontroller should check that /MIACK = "L" because it has to wait until the data to be

read is set in the data buffer.

Figure 8 shows the 24 bit data read procedure.

／ＭＩＣＳ＝“Ｌ”

Check ＭＩＡＣＫ＝“Ｌ”

（If MＩＡＣＫ＝“Ｈ” , wait until MIACK = “Ｌ”)

Transfer 24-bit command

(data read = xxxx1xh)

Set 16 bit address and the number of

words to be transferred.

Check ＭＩＡＣＫ＝“Ｌ”

（If MＩＡＣＫ＝“Ｈ” , wait until MIACK = “Ｌ”)

Can read up to eight 24-bit data word

Read 24-bit data (1)

Read 24-bit data (2)

Read 24-bit data (n)

／ＭＩＣＳ＝“Ｈ”

Data read finished

Figure 8 shows the 24-bit data read procedure.

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TC94A48FG

(4) Triggering and terminating a soft reset

A soft reset is required before the system can start a program after program boot or restart a

program.

A 24-bit command with its soft reset bit set to "1" triggers a soft reset and a command with the bit

cleared terminates a soft reset.

When trigging or terminating a soft reset, drive /MICS high after transferring the 24-bit command

because no data needs to follow the command.

Figure 9 shows the procedure for trigging or terminating a soft reset.

／ＭＩＣＳ＝“Ｌ”

Check MＩＡＣＫ = “Ｌ”

(If MIACK = “H” , wait until MIACK = “L”)

If a malfunction occurs, perform a

hard reset prior to a soft reset.

“1” triggers a reset

“0” terminates a reset

Transfer 24-bit command

(soft reset ON/OFF = 0000x0h)

／ＭＩＣＳ＝“Ｈ”

Soft reset triggered or terminated

Figure 9 Procedure for Trigging or Terminating a Soft Reset

18

2005-09-28

TC94A48FG

2.2 I²C Bus Mode

2.2.1

Data Transfer Format in I²C Bus Mode

Figure 10 shows the data transfer format in I²C bus mode.

In I²C bus mode, the host microcontroller first transfers an I²C address (write = 30h) and then checks

that the ACK bit is low. If the ACK bit is high, it retransmits a start condition (without transmitting a

stop condition) and then transfers an I²C address of 30h. After transferring an I²C address, the host

microcontroller transfers a 24-bit command. When the host microcontroller writes data to the

TC94A48FG, it writes as many 24-bit data words as specified with the 24-bit command (1 to 8 words)

and then transfers an end condition.

When the host microcontroller reads data from the TC94A48FG, it transfers a 24-bit command and

then, without transmitting an end condition, transfers an I²C address (read =31h) and check that the

ACK bit is low. If the ACK bit is high, the host microcontroller retransmits a start condition (without

transmitting a stop condition) and then transfers an I²C address of 31h. After checking that the ACK

bit is low, the host microcontroller reads as many 24-bit data words as specified with the 24-bit

command (1 to 8 words). During a read, the host microcontroller sets the ACK bit to low after reading

every eight bits. The ACK bit accompanying the last eight bits must be set to high, after which the

host microcontroller transmits a stop condition. When transferring only a 24-bit command without

reading or writing data, transmit an end condition after transferring the command.

Figures 11 to 13 show the data transfer formats for writing, reading, and transferring a command

only.

SDA

SCL

I²C Address(30h)

DATA Hi(8bit)

DATA Mid(8bit)

DATA Low(8bit)

R/W ACK

ACK

I²C Address

24bit Command and 24bit DATA (1～8word)

Start Condition

Stop Condition

Figure 10 Data Transmission Format in I²C Mode

(30h)

24bit COMMAND

24bit Write DATA(1word～8word)

START I²C Address

W

A

COMMAND(H) A

A

STOP

COMMAND(M)

COMMAND(L)

DATA(H)

DATA(M)

DATA(L)

Each ACK signal sent from TC94A48FG to Host

An interval of at least 1fs(32μs@1fs=32kHz) is required before next START

Figure 11 Format for Writing

24bit Read DATA(1word～8word)

(30h)

24bit COMMAND

(31h)

I2C Address

COMMAND(H)

RD(L)

START

W

A

COMMAND(M)

A

^COMMAND(L)A

I2C Address

R

A

RD(H)

A

RD(M)

A

STOP

START

Each ACK signal sent from TC94A48FG to Host

An interval of at least 1fs(32μs@1fs=32kHz)

is required before next START

These ACK signals are sent from host to TC94A48FG

This ACK signal is set to “H” by the Host

Figure 12 Format for Reading

(30h)

24bit COMMAND

START I²C Address

W

A

STOP

COMMAND(L)

COMMAND(H)

COMMAND(M)

Each ACK signal sent from

TC94A48FG to Host

Figure 13 Format for Transferring a Command Only

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2005-09-28

TC94A48FG

2.2.2

(1) Program boot and program start

Data Transfer Method in I²C Mode

The TC94A48FG has 1k-word RAM assigned to program addresses 000h to 3FFh, in which 000h to

003h are interrupt vector addresses. To enable the TC94A48FG to operate, a program must be booted

to an interrupt vector address. If you want to store a program in the area from 004h to 3FFh, a

program loading process must follow the interrupt vector address. For a program boot, the 24-bit

command transferred upon a reset must have the program RAM boot start bit and soft reset bit set to

"1" (command = xxxx60h).

The command must be followed by 16-bit program data, set in lower bits in 24-bit data.

The write address is automatically incremented (by one) from the command (000h). The program boot

completes once an end condition is transmitted upon transferring the required number of words. The

write address for a program boot always starts from the command (000h). To start the program,

transfer a 24-bit command with the soft reset bit cleared and then transmit an end condition without

transferring data.

Figure 14 shows the program boot and program start procedure.

20

2005-09-28

TC94A48FG

Hard reset

(or soft reset)

ＳＴＡＲＴＣｏｎｄｉｔｉｏｎ

Transfer I2CꢀＡｄｄｒｅｓｓ（３０ｈ）

Check ACK bit = “L”

If ACK = “H” , restart from

START condition.

Set the program boot and soft reset

bits to “H”

Write 24-bit command

(program boot = 000060h)

Write program data

(16 bits at address 0000h)

Program data stored in lower 16bits

Bootable for address of up to 3FFh

Write program data

(16 bits at address 0001h)

Write program data

(16bits at address 3FEh)

Write program data

(16bits at address 3FFh)

Program boot finished

ＳＴＯＰＣｏｎｄｉｔｉｏｎ

ＳＴＡＲＴＣｏｎｄｉｔｉｏｎ

Transfer I2CꢀＡｄｄｒｅｓｓ（３０ｈ）

Check ACK bit = “L”

If ACK = “H” , restart from

START condition.

Write 24-bit command

(soft reset OFF = 000000h)

ＳＴＯＰＣｏｎｄｉｔｉｏｎ

Start program

Figure 14 Program Boot and Program Start Procedure

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2005-09-28

TC94A48FG

(2)

Writing 24-bit data

When the host microcontroller writes data to the TC94A48FG during the execution of a program, it

sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "0" and sets the number of

words to be written. Then, it transfers the 24-bit command, followed by a required number of 24-bit

data words.

An interval of at least 1fs(32μs@1fs=32kHz) is required before next started.

Figure 15 shows the 24 bit data write procedure.

ＳＴＡＲＴꢀＣｏｎｄｉｔｉｏｎ

If ACK = “H” , restart from

START condition.

Transfer I2CꢀＡｄｄｒｅｓｓ（３０ｈ）

Check ACK bit = “L”

Write 24-bit command

(data write = xxxx0xh)

Set 16-bit address and the number of

words to be transferred.

Write 24-bit data (1)

Write 24-bit data (2)

Can write up to eight 24-bit data words

Write 24-bit data (n)

ＳＴＯＰꢀＣｏｎｄｉｔｉｏｎ

Data write finished

Figure 15 shows the 24-bit Data Write Procedure.

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2005-09-28

TC94A48FG

(3)

Reading 24-bit data

When the host microcontroller reads data from the TC94A48FG during the execution of a program, it

sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "1" and sets the number of

words to be read. Then, it transfers the 24-bit command, waits about 1fs, and then transfers an I2C

address of 31h, followed by a start condition. Finally, it reads a required number of 24-bit data words.

During a read, the host microcontroller should set the ACK bits to low but the ACK bit accompanying

the last eight bits of data must be high, thus causing the TC94A48FG to relinquish the SDA bus line

so that the host microcontroller can transmit a stop condition.

The host microcontroller should wait about 1fs after transferring a command because it has to wait

until the data to be read is set in the data buffer of the TC94A48FG.

Figure 16 shows the 24-bit data read procedure.

ＳＴＡＲＴＣｏｎｄｉｔｉｏｎ

If ACK = “H” , restart from

START condition.

Transfer I2C Ａｄｄｒｅｓｓ(30h)

Check ACK bit = “L”

Set a 16-bit address and the number

Transfer 24-bit command

of words to be transferred.

(data read = xxxx1xh)

Wait about 1fs

ＳＴＡＲＴＣｏｎｄｉｔｉｏｎ

If ACK = “H” , restart from

START condition.

Transfer I2C Ａｄｄｒｅｓｓ(31h)

Check ACK bit = “L”

Read 24-bit data (1)

Can read up to eight 24-bit

data words

Read 24-bit data (2)

Read 24-bit data (n)

ＳＴＯＰＣｏｎｄｉｔｉｏｎ

Set the last ACK bit to “H”

Data read finished

Figure 16 shows the 24-bit Data Read Procedure

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2005-09-28

TC94A48FG

(4)

Triggering and terminating a soft reset

A soft reset is required before the system can start a program after program boot or restart a

program.

A 24-bit command with its soft reset bit set to "1" triggers a soft reset and a command with the bit

cleared terminates a soft reset.

When trigging or terminating a soft reset, transmit a stop condition after transferring the 24-bit

command because no data needs to follow the command.

Figure 17 shows the procedure for triggering or terminating a soft reset.

ＳＴＡＲＴꢀＣｏｎｄｉｔｉｏｎ

If ACK = “H” , restart from

START Condition.

Transfer I2CꢀＡｄｄｒｅｓｓ（３０ｈ）

Check ACK bit = “L”

If a system crash(malfunction)

occurs, perform a hard reset

prior to a soft reset.

Transfer 24-bit command

“1” triggers a reset

(soft reset ON/OFF = 0000x0h)

“0” terminates a reset

ＳＴＯＰꢀＣｏｎｄｉｔｉｏｎ

Soft reset triggered or terminated

Figure 17 Procedure for Triggering or Terminating a Soft Reset

3. Write and Read Commands

The specifications of write and read commands depend on the built-in program. For details, refer to the

program explanation data sheet.

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2005-09-28

TC94A48FG

Maximum Ratings (Ta = 25°C)

Characteristics

Symbol

Rating

Unit

Supply Voltage

V

−0.3~4.0

V

DD

Input voltage 1

V

−0.3~V

+ 0.1

in1

in2

DD

Input voltage 2 (Note10)

Power dissipation

Operating temperature

Storage temperature

−0.3~+ 5.5

V

P

400

mW

°C

D

T

opr

−40~+85

−55~+150

T

stg

Note10: SDI0~3, LRCKI0~1, BCKI0~1, GPI0~1, /MICS, /MICK, /MIDIO, MILP, BTMD, MIMD, /RST

Electrical Characteristics

(unless otherwise specified,

Ta = 25°C, V_DD= V_DDX= V_DD12= V_DD3= V_DD45= V_DD6= V_DDP= V_DDA= 3.3V)

DC Characteristics

Test

circuit

Characteristics

Symbol

Test Condition

Ta = −40~85°C

Min.

Typ.

Max.

Unit

Operating supply voltage

Operating frequency range

PLL clock frequency range

Operating supply current

V

⎯

3.0

30

90

⎯

3.3

⎯

3.6

75

V

DD

f

⎯

Using PLL for DSP clock

MHz

mA

opr

f

⎯

225

100

plo

I

⎯

fopr =75MHz (75MIPS)

90

DD

Clock pins (XI,XO)

Test

circuit

Characteristics

Symbol

Test Condition

XI pin

Min.

Typ.

Max.

Unit

V

“H” level

V

IH1

2.8

⎯

0.5

−2.5

⎯

Input voltage(1)

⎯

“L” level

“H” level

“L” level

V

IL1

I

V

= 2.8 V

= 0.5 V

⎯

OH1

OH

OL

Output voltage(1)

XO pin

mA

I

3.0

OL1

Input pins

Test

circuit

Characteristics

Symbol

Test Condition

Min.

Typ.

Max.

Unit

V

“H” level

“L” level

“H” level

“L” level

V

IH2

2.8

⎯

0.5

10

⎯

Input voltage(2)

⎯

(Note 11)

V

IL2

Input leakage

current

I

V

= V

DD

(Note 11),

(Note 12)

⎯

IH2

IN

µA

I

= 0 V

−10

IL2

Note 11: SDI0~3, LRCKI0~1, BCKI0~1, GPI0~1, /MICS, /MICK, /MIDIO, MILP, BTMD, MIMD, /RST, TEST0~1, PLLC

Note 12 : XI

25

2005-09-28

TC94A48FG

Output pins

Test

circuit

Characteristics

Symbol

Test Condition

Min.

Typ.

Max.

Unit

“H” level

“L” level

“H” level

“L” level

I

V

= 2.8 V

(Note 13)

(Note 14)

(Note 15)

⎯

5

⎯

−5

⎯

OH2

OH

OL

OH

OL

OH

Output current(2)

Output current(3)

⎯

I

= 0.5 V

= 2.8 V

= 0.5 V

OL2

OH3

mA

I

⎯

3

−3

⎯

I

OL3

OL4

OZ5

Output current(4)

I

⎯

5

⎯

Output-off leakage current

I

= V

⎯

±10

µA

DD

Note 13: SDO0~3, LRCKO, BCKO (push-pull output)

Note 14: MCKO (push-pull output)

Note 15: GPO0~1, /MIDIO, /MIACK (open-drain output)

26

2005-09-28

TC94A48FG

AC Characteristics

•

The gain through the firmware is 0 dB (pass-through), except for +2 dB for DC-cut-HPF.

VDD (for all power supplies) = 3.3V, Ta = 25°C

Test circuit

MCU

Digital SG/Analyzer I/F

10kΩ

0.01uF

220Ω

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 6353

439

329

BTMD

LRCKO

50 MIMD

51 /RST

52 VDD

53 GND

54 TEST1

55 TEST0

56 GNDL

57 LIN

SDO0 31

SDO1 30

SDO2 29

SDO3 28

BCKI0 27

BCKI1 26

LRCKI0 25

LRCKI1 24

SDI0 23

AGND

1kΩ

TC94A48FG

Lch

Rch

2200pF 4.7μF

58 ADVL

59 VDDA

60 ADVR

61 RIN

47μF

SDI1 22

SDI2 21

1kΩ

SDI3 20

2200pF 4.7μF

62 GNDR

63 GNDX

64 XI

GND 19

VDD 18

VDD6

17

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

47uF

1MΩ

22pF

Analog Analog

VDD GND

Digital Digital

VDD GND

270Ω

2200pF

2200pF 2200pF

2200pF

10μF

10kΩ

10μF

10kΩ

10μF

10kΩ

10μF

10kΩ

10μF

10kΩ

DAC1 DAC2

DAC3 DAC4

DAC5 DAC6

27

2005-09-28

TC94A48FG

AD Converter: LIN and RIN pin input, Vin_ref: 1 kHz, 800 mVrms (unless otherwise

specified), SDO0 pin output monitored

Characteristics

Maximum input signal

Symbol

Test Condition

Min.

Typ.

Max.

Unit

Input level that drives ADC output to

digital full scale.

Vin

Zin

⎯

20

87

⎯

27

93

800 mVrms

Input impedance

S/N ratio

Each of LIN and RIN pins

34

kΩ

A-Weight, Input AC shorted,

Crystal: 11.2896 MHz

S/Na

⎯

20 kHz LPF,

Crystal: 11.2896 MHz

THD + N

THDa

CTa

⎯

−83

−85

−77

−78

dB

20 kHz LPF, Lch to Rch/ Rch to Lch,

Crystal: 11.2896 MHz

Crosstalk

A-Weight, -60dB for Vin_ref input,

Crystal: 11.2896 MHz

Dynamic range

L to R gain error

DRa

Vdlr

87

93

0

⎯

−0.5

0.5

DA Converter: SDO0 to SDO3 pin input, SDI0_ref = 0 dBFS, 1 kHz (unless otherwise

specified), DAO1 to DAO6 pin output monitored.

Characteristics

Output signal level

Symbol

Ao

Test Condition

Min.

790

90

Typ.

830

98

Max.

Unit

Output voltage at digital full-scale input

870 mVrms

A-Weight,

S/N ratio

THD + N

Crosstalk

S/Nd

⎯

Crystal: 11.2896 MHz

20 kHz LPF

THDd

CTd

⎯

−88

−90

−75

Crystal: 11.2896 MHz

dB

20 kHz LPF,

−83

Crystal: 11.2896 MHz

A-Weight

Crystal: 11.2896 MHz

Dynamic range

DRd

88

95

0

⎯

Channel-to-channel gain error

Vddo

DAO1~DAO6 pin output monitored.

−0.5

0.5

28

2005-09-28

TC94A48FG

Timing

Clock input pin (XI)

Characteristics

Symbol

Test Condition

Min.

Typ.

Max.

Unit

ns

Clock cycle

t

fs=32kHz~48kHz, 256fs input

80.0

40.0

88.6

44.3

124.0

62.0

XI

Clock “H” duration

Clock “L” duration

t

⎯

XIH

t

XIL

Reset pin (/RST)

Characteristics

Symbol

Test Condition

Min.

Typ.

Max.

Unit

Standby time

t

⎯

10

⎯

ms

RRS

Reset pulse width

t

1.0

µs

WRS

Note 16: The /RST pin must be driven low at power-on.

Audio Serial Interface (BCKI0~1, BCKO, LRCKI0~1, LRCKO, SDI0~3, SDO0~3)

Characteristics

LRCKIx setup time

Symbol

Test Condition

Min.

Typ.

Max.

Unit

t

CL = 30 pF

75

−75

50

⎯

75

⎯

60

40

LBS

fs = 48 kHz or lower

BCKI0 and BCKI1 input: 64 fs or lower

LRCKIx hold time

t

LBH

SDIx setup time

t

SDI

SDIx hold time

t

50

HDI

BCKIx clock cycle

t

300

150

⎯

BCK

BCH

ns

BCKIx clock “H” duration

BCKIx clock “L” duration

SDOx output delay(1)

SDOx output delay(2)

LRCKO output delay

t

BCL

DO1

DO2

t

C

L

C

L

C

L

= 30 pF

⎯

t

⎯

DCLR

29

2005-09-28

TC94A48FG

Microcontroller Interface

Normal Transmission Mode (/MICS, /MICK, /MIDIO, MILP, /MIACK)

Characteristics

Standby time

Symbol

Test Condition

Min.

Typ.

Max.

Unit

ms

t

⎯

20

0.5

1.0

0.5

⎯

STB

/MICS fall to /MICK rise setup time

/MIACK fall to /MICK rise setup time

/MICK clock cycle

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

/MICK “L” duration

⎯

0.5

⎯

1.0

⎯

/MICK “H” duration

/MICK rise to /MILP fall setup time

MILP “L” duration

µs

/MIDIO input data setup time

/MIDIO input data hold time

/MIDIO output data delay

/MICS “H” duration

t

10

11

12

13

t

0.5

⎯

/MIACK output delay

MILP rise to /MICS rise setup time

0.5

Note 17: The /MIACK output timing and /MIACK "H" duration vary with the firmware.

I²C Mode (/MICK, /MIDIO)

Characteristics

Symbol

f

Test Condition

Min.

Typ.

Max.

Unit

kHz

/MICK clock frequency

/MICK “H” duration

C

L

C

L

C

L

C

L

C

L

C

L

= 400 pF

0

⎯

400

⎯

IFCK

t

0.6

1.3

0.2

0

H

/MICK “L” duration

t

⎯

L

Data setup time

t

⎯

DS

DH

Data hold time

0.9

⎯

Transmission start condition hold time

t

0.6

SCH

Repeated transmission start condition

setup time

µs

t

C

L

C

L

= 400 pF

0.6

⎯

SCS

ECS

Transmission end condition setup

time

Data transmission interval

I²C rise time

t

C

L

C

L

C

L

= 400 pF

1.3

⎯

BUF

t

0.3

R

I²C fall time

t

⎯

F

30

2005-09-28

TC94A48FG

AC Characteristics Measurement Points

1. Clock Pin (XI)

XI

50%

t_XIH

t_XIL

t_XI

2. Reset Pin (/RST)

100%

VDD

90%

0%

50%

/RST

t_RRS

t_WRS

3. Audio Serial Interface (LRCKIx, BCKIx, SDIx, LRCKO, BCKO, SDOx, MCKO)

XI

50%

t_DCLR

50%

100%

0%

LRCKO

t_BCK

t_BCL

t_BCH

LRCKIx/

LRCKO

t_LBH

t_LBS

BCKIx/

BCKO

SDIx

t_SDI

t_HDI

SDOx

t_DO1

t_DO2

31

2005-09-28

TC94A48FG

4. Microcontroller Interface

4-1. Serial Mode (/MICS, /MICK, /MIDIO, MILP, /MIACK)

/RST

/MICS

t_STB

t₁

t₂

/MICS

/MIACK

t₃

t₁₂

t₄

t₅

t₆

/MICK

MILP

t₇

t₈

t₉

/MIDIO

DATA IN

DATA OUT

t₁₀

t₁₃

t₁₁

/MICS

/MIACK

/MICK

t₇

MILP

t₆

/MIDIO

DATA IN

DATA OUT

32

2005-09-28

TC94A48FG

4-2. I²C Mode (/MICK, /MIDIO)

/RST

/MIDIO

(SDA)

t_STB

t_BUF

/MIDIO

(SDA)

/MICK

(SCL)

t_SCH

t_R

t_L

t_H

t_DS

t_DH

t_SCS

t_F

t_ECS

33

2005-09-28

TC94A48FG

Equivalent Circuit Diagrams

Type

Equivalent Circuit Diagram

Description

Schmitt Input

A

Schmitt Input.

5V tolerant.

B

C

D

A voltage can be applied to this pin even when the power

supply pin of the TC94A48FG is driven to 0V.

Push-pull output.

The amplitude is 3.3 V. If external devices require 5V

amplitude, perform a level conversion.

Open-drain output

This pin must be pulled up to VDD or 5V externally.

Schmitt input and open-drain output

This pin must be pulled up to VDD or 5V externally. A

voltage can be applied to this pin even when the power

supply pin of the TC94A48FG is driven to 0V.

E

[Caution] When using the pin for input, connect it to an

open-drain output pin of an external device.

Type A: TEST0, TEST1

Type B: SDI0~3, LRCKI0~1, BCKI0~1, GPI0~1, BTMD, MILP, /MICK, /MICS, MIMD, /RST

Type C: SDO0~3, MCKO, BCKO, LRCKO

Type D: GPO0~1, /MIACK

Type E: /MIDIO

34

2005-09-28

TC94A48FG

Package Dimensions

LQFP64-P-1010-0.50E

Unit: mm

(Note) Palladium plate

Weight : 0.4g (typ.)

35

2005-09-28

TC94A48FG

36

2005-09-28


型号：	TC94A48FG
厂家：	TOSHIBA
描述：	Single-chip Audio Digital Signal Processor 单芯片音频数字信号处理器数字信号处理器
文件：	总36页 (文件大小：629K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC94A48FG [TOSHIBA]

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