TC58512FTI(EL) [TOSHIBA]
IC,EEPROM,NAND FLASH,64MX8,CMOS,TSSOP,48PIN,PLASTIC;
| 型号： | TC58512FTI(EL) |
| 厂家： | 
TOSHIBA |
| 描述： | IC,EEPROM,NAND FLASH,64MX8,CMOS,TSSOP,48PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总43页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC58512FTI
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64M × 8 BITS) CMOS NAND E2PROM
DESCRIPTION
The TC58512 is a single 3.3 V 512-Mbit (553,648,128) bit NAND Electrically Erasable and Programmable
2
Read-Only Memory (NAND E PROM) organized as 528 bytes × 32 pages × 4096 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell array
in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes
× 32 pages).
The TC58512 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
•
Organization
•
•
•
Power supply
V
= 2.7 V to 3.6 V
CC
Memory cell allay 528 × 128K × 8
Program/Erase Cycles 1E5 cycle (with ECC)
Access time
Register
528 × 8
Page size
Block size
528 bytes
Cell array to register 25 µs max
(16K + 512) bytes
Serial Read Cycle
Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
50 ns min
•
•
Modes
•
Read, Reset, Auto Page Program
Auto Block Erase, Status Read
Multi Block Program, Multi Block Erase
Mode control
10 mA typ.
10 mA typ.
10 mA typ.
100 µA
Standby
Serial input/output
•
Package
Command control
TSOPI48-P-1220-0.50 (Weight: 0.53 g typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
NC
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
I/O1 to I/O8
I/O port
NC
2
NC
NC
3
NC
CE
Chip enable
NC
4
NC
NC
5
I/O8
I/O7
I/O6
I/O5
NC
WE
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
GND
RY/BY
RE
6
7
RE
8
CE
9
CLE
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
ALE
V
V
V
CC
CC
SS
V
SS
WP
NC
NC
NC
NC
RY/BY
GND
CLE
ALE
WE
WP
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
Ground input
Power supply
Ground
V
CC
NC
NC
NC
V
SS
NC
NC
NC
NC
000707EBA1
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
2001-03-05 1/43
TC58512FTI
BLOCK DIAGRAM
V
V
CC SS
Status register
Address register
Column buffer
Column decoder
Data register
Sense amp
I/O1
to
I/O Control circuit
I/O8
Command register
CE
CLE
ALE
WE
RE
Logic control
Control
Memory cell array
WP
RY/BY
RY/BY
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
V
V
V
P
Power Supply Voltage
Input Voltage
−0.6 to 4.6
−0.6 to 4.6
V
V
CC
IN
Input/Output Voltage
Power Dissipation
−0.6 V to V
+ 0.3 V (≤ 4.6 V)
CC
V
I/O
D
0.3
W
°C
°C
°C
T
T
T
Soldering Temperature (10s)
Storage Temperature
260
solder
stg
opr
−55 to 150
−40 to 70
Operating Temperature
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMB0L
PARAMETER
CONDITION
MIN
MAX
UNIT
C
C
*
Input
V
V
= 0 V
10
10
pF
pF
IN
IN
Output
= 0 V
OUT
OUT
This parameter is periodically sampled and is not tested for every device.
2001-03-05 2/43
TC58512FTI
VALID BLOCKS (1)
SYMBOL
PARAMETER
Number of Valid Blocks
MIN
TYP.
MAX
4096
UNIT
N
4016
Blocks
VB
(1) The TC58512 occasionally contains unusable blocks. Refer to Application Note (14) toward the end of this document.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP.
MAX
3.6
UNIT
V
V
V
*
2.7
2.0
3.3
V
V
V
CC
High Level input Voltage
Low Level Input Voltage
V
+ 0.3
CC
IH
IL
−0.3*
0.8
−2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS (Ta = - 40° to 70°C, V = 2.7 V to 3.6 V)
CC
SYMBOL
PARAMETER
CONDITION
MIN
TYP.
MAX
UNIT
I
I
I
Input Leakage Current
Output Leakage Current
V
V
= 0 V to V
10
10
10
30
µA
µA
IL
IN
CC
= 0.4 V to V
LO
OUT
CC
Operating Current (Serial Read) CE = V , I
= 0 mA, t = 50 ns
cycle
mA
CCO1
IL OUT
Operating Current
(Command Input)
I
I
I
t
t
t
= 50 ns
= 50 ns
= 50 ns
10
10
10
30
30
30
mA
mA
mA
CCO3
CCO4
CCO5
cycle
cycle
cycle
Operating Current (Data Input)
Operating Current
(Address Input)
I
I
I
I
Programming Current
Erasing Current
2.4
10
10
8
30
30
1
mA
mA
mA
µA
V
CCO7
CCO8
CCS1
CCS2
Standby Current
CE = V
CE = V
IH
Standby Current
− 0.2 V
100
CC
V
V
High Level Output Voltage
Low Level Output Voltage
I
I
= −400 µA
= 2.1 mA
OH
OL
OH
OL
0.4
V
I
(RY/BY ) Output Current of RY/BY pin
V
= 0.4 V
OL
mA
OL
2001-03-05 3/43
TC58512FTI
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = - 40° to 70°C, V = 2.7 V to 3.6 V)
CC
SYMBOL
PARAMETER
MIN
MAX
UNIT
NOTES
t
CLE Setup Time
CLE Hold Time
0
10
0
35
35
30
20
35
45
25
200
200
1 +
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
CLS
t
CLH
t
CE Setup Time
CE Hold Time
CS
t
10
25
0
CH
t
Write Pulse Width
ALE Setup Time
WP
t
ALS
ALH
t
ALE Hold Time
10
20
10
50
15
100
20
35
50
100
10
15
0
t
Data Setup Time
Data Hold Time
DS
DH
t
t
t
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Read Pulse Width
Read Cycle Time
WC
WH
t
WW
t
RR
t
RP
t
RC
t
RE Access Time (Serial Data Access)
CE High Time for Last Address in Serial Read Cycle
RE Access Time (ID Read)
REA
t
(2)
CEH
t
REAID
t
Data Output Hold Time
OH
t
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
RHZ
CHZ
REH
t
t
t
IR
Output-High-impedance-to- RE Rising Edge
RE Access Time (Status Read)
CE Access Time (Status Read)
RE High to WE Low
t
0
RSTO
t
CSTO
t
RHW
WHC
WHR
t
WE High to CE Low
30
30
100
100
50
t
WE High to RE Low
t
ALE Low to RE Low (ID Read)
CE Low to RE Low (ID Read)
Memory Cell Array to Starting Address
WE High to Busy
AR1
t
CR
t
R
t
WB
t
ALE Low to RE Low (Read Cycle)
RE Last Clock Rising Edge to Busy (in Sequential Read)
AR2
t
RB
t
CE High to Ready (When interrupted by CE in Read Mode)
Device Reset Time (Read/Program/Erase)
µs
µs
(1) (2)
CRY
t ( RY/BY )
r
t
6/10/500
RST
AC TEST CONDITIONS
PARAMETER
CONDITION
Input level
2.4 V, 0.4 V
3 ns
1.5 V, 1.5 V
1.5 V, 1.5 V
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
C (100 pF) + 1 TTL
L
2001-03-05 4/43
TC58512FTI
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when t
is greater than or equal to 100 ns. If the RE to CE delay
is less than 30 ns, RY/BY signal stays Ready.
CEH
t
≥ 100 ns
CEH
*
*: V or V
IH IL
CE
RE
A : 0 to 30 ns → Busy signal is not output.
525
526
527
A
RY/BY
Busy
t
CRY
PROGRAMMING AND ERASING CHARACTERISTICS (Ta = - 40° to 70°C, V = 2.7 V to 3.6 V)
CC
SYMBOL
PARAMETER
Programming Time
MIN
TYP.
200
MAX
1000
UNIT
NOTES
t
t
t
µs
PROG
Dummy Busy Time for Multi Block
Programming
2
200
2
10
1000
3
µs
µs
DBSY
Multi Block Program Busy Time
MBPBSY
Number of Programming Cycles on Same
Page
N
(1)
t
Block Erasing Time
10
ms
BERASE
(1): Refer to Application Note (12) toward the end of this document.
2001-03-05 5/43
TC58512FTI
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
CLE
ALE
CE
RE
Setup Time
Hold Time
WE
t
t
DH
DS
I/O1
to I/O8
: V or V
IH
IL
Command Input Cycle Timing Diagram
CLE
t
t
CLH
CLS
t
t
CS
CH
CE
WE
t
WP
t
t
ALH
ALS
ALE
t
t
DH
DS
I/O1
to I/O8
: V or V
IH
IL
2001-03-05 6/43
TC58512FTI
Address Input Cycle Timing Diagram
t
CLS
CLE
CE
t
t
t
t
WC
CS
WC
WC
t
t
t
t
t
t
t
WP
WP
WH
WP
WH
WP
WH
WE
ALE
t
t
ALH
ALS
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
I/O1
to I/O8
A0 to A7
A9 to A16
A17 to A24
A25
: V or V
IH
IL
Data Input Cycle Timing Diagram
t
CLH
CLE
CE
t
CH
t
t
ALS
WC
ALE
WE
t
t
t
t
WP
WP
WH
WP
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
I/O1
to I/O8
D 0
IN
D 1
IN
D 527
IN
: V or V
IH
IL
2001-03-05 7/43
TC58512FTI
Serial Read Cycle Timing Diagram
t
RC
CE
RE
t
t
t
t
t
CHZ
RP
REH
RP
RP
t
t
t
OH
OH
OH
t
t
t
t
t
t
REA
RHZ
REA
RHZ
REA
RHZ
I/O1
to I/O8
t
RR
RY/BY
Status Read Cycle Timing Diagram
t
CLS
CLE
t
t
CLH
CLS
t
CS
CE
WE
RE
t
t
CH
WP
t
t
t
t
CHZ
WHC
CSTO
t
WHR
t
OH
t
t
DH
DS
IR
t
t
RHZ
RSTO
Status
output
I/O1
to I/O8
70H*
RY/BY
* 70H represents the hexadecimal number
: V or V
IH IL
2001-03-05 8/43
TC58512FTI
Read Cycle (1) Timing Diagram
CLE
t
t
CLH
CLS
t
CEH
t
CS
t
CH
CE
WE
ALE
RE
t
t
CRY
WC
t
t
t
t
AR2
ALS
ALH
WB
t
ALH
t
t
t
RC
R
RR
t
t
t
t
t
t
t
t
t
t
t
REA
DS DH
DS DH
DS DH
DS DH
DS DH
I/O1
to I/O8
A0 to
A7
A9
A17
D
D
D
D
OUT
OUT
OUT
OUT
00H
A25
to A16
to A24
N
N + 1
N + 2
527
t
RB
Column address
N*
RY/BY
: V or V
IH
IL
Read Cycle (1) Timing Diagram: When Interrupted by CE
CLE
t
t
CLH
CLS
t
CS
t
CH
CE
WE
ALE
RE
t
t
WC
CHZ
t
t
t
t
AR2
ALS
ALH
WB
t
ALH
t
t
t
RC
R
RR
t
RHZ
t
t
t
t
t
t
t
t
t
t
t
t
DS DH
DS DH
DS DH
DS DH
DS DH
REA
OH
I/O1
to I/O8
A0 to
A7
A9
A17
D
D
D
OUT
OUT
OUT
00H
A25
to A16
to A24
N
N + 1
N + 2
Column address
N*
RY/BY
*: Read operation using 00H command N: 0 to 255
: V or V
IH IL
2001-03-05 9/43
TC58512FTI
Read Cycle (2) Timing Diagram
CLE
t
t
CLH
CLS
t
t
CH
CS
CE
WE
ALE
RE
t
t
t
t
AR2
ALH
ALS
ALH
t
t
t
RC
R
RR
t
WB
t
t
t
t
t
REA
DS DH
DS DH
I/O1
to I/O8
A9 to
A16
A17
01H
A0 to A7
A25
D
OUT
D
OUT
D
OUT
to A24
256 + N 256 + N + 1
527
Column address
N*
RY/BY
: V or V
IH
IL
*: Read operation using 01H command N: 0 to 255
Read Cycle (3) Timing Diagram
CLE
t
t
CLH
CLS
t
t
CH
CS
CE
WE
ALE
RE
t
t
t
t
AR2
ALH
ALS
ALH
t
t
t
RC
R
RR
t
WB
t
t
t
t
t
REA
DS DH
DS DH
I/O1
to I/O8
A9 to
A16
A17
50H
A0 to A7
A25
D
OUT
D
OUT
D
OUT
to A24
512 + N 512 + N + 1
527
Column address
N*
RY/BY
: V or V
IH
IL
*: Read operation using 50H command N: 0 to 15
2001-03-05 10/43
TC58512FTI
Sequential Read (1) Timing Diagram
CLE
CE
WE
ALE
RE
I/O1
to I/O8
A0
to
A9 A17
to to
00H
A25
N
N + 1 N + 2
527
0
1
2
527
A7 A16 A24
Column
Page
address
M
t
t
R
R
address
N
RY/BY
Page M
access
Page M + 1
access
: V or V
IH
IL
Sequential Read (2) Timing Diagram
CLE
CE
WE
ALE
RE
I/O1
to I/O8
A0
to
A9 A17
to to
01H
A25
527
0
1
2
527
A7 A16 A24
Column
Page
address
M
t
t
R
R
256 + 256 + 256 +
N + 1 N + 2
address
N
N
RY/BY
Page M
access
Page M + 1
access
: V or V
IH
IL
2001-03-05 11/43
TC58512FTI
Sequential Read (3) Timing Diagram
CLE
CE
WE
ALE
RE
I/O1
to I/O8
A9 A17
A0
50H
A25
527
512 513 514
527
to
to
to A7
A16 A24
Column
address
N
Page
t
t
R
R
512 + 512 + 512 +
N + 1 N + 2
address
M
N
RY/BY
Page M
access
Page M + 1
access
: V or V
IH
IL
2001-03-05 12/43
TC58512FTI
Auto-Program Operation Timing Diagram
t
CLS
CLE
CE
t
t
CLH
CLS
t
CS
t
t
CH
CS
WE
ALE
RE
t
t
ALH
ALH
t
t
t
ALS
ALS
PROG
t
WB
t
DS
t
t
t
t
t
t
t
DS DH
DS DH
DH
DS DH
I/O1
to I/O8
A0 to
A7
A9
A17
D
IN
80H
A25
D 0
IN
D 1
IN
10H
70H
to A16 to A24
527
Status
output
RY/BY
: V or V
IH
: Do not input data while data is being output.
IL
Auto Block Erase Timing Diagram
CLE
t
CLS
t
t
CLH
CLS
t
CS
CE
WE
ALE
RE
t
t
t
t
BERASE
ALS
ALH
WB
t
t
DS DH
I/O1
to I/O8
A9
A17
60H
A25
D0H
70H
to A16 to A24
Status
output
Auto Block
Erase Setup
command
Erase Start
command
Status Read
command
RY/BY
Busy
: V or V
IH
: Do not input data while data is being output.
IL
2001-03-05 13/43
TC58512FTI
Multi Block Programming Timing (to be continued)
t
CLS
CLE
CE
t
t
CLS
CLH
t
CS
t
t
CH
CS
WE
ALE
RE
t
t
ALH
ALH
t
t
DBSY
ALS
t
ALS
t
WB
t
DS
t
t
t
t
t
DH
DS DH
DS DH
I/O1
to /O8
A17
A0 to
A7
A9
to A16
A0 to
80H
A25
D 0
IN
D 1
IN
11H
80H
A7
to A24
D 527
IN
RY /BY
: V or V
IH
Auto program (dummy)
IL
Max 3 times repeat
31 times repeat
Last district input
1
2
(Page 0 to 30 programming in multi block)
Max 4 blocks programming
2001-03-05 14/43
TC58512FTI
(continuation 1) Multi Block Programming Timing
t
CLS
CLE
CE
t
t
CLS CLH
t
CS
t
CH
WE
ALE
RE
t
t
ALH
ALH
t
t
MBPBSY
ALS
t
ALS
t
WB
t
DS
t
t
t
t
t
DH
DS DH
DS DH
I/O1
to I/O8
A17
A0 to
A7
A9
to A16
A0 to
80H
A25
D 0
IN
D 1
IN
15H
80H
A7
to A24
D 527
IN
RY /BY
: V or V
IH
Auto program (multi block program)
IL
Max 3
: Do not input data while data is being output.
times
repeat
Last district input
2
3
31 times repeat
Max 3 times repeat
(Page 0 to 30 programming in multi block)
Max 4 blocks programming
2001-03-05 15/43
TC58512FTI
(continuation 2) Multi Block Programming Timing
t
CLS
t
CLE
CE
t
t
CLS
CLH
CS
t
t
CH
CS
WE
ALE
RE
t
t
ALH
ALH
t
t
DBSY
ALS
t
ALS
t
WB
t
DS
t
t
t
t
t
DH
DS DH
DS DH
I/O1
to I/O8
A17
A0 to
A7
A9
to A16
A0 to
80H
A25
D 0
IN
D 1
IN
11H
80H
A7
to A24
D 527
IN
RY /BY
: V or V
IH
Auto program (dummy)
IL
: Do not input data while data is being output.
3
4
Max 3 times repeat
Last district input
(Last pages programming in multi block)
Max 4 blocks programming
2001-03-05 16/43
TC58512FTI
(continuation 3) Multi Block Programming Timing
t
CLS
CLE
CE
t
t
CLS CLH
t
CS
t
CH
WE
ALE
RE
t
t
ALH
ALH
t
t
Prog
ALS
t
ALS
t
WB
t
DS
t
t
t
t
t
t
t
DS DH
DS DH
DH
DS DH
I/O1
to I/O8
A17
A0 to
A7
A9
to A16
80H
A25
D 0
IN
D 1
IN
10H
71H
to A24
Status
output
D 527
IN
RY /BY
: V or V
IH
Auto program (true)
IL
: Do not input data while data is being output.
4
5
Max 3
times
repeat
Last district input
(Last pages programming in multi block)
Max 4 blocks programming
Status read
2001-03-05 17/43
TC58512FTI
Multi Block Erase Timing Diagram
CLE
t
CLS
t
t
CLH
CLS
t
CS
CE
WE
ALE
RE
t
t
t
t
BERASE
ALS
ALH
WB
t
t
DS DH
I/O1
to I/O8
A9 to
A16
A17 to
A24
60H
A25
D0H
71H
Status
output
Auto Block
Erase Start
command
Status Read
command
RY/BY
Busy
Erase Setup
command
Max 4 times repeat
: V or V
IH
IL
: Do not input data while data is being output.
2001-03-05 18/43
TC58512FTI
ID Read (1) Operation Timing Diagram
CLE
t
CLS
t
CLS
t
t
t
CS
CH
CS
CE
WE
ALE
RE
t
CH
t
CR
t
t
t
t
ALH
ALS
ALH
AR1
t
t
t
t
REAID
DS DH
REAID
I/O1
to I/O8
90H
00
98H
76H
Address
input
Maker code Device code
: V or V
IH
IL
ID Read (2) Operation Timing Diagram
CLE
t
CLS
t
CLS
t
t
t
CS
CH
CS
CE
WE
ALE
RE
t
CH
t
CR
t
t
t
t
ALH
ALS
ALH
AR1
t
t
t
REAID
DS DH
I/O1
to I/O8
91H
00
20H
Address
input
: V or V
IH IL
2001-03-05 19/43
TC58512FTI
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs
are configured as shown in Figure 1.
NC
NC
1
48 NC
47 NC
46 NC
45 NC
44 I/O8
43 I/O7
42 I/O6
41 I/O5
40 NC
39 NC
38 NC
Command Latch Enable: CLE
2
NC
3
NC
4
The CLE input signal is used to control loading of the
operation mode command into the internal command
register. The command is latched into the command
register from the I/O port on the rising edge of the WE
signal while CLE is High.
NC
5
GND
RY/BY
RE
6
7
8
9
CE
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
V
37
36
V
CC
V
SS
CC
V
SS
Address Latch Enable: ALE
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
35 NC
34 NC
33 NC
32 I/O4
31 I/O3
30 I/O2
29 I/O1
28 NC
27 NC
26 NC
25 NC
The ALE signal is used to control loading of either
address information or input data into the internal
address/data register.
Address information is latched on the rising edge of
WE if ALE is High.
Input data is latched if ALE is Low.
Figure 1. Pinout
CE
Chip Enable:
The device goes into a low-power Standby mode when CE goes High during a Read operation. The CE
signal is ignored when device is in Busy state (RY/BY = L), such as during a Program or Erase operation, and
will not enter Standby mode even if the CE input goes High. The CE signal must stay Low during the Read
mode Busy state to ensure that memory array data is correctly transferred to the data register.
WE
Write Enable:
The WE signal is used to control the acquisition of data from the I/O port.
RE
Read Enable:
The RE signal controls serial data output. Data is available t
after the falling edge of RE .
REA
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the
device.
WP
Write Protect:
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
RY/BY
Ready/Busy:
The RY/BY output signal is used to indicate the operating condition of the device. The RY/BY signal is in
Busy state ( RY/BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY/BY = H) after completion of the operation. The output buffer for this signal is an open drain.
2001-03-05 20/43
TC58512FTI
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1
A page consists of 528 bytes in which 512 bytes are used for
I/O8
main memory storage and 16 bytes are for redundancy or for
other uses.
512
16
1 page = 528 bytes
1 block = 528 bytes × 32 pages = (16K + 512) bytes
Capacity = 528 bytes × 32 pages × 4096 blocks
32 pages
1 block
131072 pages
4096 blocks
An address is read in via the I/O port over four consecutive
clock cycles, as shown in Table 1.
8I/O
528
Figure 2. Schematic Cell Layout
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0 to A7 : Column address
A9 to A25 : Page address
First cycle
A7
A16
A24
*L
A6
A15
A23
*L
A5
A14
A22
*L
A4
A13
A21
*L
A3
A12
A20
*L
A2
A11
A19
*L
A1
A10
A18
*L
A0
A9
Second cycle
Third cycle
Fourth cycle
A14 to A25 : Block address
A9 to A13 : NAND address in block
A17
A25
* : A8 is automatically set to Low or High by a 00H command or a 01H command.
* : l/O2 to l/O8 must be set to Low in the fourth cycle.
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the fourteen different
command operations shown in Table 3. Address input, command input and data input/output are controlled by
the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2.
Table 2. Logic Table
CLE
ALE
CE
WE
RE
WP
Command Input
H
L
L
L
*
L
L
H
L
*
L
L
L
L
*
*
*
H
H
H
*
*
Data Input
Address Input
*
Serial Data Output
During Programming (Busy)
During Erasing (Busy)
Program, Erase Inhibit
H
*
*
*
*
*
H
H
L
*
*
*
*
*
*
H: V , L: V , *: V or V
IL
IH
IL
IH
2001-03-05 21/43
TC58512FTI
Table 3. Command table (HEX)
First Cycle Second Cycle Acceptable while Busy
Serial Data Input
Read Mode (1)
Read Mode (2)
Read Mode (3)
Reset
80
00
01
50
FF
10
11
HEX data bit assignment
(Example)
Serial Data Input: 80H
Q
1
0
0
6
0
5
0
4
0
3
0
2
0
Auto Program (True)
Auto Program (Dummy)
I/O8 7
I/O1
Auto Program
(Multi Block Program)
15
Auto Block Erase
Status Read (1)
Status Read (2)
ID Read (1)
60
70
71
90
91
D0
Q
Q
ID Read (2)
Once the device has been set to Read mode by a 00H, 01H or 50H command, additional Read commands are
not needed for sequential page Read operations.
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states
CLE
ALE
CE
WE
RE
I/O1 to I/O8
Power
Output Select
Output Deselect
Standby
L
L
L
L
L
L
L
L
H
H
H
L
H
*
Output
Active
Active
High impedance
High impedance
H
Standby
H: V , L: V , *: V or V
IL
IH
IL
IH
2001-03-05 22/43
TC58512FTI
DEVICE OPERATION
Read Mode (1)
Read mode (1) is set when a “00H” command is issued to the Command register. Refer to Figure 3 below for
timing details and the block diagram.
CLE
CE
WE
ALE
RE
RY/BY
Busy
N
M
I/O
00H
M
Start-address
input
A data transfer operation from the cell array to the register
527
starts on the rising edge of WE in the fourth cycle (after the
address information has been latched). The device will be in
Busy state during this transfer period. The CE signal must stay
Low after the fourth address input and during Busy state.
After the transfer period the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start pointer designated in the address input cycle.
Select page
N
Cell array
Figure 3. Read mode (1) operation
Read Mode (2)
CLE
CE
WE
ALE
RE
RY/BY
I/O
Busy
N
M
01H
Start-address
input
256
M
527
The operation of the device after input of the 01H command is
the same as that of Read mode (1). If the start pointer is to be set
after column address 256, use Read mode (2).
Select page
N
However, for a Sequential Read, output of the next page starts
from column address 0.
Cell array
Figure 4. Read mode (2) operation
2001-03-05 23/43
TC58512FTI
Read Mode (3)
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra
16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527.
CLE
CE
WE
ALE
RE
RY/BY
I/O
Busy
50H
Addresses bits A0 to A3 are used to set the start pointer for the
A0 to
A3
redundant memory cells, while A4 to A7 are ignored.
Once a “50H” command has been issued, the pointer moves to
the redundant cell locations and only those 16 cells can be
addressed, regardless of the value of the A4-to-A7 address.
(A “00H” command is necessary to move the pointer back to
the 0-to-511 main memory cell location.)
512
527
Figure 5. Read mode (3) operation
Sequential Read (1) (2) (3)
This mode allows the sequential reading of pages without additional address input.
00H
01H
Address input
Data output
Data output
(50H)
50H
t
t
t
R
R
R
RY/BY
Busy
Busy
527
Busy
(00H)
0
527
(01H) 256
A
512 527
A
A
Sequential Read (1)
Sequential Read (2)
Sequential Read (3)
Sequential Read modes (1) and (2) output the contents of addresses 0 to 527 as shown above, while Sequential
Read mode (3) outputs the contents of the redundant address locations only.
When the pointer reaches the last address, the device continues to output the data from this address** on each
RE clock signal.
** Column address 527 on the last page
2001-03-05 24/43
TC58512FTI
Status Read
The TC58512 has two Status Read commands. One is Status Read (1) command “70H” and the other is Status
Read (2) command “71H”.
The device automatically implements the execution and verification of the Program and Erase operations. The
Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of a
Program or Erase operation, and determine whether the device is in Protect mode. The device status is output
via the I/O port on the RE clock after a Status Read command “70H” or “71H” input.
The resulting information of Status Read (1) command “70H” is outlined in Table 5 below and the resulting
information of Status Read (2) command “71H” is outlined in the explanation for Multi Block Program and Multi
Block Erase toward the end of this document.
Table 5. Status output table for Status Read (1) command “70H”
STATUS
OUTPUT
Fail: 1
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
Pass/Fail
Not Used
Pass: 0
0
Not Used
0
The Pass/Fail status on I/O1 is only
valid when the device is in the Ready
state.
Not Used
0
Not Used
0
Not Used
0
Ready/Busy
Write Protect
Ready: 1
Protect: 0
Busy: 0
Not Protected: 1
An application example with multiple devices is shown in Figure 6.
CE1
CE2
CE3
CEN
CEN +1
CLE
ALE
WE
RE
Device
1
Device
2
Device
3
Device
N
Device
N + 1
I/O1
to I/O8
RY/BY
RY/BY
CLE
ALE
WE
Busy
CE1
CEN
RE
I/O
70H
70H
Status on Device 1
Status on Device N
Figure 6. Status Read timing application example
System Design Note: If the RY/BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.
2001-03-05 25/43
TC58512FTI
Auto Page Program
The device carries out an Automatic Page Program operation when it receives a “10H” Program command after
the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
Pass
80
10
70
I/O
Fail
Data input Address Data input Program
command input
Status Read
command
0 to 527 command
RY/BY
RY/BY automatically returns to Ready after
completion of the operation.
Data input
Program
Reading & verification
Selected
page
The data is transferred (programmed) from the register to the selected
page on the rising edge of WE following input of the “10H” command.
After programming, the programmed data is transferred back to the
register to be automatically verified by the device. If the programming
does not succeed, the Program/Verify operation is repeated by the device
until success is achieved or until the maximum loop number set in the
device is reached.
Figure 7. Auto Page Program operation
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0H”
which follows the Erase Setup command “80H”. This two-cycle process for Erase operations acts as an ertra layer
of protection from aceidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Pass
60
D0
70
I/O
Fail
Block Address Erase Start
input: 3 cycles command
Status Read
command
RY/BY
Busy
2001-03-05 26/43
TC58512FTI
Multi Block Program
The device carries out an Multi Block Program operation when it receives a “15H” or “10H” Program command
after some sets of the address and data have been input.
In the interval of the Multi District adress and the (512 + 16 byte) data input, “11H” Dummy Program
command is used when it still continues the data input into another District.
The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)
Dummy
Program
command
Dummy
Program
command
Dummy
Program
command
Multi block
Program
command
Data input
command
Data input
command
Data input
command
Data input
command
80
11
80
11
80
11
80
15
Address Data input
Address Data input
input 0 to 527
Address Data input
input 0 to 527
Address Data input
input 0 to 527
input
0 to 527
RY/BY
80
11
80
11
80
11
80
15
Data input
(District 0)
(District 1)
(District 2)
(District 3)
After “15H” Multi Block Program command, physical programing starts as follows.
Program
Selected
page
Reading & verification
The data is transferred (programmed) from the register to the selected page on the rising edge of -WE
following input of the “15H” command. After programming, the programmed data is transferred back to the
register to be automatically verified by the device. If the programming does not succeed, the
Program/Verify operation is repeated by the device until success is achieved or until the maximum loop
number set in the device is reached.
2001-03-05 27/43
TC58512FTI
Starting the above operation from 1st page of the selected erase blocks, and then repeating the operation total
31 times with incrementing the page address in the blocks, and then input the last page data of the blocks, “10H”
command executes final programming.
In this full sequence, the command sequence is following.
80
80
11
11
80
80
11
11
80
80
11
11
80
80
15
15
1st
80
80
11
11
80
80
11
11
80
80
11
11
80
80
15
10
31st
32nd
After the “10H” command, the total results of the above operation is shown through the Status Read command.
Pass
10
71
I/O
Status Read
command
Fail
RY/BY
The Status discription is following.
STATUS
OUTPUT
Fail: 1
I/O1 describes total Pass/Fail condition.
If at least one fail occurred in 32 times × 4
(512 + 16 byte) page write operation, it
shows “Fail” condition.
I/O1
Total Pass/Fail
District 0 Pass/Fail
District 1 Pass/Fail
District 2 Pass/Fail
District 3 Pass/Fail
Not Used
Pass: 0
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
Pass: 0
Fail: 1
Fail: 1
Fail: 1
Fail: 1
Pass: 0
I/O2 describes total Pass/Fail condition.
If more than one fail occurred in 32 times ×
1 (512 + 16 byte) page write operation in
District 0 area, it shows “Fail” condition.
Pass: 0
Pass: 0
Do not care
Ready: 1
Protect: 0
I/O3, I/O4 and I/O5 are as same manner
as I/O2.
Ready/Busy
Busy: 0
Write Protect
Not Protect: 1
2001-03-05 28/43
TC58512FTI
Internal addressing in relation with the Districts
To use Multi Block Program operation, the internal addressing should be conscious in relation with the
District.
•
•
•
The device consists from 4 Districts.
Each District consists from 1024 erase blocks.
The allocation rule is follows.
District 0: Block 0, Block 4, Block 8, Block 12, ···.., Block 4092
District 1: Block 1, Block 5, Block 9, Block 13, ···.., Block 4093
District 2: Block 2, Block 6, Block10, Block 14, ···.., Block 4094
District 3: Block 3, Block 7, Block11, Block 15, ···.., Block 4095
Address input restriction for the Multi Block Program operation
In selecting the blocks for the Multi Block Program operation, following is the restriction and acceptance.
(Restriction)
Maximum one block should be selected from each District.
The data input operation should be started from the same number page of the each selected block and then, the
page number in the blocks should be same number at the same time programming.
(Acceptance)
There is no order limitation of the District for the address input.
Any number of the District can be select for the programming.
So, for example, following operation is in acceptance.
(80) [District 2] (11) (80) [District 0] (11) (80) [District 1] (15)
It requires no mutual address relation between the selected blocks from each District.
Operating restriction during the Multi Block Program operation
(Restriction)
Starting from 1st page data input, until issuing “10H” command, any other command out of defined sequence can
not be issued except Status Read command and Reset command.
(Acceptance)
The data input operation can be terminated with “10H” command instead of “15H” command in the middle of the
page number in the block.
In this case the Status represents the reflected value accumulated from 1st page programming of this sequence
and up to the last page programming terminated by “10H” command.
Status Read operation
Untill the Ready condition after the programming terminated by “10H” command, effective bit in the Status
data is limited on Ready/Busy bit.
In other words, Pass/Fail condition can be checked only in the Ready condition after “10H” command.
2001-03-05 29/43
TC58512FTI
Multi Block Erase
The device carries out a Multi Block Erase operation when it receives a “D0H” command after some sets of the
address have been input.
After the “D0H” command, the total results of Erase operation is shown through the Status Read (2) command
“71H”.
Pass
D0
71
I/O
Status Read
command
Fail
RY/BY
The Status discription is following.
STATUS
OUTPUT
Fail: 1
I/O1 describes total Pass/Fail condition.
If at least one fail occurred in Max 4 Blocks
erase operation, it shows “Fail” condition.
I/O1
Total Pass/Fail
District 0 Pass/Fail
District 1 Pass/Fail
District 2 Pass/Fail
District 3 Pass/Fail
Not Used
Pass: 0
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
Pass: 0
Fail: 1
Fail: 1
Fail: 1
Fail: 1
Pass: 0
I/O2 describes Pass/Fail condition.
If fail occurred in District 0 area, it shows
“Fail” condition.
Pass: 0
Pass: 0
I/O3, I/O4 and I/O5 are as same manner
as I/O2.
Do not care
Ready: 1
Protect: 0
Ready/Busy
Busy: 0
Write Protect
Not Protect: 1
Internal addressing in relation with the Districts
To use Multi Block Erase operation, the internal addressing should be conscious in relation with the Districts.
•
•
•
The device consists from 4 Districts.
Each District consists from 1024 erase blocks.
The allocation rule is follows.
District 0: Block 0, Block 4, Block 8, Block 12, ···.., Block 4092
District 1: Block 1, Block 5, Block 9, Block 13, ···.., Block 4093
District 2: Block 2, Block 6, Block10, Block 14,···.., Block 4094
District 3: Block 3, Block 7, Block11, Block 15, ···.., Block 4095
Address input restriction for the Multi Block Erase operation
In selecting the blocks for the Multi Block Erase operation, following is the restriction and acceptance.
(Restriction)
Maximum one block should be selected from each District.
(Acceptance)
There is no order limitation of the District for the address input.
Any number of the Districts can be select for the erase operation.
So, for example, following operation is in acceptance.
(60) [District 2] (60) [District 0] (60) [District 1] (D0)
It requires no mutual address relation between the selected blocks from each District.
2001-03-05 30/43
TC58512FTI
Reset
The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally
generated voltage is discharged to 0 volts and the device enters Wait state.
The response to an “FFH” Reset command input during the various device operations is as follows:
When a Reset (FFH) command is input during programming
Figure 8.
80
10
FF
00
Internal V
PP
RY/BY
t
(max 10 µs)
RST
When a Reset (FFH) command is input during erasing
Figure 9.
00
D0
FF
Internal erase
voltage
RY/BY
t
(max 500 µs)
RST
When a Reset (FFH) command is input during Read operation
Figure 10.
00
00
FF
RY/BY
t
(max 6 µs)
RST
When a Status Read command (70H) is input after a Reset
Figure 11.
FF
70
I/O status: Pass/Fail → Pass
Ready/Busy → Ready
RY/BY
FF
70
I/O status: Ready/Busy → Busy
RY/BY
When two or more Reset commands are input in succession
Figure 12.
(1)
FF
(2)
FF
(3)
FF
RY/BY
FF
FF
The second
command is invalid, but the third
command is valid.
2001-03-05 31/43
TC58512FTI
ID Read (1)
The TC58512 contains ID codes which identify the device type and the manufacturer.
The TC58512 has 2 types of ID read command, i.e. ID Read (1) command 90H and ID Read (2) command 91H.
ID Read (1) command 90H provides maker code and device code. The ID codes can be read out under the
following timing conditions:
CLE
t
CR
CE
WE
ALE
RE
t
AR1
t
REAID
I/O
90H
00
98H
76H
ID Read command (1)
Address
00
Maker code
Device code
For the specifications of the access times t
, t
and t
refer to the AC Characteristics.
AR1
REAID CR
Figure 13. ID Read timing
Table 6. ID Codes read out by ID read command (1) 90H
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Hex Data
Maker code
Device code
1
0
0
1
0
1
1
1
1
0
0
1
0
1
0
0
98H
76H
2001-03-05 32/43
TC58512FTI
ID Read (2)
ID Read (2) command 91H provides ×4-block mode availability. If ID code read out by 91H is 20H, it indicates
the device has ×4-block mode.
CLE
t
CR
CE
WE
ALE
RE
t
AR1
t
REAID
I/O
91H
00
20H
ID Read command (2)
Address
00
Extended ID code
For the specifications of the access times t
, t
and t
refer to the AC Characteristics.
AR1
REAID CR
Figure 14. ID Read timing
Table 7. ID Codes read out by command 91H
I/O8
0
I/O7
0
I/O6
1
I/O5
0
I/O4
0
I/O3
0
I/O2
0
I/O1
0
Hex Data
20H
Extended ID code
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TC58512FTI
APPLICATION NOTES AND COMMENTS
(1)
Power-on/off sequence:
The WP signal is useful for protecting against data corruption at power-on/off. The following timing
sequence is necessary.
The WP signal may be negated any time after the V
power up sequence.
reaches 2.5 V and CE signal is kept high in
CC
2.7 V
2.5 V
V
CC
0 V
Don’t
care
Don’t
care
CE , WE , RE
CLE, ALE
V
IH
V
V
IL
IL
WP
Operation
Figure 15. Power-on/off Sequence
In order to operate this device stably, after V
CC
becomes 2.5 V, it recommends starting access after about
200 µs.
(2)
(3)
Status after power-on
The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
Figure 16.
Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4)
(5)
Restriction of command while Busy state
During Busy state, do not input any command except 70H, 71H and FFH.
Acceptable commands after Serial Input command “80H”
Once the Serial Input command “80H” has been input, do not input any command other than the Program
Execution command “10H”, “11H” or “15H” or the Reset command “FFH”.
If a command other than “10H”, “11H”, “15H” or “FFH” is input, the Program operation is not performed.
80
XX
10
For this operation the “FFH” command is needed.
Command other than
“10H”, “11H”, “15H” or “FFH”
Programming cannot be executed.
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TC58512FTI
(6)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (32)
DATA IN: Data (1)
Data (32)
Data register
Data register
Page 0
Page 1
Page 2
Page 0
Page 1
Page 2
(1)
(2)
(3)
(2)
(16)
(3)
Page 15
Page 31
Page 15
(16)
(32)
(1)
Page 31
(32)
Figure 17. page programming within a block
(7)
Status Read during a Read operation
00
[A]
command
CE
00
70
WE
RY/BY
RE
Status Read
command input
Address N
Status Read
Status output
Figure 18.
The device status can be read out by inputting the Status Read command “70H” in Read mode.
Once the device has been set to Status Read mode by a “70H” command, the device will not return to Read
mode.
Therefore, a Status Read during a Read operation is prohibited.
However, when the Read command “00H” is input during [A], Status mode is reset and the device returns
to Read mode. In this case, data output starts automatically from address N and address input is unnecessary
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TC58512FTI
(8)
Pointer control for “00H”, “01H” and “50H”
The device has three Read modes which set the destination of the pointer. Table 7 shows the destination of
the pointer, and Figure 14 is a block diagram of their operations.
Table 8. Pointer Destination
0
255 256
511 512 527
C
A
B
Read Mode
Command
Pointer
(1)
(2)
(3)
00H
01H
50H
0 to 255
256 to 511
512 to 527
(1) 00H
(2) 01H
(3) 50H
Pointer control
Figure 19. Pointer control
The pointer is set to region A by the “00H” command, to region B by the “01H” command, and to region C by
the “50H” command.
(Example)
The “00H” command must be input to set the pointer back to region A when the pointer is pointing to region
C.
00H
50H
01H
50H
Add
Add
Add
Start point
A area
Add
Add
Add
Start point
A area
Add
Add
Start point
C area
00H
Start point
C area
Start point
C area
Start point
A area
Start point
B area
Start point
A area
To program region C only, set the start point to region C using the 50H command.
50H
80H
10H
Add
Add
DIN
DIN
Start point
C Area
Programming region C only
Programming region B and C
01H
80H
10H
Start point
B Area
Figure 20. Example of How to Set the Pointer
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TC58512FTI
(9)
RY/BY : termination for the Ready/Busy pin ( RY/BY )
A pull-up resistor needs to be used for termination because the RY/BY buffer consists of an open drain
circuit.
V
CC
Ready
3.0 V
V
CC
V
CC
3.0 V
R
Device
1.0 V
Busy
1.0 V
RY/BY
C
L
t
t
r
f
V
SS
V
= 3.3 V
CC
Ta = 25°C
1.5 µs
1.0 µs
0.5 µs
15 ns
10 ns
5 ns
Figure 21.
C
= 100 pF
L
t
f
t
t
f
r
t
r
This data may vary from device to device.
We recommend that you use this data as a reference
when selecting a resistor value.
0
1 KΩ
2 KΩ
3 KΩ
4 KΩ
R
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TC58512FTI
(10)
Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:
Enable Programming
WE
80
10
10
D0
D0
DIN
WP
RY/BY
t
(100 ns min)
WW
Disable Programming
WE
DIN
80
WP
RY/BY
t
(100 ns min)
WW
Enable Erasing
WE
DIN
60
WP
RY/BY
t
(100 ns min)
WW
Disable Erasing
WE
DIN
60
WP
RY/BY
t
(100 ns min)
WW
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TC58512FTI
(11)
When five address cycles are input
Although the device may read in a fifth address, it is ignored inside the chip.
Read operation
CLE
CE
WE
ALE
I/O
00H, 01H or 50H
Address input
ignored
RY/BY
WE Internal read operation starts when WE goes High in the fourth cycle.
Figure 22.
Program operation
CLE
CE
WE
ALE
I/O
80H
Address input
Data input
ignored
Figure 23.
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TC58512FTI
(12)
Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 3 segments. Each segment can be programmed individually as follows:
1st programming
2nd programming
nth programming
Result
Data Pattern 1
All 1s
All 1s
All 1s
Data Pattern 2
All 1s
Data Pattern 3
Data Pattern 3
Data Pattern 1
Data Pattern 2
Figure 24.
Note: The input data for unprogrammed or previously programmed page segments must be “1”
(i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all “1”).
(13)
Note regarding the RE signal
RE The internal column address counter is incremented synchronously with the RE clock in Read mode.
Therefore, once the device has been set to Read mode by a “00H”, “01H” or “50H” command, the internal
column address counter is incremented by the RE clock independently of the address input timing, If the
RE clock input pulses start before the address input, and the pointer reaches the last column address, an
internal read operation (array to register) will occur and the device will enter Busy state. (Refer to Figure 25.)
Address input
I/O
WE
RE
00H/01H/50H
RY/BY
Figure 25.
Hence the RE clock input must start after the address input.
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TC58512FTI
(14)
Invalid blocks (bad blocks)
The device contains unusable blocks. Therefore, at the time of use, please check whether a block is bad and
do not use these bad blocks.
At the time of shipment, all data bytes in a Valid Block are FFH. For Bad
Block, all bytes are not in the FFH state. Please don’t perform erase
operation to Bad Block.
Bad Block
Check if the device has any bad blocks after installation into the system.
Figure 27 shows the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
isolated from the Bit line by the Select gate
Bad Block
Figure 26.
The number of valid blocks at the time of shipment is as follows:
MIN
TYP.
MAX
4096
UNIT
Block
Valid (Good) Block Number
4016
Bad Block Test Flow
Read Check: to verify all pages in the block
with FF (Hex)
Start
Block No = 1
Fail
Read Check
Pass
Block No. = Block No. + 1
Bad Block *1
No
Block No. = 4096
Yes
End
*1: No erase operation is allowed to detected bad blocks
Figure 27
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TC58512FTI
(15)
Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE
Erase Failure
DETECTION AND COUNTERMEASURE SEQUENCE
Status Read after Erase → Block Replacement
Block
Page
Programming
Failure
Status Read after Program → Block Replacement
Programming
Failure
1 → 0
(1) Block Verify after Program → Retry
Single Bit
(2) ECC
•
•
ECC: Error Correction Code
Block Replacement
Program
Error occurs
When an error happens in Block A, try to
reprogram the data into another Block (Block B)
by loading from an external buffer. Then,
prevent further system accesses to Block A (by
creating a bad block table or by using an
another appropriate scheme).
Buffer
memory
Block A
Block B
Figure 28.
Erase
When an error occurs in an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).
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TC58512FTI
Package Dimensions
Weight: 0.53 g (typ.)
2001-03-05 43/43
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