XC61GN5902HL [TOREX]

Power Management Circuit;


型号：	XC61GN5902HL
厂家：	Torex Semiconductor
描述：	Power Management Circuit
文件：	总16页 (文件大小：1377K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC61GSeries

ETR0203_001

Low Voltage Detectors (V_DF= 0.8V～1.5V)

Standard Voltage Detectors (V_DF1.6V～6.0V)

■GENERAL DESCRIPTION

The XC61G series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser

trimming technologies.

Detect voltage is extremely accurate with minimal temperature drift.

Both CMOS and N-channel open drain output

configurations are available.

■APPLICATIONS

■FEATURES

Highly Accurate

: ±2%

●Microprocessor reset circuitry

●Memory battery back-up circuits

●Power-on reset circuits

Low Power Consumption : 0.7 μA [ VIN=1.5V ] (TYP.)

Detect Voltage Range

: 0.8V ~ 1.5V in 100mV

increments (Low Voltage)

: 1.6V～6.0V in 100mV

increments (Standard Voltage)

●Power failure detection

Operating Voltage Range : 0.7V ~ 6.0V (Low Voltage)

0.7V 10.0V (Standard Voltage)

●System battery life and charge voltage monitors

～

Detect Voltage Temperature characteristics

: ±100ppm/℃ (TYP.)

Output Configuration

CMOS

: N-channel open drain or CMOS

Ultra Small Package

: USP-3 (120mW)

■TYPICAL APPLICATION CIRCUITS

■TYPICAL PERFORMANCE CHARACTERISTICS

1/16

XC61G Series

■PIN CONFIGURATION

■PIN ASSIGNMENT

PIN NUMBER

PIN NAME

FUNCTION

USP-3

VIN

VSS

Supply Voltage

Ground

VOUT

Output

■PRODUCT CLASSIFICATION

●Ordering Information

XC61G ①②③④⑤⑥⑦

DESIGNATOR

DESCRIPTION

SYMBOL

DESCRIPTION

: CMOS output

①

Output Configuration

: N-ch open drain output

: e.g. 0.8V → ②0, ③8

: e.g. 1.5V → ②1, ③5

: No delay

② ③

Detect Voltage

08 ~ 60

④

⑤

⑥

Output Delay

Detect Accuracy

Package

: Within ±2%

: USP-3

: Embossed tape, standard feed

: Embossed tape, reverse feed

⑦

Device Orientation

■BLOCK DIAGRAMS

(1) CMOS Output

(2) N-ch Open Drain Output

2/16

XC61G

Series

■ABSOLUTE MAXIMUM RATINGS

Ta = 25℃

PARAMETER

Input Voltage

SYMBOL

RATINGS

9.0

UNITS

VIN

12.0

Output Current

IOUT

CMOS

VSS -0.3 ~ VIN +0.3

VSS -0.3 ~ 9.0

VSS -0.3 ~ 12.0

120

Output Voltage

Power Dissipation

VOUT

N-ch Open Drain Output *1

N-ch Open Drain Output *2

USP-3

℃

Operating Temperature Range

Storage Temperature Range

Topr

Tstg

-40～+85

-40～+125

℃

■ELECTRICAL CHARACTERISTICS

VDF (T) = 0.9 to 1.5V ± 2%

Ta=25℃

PARAMETER

Detect Voltage

SYMBOL

VDF

CONDITIONS

MIN.

VDF

TYP.

VDF

MAX.

VDF

UNITS CIRCUITS

x 0.98

VDF

x 1.02

VDF

Hysteresis Range

VHYS

x 0.02 x 0.05 x 0.08

0.7

0.8

0.9

1.0

1.1

2.3

2.7

3.0

3.2

3.6

6.0

10.0

VIN = 1.5V

VIN = 2.0V

VIN = 3.0V

VIN = 4.0V

VIN = 5.0V

Supply Current

ISS

μA

VDF(T) = 0.9V to 1.5V

VDF(T) = 1.6V to 6.0V

0.7

Operating Voltage

VIN

VIN =0.7V 0.10

VIN =1.0V 0.85

0.80

N-ch, VDS = 0.5V

Output Current

(Low Voltage)

2.70

-7.5

2.2

CMOS, P-ch, VDS=2.1V

VIN =6.0V

VIN =1.0V

VIN =2.0V

VIN =3.0V

VIN =4.0V

VIN =5.0V

-1.5

1.0

3.0

5. 0

6.0

7.0

7.7

IOUT

N-ch, VDS = 0.5V

10.1

11.5

13.0

Output Current

(Standard Voltage)

CMOS,

P-ch, VDS=2.1V

VIN =8.0V

-10.0

-2.0

Temperature

Characteristics

ΔVDF

ppm/

℃

-40℃ ≦ Topr ≦ 85℃

±100

Topr･

VDF

Delay Time

tDLY

0.2

(VDR → VOUT inversion)

NOTE:

V^DF(T): Setting detect voltage

Release Voltage: V^DR= VDF + VHYS

3/16

XC61G Series

■OPERATIONAL EXPLANATION

●CMOS output

① When input voltage (VIN) rises above detect voltage (VDF), output voltage (VOUT) will be equal to VIN.

(A condition of high impedance exists with N-ch open drain output configurations.)

② When input voltage (VIN) falls below detect voltage (VDF), output voltage (VOUT) will be equal to the ground voltage

(VSS) level.

③ When input voltage (VIN) falls to a level below that of the minimum operating voltage (VMIN), output will become

unstable. In this condition, VIN will equal the pulled-up output (should output be pulled-up.)

④ When input voltage (VIN) rises above the ground voltage (VSS) level, output will be unstable at levels below the

minimum operating voltage (VMIN). Between the VMIN and detect release voltage (VDR) levels, the ground voltage (VSS)

level will be maintained.

⑤ When input voltage (VIN) rises above detect release voltage (VDR), output voltage (VOUT) will be equal to VIN.

(A condition of high impedance exists with N-ch open drain output configurations.)

⑥ The difference between VDR and VDF represents the hysteresis range.

●Timing Chart

4/16

XC61G

Series

■NOTES ON USE

1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent

damage to the device.

2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur

as a result of voltage drops at RIN if load current (IOUT) exists. (refer to the Oscillation Description (1) below)

3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch

output configurations, oscillation may occur as a result of through current at the time of voltage release even if load

current (IOUT) does not exist. (refer to the Oscillation Description (2) below )

4. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's

supply current flowing through the VIN pin.

5. In order to stabilize the IC's operations, please ensure that VIN pin's input frequency's rise and fall times are more than

several μ sec / V.

6. Please use N-ch open drains configuration, when a resistor RIN is connected between the VIN pin and power source.

In such cases, please ensure that RIN is less than 10kΩ and that C is more than 0.1μF.

●Oscillation Description

(1) Output current oscillation with the CMOS output configuration

When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load

current (IOUT) will flow at RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor, located between the

input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the

voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will

commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the

voltage level at the VIN pin will rise and release operations will begin over again.

Oscillation may occur with this " release - detect - release " repetition.

Further, this condition will also appear via means of a similar mechanism during detect operations.

(2) Oscillation as a result of through current

Since the XC61G series are CMOS IC S, through current will flow when the IC's internal circuit switching operates (during

release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at the through

current's resistor (RIN) during release voltage operations. (refer to Figure 3 )

Since hysteresis exists during detect operations, oscillation is unlikely to occur.

5/16

XC61G Series

■TEST CIRCUITS

6/16

XC61G

Series

■TYPICAL PERFORMANCE CHARACTERISTICS

●Low Voltage

7/16

XC61G Series