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T431616E [TMT]

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM; 1M ×16 SDRAM 512K X 16位X 2Banks同步DRAM
T431616E
型号： T431616E
厂家： TAIWAN MEMORY TECHNOLOGY    TAIWAN MEMORY TECHNOLOGY
描述：

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
1M ×16 SDRAM 512K X 16位X 2Banks同步DRAM

动态存储器
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TE  
tmCH  
T431616D/E  
1M x 16 SDRAM  
SDRAM  
512K x 16bit x 2Banks Synchronous DRAM  
FEATURES  
GRNERAL DESCRIPTION  
Fast access time: 5/6/7 ns  
The T431616D/E SDRAM is a high-speed CMOS  
synchronous DRAM containing 16 Mbits. It is internally  
configured as a dual 512K word x 16 DRAM with a  
synchronous interface (all signals are registered on the  
positive edge of the clock signal, CLK). Each of the  
512K x 16 bit banks is organized as 2048 rows by 256  
columns by 16 bits. Read and write accesses to the  
SDRAM are burst oriented; accesses start at a selected  
location and continue for a programmed number of  
locations in a programmed sequence. Accesses begin  
with the registration of a BankActivate command which  
is then followed by a Read or Write command.  
Fast clock rate: 200/166/143 MHz  
Self refresh mode: standard and low power  
Internal pipelined architecture  
512K word x 16-bit x 2-bank  
Programmable Mode registers  
- CAS# Latency: 1, 2, or 3  
•
•
•
•
•
- Burst Length: 1, 2, 4, 8, or full page  
- Burst Type: interleaved or linear burst  
- Burst stop function  
Individual byte controlled by LDQM and UDQM  
Auto Refresh and Self Refresh  
4096 refresh cycles/64ms  
•
•
•
•
•
•
•
•
•
The T431616D/E provides for programmable Read  
or Write burst lengths of 1, 2, 4, 8, or full page, with a  
burst termination option. An auto precharge function  
may be enabled to provide a self-timed row precharge  
that is initiated at the end of the burst sequence. The  
refresh functions, either Auto or Self Refresh are easy to  
use. By having a programmable mode register, the  
system can choose the most suitable modes to maximize  
its performance. These devices are well suited for  
applications requiring high memory bandwidth and  
particularly well suited to high performance PC  
applications  
CKE power down mode  
JEDEC standard +3.3V 0.3V power supply  
Interface: LVTTL  
±
50-pin 400 mil plastic TSOP II package  
60-ball, 6.4x10.1mm VFBGA package  
Lead Free Package available for both TSOP II and  
VFBGA  
Low Operating Current for T431616E  
•
Key Specifications  
T431616D/E  
-5/6/7  
5/6/7ns  
tCK3  
tRAS  
tAC3  
tRC  
Clock Cycle time(min.)  
Row Active time(max.)  
Access time from CLK(max.)  
Row Cycle time(min.)  
35/42/42 ns  
4.5/5/5.5 ns  
48/54/63 ns  
ORDERING INFORMATION  
Part Number  
T431616D-5S/C  
T431616D-5SG/CG  
T431616D-6S/C  
T431616D-6SG/CG  
T431616D-7S/C  
T431616D-7SG/CG  
T431616E-7S/C  
Frequency  
200MHz  
200MHz  
166MHz  
166MHz  
143MHz  
143MHz  
143MHz  
143MHz  
Package  
TSOP II / VFBGA  
TSOP II / VFBGA  
TSOP II / VFBGA  
TSOP II / VFBGA  
TSOP II / VFBGA  
TSOP II / VFBGA  
TSOP II / VFBGA  
TSOP II / VFBGA  
T431616E-7SG/CG  
G : indicates Lead Free Package  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 1  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
PIN ARRANGEMENT  
TSOP-II (Top View)  
BGA (Top View)  
1
2
3
4
5
6
7
V D D  
D Q 0  
D Q 1  
V SSQ  
D Q 2  
D Q 3  
V D D Q  
D Q 4  
D Q 5  
V SSQ  
V ss  
1
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
A
B
C
D
E
F
DQ0  
VDD  
VSS  
DQ15  
D Q 15  
D Q 14  
V SSQ  
D Q 13  
D Q 12  
V D D Q  
D Q 11  
D Q 10  
V SSQ  
D Q 9  
D Q 8  
V D D Q  
N .C  
2
3
DQ1  
DQ2  
DQ3  
DQ5  
DQ6  
DQ7  
DQ14  
VDDQ  
VSSQ  
DQ4  
VSSQ  
4
DQ13 VDDQ  
5
6
DQ12  
DQ11  
7
8
VDDQ  
VSSQ  
NC  
DQ10 VSSQ  
9
10  
11  
12  
13  
DQ9  
DQ8  
VDDQ  
NC  
D Q 6  
D Q 7  
50PIN T SO P(II)  
(400m il x 825m il)  
(0.8 m m P IN P IT C H )  
G
H
V D D Q  
NC  
NC  
NC  
NC  
NC  
NC  
LD Q M  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
U D Q M  
C LK  
C K E  
N .C  
W E  
C A S  
R A S  
C S  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
LDQM  
J
K
L
WE#  
UDQM  
RAS#  
NC  
CLK  
CAS#  
NC  
A9  
CS#  
NC  
A 11  
A 10  
A 9  
CKE  
A11  
A8  
A 8  
NC  
M
N
A 0  
A 1  
A 7  
A 6  
A0  
A10  
A7  
A5  
A4  
A 2  
A 5  
A 3  
A 4  
P
R
A2  
A3  
A1  
A6  
V D D  
V ss  
VDD  
VSS  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 2  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
BLOCK DIAGRAM  
LWE  
Bank Select  
Data Input Register  
LDQM  
512K x 16  
512K x 16  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LDQM  
LCAS  
Timing Register  
RAS  
CLK  
CKE  
CS  
CAS  
WE  
L(U)DQM  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 3  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Pin Descriptions (Table 1. Pin Details of T431616D/E)  
Symbol  
Type  
Description  
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive  
CLK  
Input  
edge of CLK. CLK also increments the internal burst counter and controls the output registers.  
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low  
synchronously with clock(set-up and hold time same as other inputs), the internal clock is  
suspended from the next clock cycle and the state of output and burst address is frozen as long as  
the CKE remains low. When both banks are in the idle state, deactivating the clock controls the  
entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device  
enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the  
same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh  
modes, providing low standby power.  
CKE  
Input  
Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or BankPrecharge  
A11  
Input  
Input  
command is being applied.  
Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0-A10)  
and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select  
one location out of the 256K available in the respective bank. During a Precharge command, A10  
is sampled to determine if both banks are to be precharged (A10 = HIGH). The address inputs also  
provide the op-code during a Mode Register Set command.  
A0-A10  
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder.  
All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection  
on systems with multiple banks. It is considered part of the command code.  
CS#  
Input  
Input  
Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the  
CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are  
asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the  
Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the  
BankActivate command is selected and the bank designated by BS is turned on to the active state.  
When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by  
BS is switched to the idle state after the precharge operation.  
RAS#  
Column Address Strobe: The CAS# signal defines the operation commands in conjunction with  
the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held  
"HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW."  
Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH."  
CAS#  
WE#  
Input  
Write Enable: The WE# signal defines the operation commands in conjunction with the RAS#  
and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the  
BankActivate or Precharge command and Read or Write command.  
Input  
Input  
Data Input/Output Mask: LDQM and UDQM are byte specific, nonpersistent I/O buffer  
controls. The I/O buffers are placed in a high-z state when LDQM/UDQM is sampled HIGH.  
Input data is masked when LDQM/UDQM is sampled HIGH during a write cycle. Output data is  
masked (two-clock latency) when LDQM/UDQM is sampled HIGH during a read cycle. UDQM  
masks DQ15-DQ8, and LDQM masks DQ7-DQ0.  
LDQM,  
UDQM  
Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK.  
DQ0-DQ15 Input/Output  
The I/Os are byte-maskable during Reads and Writes.  
No Connect: These pins should be left unconnected.  
NC  
VDDQ  
VSSQ  
VDD  
VSS  
-
DQ Power: Provide isolated power to DQs for improved noise immunity. ( 3.3V 0.3V )  
Supply  
Supply  
Supply  
Supply  
±
DQ Ground: Provide isolated ground to DQs for improved noise immunity. ( 0 V )  
Power Supply: +3.3V 0.3V  
±
Ground  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 4  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Operation Mode  
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the  
truth table for the operation commands.  
Table 2. Truth Table (Note (1), (2) )  
Command  
State CKEn-1 CKEn DQM(6) A11 A10 A0-9 CS# RAS# CAS# WE#  
Idle(3)  
Any  
Any  
Active(3)  
Active(3)  
Active(3)  
Active(3)  
Idle  
Any  
Active(4)  
Any  
Idle  
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
V
X
X
X
X
X
X
V
L
H
L
H
L
H
V
X
X
X
X
X
X
V
X
X
V
V
V
V
V
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
X
L
L
L
H
H
H
L
L
L
L
L
H
H
X
L
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
BankActivate  
BankPrecharge  
PrechargeAll  
Write  
H
H
H
H
L
H
H
X
L
Write and AutoPrecharge  
Read  
Read and Autoprecharge  
Mode Register Set  
No-Operation  
Burst Stop  
Device Deselect  
AutoRefresh  
SelfRefresh Entry  
SelfRefresh Exit  
Idle  
Idle  
L
L
H
X
H
X
X
H
X
X
H
X
X
X
H
X
X
H
X
X
H
X
X
(SelfRefresh)  
Clock Suspend Mode Entry  
Power Down Mode Entry  
Active  
Any(5)  
H
H
L
L
X
X
X
X
X
X
X
X
Clock Suspend Mode Exit  
Power Down Mode Exit  
Active  
Any  
L
L
H
H
X
X
X
X
X
X
X
X
(PowerDown)  
Data Write/Output Enable  
Data Mask/Output Disable  
Active  
Active  
H
H
X
X
L
H
X
X
X
X
X
X
Note: 1. V=Valid X=Don't Care L=Low level H=High level  
2. CKEn signal is input level when commands are provided.  
CKEn-1 signal is input level one clock cycle before the commands are provided.  
3. These are states of bank designated by BS signal.  
4. Device state is 1, 2, 4, 8, and full page burst operation.  
5. Power Down Mode can not enter in the burst operation.  
When this command is asserted in the burst cycle, device state is clock suspend mode.  
6. LDQM and UDQM  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 5  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Commands  
1
BankPrecharge command  
(RAS# = "L", CAS# = "H", WE# = "L", A11 = “V”, A10 = "L", A0-A9 = Don't care)  
The BankPrecharge command precharges the bank disignated by A11 signal. The precharged bank is  
switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is satisfied  
from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by  
t
RAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the  
end of precharge, the precharged bank is still in the idle state and is ready to be activated again.  
2
3
PrechargeAll command  
(RAS# = "L", CAS# = "H", WE# = "L", A11 = Don't care, A10 = "H", A0-A9 = Don't care)  
The PrechargeAll command precharges both banks simultaneously and can be issued even if both banks are  
not in the active state. Both banks are then switched to the idle state.  
Read command  
(RAS# = "H", CAS# = "L", WE# = "H", A11= “V”, A9 = "L", A0-A7 = Column Address)  
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an  
active bank. The bank must be active for at least tRCD(min.) before the Read command is issued. During read  
bursts, the valid data-out element from the starting column address will be available following the CAS# latency  
after the issue of the Read command. Each subsequent data-out element will be valid by the next positive clock  
edge (refer to the following figure). The DQs go into high-impedance at the end of the burst unless other  
command is initiated. The burst length, burst sequence, and CAS# latency are determined by the mode register,  
which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap  
to column 0 and continue).  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
COMMAND  
READ A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
CAS# latency=1  
DOUT A  
DOUTA  
DOUT A  
DOUT A  
3
0
1
2
t
, DQ's  
CK1  
CAS# latency=2  
, DQ's  
DOUT A  
DOUTA  
DOUT A  
DOUT A  
3
0
1
2
t
CK2  
CAS# latency=3  
, DQ's  
DOUT A  
DOUTA  
1
DOUT A  
DOUT A  
3
0
2
t
CK3  
Burst Read Operation  
(Burst Length = 4, CAS# Latency = 1, 2, 3)  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 6  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks earlier (i.e.  
LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto precharge function may  
be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end  
of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The  
interrupt coming from the Read command can occur on any clock cycle following a previous Read command  
(refer to the following figure).  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
COMMAND  
READ A  
READ B  
DOUT A  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
CAS# latency=1  
DOUT B  
DOUT B  
DOUT B  
DOUT B  
3
0
0
1
2
t
, DQ's  
CK1  
CAS# latency=2  
, DQ's  
DOUT A  
DOUT B  
DOUT B  
DOUT B  
2
DOUT B  
DOUT B  
0
0
1
3
t
CK2  
CAS# latency=3  
, DQ's  
DOUT A  
DOUT B  
DOUT B  
DOUT B  
3
0
0
1
2
t
CK3  
Read Interrupted by a Read  
(Burst Length = 4, CAS# Latency = 1, 2, 3)  
The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from  
a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior to the Write command  
to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-  
impedance on the DQ pins must occur between the last read data and the Write command (refer to the following  
three figures). If the data output of the burst read occurs at the second clock of the burst write, the  
LDQM/UDQM must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus  
contention.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
DQM  
COMMAND  
DQ's  
NOP  
READ A  
NOP  
NOP  
NOP  
NOP  
WRITE B  
DINB  
NOP  
NOP  
DOUT A  
0
DINB  
DINB  
2
0
1
Must be Hi-Z before  
the Write Command  
: "H" or "L"  
Read to Write Interval  
(Burst Length ≥ 4, CAS# Latency = 3)  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 7  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
1 Clk Interval  
DQM  
BANKA  
ACTIVATE  
COMMAND  
NOP  
NOP  
NOP  
READ A  
WRITE A  
NOP  
DIN A  
DIN A  
NOP  
NOP  
DIN  
CAS# latency=1  
DIN  
DIN  
A
A
DIN  
DIN  
A
A
A
A
0
1
1
2
3
t
, DQ's  
CK1  
Must be Hi-Z before  
the Write Command  
CAS# latency=2  
DIN  
t
, DQ's  
0
2
3
CK2  
: "H" or "L"  
Read to Write Interval  
(Burst Length ≥ 4, CAS# Latency = 1, 2)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
DQM  
COMMAND  
NOP  
NOP  
NOP  
WRITE B  
DIN B  
NOP  
NOP  
NOP  
NOP  
READ A  
CAS# latency=1  
DOUT A  
DIN B  
DIN B  
DIN B  
0
0
1
2
3
t
, DQ's  
CK1  
Must be Hi-Z before  
the Write Command  
CAS# latency=2  
, DQ's  
DIN B  
DIN B  
1
DIN B  
DIN B  
t
0
2
3
CK2  
: "H" or "L"  
Read to Write Interval  
(Burst Length ≥ 4, CAS# Latency = 1, 2)  
A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll  
command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll  
command is issued in different CAS# latency.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
Bank,  
Bank,  
Row  
ADDR ESS  
Bank (s)  
Precharge  
DOUT  
Col  
A
tRP  
COM M AND  
READ  
A
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Activate  
CAS# latency=1  
DOUT  
A
DOUT A  
2
DOUT A  
A
0
1
3
t
, DQ's  
CK1  
CAS# la tency=2  
, DQ's  
DOUT  
A
DOUT A  
DOUT A  
DOUT  
A
2
0
2
1
3
t
CK2  
CAS# la tency=3  
, DQ's  
DOUT  
A
DOUT A  
DOUT A  
DOUT A  
3
0
1
t
CK3  
Read to Precharge  
(CAS# Latency = 1, 2, 3)  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 8  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
4
Read and AutoPrecharge command  
(RAS# = "H", CAS# = "L", WE# = "H", A11 = “V”, A10 = "H", A0-A7 = Column Address)  
The Read and AutoPrecharge command automatically performs the precharge operation after the read  
operation. Once this command is given, any subsequent command cannot occur within a time delay of tRP(min.)  
{
+ burst length . At full-page burst, only the read operation is performed in this command and the auto precharge  
}
function is ignored.  
5
Write command  
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "L", A0-A7 = Column Address)  
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an  
active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write  
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data  
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs  
remain with high-impedance at the end of the burst unless another command is initiated. The burst length and  
burst sequence are determined by the mode register, which is already programmed. A full-page burst will  
continue until terminated (at the end of the page it will wrap to column 0 and continue).  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
NOP  
NOP  
NOP  
COMMAND  
NOP  
WRITE A  
NOP  
NOP  
NOP  
NOP  
DIN  
A
DIN A  
DIN  
A
DIN A  
3
don't care  
DQ0 - DQ3  
0
1
2
The first data element and the write  
are registered on the same clock edge.  
Extra data is masked.  
Burst Write Operation  
(Burst Length = 4, CAS# Latency = 1, 2, 3)  
A write burst without the auto precharge function may be interrupted by a subsequent Write,  
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from  
Write command can occur on any clock cycle following the previous Write command (refer to the following  
figure).  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
NOP  
NOP  
NOP  
COMMAND  
NOP  
WRITE A  
WRITE B  
NOP  
NOP  
NOP  
1 Clk Interval  
DIN DIN B  
A
DIN B  
DIN B  
DIN B  
3
DQ's  
0
0
1
2
Write Interrupted by a Write  
(Burst Length = 4, CAS# Latency = 1, 2, 3)  
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P. 9  
Publication Date: FEB. 2007  
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tmCH  
T431616D/E  
The Read command that interrupts a write burst without auto precharge function should be issued one cycle  
after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data  
must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to  
the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not  
be executed.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
NOP  
NOP  
NOP  
COMMAND  
NOP  
WRITE A  
READ B  
NOP  
NOP  
NOP  
CAS# latency=1  
DOUT B  
DOUT B  
DOUT B  
DOUT B  
DIN  
DIN  
A
0
2
3
0
1
t
, DQ's  
CK1  
CAS# latency=2  
, DQ's  
DOUT B  
DOUT B  
A
DOUT B  
DOUT B  
1
don't care  
don't care  
2
3
0
0
t
CK2  
CAS# latency=3  
, DQ's  
DOUT B  
DOUT B  
DOUT B  
DOUT B  
3
DIN  
A
don't care  
t
0
1
2
0
CK3  
Input data must be removedfrom the DQ's at least one clock  
cycle before the Read data appearson the outputs to avoid  
data contention.  
Input data for the write is masked.  
Write Interrupted by a Read  
(Burst Length = 4, CAS# Latency = 1, 2, 3)  
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function  
should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals  
t
WR/tCK rounded up to the next whole number. In addition, the LDQM/UDQM signals must be used to mask input  
data, starting with the clock edge following the last data-in element and ending with the clock edge on which the  
BankPrecharge/PrechargeAll command is entered (refer to the following figure).  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
DQM  
t
RP  
COMMAND  
WRITE  
Precharge  
BANK (S)  
NOP  
NOP  
Activate  
ROW  
NOP  
NOP  
BANK  
COL n  
ADDRESS  
DQ  
t
WR  
DIN  
n
DIN  
n + 1  
: don't care  
Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.  
Write to Precharge  
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P. 10  
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T431616D/E  
6
Write and AutoPrecharge command (refer to the following figure)  
(RAS# = "H", CAS# = "L", WE# = "L", A11 = “V”, A10 = "H", A0-A7 = Column Address)  
The Write and AutoPrecharge command performs the precharge operation automatically after the write  
operation. Once this command is given, any subsequent command can not occur within a time delay of (burst  
{
length -1) + tWR + tRP(min.) . At full-page burst, only the write operation is performed in this command and the  
}
auto precharge function is ignored.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
Bank A  
Write A  
COMMAND  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
AutoPrecharge  
Activate  
tDAL  
CAS# latency=1  
DIN  
DIN  
DIN  
A
A
A
DIN A  
DIN A  
DIN A  
0
0
0
1
1
1
*
*
*
t
, DQ's  
CK1  
tDAL  
CAS# latency=2  
, DQ's  
t
CK2  
tDAL  
CAS# latency=3  
t
, DQ's  
CK3  
Begin AutoPrecharge  
Bank can be reactivatedat completionof tDAL  
tDAL= tWR + tRP  
*
Burst Write with Auto-Precharge  
(Burst Length = 2, CAS# Latency = 1, 2, 3)  
7
Mode Register Set command  
(RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data)  
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode  
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode  
register to make SDRAM useful for a variety of different applications. The default values of the Mode Register  
after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins  
A0~A9 and A11 in the same cycle is the data written to the mode register. One clock cycle is required to  
complete the write in the mode register (refer to the following figure). The contents of the mode register can be  
changed using the same command and the clock cycle requirements during operation as long as both banks are in  
the idle state.  
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T0  
T 1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
CLK  
t
CK2  
CKE  
CS#  
Clock min.  
RAS#  
CAS#  
WE#  
A11  
A10  
Address Key  
A0-A9  
DQM  
tRP  
Hi-Z  
DQ  
Mode Register  
SetCommand  
PrechargeAll  
Any  
Command  
Mode Register Set Cycle  
(CAS# Latency = 1, 2, 3)  
The mode register is divided into various fields depending on functionality.  
Burst Length Field (A2~A0)  
•
This field specifies the data length of column access using the A2~A0 pins and selects the Burst  
Length to be 1, 2, 4, 8, or full page.  
A2  
0
0
A1  
0
0
A0  
0
1
Burst Length  
1
2
0
1
0
4
0
1
1
8
1
1
1
1
0
0
1
1
0
1
0
1
Reserved  
Reserved  
Reserved  
Full Page  
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to change products or specifications without notice.  
P. 12  
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tmCH  
T431616D/E  
Addressing Mode Select Field (A3)  
•
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential  
Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length  
of 4 and 8.  
A3  
0
Addressing Mode  
Sequential  
1
Interleave  
--- Addressing Sequence of Sequential Mode  
An internal column address is performed by increasing the address from the column address which  
is input to the device. The internal column address is varied by the Burst Length as shown in the  
following table. When the value of column address, (n + m), in the table is larger than 255, only  
the least significant 8 bits are effective.  
Data n  
0
n
1
2
3
4
5
6
7
-
-
255 256 257  
n+255 n+1  
-
-
n+1  
n+2  
n+3  
n+4  
n+5  
n+6  
n+7  
n
Column Address  
2 words:  
4 words:  
8 words:  
Burst Length  
Full Page: Column address is repeated until terminated.  
--- Addressing Sequence of Interleave Mode  
A column access is started in the input column address and is performed by inverting the address  
bits in the sequence shown in the following table.  
Data n  
Data 0  
Data 1  
Data 2  
Data 3  
Data 4  
Data 5  
Data 6  
Data 7  
Column Address  
Burst Length  
4 words  
A7 A6 A5 A4 A3 A2 A1 A0  
A7 A6 A5 A4 A3 A2 A1 A0#  
A7 A6 A5 A4 A3 A2 A1# A0  
A7 A6 A5 A4 A3 A2 A1# A0#  
A7 A6 A5 A4 A3 A2# A1 A0  
A7 A6 A5 A4 A3 A2# A1 A0#  
A7 A6 A5 A4 A3 A2# A1# A0  
A7 A6 A5 A4 A3 A2# A1# A0#  
8 words  
CAS# Latency Field (A6~A4)  
•
This field specifies the number of clock cycles from the assertion of the Read command to the first  
read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The  
minimum whole value satisfying the following formula must be programmed into this field.  
tCAC(min) ≤ CAS# Latency X tCK  
A6  
0
0
A5  
0
0
A4  
0
1
CAS# Latency  
Reserved  
1 clock  
0
1
0
2 clocks  
0
1
1
3 clocks  
1
X
X
Reserved  
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P. 13  
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T431616D/E  
Test Mode field (A8~A7)  
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.  
•
A8  
0
A7  
0
Test Mode  
normal mode  
0
1
1
X
Vendor Use Only  
Vendor Use Only  
Single Write Mode (A9)  
•
This bit is used to select the write mode. When the BS bit is "0", the Burst-Read-Burst-Write mode is  
selected. When the BS bit is "1", the Burst-Read-Single-Write mode is selected.  
A9  
0
1
Single Write Mode  
Burst-Read-Burst-Write  
Burst-Read-Single-Write  
Note: A10 and A11 should stay “L” during mode set cycle.  
8
9
No-Operation command  
(RAS# = "H", CAS# = "H", WE# = "H")  
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low).  
This prevents unwanted commands from being registered during idle or wait states.  
Burst Stop command  
(RAS# = "H", CAS# = "H", WE# = "L")  
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only  
effective in a read/write burst without the auto precharge function. The terminated read burst ends after a delay  
equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the  
following figure.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
READ A  
NOP  
NOP  
NOP  
COMMAND  
NOP  
NOP  
Burst Stop  
DOUT A  
NOP  
NOP  
The burst ends after a delay equal to the CAS# latency.  
CAS# latency=1  
DOUT A  
DOUT A  
DOUT A  
0
1
2
3
t
, DQ's  
CK1  
CAS# latency=2  
, DQ's  
DOUT A  
DOUT A  
DOUT A  
2
DOUT A  
3
0
1
t
CK2  
CAS# latency=3  
, DQ's  
DOUT A  
0
DOUT A  
DOUT A  
DOUT A  
3
1
2
t
CK3  
Termination of a Burst Read Operation  
(Burst Length • 4, CAS# Latency = 1, 2, 3)  
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T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
CLK  
NOP  
NOP  
NOP  
COMMAND  
NOP  
WRITE A  
NOP  
Burst Stop  
don't care  
NOP  
NOP  
CAS# latency=1, 2, 3  
DQ's  
DIN A  
DIN  
A
DIN A  
2
1
0
Input data for the Write is masked.  
Termination of a Burst Write Operation  
(Burst Length = X, CAS# Latency = 1, 2, 3)  
10 Device Deselect command  
(CS# = "H")  
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address  
inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation  
command.  
11 AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)  
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A11 = “Don‘t care, A0-A9 = Don't care)  
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-  
before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each  
time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address  
bits a "don't care" during an AutoRefresh command. The internal refresh counter increments automatically on  
every auto refresh cycle to all of the rows. The refresh operation must be performed 2048 times within 32ms. The  
time required to complete the auto refresh operation is specified by tRC(min.). To provide the AutoRefresh  
command, both banks need to be in the idle state and the device must not be in power down mode (CKE is high  
in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed.  
The precharge time requirement, tRP(min), must be met before successive auto refresh operations are performed.  
12 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)  
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A9 = Don't care)  
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data  
retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM  
become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is  
internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an  
indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on  
CKE (SelfRefresh Exit command).  
13 SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)  
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")  
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device  
Deselect commands must be issued for tRC(min.) because time is required for the completion of any bank  
currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a  
burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh  
mode.  
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P. 15  
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tmCH  
T431616D/E  
14 Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in Timing  
Waveforms)  
(CKE = "L")  
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent  
cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is  
suspended. On the other hand, when both banks are in the idle state, this command performs entry into the  
PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode.  
The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms)  
since the command does not perform any refresh operations.  
15 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing Waveforms,  
CKE= "H")  
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the  
subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown  
mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required  
when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock  
cycle from the end of this command.  
16 Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")  
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every word of the  
input data. During a read cycle, the LDQM/UDQM functions as the controller of output buffers. LDQM/UDQM  
is also used for device selection, byte selection and bus control in a memory system. LDQM controls DQ0 to  
DQ7, UDQM controls DQ8 to DQ15.  
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P. 16  
Publication Date: FEB. 2007  
Revision: A  
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tmCH  
T431616D/E  
Absolute Maximum Rating  
Symbol  
Item  
Rating  
-5/6/7  
Unit  
Note  
VIN, VOUT  
VDD, VDDQ  
TOPR  
Input, Output Voltage  
Power Supply Voltage  
Operating Temperature  
Storage Temperature  
- 1.0 ~ 4.6  
-1.0 ~ 4.6  
0 ~ 70  
- 55 ~ 125  
1
V
V
1
1
1
1
1
1
C
C
°
TSTG  
PD  
IOUT  
°
Power Dissipation  
Short Circuit Output Current  
W
mA  
50  
Recommended D.C. Operating Conditions (Ta = -0~70 C)  
°
Symbol  
Parameter  
Min.  
Typ.  
3.3  
3.3  
-
Max.  
3.6  
3.6  
VDDQ+0.3  
0.8  
Unit  
V
V
V
V
Note  
VDD  
VDDQ  
VIH  
Power Supply Voltage  
3.0  
3.0  
2.0  
- 0.3  
2
2
2
2
Power Supply Voltage(for I/O Buffer)  
LVTTL Input High Voltage  
LVTTL Input Low Voltage  
VIL  
-
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25 C)  
°
Symbol  
CI  
CI/O  
Parameter  
Input Capacitance  
Input/Output Capacitance  
Min.  
Max.  
Unit  
pF  
pF  
2
4
5
7
Note: These parameters are periodically sampled and are not 100% tested.  
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P. 17  
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T431616D/E  
Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, Ta = 0~70 C)  
°
- 5/6/7(T431616D) - 7(T431616E)  
Description/Test condition  
Symbol  
Max.  
Max.  
Unit Note  
Operating Current  
1 bank  
130/115/100  
40  
3
tRC ≥ tRC(min), Outputs Open, Input  
IDD1  
operation  
signal one transition per one cycle  
Precharge Standby Current in non-power down mode  
tCK = tCK(min), CS# ≥ VIH, CKE = V  
3
25  
2
15  
0.8  
0.8  
Input signals are changed once duringI3H0ns.  
Precharge Standby Current in power down mode  
IDD2N  
IDD2P  
tCK = tCK(min), CKE ≤ VIL(max)  
3
Precharge Standby Current in power down mode  
2
mA  
IDD2PS  
tCK = ∞,CKE ≤ VIL(max)  
Active Standby Current in power down mode  
CKE ≤ VIL(max), tCK = tCK(min)  
2
1.5  
20  
3
IDD3P  
IDD3N  
IDD4  
Active Standby Current in non-power down mode  
CKE ≥ VIL(max), tCK = tCK(min)  
40  
165/150/140  
115/100/90  
2
Operating Current (Burst mode)  
40  
3, 4  
3
t
CK=tCK(min), Outputs Open, Multi-bank interleave,gapless data  
Refresh Current  
tRC ≥ tRC(min)  
40  
IDD5  
Self Refresh Current  
0.6  
IDD6  
V
IH ≥ VDD - 0.2, 0V ≤ VIL ≤ 0.2V  
Parameter  
Description  
Min.  
Max.  
Unit Note  
IIL  
Input Leakage Current  
( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V )  
- 10  
10  
uA  
IOL  
VOH  
VOL  
Output Leakage Current  
- 10  
2.4  
-
10  
-
uA  
V
Output disable, 0V ≤ VOUT ≤ VDDQ  
)
LVTTL Output "H" Level Voltage  
( IOUT = -2mA )  
LVTTL Output "L" Level Voltage  
( IOUT = 2mA )  
0.4  
V
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P. 18  
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Revision: A  
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tmCH  
T431616D/E  
Electrical Characteristics and Recommended A.C. Operating Conditions  
(VDD = 3.3V±0.3V, Ta = -0~70 C) (Note: 5, 6, 7, 8)  
°
- 5/6/7/7L  
Symbol  
A.C. Parameter  
Min.  
Max.  
Unit Note  
tRC  
Row cycle time  
(same bank)  
48/54/63/63  
9
tRCD  
RAS# to CAS# delay  
(same bank)  
15/16/16/16  
9
ns  
9
tRP  
Precharge to refresh/row activate command  
15/16/16/16  
10/12/14/14  
(same bank)  
tRRD  
Row activate to row activate delay  
(different banks)  
9
tRAS  
Row activate to precharge time  
(same bank)  
35/42/42/42  
100,000  
tWR  
Write recovery time  
Cycle  
10  
2
tCK1  
tCK2  
tCK3  
tCH  
CL* = 1  
CL* = 2  
CL* = 3  
-/20/20/20  
-/7/8/8  
5/6/7/7  
2/2/2.5/2.5  
2/2/2.5/2.5  
Clock cycle time  
ns  
11  
11  
Clock high time  
Clock low time  
tCL  
tAC1  
tAC2  
tAC3  
tCCD  
tOH  
tLZ  
tHZ  
tIS  
tIH  
tPDE  
tREF  
Access time from CLK  
(positive edge)  
CL* = 1  
CL* = 2  
CL* = 3  
-/8/13/13  
-/6/6.5/6.5  
4.5/5/5.5/5.5  
11  
10  
CAS# to CAS# Delay time  
Data output hold time  
Data output low impedance  
Data output high impedance  
Data/Address/Control Input set-up time  
Data/Address/Control Input hold time  
PowerDown Exit set-up time  
Refresh time  
1
1.8/2/2/2  
1
Cycle  
3/4/5/5  
64  
8
11  
11  
2
1
2
ns  
ms  
* CL is CAS# Latency.  
Note:  
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.  
2. All voltages are referenced to VSS. VIH(Max)=4.6 for pulse width≤5ns.VIL(Min)=-1.5Vfor pulse width≤5ns.  
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and  
tRC. Input signals are changed one time during tCK.  
4. These parameters depend on the output loading. Specified values are obtained with the output open.  
5. Power-up sequence is described in Note 12.  
6. A.C. Test Conditions  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 19  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
LVTTL Interface  
Reference Level of Output Signals  
1.4V / 1.4V  
Output Load  
Input Signal Levels  
Reference to the Under Output Load (B)  
2.4V / 0.4V  
1ns  
Transition Time (Rise and Fall) of Input Signals  
Reference Level of Input Signals  
1.4V  
1.4V  
3.3V  
50Ω  
1.2kΩ  
50Ω  
Z0=  
Output  
Output  
30pF  
30pF  
870Ω  
LVTTL D.C. Test Load (A)  
LVTTL A.C. Test Load (B)  
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1 ns).  
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.  
9. These parameters account for the number of clock cycle and depend on the operating frequency of the clock as follows:  
the number of clock cycles = specified value of timing/Clock cycle time  
(count fractions as a whole number)  
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.  
11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns  
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be  
added to the parameter.  
12. Power up Sequence  
Power up must be performed in the following sequence.  
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and both  
CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time.  
2) After power-up, a pause of 200us minimum is required. Then, it is recommended that LDQM/UDQM is held  
"HIGH" (VDD levels) to ensure DQ output is in high impedance.  
3) Both banks must be precharged.  
4) Mode Register Set command must be asserted to initialize the Mode register.  
5) A minimum of 2 Auto-Refresh dummy cycles must be required before or after the Mode Register Set command  
in step 4 to stabilize the internal circuitry of the device.  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 20  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Timing Waveforms  
Figure 1. AC Parameters for Write Timing  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
tCL  
tCH  
tIS  
tIH  
Begin AutoPrecharge  
Bank A  
Begin AutoPrecharge  
Bank B  
CKE  
CS#  
tIS  
tIS  
RAS#  
CAS#  
WE#  
A11  
tIH  
RBx  
RBx  
RAy  
RAy  
RAz  
RAz  
RBy  
RBy  
RAx  
A10  
tIS  
A0-A9  
CAx  
CBx  
RBx  
CAy  
DQM  
DQ  
tDAL  
tRCD  
tIS  
tWR  
tRC  
tRP  
tRRD  
tIH  
Hi-Z  
Ax0 Ax1 Ax2  
Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3  
Activate  
Writewith  
Activate  
Writewith  
Activate  
Write  
Command  
Bank A  
Precharge  
Activate  
Activate  
Command  
Bank B  
Command AutoPrecharge Command AutoPrecharge Command  
Command Command  
Bank A  
Command  
Bank A  
Bank B  
Command  
Bank B  
Bank A  
Bank A  
Bank A  
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P. 21  
Publication Date: FEB. 2007  
Revision: A  
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T431616D/E  
Figure 2. AC Parameters for Read Timing  
(Burst Length=2, CAS# Latency=2)  
T0  
T 1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
T 11 T12  
T13  
CLK  
CKE  
tCK2  
CH tCL  
t
Begin AutoPrecharge  
Bank B  
IS  
t
IH  
t
IH  
t
tIS  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
tIH  
RBx  
RAx  
RAy  
RAy  
IS  
t
A0-A9  
CBx  
RAx  
CAx  
RBx  
tRRD  
tRAS  
tRC  
DQM  
DQ  
AC2  
t
t
AC2  
t
tRP  
HZ  
t
RCD  
t
Hi-Z  
LZ  
Ax0  
Bx0  
Bx1  
Ax1  
HZ  
t
OH  
t
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Activate  
Command  
Bank B  
Read with  
Precharge  
Command  
Bank A  
Activate  
Command  
Bank A  
Auto Precharge  
Command  
Bank B  
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to change products or specifications without notice.  
P. 22  
Publication Date: FEB. 2007  
Revision: A  
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tmCH  
T431616D/E  
Figure 3. Auto Refresh (CBR)  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK2  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
A0-A9  
DQM  
RAx  
CAx  
tRC  
tRC  
tRP  
Ax0  
Ax2  
Ax1  
Ax3  
DQ  
Read  
Command  
Bank A  
PrechargeAll AutoRefresh  
AutoRefresh  
Command  
Activate  
Command  
Bank A  
Command  
Command  
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P. 23  
Publication Date: FEB. 2007  
Revision: A  
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tmCH  
T431616D/E  
Figure 4. Power on Sequene and Auto Refresh (CBR)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK2  
High level  
Minimum of 2 Refresh Cycles are required  
is reauired  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
Address Key  
A0-A9  
DQM  
DQ  
tRP  
tRC  
Hi-Z  
(*)  
(*)  
PrechargeALL  
Command  
1st AutoRefresh  
Command  
Mode Register  
Set Command  
2nd Auto Refresh  
Command  
Any  
Command  
Inputs must be  
stable for 200 µs  
Note (*) : The Auto Refresh command can be issued before or after Mode Register Set command  
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P. 24  
Publication Date: FEB. 2007  
Revision: A  
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T431616D/E  
Figure 5. Self Refresh Entry & Exit Cycle  
T0  
T1  
T2  
T3  
T4  
T5  
T7  
T8  
T9  
T10 T11 T12 T13 T14 T15 T16 T17 T18  
T19  
T6  
CLK  
*Note 2  
tRC(min) *Note 7  
*Note 4  
*Note 1  
*Note 3  
CKE  
CS#  
PDE  
t
tSRX  
*Note 5  
tIS  
*Note 6  
RAS#  
CAS#  
A11  
*Note 8  
*Note 8  
A0-A9  
WE#  
DQM  
DQ  
Hi-Z  
Hi-Z  
Self Refresh Enter  
SelfRefresh Exit  
AutoRefresh  
Note: To Enter SelfRefresh Mode  
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.  
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.  
3. The device remains in SelfRefresh mode as long as CKE stays "low".  
Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.  
To Exit SelfRefresh Mode  
1. System clock restart and be stable before returning CKE high.  
2. Enable CKE and CKE should be set high for minimum time of tSRX  
3. CS# starts from high.  
.
4. Minimum tRC is required after CKE going high to complete SelfRefresh exit.  
5. 2048 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses  
burst refresh.  
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to change products or specifications without notice.  
P. 25  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 6.1. Clock Suspension During Burst Read (Using CKE)  
(Burst Length=4, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6  
T
7
T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22  
CLK  
tCK1  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
A0-A9  
RAx CAx  
DQM  
DQ  
tHZ  
Ax3  
Hi-Z  
Ax0  
Ax1  
Ax2  
Clock Suspend  
2 Cycles  
Clock Suspend  
3 Cycles  
Activate  
Command  
Bank A  
Clock Suspend  
1 Cycle  
Read  
Command  
Bank A  
Note: CKE to CLK disable/enable = 1 clock  
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P. 26  
Publication Date: FEB. 2007  
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T431616D/E  
Figure 6.2. Clock Suspension During Burst Read (Using CKE)  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK2  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
A0-A9  
DQM  
DQ  
CAx  
RAx  
tHZ  
Hi-Z  
Ax3  
Ax0  
Ax1  
Ax2  
Clock Suspend  
2 Cycles  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Clock Suspend  
1 Cycle  
Clock Suspend  
3 Cycles  
Note: CKE to CLK disable/enable = 1 clock  
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P. 27  
Publication Date: FEB. 2007  
Revision: A  
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T431616D/E  
Figure 6.3. Clock Suspension During Burst Read (Using CKE)  
(Burst Length=4, CAS# Latency=3)  
T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK3  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
A0-A9  
DQM  
DQ  
RAx  
CAx  
tHZ  
Hi-Z  
Ax3  
Ax0  
Ax1  
Ax2  
Clock Suspend  
3 Cycles  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Clock Suspend Clock Suspend  
1 Cycle 2 Cycles  
Note: CKE to CLK disable/enable = 1 clock  
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P. 28  
Publication Date: FEB. 2007  
Revision: A  
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tmCH  
T431616D/E  
Figure 7.1. Clock Suspension During Burst Write (Using CKE)  
(Burst Length = 4, CAS# Latency = 1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK1  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
A0-A9  
RAx CAx  
DQM  
DQ  
Hi-Z  
DAx0  
DAx1  
DAx2  
DAx3  
Activate  
Command  
Bank A  
Clock Suspend Clock Suspend  
1 Cycle 2 Cycles  
Clock Suspend  
3 Cycles  
Write  
Command  
Bank A  
Note: CKE to CLK disable/enable = 1 clock  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 29  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 7.2. Clock Suspension During Burst Write (Using CKE)  
(Burst Length=4, CAS# Latency=2)  
T2  
2
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21  
CLK  
tCK2  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
A0-A9  
DQM  
DQ  
RAx  
RAx  
CAx  
Hi-Z  
DAx2  
DAx3  
DAx0  
DAx1  
Activate  
Command  
Bank A  
Clock Suspend Clock Suspend  
1 Cycle 2 Cycles  
Clock Suspend  
3 Cycles  
Write  
Command  
Bank A  
Note: CKE to CLK disable/enable = 1 clock  
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to change products or specifications without notice.  
P. 30  
Publication Date: FEB. 2007  
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T431616D/E  
Figure 7.3. Clock Suspension During Burst Write (Using CKE)  
(Burst Length=4, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK3  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
A0-A9  
RAx  
CAx  
DQM  
DQ  
Hi-Z  
DAx0  
DAx2  
DAx3  
DAx1  
Activate  
Command  
Bank A  
Clock Suspend Clock Suspend  
1 Cycle 2 Cycles  
Write  
Command  
Bank A  
Clock Suspend  
3 Cycles  
Note: CKE to CLK disable/enable = 1 clock  
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to change products or specifications without notice.  
P. 31  
Publication Date: FEB. 2007  
Revision: A  
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tmCH  
T431616D/E  
Figure 8. Power Down Mode and Clock Mask  
(Burst Lenght=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
CS#  
tCK2  
tPDE  
tIS  
Valid  
RAS#  
CAS#  
WE#  
A11  
RAx  
A10  
CAx  
RAx  
A0~A9  
DQM  
tHZ  
Hi-Z  
Ax0  
Ax1  
Ax3  
Ax2  
DQ  
ACTIVE  
STANDBY  
PRECHARGE  
STANDBY  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Clock Mask  
Start  
Clock Mask  
End  
Precharge  
Command  
Bank A  
Power Down  
Mode Exit  
Any  
Command  
Power Down  
ModeEntry  
Power Down  
Mode Exit  
Power Down  
ModeEntry  
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P. 32  
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Figure 9.1. Random Column Read (Page within same Bank)  
(Burst Length=4, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK1  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAz  
RAz  
RAw  
RAw  
CAw  
CAy  
CAz  
CAx  
A0~A9  
DQM  
Hi-Z  
DQ  
Aw0 Aw1 Aw2 Aw3 Ax0  
Ax1  
Ay1 Ay2 Ay3  
Az1 Az2 Az3  
Ay0  
Az0  
Activate  
Command  
Bank A  
Read  
Read  
Precharge  
Command  
Bank A  
Read  
Command  
Bank A  
Command Command  
Bank A  
Bank A  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
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P. 33  
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T431616D/E  
Figure 9.2. Random Column Read (Page within same Bank)  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAz  
RAw  
RAz  
CAz  
CAw  
CAx  
CAy  
RAw  
A0~A9  
DQM  
Hi-Z  
Az0  
Ay0  
DQ  
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1  
Ay1 Ay2 Ay3  
Precharge  
Az1 Az2 Az3  
Activate  
Read  
Read  
Read  
Command  
Bank A  
Activate  
Read  
Command  
Bank A  
Command Command  
Command  
Bank A  
Command Command  
Bank A  
Bank A  
Bank A  
Bank A  
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P. 34  
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T431616D/E  
Figure 9.3. Random Column Read (Page within same Bank)  
(Burst Length=4, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK3  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAz  
A10  
RAw  
CAy  
CAz  
CAw  
RAz  
RAw  
A0~A9  
DQM  
CAx  
Hi-Z  
Az0  
Ay0  
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1  
Ay1 Ay2 Ay3  
DQ  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Read  
Command  
Bank A  
Read  
Command  
Bank A  
Precharge  
Command  
Bank A  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
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P. 35  
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T431616D/E  
Figure 10.1. Random Column Write (Page within same Bank)  
(Burst Length=4, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK1  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RBz  
RBz  
RBw  
CBw  
CBy  
RBw  
CBz  
A0~A9  
DQM  
CBx  
Hi-Z  
DQ  
DBy1 DBy2 DBy3  
DBw0 DBw1DBw2 DBw3 DBx0 DBx1  
DBz1 DBz2 DBz3  
DBy0  
Write  
DBz0  
Write  
Activate  
Command  
Bank A  
Precharge  
Command  
Bank B  
Write  
Command  
Bank A  
Command  
Bank B  
Command  
Bank B  
Write  
Activate  
Command  
Bank B  
Command  
Bank B  
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P. 36  
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T431616D/E  
Figure 10.2. Random Column Write (Page within same Bank)  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RBz  
RBw  
RBz  
CBz  
CBy  
CBw  
CBx  
RBw  
A0~A9  
DQM  
Hi-Z  
DBz0  
Write  
DBy0  
Write  
DBw0 DBw1DBw2 DBw3 DBx0 DBx1  
DBy1 DBy2 DBy3  
DBz1  
DBz2 DBz3  
DQ  
Activate  
Write  
Write  
Command  
Bank B  
Precharge  
Command Command  
Activate  
Command Command  
Command  
Bank B  
Command  
Bank B  
Bank A  
Bank B  
Bank B  
Bank B  
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P. 37  
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T431616D/E  
Figure 10.3. Random Column Write (Page within same Bank)  
(Burst Length=4, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK3  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RBz  
RBw  
RBz  
CBz  
CBw  
RBw  
CBx  
CBy  
A0~A9  
DQM  
Hi-Z  
DBy0  
Write  
DBz0  
Write  
DBz2  
DBz1  
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1  
DBy1 DBy2 DBy3  
DQ  
Activate  
Command  
Bank A  
Write  
Command  
Bank B  
Write  
Command  
Bank B  
Precharge  
Command  
Bank B  
Activate  
Command  
Bank B  
Command  
Bank B  
Command  
Bank B  
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P. 38  
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T431616D/E  
Figure 11.1. Random Row Read (Interleaving Banks)  
(Burst Length=8, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK1  
High  
CS#  
RAS#  
CAS#  
WE#  
A11  
RBx  
RAx  
RAx  
RBy  
RBy  
A10  
CAx  
RBx  
CBy  
CBx  
A0~A9  
DQM  
tRCD  
tRP  
tAC1  
Hi-Z  
DQ  
By0  
By1 By2  
Ax0 Ax1 Ax2 Ax3  
Ax4 Ax5 Ax6 Ax7  
Bx6  
Bx0  
Bx1 Bx2 Bx3 Bx4 Bx5  
Bx7  
Activate  
Precharge  
Command  
Bank B  
Read  
Command  
Bank B  
Precharge  
Command  
Bank A  
Activate  
Command  
Bank A  
Command  
Bank B  
Activate  
Command  
Bank B  
Read  
Read  
Command  
Bank A  
Command  
Bank B  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 39  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 11.2. Random Row Read (Interleaving Banks)  
(Burst Length=8, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RBx  
RBx  
RAx  
RAx  
RBy  
RBy  
CBx  
CAx  
CBy  
A0~A9  
DQM  
tRCD  
tAC2  
tRP  
Hi-Z  
DQ  
Bx0  
Bx1 Bx2  
Bx3 Bx4  
Bx5 Bx6 Bx7  
Ax1 Ax2 Ax3  
By0 By1  
Ax6  
Ax7  
Ax4 Ax5  
Ax0  
Activate  
Command  
Bank B  
Read  
Command  
Bank B  
Activate  
Command  
Bank A  
Precharge  
Activate  
Command  
Bank B  
Read  
Command  
Bank B  
Command  
Bank B  
Read  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 40  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 11.3. Random Row Read (Interleaving Banks)  
(Burst Length=8, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK3  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RBx  
RAx  
RAx  
RBy  
RBx  
RBy  
CBy  
CBx  
CAx  
A0~A9  
DQM  
tRP  
tRCD  
tAC3  
Hi-Z  
DQ  
Ax7  
By0  
Bx6  
Bx0 Bx1 Bx2 Bx3  
Bx4 Bx5  
Bx7  
Ax0 Ax1 Ax2  
Ax3  
Ax4 Ax5 Ax6  
Activate  
Command  
Bank B  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Precharge  
Command  
Bank B  
Activate  
Command  
Bank B  
Read  
Command  
Bank B  
Precharge  
Command  
Bank A  
Read  
Command  
Bank B  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 41  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 12.1. Random Row Write (Interleaving Banks)  
(Burst Length=8, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK1  
CKE  
High  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAy  
RAy  
RAx  
RAx  
RBx  
RBx  
A0~A9  
DQM  
CAy  
CBx  
CAx  
tRCD  
tRP  
tWR  
Hi-Z  
DQ  
DBx7  
DAx7 DBx0 DBx1 DBx2 DBx3DBx4 DBx5 DBx6  
DAy0 DAy1 DAy2  
DAx6  
DAy3  
DAx0 DAx1 DAx2DAx3 DAx4 DAx5  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Precharge  
Command  
Bank A  
Precharge  
Command  
Bank B  
Write  
Command  
Bank A  
Write  
Activate  
Command  
Bank A  
Write  
Command  
Bank A  
Command  
Bank B  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 42  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 12.2. Random Row Write (Interleaving Banks)  
(Burst Length=8, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAx  
RAy  
RAy  
A10  
RBx  
RBx  
RAx  
CAx  
CBx  
CAy  
A0~A9  
DQM  
tRCD  
tWR*  
tRP  
tWR*  
Hi-Z  
DQ  
DBx7  
DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6  
DAy3  
DAy4  
DAx6  
DAy0 DAy1DAy2  
DAx0 DAx1 DAx2 DAx3 DAx4DAx5  
Activate  
Command Command  
Bank A Bank A  
Write  
Activate  
Command  
Bank B  
Write  
Command  
Bank B  
Activate  
Command  
Bank A  
Write  
Command  
Bank A  
Precharge  
Precharge  
Command  
Bank B  
Command  
Bank A  
* tWR > tWR(min.)  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 43  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 12.3. Random Row Write (Interleaving Banks)  
(Burst Length=8, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK3  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAy  
RAx  
RBx  
RBx  
CAy  
RAx  
CAx  
CBx  
RAy  
A0~A9  
DQM  
tRCD  
tWR*  
tRP  
WR*  
t
Hi-Z  
DBx7  
DAy3  
DAy0 DAy1 DAy2  
DBx5 DBx6  
DAx6  
DAx7 DBx0 DBx1DBx2 DBx3 DBx4  
DQ  
DAx2 DAx3 DAx4 DAx5  
DAx0 DAx1  
Write  
Command  
Bank A  
Activate  
Command  
Bank B  
Write  
Command  
Bank B  
Precharge  
Command  
Bank A  
Activate  
Command  
Bank A  
Precharge  
Command  
Bank B  
Activate  
Command  
Bank A  
Write  
Command  
Bank A  
* tWR > tWR(min.)  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 44  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 13.1. Read and Write Cycle  
(Burst Length=4, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK1  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAx  
A10  
RAx CAx  
CAy  
CAz  
A0~A9  
DQM  
Hi-Z  
Az3  
DQ  
Ax0 Ax1 Ax2  
Ax3  
DAy0DAy1  
DAy3  
Az0 Az1  
Read  
Command  
Bank A  
Activate  
Command  
Bank A  
Write  
Command  
Bank A  
The Read Data  
Precharge  
Command  
Bank B  
The Write Data  
is Masked with a  
Zero Clock  
is Masked with a  
TwoClock  
Read  
Latency  
Latency  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 45  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 13.2. Read and Write Cycle  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RAx  
CAx  
CAz  
CAy  
A0~A9  
DQM  
Hi-Z  
Az3  
DQ  
Ax0 Ax1 Ax2 Ax3  
DAy0DAy1  
DAy3  
Az0 Az1  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Write The Write Data  
Read  
Command  
Bank A  
The Read Data  
Command is Masked with a  
is Masked with a  
TwoClock  
Bank A  
Zero Clock  
Latency  
Latency  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 46  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 13.3. Read and Write Cycle  
(Burst Length=4, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK3  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
CAy  
CAz  
CAx  
RAx  
A0~A9  
DQM  
Hi-Z  
Az3  
DQ  
Ax0 Ax1 Ax2 Ax3  
DAy0 DAy1  
DAy3  
Az0 Az1  
Read  
Command  
Bank A  
Write  
The Write Data  
Read  
The Read Data  
Activate  
Command  
Bank A  
Command is Masked with a Command  
is Masked with a  
TwoClock  
Bank A  
Zero Clock  
Latency  
Bank A  
Latency  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 47  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 14.1. Interleaving Column Read Cycle  
(Burst Length=4, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK1  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RAx  
RBw  
RBw CBw  
CBy  
RAx  
CBx  
CAy  
CBz  
A0~A9  
t
RCD tAC1  
DQM  
DQ  
Hi-Z  
Bz2 Bz3  
Ax0 Ax1 Ax2  
Ax3 Bw0 Bw1 Bx0 Bx1 By0  
By1 Ay0  
Ay1 Bz0  
Read  
Bz1  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Read  
Command  
Bank B  
Read  
Command  
Bank B  
Read  
Command  
Bank A  
Precharge  
Precharge  
Command  
Bank B  
Command Command  
Bank B  
Bank A  
Read  
Read  
Command  
Bank A  
Command  
Bank B  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 48  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 14.2. Interleaving Column Read Cycle  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAx  
RAx  
RAx  
RAx  
A10  
CAy  
CBx  
CBy  
CAy  
CBz  
CBw  
A0~A9  
DQM  
tRCD  
tAC2  
Hi-Z  
Bz2 Bz3  
DQ  
Ax0  
Ax1 Ax2  
Ax3  
By0  
Ay1  
Bz1  
Bw0 Bw1 Bx0 Bx1  
By1 Ay0  
Bz0  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Activate  
Command  
Bank B  
Read  
Command Command  
Bank B Bank B  
Read  
Read  
Command  
Bank A  
Read  
Precharge  
Command  
Bank B  
Read  
Command  
Bank B  
Command  
Bank B  
Precharge  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 49  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 14.3. Interleaved Column Read Cycle  
(Burst Length=4, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK3  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RAx  
RBx  
CAx RBx  
CBx  
CBz  
CBy  
CAy  
A0~A9  
DQM  
tAC3  
tRCD  
Hi-Z  
DQ  
Ax0  
Ax1 Ax2  
Ax3 Bx0  
Read  
Bx1 By0 By1  
Bz0 Bz1 Ay0 Ay1 Ay2 Ay3  
Precharge  
Command  
Bank A  
Activate  
Command  
Bank A  
Read  
Read  
Command  
Bank B  
Read  
Command  
Bank B  
Read Prechaerge  
Command Command  
Bank A Bank B  
Command  
Bank A  
Command  
Bank B  
Activate  
Command  
Bank B  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 50  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 15.1. Interleaved Column Write Cycle  
(Burst Length=4, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK1  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RBw  
CBy  
CBz  
RAx CAx RBw  
CBw  
CBx  
CAy  
A0~A9  
tRP  
tWR tRP  
tRCD  
tRRD  
DQM  
DQ  
Hi-Z  
DAx0  
DBz2  
DBz3  
DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1  
DBz0 DBz1  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Write  
Command Command  
Bank B Bank B  
Write  
Write  
Command Command  
Bank B Bank A  
Write  
Write  
Command  
Bank B  
Precharge  
Command  
Bank B  
Precharge  
Write  
Command  
Bank A  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 51  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 15.2. Interleaved Column Write Cycle  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RAx  
RBw  
RBw  
CBw  
CBx  
CBy  
CBz  
CAx  
CAy  
A0~A9  
DQM  
tWR  
tRCD  
tRP  
tRP  
tRRD  
Hi-Z  
DAx0  
DBz2  
DBz3  
DQ  
DAx1 DAx2 DAx3DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1  
Activate  
Write  
Activate  
Command  
Bank B  
Write  
Command  
Bank B  
Write  
Command  
Bank B  
Write  
Write  
Write  
Command  
Bank B  
Precharge  
Command  
Bank B  
Command Command  
Command Command  
Bank A  
Bank A  
Bank B  
Bank A  
Precharge  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 52  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 15.3. Interleaved Column Write Cycle  
(Burst Length=4, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK3  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RAx  
RBw  
CBw  
CBx  
CBy  
CBz  
CAx RBw  
CAy  
A0~A9  
DQM  
tRCD  
tWR  
tRP  
tWR(min)  
tRRD > tRRD(min)  
Hi-Z  
DQ  
DBz2  
DAx0  
DAx1 DAx2 DAx3DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1  
DBz3  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Write  
Command  
Bank B  
Write  
Command  
Bank B  
Write  
Command  
Bank B  
Write  
Command  
Bank A  
Write  
Command  
Bank B  
Precharge  
Command  
Bank B  
Write  
Precharge  
Command  
Bank A  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 53  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 16.1. Auto Precharge after Read Burst  
(Burst Length=4, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK1  
High  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAx  
RBy  
RBy  
RBz  
RBz  
RBx  
RBx  
A10  
CBx  
CBy  
RAx CAx  
CAy  
CBz  
A0~A9  
DQM  
DQ  
Hi-Z  
Ax1 Ax2 Ax3  
Ay0  
Ay3 By0 By1  
By3  
Bz2  
Bx0  
Bx1 Bx2  
Bx3  
Ay1 Ay2  
Ax0  
By2  
Bz0 Bz1  
Bz3  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Activate  
Command  
Bank B  
Read with  
Activate  
Auto Precharge  
Command  
Bank B  
Command  
Bank B  
Read with  
Read  
Read with  
Read with  
Auto Precharge  
Command  
Bank B  
Command  
Bank A  
Auto Precharge  
Command  
Bank A  
Auto Precharge  
Command  
Bank B  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 54  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 16.2. Auto Precharge after Read Burst  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RAz  
RAz  
RBx  
RBx  
RBy  
RBy  
RAx  
CAz  
CAx  
CBx  
RAy  
CBy  
A0~A9  
DQM  
Hi-Z  
Ax1 Ax2 Ax3 Bx0  
Bx1 Bx2  
Bx3 Ay0 Ay1  
Activate  
Ay2 Ay3  
By0 By1  
Activate  
By3  
Az2  
Ax0  
By2  
DQ  
Az0  
Az1  
Activate  
Read  
Activate  
Read with  
Read with  
Read with  
Read with  
Command Command  
Command Auto Precharge  
Auto Precharge Command Auto Precharge Command Auto Precharge  
Bank A  
Bank A  
Bank B  
Command  
Bank B  
Command  
Bank A  
Bank B  
Command  
Bank B  
Bank A  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 55  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 16.3. Auto Precharge after Read Burst  
(Burst Length=4, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK3  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RBx  
RBx  
RBy  
RBy  
CAx  
CBx  
CAy  
CBy  
RAx  
A0~A9  
DQM  
Hi-Z  
DQ  
Ax0  
By2  
Ax1 Ax2 Ax3 Bx0  
Bx1 Bx2  
Bx3 Ay0 Ay1  
Ay2 Ay3  
By0 By1  
By3  
Activate  
Command  
Bank A  
Activate  
Read with  
Activate  
Command  
Bank B  
Read with  
Command  
Bank B  
Auto Precharge  
Command  
Bank B  
Auto Precharge  
Command  
Bank B  
Read with  
Read  
Auto Precharge  
Command  
Command  
Bank A  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 56  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 17.1. Auto Precharge after Write Burst  
(Burst Length=4, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK1  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAx  
RBx  
RBx  
RAz  
RAz  
RBy  
RBy  
A10  
A0~A9  
DQM  
RAx CAx  
CBx  
CAz  
CAy  
CBy  
Hi-Z  
DAx0  
DBy1 DBy2 DBy3  
DAz0 DAz0  
DAz0 DAz0  
DQ  
DAx1 DAx2 DAx3  
Activate  
DAy0  
DAy3 DBy0  
DBx0 DBx1 DBx2 DBx3  
DAy1 DAy2  
Writewith  
Writewith  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Activate  
Command  
Bank A  
Auto Precharge  
Command  
Bank B  
Auto Precharge  
Command  
Bank B  
Command  
Bank B  
Write  
Command  
Bank A  
Writewith  
Writewith  
Auto Precharge  
Command  
Auto Precharge  
Command  
Bank A  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 57  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 17.2. Auto Precharge after Write Burst  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAx  
RBy  
RBy  
RBx  
RBx  
RAz  
RAz  
A10  
A0~A9  
DQM  
CAy  
CBx  
CAz  
CAx  
CBy  
RAx  
Hi-Z  
DAx0  
Write  
DBy1  
DAz2 DAz3  
DBy2 DBy3  
Activate  
DQ  
DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1DAy2 DAy3  
DBy0  
DAz0 DAz1  
Activate  
Command Command  
Bank A Bank A  
Activate  
Writewith  
Writewith  
Auto Precharge  
Command  
Activate  
Writewith  
Writewith  
Command Auto Precharge  
Command Auto Precharge Command Auto Precharge  
Bank B  
Command  
Bank B  
Bank B  
Command  
Bank B  
Bank A  
Command  
Bank A  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 58  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 17.3. Auto Precharge after Write Burst  
(Burst Length=4, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK3  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
`
RAx  
RBy  
RBy  
RBx  
RBx  
A10  
CAx  
CAy  
CBy  
RAx  
CBx  
A0~A9  
DQM  
Hi-Z  
DAx0  
DBy1 DBy2 DBy3  
DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3  
DBy0  
DQ  
Activate  
Command  
Bank A  
Activate  
Writewith  
Auto Precharge  
Command  
Writewith  
Auto Precharge  
Command  
Activate  
Command  
Bank B  
Writewith  
Auto Precharge  
Command  
Command  
Bank B  
Write  
Bank B  
Bank A  
Bank B  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 59  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 18.1. Full Page Read Cycle  
(Burst Length=Full Page, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK1  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RBx  
RBx  
RBy  
RBy  
CBx  
RAx CAx  
A0~A9  
DQM  
tRP  
tRRD  
Hi-Z  
DQ  
Bx+6 Bx+7  
Ax+1  
Ax  
Ax+2  
Bx+1  
Bx+2 Bx+3 Bx+4 Bx+5  
Ax-2 Ax-1 Ax  
Ax+1 Bx  
Activate  
Activate  
Precharge  
Read  
Command  
Bank B  
Command Command  
Command  
Bank B  
The burst counter wraps  
from the highest order  
page address back to zero  
during this time interval  
Bank A  
Read  
Bank B  
Burst Stop  
Command  
Activate  
Command  
Bank B  
Full Page burst operation doesnot  
terminate when the burst length is satisfied;  
the burst counter increments and continues  
bursting beginning with the starting address.  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 60  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 18.2. Full Page Read Cycle  
(Burst Length=Full Page, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RBx  
RAx  
RBy  
RBy  
RAx  
CBx  
CAx  
RBx  
A0~A9  
DQM  
tRP  
Hi-Z  
Ax  
Ax+2 Ax-2 Ax-1 Ax  
Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4Bx+5  
Full Page burst operation doesnot  
DQ  
Ax+1  
Bx+6  
Activate  
Read  
Activate  
Command  
Bank B  
Read  
Command  
Precharge  
Command  
Bank B  
Activate  
Command  
Bank B  
Command Command  
terminate when the burst length is satisfied;  
Bank A  
Bank A  
Bank B  
The burst counter wraps  
from the highest order  
page address back to zero  
during this time interval  
the burst counter increments and continues  
bursting beginning with the starting address.  
Burst Stop  
Command  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 61  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 18.3. Full Page Read Cycle  
(Burst Length=Full Page, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK3  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RBy  
RBy  
RBx  
RBx  
CAx  
RAx  
CBx  
A0~A9  
DQM  
tRP  
Hi-Z  
Ax+1  
DQ  
Ax  
Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Activate  
Command  
Bank B  
Read  
Command  
Bank B  
Precharge  
Command  
Bank B  
Activate  
Command  
Bank B  
Full Page burst operation doesnot  
terminate when the burst length is  
satisfied; the burst counter  
increments and continues  
The burst counter wraps  
from the highest order  
page address back to zero  
during this time interval  
bursting beginning with the  
Burst Stop  
Command  
starting address.  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 62  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 19.1. Full Page Write Cycle  
(Burst Length=Full Page, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK1  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RBx  
RAx  
RBy  
RBy  
RAx  
CAx RBx  
CBx  
A0~A9  
DQM  
Hi-Z  
DBx+1  
DBx+2  
DBx  
DAx+1  
DBx+3  
DQ  
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx  
DBx+4 DBx+5 DBx+6 DBx+7  
Data is ignored  
Activate  
Command  
Bank B  
Activate  
Command  
Bank A  
Write  
Precharge  
Command  
Bank B  
Command  
Bank B  
Full Page burst operation does  
not terminate when the burst  
length is satisfied; the burst counter  
increments and continues bursting  
beginning with the starting address.  
Burst Stop  
Command  
The burst counter wraps  
Activate  
Command  
Bank B  
from the highest order  
page address back to zero  
during this time interval  
Write  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 63  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 19.2. Full Page Write Cycle  
(Burst Length=Full Page, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RBx  
RBx  
RBy  
RBy  
CBx  
RAx  
CAx  
A0~A9  
DQM  
Hi-Z  
DAx+1  
DBx+3  
DBx DBx+1  
Write  
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx  
DBx+2  
DBx+4 DBx+5 DBx+6  
Data is ignored  
DQ  
Activate  
Command  
Bank A  
Write  
Command  
Bank A  
Activate  
Command  
Bank B  
Precharge  
Command  
Bank B  
Activate  
Command  
Bank B  
Command  
Bank B  
Full Page burst operation does  
not terminate when the burst  
length is satisfied; the burst counter  
increments and continues bursting  
beginning with the starting address.  
The burst counter wraps  
from the highest order  
page address back to zero  
during this time interval  
Burst Stop  
Command  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 64  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 19.3. Full Page Write Cycle  
(Burst Length=Full Page, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK3  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAx  
RBx  
RBx  
RBy  
RBy  
A10  
A0~A9  
DQM  
CBx  
RAx  
CAx  
Data is ignored  
Hi-Z  
DBx DBx+1  
Write  
DAx+1  
DBx+3  
DBx+4 DBx+5  
DQ  
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx  
DBx+2  
Activate  
Command  
Bank A  
Write  
Command  
Bank A  
Precharge  
Command  
Bank B  
Activate  
Command  
Bank B  
Activate  
Command  
Bank B  
Command  
Bank B  
The burst counter wraps  
from the highest order  
page address back to zero  
during this time interval  
Full Page burst operation does  
not terminate when the burst  
length is satisfied; the burst counter  
increments and continues bursting  
beginning with the starting address.  
Burst Stop  
Command  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 65  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 20. Byte Write Operation  
(Burst Length=4, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
CAy  
CAx  
CAz  
RAx  
A0~A9  
LDQM  
UDQM  
DQ0 - DQ7  
DQ8 - DQ15  
Ax0 Ax1 Ax2  
DAy2  
DAy1  
Az1 Az2  
Ax1  
Ax2 Ax3  
DAy0 DAy1  
DAy3  
Az0  
Az1 Az2 Az3  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Write  
Command  
Bank A  
Upper 3 Bytes  
are masked  
Lower Byte  
is masked  
Upper 3 Bytes  
Read  
Lower Byte  
is masked  
Lower Byte  
is masked  
are masked Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 66  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 21. Random Row Read (Interleaving Banks)  
(Burst Length=2, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK1  
High  
Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto Begin Auto  
CKE  
CS#  
Precharge  
Bank B  
Precharge  
Bank A  
Precharge  
Bank B  
Precharge  
Bank A  
Precharge  
Bank B  
Precharge  
Bank A  
Precharge  
Bank B  
Precharge  
Bank A  
Precharge  
Bank B  
Precharge  
Bank A  
RAS#  
CAS#  
WE#  
A11  
RAw  
RAx  
RBz  
RBv  
RAv  
RBy  
RAy  
RAz  
RAu  
RBx  
RBu  
RBw  
A10  
A0~A9  
DQM  
RBu  
CBv  
t
RAv  
CAw  
t
RAx CAx  
RBy CBy  
RAy CAy RBz  
CBz RAz  
CBu RAu CAu  
RBv  
CAv  
CBw RAw  
CBx  
t
RBx  
RBw  
t
t
t
t
t
t
t
RP  
RP  
RP  
RP  
RP  
RP  
RP  
RP  
RP  
RP  
Bu0  
Bu1 Au0  
Au1  
Bv0 Bv1  
Av0  
Av1 Bw0 Bw1 Aw0 Aw1 Bx0 Bx1  
Ax0 Ax1 By0  
By1 Ay0 Ay1  
Bz0  
DQ  
Activate  
Command  
Bank B  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Activate  
Command  
Bank A  
Activate  
Command  
Bank B  
Activate  
Command  
Bank A  
Read  
Read  
Read  
Read  
Read  
Read  
Read  
Read  
Read  
Read  
Read  
Bank B  
with Auto  
Precharge  
Bank B  
with Auto  
Precharge  
Bank A  
with Auto  
Precharge  
Bank B  
with Auto  
Precharge  
Bank A  
with Auto  
Precharge  
Bank B  
with Auto  
Precharge  
Bank A  
with Auto  
Precharge  
Bank B  
with Auto  
Precharge  
Bank A  
with Auto  
Precharge  
Bank B  
with Auto  
Precharge  
Bank A  
with Auto  
Precharge  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 67  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 22. Full Page Random Column Read  
(Burst Length=Full Page, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK2  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RAx  
RBx  
RBx  
RBw  
RBw  
CAx  
CAz  
CBx CAy  
CBy  
CBz  
A0~A9  
tRP  
DQM  
DQ  
tRRD  
tRCD  
Ax0 Bx0 Ay0 Ay1  
By0 By1 Az0 Az1  
Az2 Bz0 Bz1  
Bz2  
Activate  
Command  
Bank B  
Read  
Command  
Bank B  
Read  
Command  
Bank B  
Read  
Command  
Bank A  
Read  
Command  
Bank B  
Precharge  
Command Bank B  
(Precharge Temination)  
Activate  
Command  
Bank A  
Read  
Activate  
Read  
Command  
Bank A  
Command  
Bank B  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 68  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 23. Full Page Random Column Write  
(Burst Length=Full Page, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK2  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAx  
RBx  
RBw  
A10  
RAx  
RBx CAx  
CAz  
CBx CAy  
CBy  
CBz  
RBw  
A0~A9  
tRP  
tWR  
DQM  
DQ  
tRRD  
tRCD  
DBz2  
DAx0DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1  
Activate  
Command  
Bank B  
Write  
Command  
Bank B  
Write  
Command  
Bank B  
Write  
Command  
Bank A  
Write  
Command  
Bank B  
Precharge  
Command Bank B  
(Precharge Temination)  
Activate  
Command  
Bank A  
Write  
Write  
Activate  
Command  
Bank B  
Command  
Bank A  
Command  
Bank A  
Write Data  
is masked  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 69  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 24.1. Precharge Termination of a Burst  
(Burst Length=Full Page, CAS# Latency=1)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
tCK1  
CS#  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RAy  
RAy  
RAz  
CAy  
RAx  
CAx  
RAz  
CAz  
A0~A9  
tRP  
tWR  
tRP  
Precharge  
Termination of  
a Read Burst.  
DQM  
DQ  
DAz6 DAz7  
DAx0 DAx1DAx2 DAx3 DAx4  
DAz0  
DAz1 DAz2DAz3  
DAz4 DAz5  
Ay0 Ay1 Ay2  
Read  
Precharge  
Command  
Bank A  
Write  
Command  
Bank A  
Activate  
Command  
Bank A  
Precharge  
Command  
Bank A  
Precharge Termination  
of a Write Burst.  
Command  
Bank A  
Writedata is masked.  
Write  
Activate  
Command  
Bank A  
Activate  
Command  
Bank A  
Command  
Bank A  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 70  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 24.2. Precharge Termination of a Burst  
(Burst Length=8 or Full Page, CAS# Latency=2)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
CKE  
CS#  
tCK2  
High  
RAS#  
CAS#  
WE#  
A11  
A10  
RAx  
RAy  
RAy  
RAz  
RAz  
CAy  
CAz  
RAx  
CAx  
A0~A9  
DQM  
DQ  
tRP  
tWR  
tRP  
tRP  
DAx0 DAx1DAx2 DAx3  
Ay0 Ay1 Ay2  
Az0 Az1 Az2  
Precharge  
Command  
Bank A  
Precharge  
Command  
Bank A  
Activate  
Command  
Bank A  
Write  
Command  
Bank A  
Precharge  
Command  
Bank A  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Activate  
Command  
Bank A  
Read  
Command  
Bank A  
Precharge Termination  
of a Read Burst  
Precharge Termination  
of a Write Burst.  
Writedata is masked.  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 71  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
Figure 24.3. Precharge Termination of a Burst  
(Burst Length=4, 8 or Full Page, CAS# Latency=3)  
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22  
CLK  
tCK3  
High  
CKE  
CS#  
RAS#  
CAS#  
WE#  
A11  
RAx  
RAy  
RAy  
RAz  
RAz  
A10  
CAy  
RAx  
CAx  
A0~A9  
tWR  
tRP  
tRP  
DQM  
DQ  
Ay0 Ay1 Ay2  
DAx0 DAx1  
Precharge  
Command  
Bank A  
Read  
Command  
Bank A  
Precharge  
Command  
Bank A  
Activate  
Command  
Bank A  
Activate  
Command  
Bank A  
Write  
Command  
Bank A  
Activate  
Command  
Bank A  
Precharge Termination  
of a Read Burst  
Write Data  
is masked  
Precharge Termination  
of a Write Burst  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 72  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
50 Pin TSOP II Package Outline Drawing Information  
50  
26  
θ°  
L
L1  
1
25  
D
L
L1  
e
S
B
y
Symbol  
Dimension in inch  
Dimension in mm  
Min  
Normal  
-
Max  
0.047  
0.008  
0.039  
0.018  
-
0.83  
0.402  
-
Min  
Normal  
-
Max  
1.20  
0.20  
1
A
A1  
A2  
B
c
D
-
0.002  
-
0.012  
-
0.82  
0.398  
-
-
0.05  
-
0.3  
-
20.82  
10.11  
-
0.005  
-
0.125  
-
0.015  
0.006  
0.825  
0.400  
0.031  
0.375  
0.155  
20.95  
10.16  
0.80  
0.45  
-
21.08  
10.21  
-
E
e
HE  
L
L1  
S
y
θ
0.459  
0.463  
0.020  
0.0315  
0.035  
-
0.467  
0.024  
-
11.66  
11.76  
0.50  
0.80  
0.88  
-
11.86  
0.60  
-
0.016  
0.40  
-
-
-
-
-
-
-
-
0.004  
5°  
0.10  
5°  
-
-
0°  
0°  
Notes :  
1. Dimension D&E do not include interiead flash.  
2. Dimension B does not include dambar protrusion/intrusion.  
3. Dimension S includes end flash.  
4. Controlling dimension : mm  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 73  
Publication Date: FEB. 2007  
Revision: A  
TE  
tmCH  
T431616D/E  
60-Ball (6.4mm x 10.1mm)VFBGA  
Units in mm  
TOP VIEW  
BOTTOM VIEW  
A1 CORNER  
A1 CORNER  
M
N P R  
R P N M L K J H G F E D C B A  
A B C D E F G H J K L  
C
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A B  
D
D1  
B1  
A1  
C1  
E3  
E2  
E
E1  
SEATING PLANE  
Dimension in mm  
Dimension in inch  
Nom  
Symbol  
Min  
6.30  
10.00  
-
-
-
Nom  
6.40  
Max  
6.50  
10.20  
-
Min  
Max  
2.56  
0.402  
-
A
A1  
B
0.248  
2.52  
0.398  
10.10  
3.90(typ)  
9.10(typ)  
0.65(typ)  
0.65(typ)  
0.4  
0.394  
-
0.154(typ)  
0.358(typ)  
0.026(typ)  
0.026(typ)  
0.016  
B1  
C
-
-
-
-
-
-
-
-
C1  
D
-
0.35  
0.35  
0.22  
-
0.45  
0.45  
0.32  
1.00*  
-
0.014  
0.014  
0.009  
-
0.018  
0.018  
0.13  
0.039  
-
D1  
E
0.4  
0.016  
0.27  
0.11  
E1  
E2  
E3  
-
-
-
0.21  
-
0.008  
0.42  
0.45  
0.48  
0.017  
0.018  
0.019  
Note : * if lead free package “E1” max.=1.2mm(0.047 inch)  
TM Technology Inc. reserves the right  
to change products or specifications without notice.  
P. 74  
Publication Date: FEB. 2007  
Revision: A  

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