首页 > T15N1024A

T15N1024A

更新时间：2024-09-18 02:11:02

品牌：TMT

描述：128K X 8 LOW POWER CMOS STATIC RAM

PDF下载

中文翻译

PCB计价

概述
数据手册

如果您发现信息不准确，欢迎纠错

T15N1024A 概述

128K X 8 LOW POWER CMOS STATIC RAM 128K ×8低功耗CMOS静态RAM

T15N1024A 数据手册

通过下载T15N1024A数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载

tmCH

T15N1024A

128K X 8 LOW POWER

CMOS STATIC RAM

SRAM

FEATURES

GENERAL DESCRIPTION

• Low-power consumption

- Active: 40mA at 55ns (Max.)

- CMOS Stand-by: 10uA (Max.)

• 55/70/100 ns access time

The T15N1024A is a very Low Power CMOS

Static RAM organized as 131,072 words by 8 bits.

That operates on a wide voltage range from 2.4V

to 3.6V power supply, Fabricated using high

performance CMOS technology, Inputs and

three-state outputs are TTL compatible and allow

for direct interfacing with common system bus

structures. Data retention is guaranteed at a power

supply voltage as low as 1.5V.

• Equal access and cycle time

• Single +2.4V to 3.6V Power Supply

• TTL compatible , Tri-state output

• Common I/O capability

• Automatic power-down when deselected

• Available in 32-pin SOP ,TSOP-I(8x20mm),

TSOP-I(8x13.4mm) ,48-pin CSP packages

BLOCK DIAGRAM

• Operating temperature :

Commercial : 0 ~ +70 °C

Industrial

-40 ~ +85 °C

Vcc

Vss

PART NUMBER EXAMPLES

CORE

ARRAY

PACKAGE

CODE

Operating

Temperature

DECODER

PART NO.

T15N1024A-55D

T15N1024A-70H

T15N1024A-100P

T15N1024A-100C

T15N1024A-55DI

T15N1024A-70HI

T15N1024A-100PI

D=SOP

H=TSOP-I(8x20)

P=TSOP-I(8x13.4)

C=CSP

A16

0 ~ +70 °C

CE1

CE2

I/O1

D=SOP

CONTROL

CIRCUIT

DATA I/O

H=TSOP-I(8x20)

P=TSOP-I(8x13.4)

-40 ~ +85 °C

I/O8

T15N1024A-100CI C=CSP

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 1

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

PIN CONFIGURATIONS

A16

A14

A12

I/O1

I/O2

I/O3

VSS

VDD

A15

CE2

A13

A11

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

SOP

A11

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A11

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A13

CE2

A15

VDD

A16

A14

A12

A13

CE2

A15

VDD

A16

A14

A12

TSOP-I

(8x20mm)

TSOP-I

(8x13.4mm)

CE2

I/O5

I/O6

VSS

VDD

I/O7

I/O8

I/O1

I/O2

VDD

VSS

I/O3

I/O4

A14

48-CSP

TOP VIEW

CE1

A11

A16

A12

A15

A13

A10

PIN DESCRIPTIONS

SYMBOL DESCRIPTIONS

A0 ~ A16 Address inputs

SYMBOL DESCRIPTIONS

Output enable input

Power supply

Ground

I/O0~I/O8 Data inputs/outputs

CE1 CE2 Chip enable

VDD

VSS

Write enable input

No connection

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 2

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on Any Pin Relative to Gnd

Power Dissipation

SYM

V^R

P_D

MIN.

-0.5

MAX.

+4.6 V

0.7

UNIT

T_STG

Storage Temperature

-55

+150

+70

°C

commercial

industrial

Operating

°C

-40

+85

Temperature

*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to

the device. This is a stress rating only and function operation of the device at these or any other

conditions outside those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

TRUTH TABLE

CE2

DATA

MODE

Standby

CE 1

High-Z

Data Out

High-Z

Data In

Active, Read

Active, Output Disable

Active, Write

*Note: X = Don’t Care, L = Low, H = High

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 3

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

OPERATING CHARACTERISTICS

(Vcc = 2.4 to 3.6V, Gnd = 0V, Ta = 0 ~ +70 °C /-40°C to 85°C)

-55

-70

-100

PARAMETER SYM.

TESTCONDITIONS

UNIT

Min Max Min Max Min Max

Input Leakage

I_LI

Vcc = Max,

= Gnd to Vcc

Current

CE1 = V_IHor CE2= V_IL

or OE= V_IH

Output Leakage

I_LO

Current

or WE = V_IL

V_OUT= Gnd to Vcc

CE1 = V_IL,CE2= V_IH,

WE =V_IH,OE= V_{IH ,}

= V_IHor V_IL,

VIN

Operating Power

I_CC

Supply Current

I_OUT=0mA

Cycle time=1us,

100% duty, I_OUT=0mA,

I_CC1

CE1 ≤ 0.2V,

CE2 ≥ V_CC-0.2V,

V_IN≤ 0.2V

Average Operating

Current

Cycle time=min,

100% duty, I_OUT=0mA,

I_CC2

CE1 = V_IL,CE2= V_{IH ,}

V_IN= V_IHor V_IL

Standby Power

CE1 =V

I_SB

Supply Current

(TTL Level)

CE2= V_IL

0.5

CE1 ≥ Vcc-0.2V,

CE2 ≥ V_CC-0.2V

Standby Power

Supply Current

(CMOS Level)

I_SB1

or CE2 ≤ 0.2V

≤ 0.2V or

≥ Vcc-0.2V

V_OL

V_OH

_OL= 1.0mA

0.4

Output Low Voltage

Output High Voltage

_OH= -0.5 mA

2.1

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 4

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

RECOMMENDED OPERATING CONDITIONS

(Ta = 0 ~ +70 °C /-40°C to 85°C**)

PARAMETER

SYM

Vcc

MIN

2.4

MAX

3.6

UNIT

Supply Voltage

Gnd

0.0

1.6

Vcc+0.2

0.4

Input Voltage

-0.3

CAPACITANCE

(f = 1 MHz, Ta = 25°C,)

PARAMETER

Input Capacitance

SYMBOL

C_IN

CONDITION

MAX.

UNIT

= 0V

C_I/O

=V_OUT= 0V

Input/ Output Capacitance

Note: This parameter is guaranteed by device characterization and is not production tested.

AC TEST CONDITIONS

PARAMETER

CONDITIONS

Input Pulse Levels

0.2V to 2.1V

3.0 ns

Input Rise and Fall Times

Input and Output Timing Reference Level

1.4V

C_L=30pF+1TTL Load(55ns/70ns)

C_L=100pF+1TTL Load(Load for 100ns)

Output Load

AC TEST LOADS AND WAVEFORM

TTL

R_L

C_L

50 ohm

30 pF

C_L*

Z₀= 50 ohm

Vt =1.4V

Fig.A * Including Scope and Jig Capacitance

Fig.B Output Load Equivalent

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 5

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

AC CHARACTERISTICS(V =2.4 to 3.6V, Gnd = 0V, Ta = 0 ~ +70 °C /-40°C to 85°C)

(1) READ CYCLE

-55

-70

-100

PARAMETER

SYM.

UNIT

Min

Max

Min

Max

Min

Max

t_RC

Read Cycle Time

100

t_AA

t_ACE

t_OE

Address Access Time

100

Chip Enable Access Time

Output Enable Access Time

t_OH

Output Hold from Address Change

Chip Enable to Output in Low-Z

Chip Disable to Output in High-Z

Output Enable to Output in Low-Z

Output Disable to Output in High-Z

t_LZ

t_HZ

t_OLZ

t_OHZ

(2)WRITE CYCLE

-55

-70

-100

PARAMETER

SYM.

UNIT

Min

Max

Min

Max

Min

100

Max

t_WC

t_CW

t_AW

t_AS

Write Cycle Time

Chip Enable to Write End

Address Valid to Write End

Address Setup Time

t_WP

t_WR

t_DW

t_DH

t_WHZ

t_OW

Write Pulse Width

Write Recovery Time

Data Valid to Write End

Data Hold Time

Write Enable to Output in High-Z

Output Active from Write End

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 6

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

t_RC

Address

t_AA

t_OH

Previous Data Vaild

D_out

Data Vaild

DON'T CARE

UNDEFINED

READ CYCLE 2

(Chip Enable Controlled)

CE1

CE2

D_out

t_ACE

t_LZ

t_HZ

DON'T CARE

UNDEFINED

Notes (READ CYCLE) :

1. WE are high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. t_HZand t_OHZare defined as the time at which the outputs achieve the open circuit condition referenced to

_OHor V_OLlevels.

4. At any given temperature and voltage condition. t_HZ(max.) is less than t_LZ(min.) both for a given device

and from device to device interconnection.

5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not

100% tested.

6. Device is continuously selected with CE1 =V_IL.

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 7

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

WRITE CYCLE 1 (WE Controlled)

t _W

A d d r e s s

t _W

t _A

t _C

E 1

E 2

t _A

t _W

t _O

t _W

i g h - Z

t _D

I N

i g h - Z

C A R E

I N E D

WRITE CYCLE 2 (CE Controlled)

t _W

A d d r e s

t _{A W}

t _W

t _C

C E 1

t _{A S}

C E 2

t _W

H ig h - Z

o u t

t _D

I N

D O N 'T C A R E

U N D E F I N E D

NOTES ( WRITE CYCLE ) :

1. A write occurs during the overlap of a low CE1, a high CE2 and a low WE . A write begins at

the lateat transition among CE1 goes low, CE2 going high and WE going low. A write end at

the earliest transition among CE1 going high, CE2 going low and WE going high. tWP is

measured from the beginning of write to the end of write.

2. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change.

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 8

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

DATA RETENTION CHARACTERISTICS

(Ta = 0 ~ +70 °C /-40°C to 85°C)

PARAMETER

V_CCfor Data Retention

SYM. TEST CONDITION

MIN.

1.5

MAX.

UNIT

V_DR

I_CCDR

t_CDR

t_R

CE1≥ VDD -0.2V

CE2 ≤ 0.2V

Data Retention Current

Chip Deselect to Data Retention Time

Operation Recovery Time

V_IN≥ Vcc -0.2V or

V_IN≤ 0.2V

tRC

* VCC=1.8V

DATA RETENTION WAVEFORM

(Ta = 0 ~ +70 °C /-40°C to 85°C)

Data Retention Mode

Vcc_typ

_DR> 1.5V

Vcc_TYP

VCC

CDR

CE1>VCC-0.2V

CE2 < 0.2V

CE1

CE2

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 9

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

PACKAGE DIMENSIONS

32-LEAD SOP

E HE

Detail F

See Detail F

Seating Plane

Dimension in inches

Dimension in mm

max min. typ. max.

Symbol

Notes :

min.

typ.

1. Dimensions D max. & S

include mold flash or tie bar

burrs.

2. Dimension b does not include

dambar protrusion / intrusion.

3. Dimensions D & E include

mold mismatch and determined

at the mold parting line.

0.118

3.00

0.004

0.10

0.101 0.106 0.111 2.57

0.014 0.016 0.020 0.36

0.006 0.008 0.012 0.15

2.69

0.41

0.20

2.82

0.51

0.31

0.805 0.817

0.440 0.445 0.450 11.18 11.30 11.43

0.044 0.050 0.056 1.12 1.27 1.42

0.546 0.556 0.556 13.87 14.12 14.38

20.45 20.75

4. controlling dimension : inches

5. general appearance spec should

be based on final visual

inspection spec.

0.023 0.031 0.039 0.58

0.047 0.055 0.063 1.19

0.79

0.99

1.60

0.91

0.10

10°

1.40

0.036

0.004

10°

0°

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 10

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

PACKAGE DIMENSIONS

32-LEAD TSOP (8x20mm)

SYMBOL

DIMENSIONS IN INCHES

DIMENSIONS IN MM

MIN

NOM

MAX

MIN

NOM

MAX

1.20

0.15

1.05

0.27

0.21

0.047

0.006

0.041

0.011

0.008

0.002

0.035

0.007

0.004

0.05

0.90

0.17

0.10

0.040

1.00

0.008

0.20

0.006

0.15

0.787 TYP

0.724 TYP

0.315 TYP

0.024

20.00 TYP

18.40 TYP

8.00 TYP

0.610

0.020

0.028

0.598

0.622

0.032 TYP

0°~12°

0.813 TYP

0°~12°

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 11

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

PACKAGE DIMENSIONS

32-LEAD TSOP-I (8x13.4mm)

H D

3 2

1 6

1 7

A 2

A 1

"A "

S e a tin g p la n e

D e ta il "A "

L 1

SYMBOL Dimension in inches

Dimension in mm

1.10(MAX)

0.05±0.05

1.02(MAX)

0.20±0.10

0.15±0.02

11.8±0.2

0.044(MAX)

0.004±0.002

0.041(MAX)

0.008±0.004

0.006±0.001

0.465±0.008

0.315±0.004

0.528±0.008

0.020(TYP.)

0.020±0.004

0.031±0.008

0.002(MAX)

0° ~ 5°

8.0±0.1

13.4±0.2

0.5(TYP.)

0.5±0.1

0.8±0.2

0.05(MAX)

0° ~ 5°

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 12

Publication Date: FEB. 2003

Revision:E

tmCH

T15N1024A

PACKAGE DIMENSIONS

Units : millimeters

48-pin CSP (8 row x 6 column)

48 BALL FINE PITCH BGA (0.75mm ball pitch)

Bottom View

Top View

A1 INDEX MARK

0.50

#A1

B/2

0.30

Symbol

min

typ

0.75

6.00

3.75

8.00

5.25

0.30

1.10

0.95

0.25

max

5.95

6.05

Notes :

1. Bump counts : 48 (8 row x 6column)

2. Bump pitch : (x,y)=(0.75 x 0.75) typ.

3. All tolerance are ±0.050 unless otherwise specified.

4. ‘Y’ is coplanarity : 0.08(max)

7.95

8.05

0.25

0.35

1.20

5. Units : mm

0.20

0.30

0.08

TM Technology Inc. reserves the right

to change products or specifications without notice.

P. 13

Publication Date: FEB. 2003

Revision:E

T15N1024A 相关器件

型号	制造商	描述	价格	文档
T15N1024A-100C	TMT	128K X 8 LOW POWER CMOS STATIC RAM	获取价格
T15N1024A-100CI	TMT	128K X 8 LOW POWER CMOS STATIC RAM	获取价格
T15N1024A-100P	TMT	128K X 8 LOW POWER CMOS STATIC RAM	获取价格
T15N1024A-100PI	TMT	128K X 8 LOW POWER CMOS STATIC RAM	获取价格
T15N1024A-55D	TMT	128K X 8 LOW POWER CMOS STATIC RAM	获取价格
T15N1024A-55DI	TMT	128K X 8 LOW POWER CMOS STATIC RAM	获取价格
T15N1024A-70H	TMT	128K X 8 LOW POWER CMOS STATIC RAM	获取价格
T15N1024A-70HI	TMT	128K X 8 LOW POWER CMOS STATIC RAM	获取价格
T15N1M16A	TMT	64K X 16 LOW POWER CMOS STATIC RAM	获取价格
T15N1M16A-70C	TMT	64K X 16 LOW POWER CMOS STATIC RAM	获取价格