XPS628303ARZER [TI]
采用小型 QFN 和 SOT583 封装、精度为 1% 的 2.25V 至 5.5V、3A 降压转换器 | RZE | 8 | -40 to 125;
| 型号： | XPS628303ARZER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用小型 QFN 和 SOT583 封装、精度为 1% 的 2.25V 至 5.5V、3A 降压转换器 | RZE | 8 | -40 to 125 转换器 |
| 文件： | 总37页 (文件大小：3350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS628303
ZHCSNO6 –FEBRUARY 2023
TPS628303，采用小型WQFN 和SOT583 封装且具有1% 输出精度的2.25V 至
5.5V 输入、1A/2A/3A/4A 降压转换器
1 特性
3 说明
• 2.25V 至5.5V 输入电压范围
• 0.5V 至4.5V 可调节输出电压
• 1% FB 电压精度（TJ 为–40°C 至125°C）
• 2.0MHz 开关频率
• 35mΩ和18mΩ内部功率MOSFET
• DCS-Control 拓扑
TPS628303 是一个具有低静态电流且易于使用的同步
降压直流/直流转换器系列。TPS628303 基于 DCS-
Control 拓扑，可提供快速瞬态响应和较小的输出电
容。由于具有内部基准，该系列器件可在 -40°C 至
125°C 的结温范围内以 1% 的高反馈电压精度将输出
电压调节到 0.5V 以下。该系列器件提供两种封装，各
封装器件之间引脚对引脚兼容。
• 优化的EMI 性能
• 有助于符合CISPR 11/32 标准
TPS628303 具有一个 MODE 引脚，用于控制器件的
工作模式。省电模式可在极轻负载下保持高效率，从而
延长系统电池的运行时间。强制PWM 模式会维持连续
导通模式，从而确保超低的输出电压纹波和准固定开关
频率。该器件具有电源正常信号和受控良好的内部软启
动电路。TPS628303 能够以 100% 模式运行。在故障
保护方面，TPS628303 加入了断续短路保护以及热关
断功能。一个器件选项具有针对短路和过压事件的闭锁
保护。该系列提供两种封装：8 引脚 1.0mm × 2.0mm
QFN 封装，提供超高功率密度解决方案；8 引脚
1.6mm × 2.1mm SOT583 封装，提供易于组装的解决
方案。
– 集成片上噪声滤波电容器
– 可根据CISPR 进行测量
• 绝佳的瞬态响应
• MODE 引脚，用于选择导通模式
• 支持1.2V GPIO
• 可实现最低压降的100% 占空比
• 有源输出放电
• 电源正常状态输出
• 热关断保护
• 断续或闭锁OCP/OVP
• 可提供PSpice 和SIMPLIS 模型
• 使用TPS628303 并借助WEBENCH® Power
Designer 创建定制设计方案
封装信息
封装(1)
封装尺寸（标称值）
器件型号
2 应用
RZE（WQFN，
8）
1.00 mm × 2.00 mm × 0.80
mm
• 固态硬盘
TPS628303
DRL（SOT583， 1.60 mm × 2.10 mm × 0.60
8） mm
• 便携式电子产品
• 模拟安防摄像头和IP 网络摄像头
• 工业PC
• 工厂自动化和控制
• ASIC、SoC 和MCU 电源
• 通用负载点
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
100
95
90
85
80
75
L1
0.47 µH
VIN
VOUT
1.8 V
TPS62830x
2.25 V to 5.5 V
VIN
SW
C1
4.7 µF
C2
2x10 µF
EN
R3
100 k
R1
VOS
523 k
MODE
PG
VPG
FB
GND
70
65
60
VOUT=1.2V
VOUT=1.8V
VOUT=2.5V
VOUT=3.3V
R2
200 k
100
1m
10m
Load [A]
100m
1
3
典型应用原理图
VIN = 5V 时的效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSG98
TPS628303
ZHCSNO6 –FEBRUARY 2023
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................10
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
9.3 Power Supply Recommendations.............................21
9.4 Layout....................................................................... 21
10 Device and Documentation Support..........................23
10.1 Device Support....................................................... 23
10.2 Documentation Support.......................................... 23
10.3 支持资源..................................................................23
10.4 Trademarks.............................................................23
10.5 静电放电警告.......................................................... 23
10.6 术语表..................................................................... 23
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 绝对最大额定值...........................................................4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information Discrete......................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................6
8 Detailed Description........................................................7
8.1 Overview.....................................................................7
8.2 Functional Block Diagram...........................................7
8.3 Feature Description.....................................................8
Information.................................................................... 24
11.1 Tape and Reel Information......................................24
4 Revision History
DATE
REVISION
NOTES
February 2023
*
Advance Information
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5 Device Options
PART NUMBER
TPS628303ARZER(1)
TPS628303ADRLR(1)
OUTPUT CURRENT
OCP MODE
PACKAGE
OUTPUT VOLTAGE
WQFN-HR
Hiccup
3 A
Adjustable
SOT583
OCP/OVP
Latch-off
TPS628303BDRLR(1)
(1) Preview status
6 Pin Configuration and Functions
VIN
GND
MODE
FB
EN
VIN
EN
SW
PG
SW
PG
GND
MODE
FB
VOS
VOS
图6-2. DRL Package 8-Pin SOT Top View
图6-1. RZE Package 8-Pin WQFN Top View
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
VIN
EN
1
PWR
I
Input voltage pin. Connect the input capacitor as close as possible between VIN and GND.
Device enable pin. To enable the device, this pin must be pulled high. Pulling this pin low
disables the device. Do not leave this pin unconnected.
8
GND
SW
2
7
Ground pin.
PWR
I
Switch pin of the power stage
The device runs in PSM/PWM mode when this pin is pulled low and in forced-PWM mode
when pulled high. This event can also be done when the device is in-operation. Do not leave
this pin floating.
MODE
PG
3
6
Power good open-drain output pin. The pullup resistor can be connected to voltages up to
5.5 V. If unused, leave this pin floating.
O
FB
4
5
I
I
Feedback pin. Connect the resistive output voltage divider to this pin.
VOS
Output voltage sense pin. This pin must be connected directly after the inductor.
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7 Specifications
7.1 绝对最大额定值
在工作结温范围内测得（除非另有说明）(1)
最小值
–0.3
-0.3
最大值
单位
电压(2)
电压(2)
电压(2)
TJ
VIN、EN、MODE、FB、PG
SW（直流）
SW（AC，< 10ns）(3)
6
V
VIN + 0.3
10
V
V
-2.5
-40
150
°C
°C
工作结温
Tstg
150
–65
贮存温度
(1) 超出绝对最大额定值的运行可能会对器件造成永久损坏。绝对最大额定值并不表示器件在这些条件下或在建议运行条件以外的任何其
他条件下能够正常运行。如果在建议运行条件之外但又在绝对最大额定值范围内使用，器件可能不会完全正常运行，这可能会影响器件
的可靠性、功能性和性能，并缩短器件的寿命。
(2) 所有电压值都相对于网络接地端而言。
(3) 打开开关时
7.2 ESD Ratings
VALUE
± 2000
± 500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
2.25
0.5
3
NOM
MAX
5.5
UNIT
VIN
VOUT
CIN
L
Input voltage range
V
V
Output voltage range
4.5
Effective input capacitance (1)
Nominal output inductor
µF
µH
µF
A
0.24
12
0.47
1.0
200
3
COUT
IOUT
IPG
Effective output capacitance (1)
Output current range; TPS628303
Power Good input current capability
Operating junction temperature
2
mA
°C
TJ
125
–40
(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias
effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the
manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied.
7.4 Thermal Information Discrete
TPS628303RZE
8 pin-WQFN
TPS628303DRL
8 pin-SOT583
THERMAL METRIC(1)
UNIT
JEDEC
EVM
JEDEC
EVM
RθJA
Junction-to-ambient thermal resistance
105.7
30.7
90.9
2.7
77.6
n/a(2)
n/a(2)
2.8
110.9
41.4
22.2
0.8
80
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
n/a(2)
n/a(2)
1.3
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
30.7
44.7
22.1
28.2
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.
(2) Not applicable to an EVM.
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7.5 Electrical Characteristics
TJ = –40°C to +125°C, VIN = 2.25 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = VIN, IOUT = 0 mA, VOUT = 1.8 V,
MODE = GND, device not switching
IQ
Operating quiescent current
7
17
µA
ISD
VIN shutdown supply current
EN = low, TJ = -40 oC to 85 o
C
100
2.15
120
700
nA
V
VUVLO(+)
VUVLO(hys)
THERMAL SHUTDOWN
Rising UVLO threshold voltage (VIN
)
2.05
90
2.25
UVLO hysteresis (VIN
)
mV
TJ(SD)
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
150
20
°C
°C
TJ(HYS)
LOGIC PINs
VEN(+)
Rising EN voltage threshold
Falling EN voltage threshold
Rising MODE voltage threshold
Falling MODE voltage threshold
EN Input leakage current
0.715
0.715
V
V
VEN(-)
0.4
VMODE(+)
VMODE(-)
IEN(LKG)
IMODE(LKG)
STARTUP
tSS
V
0.4
100
100
V
VEN = HIGH
10
10
nA
nA
MODE Input leakage current
VMODE = HIGH
Internal fixed soft-start time
Enable delay time
From VOUT= 0 to VOUT= 95%
180
300
120
440
220
µs
µs
td(EN)
From EN HIGH to device starts switching
REFERENCE VOLTAGE
VFB
Feedback voltage accuracy
PWM mode
495
–1
–1
500
505
+1
mV
%
VFB
Feedback voltage accuracy
Feedback voltage accuracy
PWM mode
VFB
+2
%
PFM mode, COUT,eff ≥15 µF, L = 0.47µH
IFB(LKG)
IVOS(LKG)
POWER GOOD
FB input leakage current, adjustable version VFB = 0.5 V
10
70
nA
nA
VOS input leakage current
VEN = low
100
500
Rising power good threshold
voltage (output undervoltage)
VPG,UV(+)
VPG,UV(-)
VPG,OV(+)
VPG,OV(-)
td(PG)
Power Good low, VFB rising
Power Good high, VFB falling
Power Good high, VFB rising
Power Good low, VFB falling
94
90
96
92
98
94
%
%
%
%
µs
Falling power good threshold
voltage (output undervoltage)
Rising power good threshold
voltage (output overvoltage)
108
103
30
110
105
40
112
107
55
Falling power good threshold
voltage (output overvoltage)
High-to-low or low-to-high transition on the
PG pin
Power good deglitch delay
PG pin Leakage current when open drain
output is high
IPG(LKG)
VPG = 5.0 V
IPG = 1 mA
10
100
0.4
nA
V
VPG,OL
PG pin low-level output voltage
POWER STAGE
RDSON(HS)
RDSON(LS)
fSW
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
Switching frequency, PWM mode
35
18
57
29
VIN ≥5 V
mΩ
mΩ
MHz
VIN ≥5 V
IOUT = 1 A, VOUT = 1.8 V
2.0
OVERCURRENT PROTECTION
IHS(OC)
High-side peak current limit
TPS628303
4.0
4.6
5.3
A
A
ILS(NOC)
Low-side negative current limit
Sinking current limit on LS FET
–2.0
–1.75
OUTPUT DISCHARGE
IDIS
Output discharge current on SW pin
VIN > 2 V, VSW = 0.4 V, EN = LOW
75
400
110
mA
%
OUTPUT OVP
Overvoltage-protection (OVP) threshold
voltage
VOVP
VFB rising; devices with OVP feature only
108
112
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7.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C, VIN = 2.25 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
td(OVP)
OVP delay
Devices with OVP feature only
35
µs
7.6 Typical Characteristics
75
70
65
60
55
50
45
40
35
30
25
40
35
30
25
20
15
10
20
15
10
5
TJ = −40 C
TJ = −40 C
TJ = 25 C
TJ = 25 C
TJ = 85 C
TJ = 125 C
5
TJ = 85 C
TJ = 125 C
0
0
2.25 2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.25 2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage [V]
Input Voltage [V]
图7-1. High-Side FET On-Resistance
图7-2. Low-Side FET On-Resistance
1
0.8
0.6
0.4
0.2
0
12
10
8
TJ = −40 C
TJ = 25 C
TJ = 85 C
TJ = 125 C
6
4
TJ = −40 C
TJ = 25 C
TJ = 85 C
TJ = 125 C
2
0
2.25 2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.25 2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage [V]
Input Voltage [V]
图7-3. Shutdown Current
图7-4. Quiescent Current
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8 Detailed Description
8.1 Overview
The TPS628303 is a family of synchronous step-down converters with DCS-Control topology with an adaptive
constant on-time control and a stabilized switching frequency. The DCS-Control topology allows for a continuous
conduction mode (CCM) operation with PWM (pulse width modulation) mode and discontinuous conduction
mode (DCM) operation with PFM mode (pulse frequency modulation also known as power save mode (PSM)).
The control block for both operation modes is the same, allowing for a seamless transition between both modes
without an impact on the output voltage ripple. The MODE pin allows for an easy selection for the mode of
operation. If PSM is selected, the converter operates in DCM at light load conditions with a reduced switching
frequency to maintain a high efficiency, and seamlessly transition to CCM as the load current increases to
medium or heavy ranges. If forced-PWM is selected, the converter maintains a CCM operation regardless of the
load current to maintain a minimum output voltage ripple. The nominal switching frequency is 2 MHz with a
controlled variation over the input voltage range. The family offers a 1% output voltage accuracy over –40 °C to
+125 °C, a fast load transient regulation, an excellent EMI performance, and low output voltage ripple.
8.2 Functional Block Diagram
EN
PG
Control Logic
MODE
VFB,INT
VREF
Thermal
Shutdown
Soft-Start
UVLO
VOS
VIN
VIN
VSW
Ramp
Cff
VFB,INT
R1*
R2*
Peak Current Detect
FB
EA
VREF
HICCUP / Latch-off
Comp
VSW
Modulator
SW
Gate Drive
Ton
Output
Discharge
VIN
VSW
Zero Current Detect
0.5 V
Or
Fixed Output Voltages
VREF
GND
* R1 and R2 are implemented internally (dashed lines) for fixed output voltage versions only
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8.3 Feature Description
8.3.1 Pulse Width Modulation (PWM) Operation
If the MODE pin is LOW and at load currents larger than half the inductor ripple current, the device operates in
pulse width modulation in continuous conduction mode (CCM) as shown in 图 8-1. The PWM operation is based
on an adaptive constant on-time control with stabilized switching frequency. To achieve a stable switching
frequency in a steady state condition, the on-time is calculated as:
V
OUT
T
=
× 500ns
(1)
ON
V
IN
If the MODE pin is HIGH, the converter maintains a forced-PWM operation for all load currents.
TON
t1/fSW
t
0
Time
图8-1. Continuous Conduction Mode (PWM-CCM) Current Waveform
8.3.2 Power Save Mode (PSM) Operation
To maintain high efficiency at light loads, the device enters power save mode (PSM) at the boundary to
discontinuous conduction mode (DCM). This event happens when the output current becomes smaller than half
of the ripple current of the inductor. The device operates with a fixed on-time, and the switching frequency
decreases proportional to the load current as shown in 图8-2. It can be calculated as:
2 × I
OUT
f
=
(2)
PSM
V
V
− V
L
2
ON
IN
IN
OUT
T
×
V
OUT
t1/fPSM
t
0
Time
Skipped Pulses
图8-2. Discontinuous Conduction Mode (PSM-DCM) Current Waveform
In PSM, the output voltage rises slightly above the nominal target, which can be minimized using larger output
capacitance. At duty cycles larger than 90%, the device does not enter PSM and maintains output regulation in
PWM mode.
8.3.3 Start-up and Soft Start
When the EN voltage goes High, the device starts loading the default values into the device registers. This
action typically is done within 200 μs. After that, the internal soft-start circuitry controls the output voltage during
start-up. This control avoids excessive inrush current and ensures a controlled output voltage ramp. This control
also prevents unwanted voltage drops from high-impedance power sources or batteries. 图 8-3 shows a start-up
sequence, where the EN pin is pulled up to VIN.
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VIN
EN
0.7V
VEN(+)
Device starts
switching
Device initialization
VOUT
complete
ttd(EN)t
ttSS
t
PG
Undefined
td(PG)
图8-3. Start-Up Timing When EN is Pulled Up to VIN
图8-4 shows a start-up sequence, where an external signal is connected to the EN pin.
VIN
0.7V
EN
VEN(+)
VOUT
td(EN)
ttSSt
Device
initialization
complete
Device starts
switching
PG Undefined
td(PG)
图8-4. Start-Up Timing When an External Signal is Connected to the EN Pin
The TPS628303 can start into a pre-biased output if enabled for the first time. For a new pre-biased operation, a
power cycle is needed to disable the active output discharge. 图 8-5 shows a start-up into a pre-biased output
voltage.
Final voltage
VOUT
Prebias voltage
ttSS
t
图8-5. Start-Up into a Pre-biased Output
8.3.4 Latch-off Short-Circuit Protection and Overvoltage Protection
This information is valid for devices with HICCUP short-circuit protection.
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The switch current limit prevents the device from drawing excessive current from the battery or input voltage rail.
Excessive currents can occur with a heavy load or short circuit condition. Due to an internal propagation delay
(typically 60 ns), the actual AC peak current can exceed the static current limit during that time.
If the current limit threshold is reached, the device delivers its maximum output current. Detecting this condition
for 32 switching cycles (about 16 μs), the device turns off the high-side MOSFET for about 9.6 ms which allows
the inductor current to decrease through the low-side MOSFET's body diode and then restarts again with a soft
start cycle. As long as the overload condition is present, the device hiccups that way, limiting the output power.
In case the MODE is HIGH and the device is operating in forced-PWM, a negative current limit (ILIMN) is
enabled to prevent excessive current flowing backwards to the input. When the inductor current reaches ILIMN,
the low-side MOSFET turns off and the high-side MOSFET turns on and kept on until TON time expires.
8.3.5 Latch-off Short-Circuit Protection and Overvoltage Protection
This information is valid for devices with Latch-off short-circuit protection.
The switch current limit prevents the device from drawing excessive current from the battery or input voltage rail.
Excessive currents can occur with a heavy load or short circuit condition. Due to an internal propagation delay
(typically 60 ns), the actual AC peak current can exceed the static current limit during that time. If the current limit
threshold is reached, the device delivers its maximum output current. Detecting this condition for 32 switching
cycles (about 16 μs), the converter latches off and remains latched off until it is reset by EN or VIN.
The device has also OVP protection circuit that uses the PG window comparator. An OVP event is detected
when the FB voltage is approximately 110% × (0.5 × VREF) for a period longer than the deglitch time of 35 µs. In
this case, the converter de-asserts the PG signal and performs the overvoltage protection function. The
converter latches off both high-side and low-side FET and remains in this state until the device is reset by EN or
VIN.
8.3.6 Undervoltage Lockout
The undervoltage lockout (UVLO) function prevents misoperation of the device if the input voltage drops below
the UVLO threshold.
8.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 150°C
(typical), the device goes in thermal shutdown with a hysteresis of typically 20°C. After TJ has decreased
enough, the device resumes normal operation.
8.4 Device Functional Modes
8.4.1 Enable, Disable, and Output Discharge
The device starts operation when Enable (EN) is set High. The input threshold levels are typically 0.715 V for
rising and 0.4 V for falling signals. Do not leave EN floating. Shutdown is forced if EN is pulled Low with a
shutdown current of typically 100 nA. During shutdown, the internal power MOSFETs as well as the entire control
circuitry are turned off and the output voltage is actively discharged through the SW pin by a current sink.
Therefore VIN must remain present for the discharge to function.
8.4.2 Minimum Duty Cycle and 100% Mode Operation
There is no limitation for small duty cycles because, even at very low duty cycles, the switching frequency is
reduced as needed to always ensure a proper regulation.
If the output voltage (VOUT) comes close to the input voltage (VIN), the device enters 100% mode. While the
high-side switch is constantly turned on, the low-side switch is switched off. This is particularly useful in battery-
powered applications to achieve longest operation time by taking full advantage of the whole battery voltage
range. The difference between VIN and VOUT is determined by the voltage drop across the high-side FET and the
DC resistance of the inductor. The minimum VIN that is needed to maintain a specific VOUT value is estimated as:
V
= V
+ I
× R
+ R
L
(3)
IN, min
OUT
OUT, MAX
DS on
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where
• VIN,min = Minimum input voltage to maintain an output voltage
• IOUT,MAX = Maximum output current
• RDS(on) = High-side FET ON-resistance
• RL = Inductor ohmic resistance (DCR)
8.4.3 Power Good
The TPS628303 has a built-in power-good (PG) function. The PG pin goes high impedance when the output
voltage has reached its nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG
is Low (see 表8-1). The PG function is formed with a window comparator, which has an upper and lower voltage
threshold. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power-good output
requires a pullup resistor connecting to any voltage rail less than 5.5 V.
表8-1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH Z
LOW
EN = High, VFB ≥0.48 V
EN = High, VFB ≤0.56 V
EN = High, VFB ≤0.525 V
EN = High, VFB ≥0.55 V
EN = Low
√
√
Enable
√
√
√
√
√
Shutdown
Thermal shutdown
UVLO
TJ > TJSD
0.7 V < VIN < VUVLO
VIN < 0.7 V
Power supply removal
√
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin unconnected when not used. The PG rising edge and falling edge has a 40-µs blanking time,
as shown in 图8-6.
VPGTH
OVP
VPGTH
VO
VPGTH
UVP
VPGTH
de-glitch delay
de-glitch delay
de-glitch delay
de-glitch delay
PG
图8-6. Power-Good Behavior
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application
L1
0.47 µH
VIN
VOUT
1.8 V
TPS62830x
2.25 V to 5.5 V
VIN
SW
C1
4.7 µF
C2
2x10 µF
EN
R3
100 k
R1
523 k
VOS
MODE
PG
VPG
FB
GND
R2
200 k
图9-1. Typical Application of TPS628303 (Optimized for Solution Size)
L1
0.24 µH
VIN
VOUT
1.8 V
TPS62830x
2.25 V to 5.5 V
VIN
SW
C1
4.7 µF
C2
2x22 µF
EN
R3
100 k
R1
523 k
VOS
MODE
PG
VPG
FB
GND
R2
200 k
图9-2. Typical Application of TPS628303 (Optimized for Transient Response)
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1 as the input parameters.
表9-1. Design Parameters
DESIGN PARAMETER
Input voltage, TPS628303
Output voltage
EXAMPLE VALUE
2.25 V to 5.5 V
1.8 V
Output ripple voltage
< 15 mV
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表9-2 lists the components used for the example.
表9-2. List of Components
REFERENCE
DESCRIPTION
4.7 µF, Ceramic capacitor, 6.3 V, X7R, size 0603, JMK107BB7475KA-T
2 × 10 µF, Ceramic capacitor, 10 V, X7R, size 0603, GRM188Z71A106KA73D
0.47 µH, Power Inductor, XGL4015-471ME
MANUFACTURER
C1
C2
L1
Taiyo Yuden
Murata
Coilcraft
Std
R1
R2
R3
Depending on the output voltage, 1%, size 0402
Std
200 kΩ, Chip resistor, 1/16 W, 1%, size 0402
Std
100 kΩ, Chip resistor, 1/16 W, 1%, size 0402
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS628303 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Setting The Output Voltage
The output voltage is set by an external resistor divider according to 方程式4:
V
V
OUT
0.5 V
OUT
R1 = R2 ×
− 1 = R2 ×
− 1
(4)
V
FB
R2 can be any value between 200 kΩ and 600 kΩ to achieve high efficiency at light load while providing
acceptable noise sensitivity.
9.2.2.3 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, 方程式 5 and 方程式 6 are
given.
∆ I
L
2
I
= I
+
(5)
(6)
L, MAX
OUT, MAX
V
OUT
1 −
V
IN
∆ I = V
×
L × f
L
OUT
SW
where:
• IOUT,MAX = Maximum output current
• ΔIL = Inductor current ripple
• fSW = Switching frequency
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• L = Inductor value
TI recommends to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size must also be taken into account when selecting an appropriate
inductor. Finally, for better transient response performance, TI recommends a smaller inductance value. 表 9-3
lists recommended inductors.
表9-3. List of Recommended Inductors
MAX. DC
RESISTANCE [mΩ]
CURRENT RATING
[A]
INDUCTANCE [µH]
DIMENSIONS [mm]
MFR PART NUMBER(1)
4.4
4.8
4.8
5.1
4.8
4.7
4.7
3.6
4.0 × 4.0 × 1.6
2.0 × 1.6 × 1.0
2.0 × 1.6 × 1.0
2.0 × 1.6 × 1.0
2.0 × 1.25 × 0.8
2.0 × 1.6 × 1.0
2.0 × 1.6 × 1.0
2.0 × 1.6 × 0.8
7.5
22
22
34
17
19
20
23
XGL4015-471ME, Coilcraft
HTEN20161T-R47MDR, Cyntec
CIGT201610EHR47MNE, Samsung
TFM201610ALM-R47MTAA, TDK
LSCNE2012HKTR24MD, Taiyo Yuden
CIGT201610LHR24MNE, Samsung
DFE201610E-R24M, MuRata
0.47
0.24
CIGT201608LMR24MNE, Samsung
(1) See the Third-party Products Disclaimer.
9.2.2.4 Output Capacitor Selection
The inductor and the output capacitor together provide a low-pass filter. To simplify this process, 表 9-4 outlines
possible inductor and capacitor value combinations for most applications. Cells with the (✓) mark represent
combinations that are proven for stability by simulation and lab test. additionally, cells with the (+) mark represent
combinations that are proven for stability by simulation only. Check further combinations for each individual
application.
The DCS-Control scheme of the TPS628303 allows the use of tiny ceramic capacitors. Ceramic capacitors with
low ESR values have the lowest output voltage ripple and are recommended. To keep its low resistance up to
high frequencies and to get narrow capacitance variation with temperature, TI recommends using X7R or X5R
dielectrics. At light load currents, the converter operates in Power Save Mode and the output voltage ripple is
dependent on the output capacitor value. A larger output capacitors can be used reducing the output voltage
ripple. Considering the DC-bias derating the capacitance, the recommended minimum effective output
capacitance is 12 µF when using a 0.47-µH or larger inductor. When using a 0.24-µH or lower inductor, the
recommended minimum effective output capacitance is 22 µF. 表9-5 lists recommended capacitors.
表9-4. Matrix of Output Capacitor and Inductor Combinations (TPS628303)
NOMINAL COUT [µF](3)
VOUT [V]
0.5 ≤VOUT ≤1.8
1.8 < VOUT
NOMINAL L [µH](2)
2 × 10 or 22
2 × 22 or 47
100
+
(1)
0.47
0.24
0.47
0.24
✓
✓
✓
+
+
(1)
+
✓
+
✓
(1) This LC combination is the standard value and recommended for most applications.
(2) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
(3) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
表9-5. List of Recommended Capacitors
Nominal capacitance [µH]
Voltage rating [V]
DIMENSIONS [mm]
2.0 × 1.5 × 1.25
2.0 × 1.25 × 1.25
1.6 × 0.8 × 0.8
MFR PART NUMBER(1)
10
10
10
10
6.3
10
10
10
MSASJ21GAB7106MTNA01, Taiyo Yuden
C2012X7R1A106K125AC, TDK
GRM188Z71A106KA73#, MuRata
C1608X5R1A106K080AC, TDK
1.6 × 0.8 × 0.8
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表9-5. List of Recommended Capacitors (continued)
Nominal capacitance [µH]
Voltage rating [V]
DIMENSIONS [mm]
2.0 × 1.25 × 1.25
1.6 × 0.8 × 0.8
MFR PART NUMBER(1)
22
22
10
10
GRM21BZ71A226ME15#, MuRata
C1608X5R1A226M080AC, TDK
9.2.2.5 Input Capacitor Selection
The input capacitor is the low-impedance energy source for the converter, which helps provide stable operation.
Because the buck converter has a pulsating input current, a low ESR ceramic input capacitor is required for best
input voltage filtering to minimize input voltage spikes. The capacitor must be placed between VIN and GND pins
and as close as possible to those pins.
For most applications, a minimum effective input capacitance of 3 µF is sufficient, though a larger value reduces
input current ripple and is recommended. When operating from a high impedance source, a larger input buffer
capacitor ≥10 µF is recommended to avoid voltage drops during start-up and load transients. Additionally, small
de-coupling capacitors may also be used in case of noise at the input if the device. The input capacitor can be
increased without any limit for better input voltage filtering.
表9-6 shows a list of recommended capacitors.
表9-6. List of Recommended Capacitors
NNOMINAL CAPACITANCE
VOLTAGE RATING [V]
DIMENSIONS [mm]
MFR PART NUMBER(1)
[µH]
4.7
4.7
10
6.3
10
10
1.6 × 0.8 × 0.8
2.0 × 1.25 × 1.25
1.6 × 0.8 × 0.8
MSASJ168BB7475MTNA01, Taiyo Yuden
C2012X7R1A475K125AC, TDK
GRM188Z71A106KA73#, MuRata
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9.2.3 Application Curves
TA = 25°C, VIN = 5 V, VOUT = 1.8 V, BOM = 表9-2 unless otherwise noted.
VOUT = 3.3 V
PFM
VOUT = 3.3 V
PWM
图9-3. Efficiency versus Output Current
图9-4. Efficiency versus Output Current
100
100
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
60
55
50
45
40
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=3.3V
VIN=4.2V
VIN=5.0V
100
1m
10m
Load [A]
100m
1
3
0
0.5
1
1.5
Load [A]
2
2.5
PWM
3
VOUT = 2.5 V
PFM
VOUT = 2.5 V
图9-5. Efficiency versus Output Current
图9-6. Efficiency versus Output Current
VOUT = 1.8 V
PFM
VOUT = 1.8 V
PWM
图9-7. Efficiency versus Output Current
图9-8. Efficiency versus Output Current
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100
95
90
85
80
75
70
65
60
55
50
45
100
95
90
85
80
75
70
65
60
55
50
45
40
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
40
100
1m
10m
Load [A]
100m
1
3
3
3
0
0.5
1
1.5
Load [A]
2
2.5
3
3
3
VOUT = 1.2 V
PFM
VOUT = 1.2 V
PWM
图9-9. Efficiency versus Output Current
图9-10. Efficiency versus Output Current
100
100
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
60
55
50
45
40
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
100
1m
10m
Load [A]
100m
1
0
0.5
1
1.5
Load [A]
2
2.5
PWM
VOUT = 0.9 V
PFM
VOUT = 0.9 V
图9-11. Efficiency versus Output Current
图9-12. Efficiency versus Output Current
100
100
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
60
55
50
45
40
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
100
1m
10m
Load [A]
100m
1
0
0.5
1
1.5
Load [A]
2
2.5
TA = 25 °C
VOUT = 0.5 V
PFM
TA = 25 °C
VOUT = 0.5 V
PWM
图9-13. Efficiency versus Output Current
图9-14. Efficiency versus Output Current
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2.4x106
2.25x106
2.1x106
1.95x106
1.8x106
1.65x106
1.5x106
1.35x106
1.2x106
1.05x106
9x105
2.4x106
2.25x106
2.1x106
1.95x106
1.8x106
1.65x106
1.5x106
1.35x106
1.2x106
1.05x106
9x105
7.5x105
6x105
7.5x105
6x105
VOUT=0.5V
VOUT=0.9V
VOUT=1.2V
VOUT=2.5V
VOUT=0.5V
VOUT=0.9V
VOUT=1.2V
VOUT=2.5V
4.5x105
3x105
4.5x105
3x105
1.5x105
0x100
1.5x105
0x100
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
Load [A]
Load [A]
VIN = 3.3 V
PFM
VIN = 3.3 V
PWM
图9-15. Switching Frequency versus Output
图9-16. Switching Frequency versus Output
Current
Current
2.4x106
2.25x106
2.1x106
1.95x106
1.8x106
1.65x106
1.5x106
1.35x106
1.2x106
1.05x106
9x105
7.5x105
6x105
VOUT=0.5V
VOUT=0.9V
VOUT=1.2V
VOUT=2.5V
4.5x105
3x105
1.5x105
0x100
2.25 2.5
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage [V]
IOUT = 1 A
图9-17. Switching Frequency versus Input Voltage
IOUT= 100mA
PFM
图9-18. Output Voltage Ripple
IOUT= 2.0 A
PFM or PWM
IOUT= 1 mA to 2 A
PFM
Slew rate = 1 A/μs
图9-19. Output Voltage Ripple
图9-20. Load Transient
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IOUT= 1 A to 3 A
PWM
VIN = 3.3 V
PFM
Transient BoM
IOUT= 1 mA to 2A
Slew rate = 1 A/μs
VOUT = 0.9 V
Slew rate = 1 A/μs
图9-21. Load Transient
图9-22. Load Transient
VIN = 3.3 V
VOUT = 0.9 V
PWM
IOUT= 1 A to 3 A
VIN= 4.5 V to 5.5 V
PFM
IOUT= 100 mA
Transient BoM
Slew rate = 1 A/μs
图9-24. Line Transient
图9-23. Load Transient
VIN= 4.5 V to 5.5 V
PWM
IOUT= 2.0 A
VIN= 3.0 V to 3.6 V
PFM
IOUT= 100 mA
图9-25. Line Transient
图9-26. Line Transient
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VIN= 3.0 V to 3.6 V
PWM
IOUT= 2.0 A
IOUT= 2.0 A
PFM or PWM
TA = 25 °C
图9-27. Line Transient
图9-28. Start-up with Load
IOUT= 0 mA
PFM or PWM
TA = 25 °C
IOUT= 0 mA
PFM
TA = 25 °C
图9-29. Start-up with No Load
图9-30. Disable, Active Output Discharge at No
Load
PFM or PWM
TA = 25 °C
PFM or PWM
TA = 25 °C
图9-31. HICCUP Short-Circuit Protection
图9-32. HICCUP Short-Circuit Protection (Zoom In)
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PFM or PWM
TA = 25 °C
PFM or PWM
TPS628303BDRL
TA = 25 °C
图9-33. HICCUP Short-Circuit Protection (Zoom In
图9-34. Latch-off Short-Circuit Protection
- Second Hiccup)
PFM or PWM
TPS628303BDRL
TA = 25 °C
PFM or PWM
TPS628303BDRLR
TA = 25 °C
图9-35. Latch-off Short-Circuit Protection (Zoom
图9-36. Latch-off Overvoltage Protection
In)
9.3 Power Supply Recommendations
The TPS628303 family does not have special requirements for the input power supply and is designed to
operate from an input voltage supply range from 2.25 V to 5.5 V. The output current of the input power supply
must be rated according to the supply voltage, output voltage, and output current of the TPS628303.
9.4 Layout
9.4.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the device. See
Layout Example for the recommended PCB layout.
• The input, output capacitors and the inductor must be placed as close as possible to the IC. This action
keeps the power traces short. Routing these power traces direct and wide results in low trace resistance and
low parasitic inductance.
• The low side of the input and output capacitors must be connected properly to the GND pin to avoid a ground
potential shift.
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• The sense traces connected to FB is a signal trace. Special care must be taken to avoid noise being induced.
Keep these traces away from SW nodes. The connection of the output voltage trace for the FB resistors must
be made at the output capacitor.
• Refer to Layout Example for an example of component placement, routing, and thermal design.
9.4.2 Layout Example
GND
C2
V
V
OUT
L1
IN
C1
GND
R2
1
VIN
GND
MODE
FB
EN
SW
PG
VOS
R1
图9-37. PCB Layout Recommendation (RZE Package)
GND
C2
V
IN
V
OUT
L1
C1
1
EN
VIN
GND
SW
PG
MODE
FB
VOS
GND
R2
R1
图9-38. PCB Layout Recommendation (DRL Package)
9.4.2.1 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
The Thermal Data section in Thermal Information provides the thermal metric of the device on the EVM after
considering the PCB design of real applications. The big copper planes connecting to the pads of the IC on the
PCB improve the thermal performance of the device. For more details on how to use the thermal parameters,
see the Thermal Characteristics application notes, Thermal Characteristics of Linear and Logic Packages Using
JEDEC PCB Designs and Semiconductor and IC Package Thermal Metrics.
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.1.2 Development Support
10.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS628303 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
application note
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application note
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
XPS628303ADRLR
XPS628303BDRLR
XPS628303ARZER
SOT-5x3
SOT-5x3
DRL
DRL
RZE
8
8
8
3000
3000
3000
180
180
180
8.4
8.4
8.4
2.75
2.75
1.3
1.9
1.9
2.3
0.8
0.8
0.9
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q1
WQFN-HR
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
SOT-5x3
Package Drawing Pins
SPQ
3000
3000
3000
Length (mm) Width (mm)
Height (mm)
XPS628303ADRLR
XPS628303BDRLR
XPS628303ARZER
DRL
DRL
RZE
8
8
8
210
210
210
185
185
185
35
35
35
SOT-5x3
WQFN-HR
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PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/D 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
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EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4224486/D 11/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/D 11/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
RZE0008A
WQFN-HR - 0.8mm max height
QFN (PLASTIC QUAD FLATPACK - NO LEAD)
1.1
0.9
B
A
2.1
1.9
PIN 1 INDEX AREA
0.8 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
SYMM
4
5
6X 0.5
SYMM
2X
1.5
0.3
0.2
8X
0.1
0.05
C A B
C
1
8
(0.1)
TYP
PIN 1 ID
(45 X0.15)
0.425
0.325
8X
4228328/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
RZE0008A
WQFN-HR - 0.8mm max height
QFN (PLASTIC QUAD FLATPACK - NO LEAD)
SYMM
8X (0.575)
(R0.05) TYP
8
8X (0.25)
1
SYMM
6X (0.5)
4
5
(0.825)
LAND PATTERN EXAMPLE
0.05 MAX
ALL AROUND
SCALE:50X
0.05 MIN
ALL AROUND
METAL
SOLDERMASK
OPENING
METAL
SOLDERMASK
OPENING
NON SOLDERMASK
DEFINED
(PREFERRED)
SOLDERMASK
DEFINED
SOLDERMASK DETAILS
4228328/A 12/2021
NOTES: (continued)
3. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RZE0008A
WQFN-HR - 0.8mm max height
QFN (PLASTIC QUAD FLATPACK - NO LEAD)
SYMM
8X (0.575)
8
8X (0.25)
1
SYMM
4X (0.5)
4
5
(0.825)
SOLDERPASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
SCALE:60X
4228328/A 12/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XPS628303ADRLR
XPS628303ARZER
XPS628303BDRLR
ACTIVE
ACTIVE
ACTIVE
SOT-5X3
WQFN-HR
SOT-5X3
DRL
RZE
DRL
8
8
8
3000
3000
3000
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
Samples
Samples
Samples
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/E 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/E 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/E 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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