XDLP4621AFQXQ1 [TI]
适用于外部照明应用的汽车类 0.46 英寸 DLP® 数字微镜器件 (DMD) | FQX | 120 | -40 to 105;
| 型号： | XDLP4621AFQXQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于外部照明应用的汽车类 0.46 英寸 DLP® 数字微镜器件 (DMD) | FQX | 120 | -40 to 105 |
| 文件： | 总37页 (文件大小：1650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DLP4621-Q1
ZHCSRE5 –DECEMBER 2022
DLP4621-Q1 0.46 英寸0.9 百万像素数字微镜器件（适用于汽车外部照明）
1 特性
3 说明
• 符合汽车应用要求
DLP4621-Q1 汽车数字微镜器件 (DMD) 与 DLPC230-
Q1 DMD 控制器和 TPS99001-Q1 系统管理和照明控
制器结合使用，能够实现具有高性能、高分辨率的前照
灯系统。采用2:1 宽高比，支持超宽宽高比设计；具有
0.9 百万像素分辨率，支持高分辨率符号投影和自适应
远光灯应用。 DLP4621-Q1 的光通量经过优化，可利
用业内出色的 LED 和激光技术更大限度地提高流明。
DLP4621-Q1 汽车 DMD 微镜阵列针对底部照明而配
置，可实现更高效率以及更紧凑的光学引擎设计。
DLP4621-Q1 器件采用面板封装，可优化系统成本。
该封装针对 DMD 阵列而言具有低热阻的特点，可实现
高效的散热解决方案。
– DMD 阵列工作温度范围-40°C 至105°C
• DLP4621-Q1 汽车芯片组包括：
– DLP4621-Q1 DMD
– DLPC230-Q1 DMD 控制器
– TPS99001-Q1 系统管理和照明控制器
• 0.46 英寸对角线微镜阵列
– 7.6 μm 微镜间距
– ±12° 微镜倾斜角（相对于平面）
– Bottom 照明可实现高效率和更小的发动机尺寸
– 0.9 百万像素阵列（960 × 960，2:1），支持高
分辨率和宽宽高比汽车类应用
– 与LED 或激光照明兼容
• 600MHz subLVDS DMD 接口，可实现低功耗和低
排放
器件信息
封装(1) (2)
封装尺寸（标称值）
器件型号
DLP4621-Q1
FQX
25.2 mm × 11.0 mm
• 温度极值下DMD 刷新率为10 kHz
• DMD 存储器单元的内置自检(BIST)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 本数据表包含了有关此DMD 在前照灯应用中的规格以及应用
信息。有关抬头显示规格和应用的信息，请参阅DLP4620S-
Q1 数据表(DLPS230)。
2 应用
• 高分辨率前照灯
• 激光雷达光学滤波器
• 符号投影
• 个性化
Voltage
Monitor and
Enables
Power
1.1V
Regulation
1.8V
3.3V
6.5V
TPS9900x-Q1
VOFFSET
VBIAS
SPI
SPI
VRESET
Video
DLP462x Series
DLPC23x-Q1
SubLVDS
DMD
TMP411
Temperature
Sensor
I2C
LED
ENABLE
Flash
SPI
DLP4621-Q1 DLP® 芯片组系统方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: DLPS229
DLP4621-Q1
ZHCSRE5 –DECEMBER 2022
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Table of Contents
7.4 System Optical Considerations.................................20
7.5 DMD Image Performance Specification....................21
7.6 Micromirror Array Temperature Calculation.............. 22
7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24
8 Application and Implementation..................................26
8.1 Application Information............................................. 26
8.2 Typical Application.................................................... 26
9 Power Supply Recommendations................................30
9.1 Power Supply Power-Up Procedure......................... 30
9.2 Power Supply Power-Down Procedure.....................30
9.3 Power Supply Sequencing Requirements................ 31
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
11 Device and Documentation Support..........................33
11.1 第三方产品免责声明................................................33
11.2 Device Support........................................................33
11.3 Trademarks............................................................. 33
11.4 静电放电警告...........................................................33
11.5 DMD Handling.........................................................34
11.6 术语表..................................................................... 34
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 8
6.1 Absolute Maximum Ratings........................................ 8
6.2 Storage Conditions..................................................... 8
6.3 ESD Ratings .............................................................. 9
6.4 Recommended Operating Conditions.........................9
6.5 Thermal Information .................................................10
6.6 Electrical Characteristics...........................................10
6.7 Timing Requirements................................................ 11
6.8 Switching Characteristics .........................................14
6.9 System Mounting Interface Loads............................ 15
6.10 Physical Characteristics of the Micromirror Array ..15
6.11 Micromirror Array Optical Characteristics .............. 17
6.12 Window Characteristics.......................................... 17
6.13 Chipset Component Usage Specification............... 17
7 Detailed Description......................................................18
7.1 Overview...................................................................18
7.2 Functional Block Diagram.........................................18
7.3 Feature Description...................................................19
Information.................................................................... 34
4 Revision History
DATE
REVISION
NOTES
December 2022
*
Advance Information
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5 Pin Configuration and Functions
1
3
5
17 19 21 23
16 18 20 22 24
2
4
6
A
B
C
D
E
F
G
H
J
K
图5-1. FQX Package 120-Pin LGA Bottom View
表5-1. Pin Functions—Connector Pins
PIN
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NAME
NO.
DATA INPUTS
D_AN(0)
A3
B1
C2
F2
H2
K1
K4
I
I
I
I
I
I
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
Double
Double
Double
Double
Double
Double
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
D_AN(1)
D_AN(2)
D_AN(3)
D_AN(4)
D_AN(5)
D_AN(6)
D_AN(7)
D_AP(0)
D_AP(1)
D_AP(2)
D_AP(3)
D_AP(4)
D_AP(5)
D_AP(6)
D_AP(7)
D_BN(0)
D_BN(1)
D_BN(2)
D_BN(3)
D_BN(4)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
K6
A2
C1
SubLVDS
SubLVDS
SubLVDS
Data, Negative
Data, Positive
Data, Positive
D2
E2
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Negative
Data, Negative
Data, Negative
Data, Negative
Data, Negative
G2
K2
K3
K5
A22
B24
D23
F23
H23
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表5-1. Pin Functions—Connector Pins (continued)
PIN
NAME
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NO.
D_BN(5)
K24
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
SubLVDS
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Double
Single
Data, Negative
Data, Negative
Data, Negative
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Data, Positive
Clock, Negative
Clock, Positive
Clock, Negative
Clock, Positive
D_BN(6)
D_BN(7)
D_BP(0)
D_BP(1)
D_BP(2)
D_BP(3)
D_BP(4)
D_BP(5)
D_BP(6)
D_BP(7)
DCLK_AN
DCLK_AP
DCLK_BN
K21
K19
A23
C24
C23
E23
G23
K23
K22
K20
J1
H1
J24
H24
C3
DCLK_BP
LS_CLKN
Clock for Low Speed Interface, Negative
Clock for Low Speed Interface, Positive
Write Data for Low Speed Interface, Negative
Write Data for Low Speed Interface, Positive
LS_CLKP
C4
Single
LS_WDATAN
LS_WDATAP
CONTROL INPUTS
C5
Single
C6
Single
Asynchronous Reset Active Low. Logic High
Enables DMD
DMD_DEN_ARSTZ
E6
I
LPSDR
LS_RDATA_A
LS_RDATA_B
E19
F19
O
O
LPSDR
LPSDR
Single
Single
Read Data for Low Speed Interface
Read Data for Low Speed Interface
TEMPERATURE SENSE DIODE
TEMP_N
TEMP_P
F6
O
I
Calibrated temperature diode used to assist
accurate temperature measurements of DMD die
G6
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表5-1. Pin Functions—Connector Pins (continued)
PIN
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NAME
POWER
VBIAS
NO.
A4
A21
B3
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Supply voltage for positive bias level at
micromirrors
VBIAS
VOFFSET
VOFFSET
VOFFSET
VOFFSET
VOFFSET
VOFFSET
VRESET
VRESET
B4
B21
B22
J4
Supply voltage for high-voltage CMOS core logic.
Supply voltage for offset level at micromirrors
J21
B6
Supply voltage for negative reset level at
micromirrors
B19
VDD
VDD
VDD
A5
Power
Power
Power
A20
C20
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
D4
D19
D21
E3
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Supply voltage for Low Voltage CMOS core logic;
for LPSDR inputs; for normal high level at
micromirror address electrodes
E22
F4
G3
G21
H22
J3
J6
J19
E5
E20
F5
F20
G5
Supply voltage for SubLVDS receivers
G20
H5
H20
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表5-1. Pin Functions—Connector Pins (continued)
PIN
TYPE
SIGNAL
DATA RATE
DESCRIPTION
NAME
NO.
VSS
A1
Ground
VSS
VSS
VSS
VSS
A6
A19
A24
B2
Ground
Ground
Ground
Ground
VSS
B5
Ground
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B20
B23
C19
C21
C22
D3
Ground
Ground
Ground
Ground
Ground
Ground
Ground
D5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D6
D20
D22
E4
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
E21
F3
Common return. Ground for all power
F21
F22
G4
G19
G22
H3
H4
H6
H19
H21
J2
J5
J20
J22
J23
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表5-2. Pin Functions—Test Pads
NUMBER
TP0
SYSTEM BOARD
Do not connect.
Do not connect.
Do not connect.
TP1
TP2
MBRST(0)
Do not connect.
MBRST(1)
MBRST(6)
MBRST(7)
Do not connect.
Do not connect.
Do not connect.
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6 Specifications
6.1 Absolute Maximum Ratings
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not
imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating
Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
MIN
MAX
UNIT
SUPPLY VOLTAGE
Supply voltage for LVCMOS core logic(1)
Supply voltage for LPSDR low speed interface
VDD
2.3
2.3
V
V
V
–0.5
–0.5
–0.5
VDDI
Supply voltage for subLVDS receivers(1)
Supply voltage for HVCMOS and micromirror
electrode(1) (2)
VOFFSET
8.75
VBIAS
Supply voltage for micromirror electrode(1)
Supply voltage for micromirror electrode(1)
Supply voltage delta (absolute value)(3)
Supply voltage delta (absolute value)(4)
Supply voltage delta (absolute value)(5)
17
0.5
V
V
V
V
V
–0.5
–11
VRESET
|VDDI - VDD
|VBIAS-VOFFSET
|VBIAS - VRESET
INPUT VOLTAGE
|
0.3
|
8.75
28
|
Input voltage for LVCMOS inputs(1)
Input voltage for other inputs subLVDS(1) (6)
INPUT PINS
VDD + 0.5
VDDI + 0.5
V
V
–0.5
–0.5
|VID
|
SubLVDS input differential voltage (absolute value)(6)
810
10
mV
mA
|IID
|
SubLVDS input differential current
CLOCK FREQUENCY
Fmax_LS
Clock frequency for low speed interface LS_CLK
Max current source into temperature diode
Operating DMD array temperature
100
130
120
105
MHz
µA
TEMPERATURE DIODE
ITEMP_DIODE
ENVIRONMENTAL
TARRAY
°C
–40
(1) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw and
permanent damage to the device.
(4) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current
draw and permanent damage to the device.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw
and permanent damage to the device.
(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. SubLVDS differential
inputs must not exceed the specified limit or damage to the internal termination resistors may result.
6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
MIN
MAX
UNIT
Tstg
DMD storage temperature
125
°C
–40
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6.3 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±2000
V
±750
V(ESD)
Electrostatic discharge
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
NOM
MAX
UNIT
SUPPLY VOLTAGE
Supply voltage for LVCMOS core logic
Supply voltage for LPSDR low-speed interface
VDD
1.65
1.8
1.95
V
VDDI
Supply voltage for SubLVDS receivers
Supply voltage for HVCMOS and micromirror electrode(3)
Supply voltage for mirror electrode
1.65
8.25
1.8
8.5
1.95
8.75
16.5
–10.5
0.3
V
V
V
V
V
V
V
VOFFSET
VBIAS
15.5
16
VRESET
Supply voltage for micromirror electrode
Supply voltage delta (absolute value)(4)
Supply voltage delta (absolute value)(5)
Supply voltage delta (absolute value)(6)
–9.5
–10
|VDDI - VDD
|VBIAS-VOFFSET
|VBIAS - VRESET
LOW-SPEED LPDSR INTERFACE
|
|
8.75
28
|
fclock_LS
Clock frequency for low speed interface LS_CLK
108
44
120
56
MHz
%
DCDIN
LSIF duty cycle distortion (LS_CLK)
SUBLVDS INTERFACE
fclock_HS
Clock frequency for high-speed interface DCLK
LVDS duty cycle distortion (DCLK)
LVDS differential input voltage magnitude(7)
Common mode voltage(7)
300
44
540
56
MHz
%
DCDIN
|VID
|
150
700
525
90
250
900
350
mV
mV
mV
VCM
1100
1275
110
VSUBLVDS
ZLINE
ZIN
SubLVDS voltage(7)
Line differential impedance (PWB/trace)
Internal differential termination resistance(8)
100-Ωdifferential PCD trace
100
100
Ω
Ω
80
120
6.35
152.4
mm
ENVIRONMENTAL
TARRAY
Array Temperature(9) (11)
-40
105
2
°C
Illumination
ILLUV
Illumination, wavelength < 395 nm(10)
mW/cm2
Illumination overfill maximum heat load in area shown in
Figure 6-1
ILLOVERFILL
90 mW/mm2
(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.
(2) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections
are also required.
(3) VOFFSET supply transients must fall within specified min/max voltages.
(4) To prevent excess current, the supply voltage delta |VDDI –VDD| must be less than the specified limit.
(5) To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than the specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than the specified limit.
(7) See Figure 6-6 and Figure 6-7.
(8) See Figure 6-8.
(9) DMD Active Array temperature can be calculated as shown in the Micromirror Array Temperature Calculation.
(10) The maximum operation conditions for operating temperature and UV illumination must not be implemented simultaneously.
(11) The operating profile information for the device micromirror landed duty-cycle and temperature is provided upon request.
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6.4.1 Illumination Overfill Diagram
Limited illumination area on
window aperture
Window
Array
Window
Aperture
Window
0.5 mm
Window Aperture
0.5 mm
图6-1. Illumination Overfill Diagram
6.5 Thermal Information
DLP4621-Q1
THERMAL METRIC
FQX
120 Pins
1.5
UNIT
Thermal resistance
Thermal resistance
Active area-to-test point 1 (TP1) (1) (2)
°C/W
°C/W
Active area-to-temperature sense diode(1) (2)
0.5
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Recommended Operating Conditions . The total heat load on
the DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed
by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy
falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the
device.
(2) The thermal resistance values provided here assumes a non-uniform illumination profile. Refer to Micromirror Array Temperature
Calculation for details.
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT
IDD
Supply current: VDD(2)
Supply current: VDDI(2)
Supply current: VOFFSET
Supply current: VBIAS
Supply current: VRESET
VDD = 1.95 V
220
55
mA
mA
mA
mA
mA
IDDI
VDDI = 1.95 V
IOFFSET
IBIAS
VOFFSET = 8.75 V
VBIAS = 16.5 V
35
1.5
16
IRESET
POWER
PDD
VRESET = –10.5 V
Supply power dissipation: VDD(2)
Supply power dissipation: VDDI(2)
Supply power dissipation: VOFFSET
Supply power dissipation: VBIAS
Supply power dissipation: VRESET
VDD = 1.95 V
430
108
307
25
mW
mW
mW
mW
mW
PDDI
VDDI = 1.95 V
POFFSET
PBIAS
VOFFSET = 8.75 V
VBIAS = 16.5 V
VRESET = –10.5 V
PRESET
168
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6.6 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PTOTAL
Supply power dissipation: total
1038
mW
LVCMOS INPUT
0.7 ×
VDD
VDD +
0.3
VIH
High-level input voltage(3)
Low-level input voltage(3)
AC input high voltage(3)
AC input low voltage(3)
Input hysteresis(3)
V
V
V
V
V
0.3 ×
VDD
VIL
–0.3
0.8 ×
VDD
VDD +
0.3
VIH(AC)
VIL(AC)
VHyst
0.2 ×
VDD
–0.3
0.1 ×
VDD
0.4 ×
VDD
See Figure 6-9
IIL
Low-level input current(3)
High-level input current(3)
VDD = 1.95 V; VI = 0 V
nA
–100
IIH
VDD = 1.95 V; VI = 1.95 V
135
μA
LVCMOS OUTPUT
0.8 ×
VDD
VOH
VOL
DC output high voltage(4)
V
IOH = –2 mA
0.2 ×
VDD
DC output low voltage(4)
IOL = 2 mA
V
IOZ
High impedance output current
VDD = 1.95 V
10
µA
CAPACITANCE
Input capacitance LVCMOS
Input capacitance subLVDS
Output capacitance
F = 1 MHz
F = 1 MHz
F = 1 MHz
F = 1 MHz
10
20
10
20
pF
pF
pF
pF
CIN
COUT
CTEMP
Input capacitance subLVDS
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
(2) Supply power dissipation based on non-compressed commands and data.
(3) LPSDR input specifications are for pin DMD_DEN_ARSTZ.
(4) LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B.
6.7 Timing Requirements
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted
MIN NOM MAX UNIT
Low-Speed Interface
tr
Rise slew rate (1) (2)
(20% to 80%) × VDD
(80% to 20%) × VDD
0.25
0.25
7.7
3.1
3.1
1.5
1.5
3
V/ns
V/ns
ns
tf
Fall slew rate (1) (2)
tc
Cycle time LS_CLK
8.3
tW(H)
tW(L)
tsu
Pulse duration LS_CLK high(3) 50% to 50% reference points
Pulse duration LS_CLK low(3) 50% to 50% reference points
Setup time(3)
ns
ns
ns
LS_WDATA valid before LS_CLK↑or LS_CLK↓
th
Hold time(3)
ns
LS_WDATA valid after LS_CLK↑or LS_CLK↓
tWINDOW
Window time
Setup time + hold time
ns
For each 0.25 V/ns reduction in slew rate below 1
V/ns
tDERATING
Window time derating
0.35
ns
High-Speed Interface
tr
tf
Rise slew rate(2)
Fall slew rate(2)
20% to 80% reference points
80% to 20% reference points
0.7
0.7
1
1
V/ns
V/ns
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6.7 Timing Requirements (continued)
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted
MIN NOM MAX UNIT
tc
Cycle time DCLK (3)
1.79
0.79
0.79
0.3
1.85
ns
ns
ns
ns
ns
tW(H)
Pulse duration DCLK high(3)
Pulse duration DCLK low(3)
Window time(3) (4)
50% to 50% reference points
50% to 50% reference points
Setup time + Hold time
tW(L)
tWINDOW
tLVDS-EN+REFGEN
Power-up receiver (5)
2000
(1) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-2.
(2) See Figure 6-3.
(3) See Figure 6-4.
(4) See Figure 6-5.
(5) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
Electrical and Timing Diagrams
图6-2. LPSDR Input Rise and Fall Slew Rate
图6-3. SubLVDS Input Rise and Fall Slew Rate
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图6-4. SubLVDS Switching Parameters
图6-5. High-Speed Training Scan Window
图6-6. SubLVDS Voltage Parameters
图6-7. SubLVDS Waveform Parameters
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DCLK_AP
DCLK_BP
D_AP(7:0)
D_BP(7:0)
ESD
ESD
Internal
Termination
DCLK_AN
DCLK_BN
D_AN(7:0)
D_BN(7:0)
SubLVDS
Receiver
图6-8. SubLVDS Equivalent Input Circuit
图6-9. LPSDR Input Hysteresis
6.8 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
Output propagation, clock to Q, rising edge of LS_CLK
(differential clock signal) input to LS_RDATA output(2)
tPD
CL = 45 pF
15
Slew rate, LS_RDATA
0.5
V/ns
Output duty cycle distortion, LS_RDATA_A and LS_RDATA_B
40%
60%
(1) Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
(2) See 图6-10 and 图6-11.
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6.8.1 LPSDR and Test Load Circuit Diagrams
图6-10. LPSDR Read Out
图6-11. Test Load Circuit for Output Propagation Measurement
6.9 System Mounting Interface Loads
PARAMETER
Thermal interface area
Electrical interface area
Condition
MIN
NOM
MAX
90
UNIT
Maximum load uniformly distributed within each area(1)
Maximum load uniformly distributed within each area(1)
N
135
(1) See Figure 6-12.
System Interface Loads Diagram
Thermal Interface Area
Electrical Interface Area
图6-12. System Interface Loads
6.10 Physical Characteristics of the Micromirror Array
PARAMETER
VALUE
UNIT
M
N
Number of active columns(1)
960
960
7.6
micromirrors
micromirrors
µm
Number of active rows(1)
Micromirror (pixel) pitch—diagonal(1)
Micromirror (pixel) pitch—horizontal and vertical(1)
ε
P
10.8
µm
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6.10 Physical Characteristics of the Micromirror Array (continued)
PARAMETER
VALUE
10.373
5.189
10
UNIT
mm
Micromirror active array width
Micromirror active array height
Micromirror active border
(P × M) + (P / 2)
(P x N) / 2 + (P / 2)
mm
Pond of micromirrors (POM) (2)
micromirrors/side
(1) See 图6-13.
(2) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
6.10.1 Array Physical Characteristics Diagram
Off State
Light Path
Row 959
Row 958
Row 957
Row 956
Row 955
Row 954
Row 953
Row 952
Off-State
Tilt Direction
On-State
Tilt Direction
DMD Active Mirror Array
Row 7
Row 6
Row 5
Row 4
Row 3
Row 2
Row 1
Row 0
Array Width
Pond of Micromirrors (POM) are Omitted for Clarity
Details omitted for clarify
Not to Scale
Incoming
Illumination
Light Path
P (um)
图6-13. Micromirror Array Physical Characteristics
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6.11 Micromirror Array Optical Characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
degree
degree
Micromirror tilt angle
DMD landed state(1)
12
Micromirror tilt angle tolerance(2)
DMD efficiency(3)
1
–1
66%
420 nm –700 nm
(1) Measured relative to the plane formed by the overall micromirror array at 25°C.
(2) For some applications, it is critical to account for the micromirror tilt angle variation in the overall optical system design. With some
optical system designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some optical system designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations, or system contrast variations.
(3) DMD efficiency is measured photopically under the following conditions: 24° illumination angle, F/2.4 illumination and collection
apertures, uniform source spectrum (halogen), uniform pupil illumination, the optical system is telecentric at the DMD, and the
efficiency numbers are measured with 100% electronic micromirror landed duty-cycle and do not include system optical efficiency or
overfill loss. This number is measured under conditions described above and deviations from these specified conditions could result in
a different efficiency value in a different optical system. The factors that can influence the DMD efficiency related to system application
include: light source spectral distribution and diffraction efficiency at those wavelengths (especially with discrete light sources such as
LEDs or lasers), and illumination and collection apertures (F/#) and diffraction efficiency. The interaction of these system factors as well
as the DMD efficiency factors that are not system dependent are described in detail in DMD Optical Efficiency for Visible Wavelengths
Application Note.
6.12 Window Characteristics
PARAMETER
MIN
NOM
Corning Eagle XG
1.5119
MAX
UNIT
Window material designation
Window refractive index
Window aperture(1)
Illumination overfill
At wavelength 546.1 nm
See (1)
See (1)
.
.
(1) See the mechanical package ICD for details regarding the size and location of the window aperture.
6.13 Chipset Component Usage Specification
The DLP4621-Q1 is a component of a chipset. Reliable function and operation of the DLP4621-Q1 requires that
it be used in conjunction with the TPS99001-Q1 and DLPC230-Q1, and includes components that contain or
implement TI DMD control technology. TI DMD control technology consists of the TI technology and devices
used for operating or controlling a DLP DMD.
备注
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.
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7 Detailed Description
7.1 Overview
The DLP4621-Q1 automotive DMD consists of 921600 highly reflective, digitally switchable, micrometer-sized
mirrors organized in a two-dimensional array. As shown in Figure 6-13, the micromirror array consists of 960
micromirror columns × 960 micromirror rows in a diamond pixel configuration with a 2:1 aspect ratio.
Around the perimeter of the 960 × 960 array of micromirrors is a uniform band of border micromirrors called the
Pond of Micromirrors (POM). The border micromirrors are not user-addressable. The border micromirrors land in
the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of
the 960 × 960 active array.
Due to the diamond pixel configuration, the columns of each odd row are offset by half a pixel from the columns
of the even row. Each mirror is switchable between two discrete angular positions: –12° and +12°. The mirrors
are illuminated from the bottom which allows for compact and efficient system optical design.
7.2 Functional Block Diagram
High Speed Data Path &
Training: Bus A
High Speed Data Path &
Training: Bus B
(960, 960)
TEMP_P
TEMP_N
0.9 Mega Pixel 2:1 Aspect ratio
SRAM & Micromirror Array
(1,1)
DMD Mirror & SRAM Voltage Control
Low Speed Bus Interface & DMD Mirror
Voltage control
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7.3 Feature Description
The DLP4621-Q1 consists of a two-dimensional array of 1-bit CMOS memory cells driven by a subLVDS bus
from the DLPC230-Q1 and powered by the TPS99001-Q1. The temperature sensing diode is used to
continuously monitor the DMD array temperature.
To ensure reliable operation, the DLP4621-Q1 must be used with the DLPC230-Q1 DMD display controller and
the TPS99001-Q1 system management and illumination controller.
7.3.1 SubLVDS Data Interface
The subLVDS signaling protocol was designed to enable very fast DMD data refresh rates while simultaneously
maintaining low power and low emission.
Data is loaded into the SRAM under each micromirror using the subLVDS interface from the DLPC230-Q1. This
interface consists of 16 pairs of differential data signals plus two clock pairs into two separate buses A and B
loading the left and right half of the SRAM array. The data is latched on both transitions creating a double data
rate (DDR) interface. The subLVDS interface also implements a continuous training algorithm to optimize the
data and clock timing to allow for a more robust interface.
The entire DMD array of 0.9 million pixels can be updated at a rate of less than 100 µs as a result of the high
speed subLVDS interface.
7.3.2 Low Speed Interface for Control
The purpose of the low speed interface is to configure the DMD at power up and power down and to control the
micromirror reset voltage levels that are synchronized with the data loading. The micromirror reset voltage
controls the time when the mirrors are mechanically switched. The low speed differential interface includes two
pairs of signals for write data and clock, and two single-ended signals for output (A and B).
7.3.3 DMD Voltage Supplies
The micromirrors require unique voltage levels to control the mechanical switching from –12° to +12°. These
voltage levels are nominally 16 V, 8.5 V, and –10 V (VBIAS, VOFFSET, and VRESET), and are generated by
the TPS99001-Q1.
7.3.4 Asynchronous Reset
Reset of the DMD is required and controlled by the DLPC230-Q1 via the signal DMD_DEN_ARSTZ.
7.3.5 Temperature Sensing Diode
The DMD includes a temperature sensing diode designed to be used with the TMP411 temperature monitoring
device. The DLPC230-Q1 monitors the temperature sense diode via the TMP411. The DLPC230-Q1 operation
of the DMD timing can be adjusted based on the DMD array temperature, therefore this connection is essential
to ensure reliable operation of the DMD.
图7-1 shows the typical connection between the DLPC230-Q1, TMP411, and the DMD.
图7-1. Temperature Sense Diode Typical Circuit Configuration
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7.3.5.1 Temperature Sense Diode Theory
A temperature sensing diode is based on the fundamental current and temperature characteristics of a transistor.
The diode is formed by connecting the transistor base to the collector. Three different known currents flow
through the diode and the resulting diode voltage is measured in each case. The difference in their base–
emitter voltages is proportional to the absolute temperature of the transistor.
Refer to the TMP411-Q1 data sheet for detailed information about temperature diode theory and measurement.
图7-2 and 图7-3 illustrate the relationships between the current and voltage through the diode.
IE1
IE2
TEMP_N
+
VBE 1,2
-
TEMP_P
图7-2. Temperature Measurement Theory
100uA
10uA
1uA
Temperature (°C)
Temperature (°C)
图7-3. Example of Delta VBE Versus Temperature
7.4 System Optical Considerations
Optimizing system optical performance and image performance strongly relates to optical system design
parameter trades. Although it is not possible to anticipate every conceivable application, projector image and
optical performance is contingent on compliance to the optical system operating conditions described in the
following sections.
7.4.1 Numerical Aperture and Stray Light Control
The numerical aperture of the illumination and projection optics at the DMD optical area should be the same.
This cone angle defined by the numerical aperture should not exceed the nominal device mirror tilt angle unless
appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light
from the projection lens. The mirror tilt angle defines the DMD's capability to separate the "On" optical path from
any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces.
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7.4.2 Pupil Match
TI’s optical and image performance specifications assume that the exit pupil of the illumination optics is
nominally centered and located at the entrance pupil position of the projection optics. Misalignment of pupils
between the illumination and projection optics can degrade screen image uniformity and cause objectionable
artifacts in the display’s border and/or active area. These artifacts may require additional system apertures to
control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.4.3 Illumination Overfill
Overfill light illuminating the area outside the active array can create artifacts from the mechanical features and
other surfaces that surround the active array. These artifacts may be visible in the projected image. The
illumination optical system should be designed to minimize light flux incident outside the active array and on the
window aperture. Depending on the particular system’s optical architecture and assembly tolerances, this
amount of overfill light on the area outside of the active array may still cause artifacts to be visible.
Illumination light and overfill can also induce undesirable thermal conditions on the DMD, especially if
illumination light impinges directly on the DMD window aperture or near the edge of the DMD window. Heat load
on the aperture in the areas shown in 图6-1 should not exceed the values listed in 节6.4. This area is a 0.5-mm
wide area and length of the aperture opening. The values listed in 节 6.4 assume a uniform distribution. For a
non-uniform distribution please contact TI for additional information.
备注
TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD FAILURES
CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING LIMITS DESCRIBED
PREVIOUSLY.
7.5 DMD Image Performance Specification
表7-1. DMD Image Performance
PARAMETER(1) (2)
Dark Blemishes—Viewed on a linear blue 60 screen(3)
Light Blemishes—Viewed on a linear gray 10 screen.
Bright Pixels—Viewed on a linear gray 10 screen.
Dark Pixels—Viewed on a white screen
MIN
NOM
MAX
UNIT
4
4
0
4
micromirrors
micromirrors
(1) See the System Optical Considerations section.
(2) Blemish counts do not include reflections or shadows of the same artifact. Any artifact that is not specifically called out in this table is
acceptable. Viewing distance must be > 60 in. Screen size should be similar to application image size. All values referenced are in
linear gamma. Non-linear gamma curves may be running by default, and it should be ensured with a TI applications engineer that the
equivalent linear gamma value as specified is used to judge artifacts.
(3) Linear gray 5 may be substituted in monochrome applications.
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7.6 Micromirror Array Temperature Calculation
Array
TP1
1.10
15.40
图7-4. DMD Thermal Test Points
TP1
The active array temperature can be computed analytically from the thermal measurement point on the outside
of the package, the package thermal resistance, the electrical power, and the illumination heat load. The
relationship between array temperature and the reference ceramic temperature (TP1) in Figure 7-4 is provided
by the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC
)
(1)
(2)
(3)
QILLUMINATION = (QINCIDENT × DMD Absorption Constant)
QARRAY = QELECTRICAL + QILLUMINATION
where
• TARRAY = computed array temperature (°C)
• TCERAMIC = measured ceramic temperature at the TP1 location in DMD Thermal Test Points (°C)
• RARRAY–TO–CERAMIC = DMD package thermal resistance from array to thermal test point TP1 (°C/W),
• QARRAY = total power (electrical plus absorbed) on the DMD array (W)
• QELECTRICAL = nominal electrical power dissipation by the DMD (W)
• QILLUMINATION = absorbed illumination heat load (W)
• QINCIDENT = incident power on the DMD (W)
The DMD absorption constant is a function of illumination distribution on the active array and the array border,
angle of incidence (AOI), f number of the system, and operating state of the mirrors. The absorption constant is
higher in the OFF state than in the ON state. Equations to calculate the absorption constant are provided for
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both ON and OFF mirror states. They assume an AOI of 34 degrees, an f/1.7 system, and they account for the
distribution of light on the active array, POM, and array border.
DMD Absorption Constant (OFF state) = 0.895 –0.004783 × (% of light on ActiveArray + POM)
(4)
DMD Absorption Constant (ON state) = 0.895 –0.007208 × (% of light on ActiveArray + POM)
(5)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies.
The DMD package thermal resistance from array to ceramic (RARRAY–TO–CERAMIC) assumes a non-uniform
illumination distribution on the DMD as shown in Non-Uniform Illumination Profile. For illumination profiles more
uniform than the one highlighted in Non-Uniform Illumination Profile, the value provided here is valid. However,
for more non-uniform profiles (for example, Gaussian distribution) the thermal resistance will be higher. Please
contact TI to determine an accurate value for this case.
2.59
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0
-2.59
-5.19 -4.15 -3.11
-2.07 -1.04
0
1.04
2.07
3.11
4.15
5.19
DMD Width (mm)
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
-2.59 -2.08 -1.56 -1.04 -0.52
0 0.52 1.04 1.56 2.08 2.59
DMD Height (mm)
-5.19 -4.15 -3.11 -2.07 -1.04
0
1.04 2.07 3.11 4.15 5.19
DMD Width (mm)
图7-5. Non-Uniform Illumination Profile
The following sample calculations assume 10% of the total incident light falls outside of the active array and
POM, and the mirrors are in the OFF state.
1. TCERAMIC = 50°C (measured)
2. QINCIDENT = 10 W (measured)
3. DMD Absorption Constant = 0.895 –0.004783 × 90 = 0.46
4. QELECTRICAL = 0.4 W
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5. RARRAY–TO–CERAMIC = 1.5°C/W
6. QARRAY = 0.4 W + (0.46 x 10 W) = 5 W
7. TARRAY = 50°C x (5 W x 1.5°C/W) = 57.5°C
When designing the DMD heatsink solution, the package thermal resistance from array to reference ceramic
temperature (thermocouple location TP1 can be used to determine the temperature rise through the package as
given by the following equations:
TARRAY-TO-CERAMIC = QARRAY × RARRAY–TO–CERAMIC
(6)
7.6.1 Monitoring Array Temperature Using the Temperature Sense Diode
The active array temperature can be computed analytically from the temperature sense diode measurement, the
thermal resistance from array to diode, the electrical power, and the illumination heat load. The relationship
between array temperature and the temperature sense diode is provided by the following equations:
TARRAY = TDIODE + (QARRAY × RARRAY–TO–DIODE
)
(7)
(8)
(9)
QILLUMINATION = (QINCIDENT × DMD Absorption Constant)
QARRAY = QELECTRICAL + QILLUMINATION
where
• TARRAY = computed array temperature (°C)
• TDIODE = measured temperature sense diode temperature (°C)
• RARRAY–TO–DIODE = package thermal resistance from array to diode (°C/W)
• QARRAY = total power, electrical plus absorbed, on the DMD array (W)
Refer to Section 7.6 for details.
• QELECTRICAL = nominal electrical power dissipation by the DMD (W)
• QILLUMINATION = absorbed illumination heat load (W)
• QINCIDENT = incident power on the DMD (W)
The temperature sense diode to array thermal resistance (RARRAY–TO–DIODE) assumes a non-uniform
illumination distribution on the DMD as shown in Non-Uniform Illumination Profile. For illumination profiles more
uniform than the one highlighted in Non-Uniform Illumination Profile, the value provided here is valid. However,
for more non-uniform profiles (for example, Gaussian distribution), the thermal resistance will be higher. Please
contact TI to determine an accurate value for this case.
The following sample calculations assume 10% of the total incident light falls outside of the active array and
POM, and the mirrors are in the OFF state.
1. TDIODE = 45°C/W
2. QINCIDENT = 10 W (measured)
3. DMD Absorption Constant = 0.895 –0.004783 × 90 = 0.46
4. QELECTRICAL = 0.4 W
5. RARRAY–TO–DIODE = 0.5°C/W
6. QARRAY = 0.4 W + (0.46 × 10 W) = 5 W
7. TARRAY = 54°C + (5 W × 0.5°C/W) = 56.5°C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 90/10 indicates that the referenced pixel is in the ON state 90% of the
time (and in the OFF state 10% of the time), whereas 10/90 would indicate that the pixel is in the OFF state 90%
of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.
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Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DLP4621-Q1 chipset is designed to support projection-based automotive applications such as high
resolution adaptive driving beam (ADB) headlights.
8.2 Typical Application
The chipset consists of three components—the DLP4621-Q1 automotive DMD, the DLPC230-Q1, and the
TPS99001-Q1. The DMD is a light modulator consisting of tiny mirrors that are used to form and project images.
The DLPC230-Q1 is a controller for the DMD; it formats incoming video and controls the timing of the DMD
illumination sources and the DMD in order to display the incoming video. The TPS99001-Q1 is a high
performance voltage regulator for the DMD and a management IC for the entire chipset. In conjunction, the
DLPC230-Q1 and the TPS99001-Q1 can be used for system-level monitoring, diagnostics, and failure detection
features. 图 8-1 is a system level block diagram with these devices in the DLP headlight module configuration
and displays the primary features and functions of each device.
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VBAT
6.5V Regulator
1.1V
1.8V
3.3V
Regulators
6.5V
Supplies for
DLPC23x-Q1 and
DMD
Voltage Monitor and Enable
3.3V LDO
3.3V
System Voltage Monitor / Brownout Detect
External ADC inputs
for general use
PROJ_ON (system power enable)
Optional SPI monitor
TPS9900x-Q1
HOST_IRQ
ADC_CTRL
SPI
Watchdog 1
Watchdog 2
OpenLDI
OR
Parallel Video
DMD
Voltage
Regulator
Host
VOFFSET
VBIAS
SEQ_START
SEQ_CLK
VRESET
PARKZ
RESETZ
INTZ
I2C Diagnostic
SPI Command
1.8V
DLP462x Series
DMD
HS SubLVDS Data
LS SubLVDS Control
DMD_DEN_ARSTZ
I2C
TMP411
Flash
DMD die temperature sense
DLPC23x-Q1
SPI
VBAT
LED_SEL (enable)
LED Driver
PWM (analog dimming)
Spare
GPIO
GND
3.3V
1.8V
1.1V
Shunt Enable
DLP Chipset
Components
GND
图8-1. Headlight System Block Diagram
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8.2.1 Application Overview
图 8-1 shows the system block diagram for a DLP headlight module. The system uses the DLPC230-Q1,
TPS99001-Q1, and the DLP4621-Q1 automotive DMD to enable a headlight projection system with
unprecedented resolution and grayscale light control. The combination of the DLPC230-Q1 and TPS99001-Q1
removes the need for external SDRAM and a dedicated microprocessor. The chipset manages the illumination
control of LED sources, power sequencing functions, and system management functions. Additionally, the
chipset supports numerous system diagnostic and built-in self test (BIST) features. The following paragraphs
describe the functionality of the chipset used for a headlight projection system in more detail.
The DLPC230-Q1 is a controller for the DMD and the light sources in the DLP Headlight, HUD or Projector
module. It receives input video from the host and synchronizes DMD and light source timing in order to achieve
the desired video. The DLPC230-Q1 formats input video data that is displayed on the DMD. It synchronizes
these video segments with light source timing in order to create a video with grayscale shading and multiple
colors, if applicable.
The DLPC230-Q1 receives inputs from a host processor in the vehicle. The host provides commands and input
video data. Host commands can be sent using either the I2C bus or SPI bus. The bus that is not being used for
host commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an
OpenLDI bus or a parallel 24-bit bus. The 24-bit bus can be limited to only 8-bits or 16-bits of data for single light
source or dual light source systems depending on the system design. The SPI flash memory provides the
embedded software for the DLPC230-Q1’s ARM core, any calibration data, and default settings. The
TPS99001-Q1 provides diagnostic and monitoring information to the DLPC230-Q1 using an SPI bus and several
other control signals such as PARKZ, INTZ, and RESETZ to manage power-up and power-down sequencing.
The TMP411 uses an I2C interface to provide the DMD array temperature to the DLPC230-Q1.
The outputs of the DLPC230-Q1 are configuration and monitoring commands to the TPS99001-Q1, timing
controls to the LED or laser driver, control and data signals to the DMD, and monitoring and diagnostics
information to the host processor. The DLPC230-Q1 communicates with the TPS99001-Q1 over an SPI bus. It
uses this to configure the TPS99001-Q1 and to read monitoring and diagnostics information from the TPS99001-
Q1. The DLPC230-Q1 sends drive enable signals to the LED or laser driver, and synchronizes this with the DMD
mirror timing. The control signals to the DMD are sent using a subLVDS interface.
The TPS99001-Q1 is a highly integrated mixed-signal IC that controls DMD power and provides monitoring and
diagnostics information for the DLP headlight module. The power sequencing and monitoring blocks of the
TPS99001-Q1 properly power up the DMD and provide accurate DMD voltage rails (–16 V, 8.5 V, and 10 V),
and then monitor the system’s power rails during operation. The integration of these functions into one IC
significantly reduces design time and complexity. The TPS99001-Q1 also has several output signals that can be
used to control a variety of LED or laser driver topologies. The TPS99001-Q1 has several general-purpose
ADCs that designers can use for system level monitoring, such as over-brightness detection.
The TPS99001-Q1 receives inputs from the DLPC230-Q1, the power rails it monitors, the host processor, and
potentially several other ADC ports. The DLPC230-Q1 sends configuration and control commands to the
TPS99001-Q1 over an SPI bus and several other control signals. The DLPC230-Q1’s clocks are also
monitored by the watchdogs in the TPS99001-Q1 to detect any errors. The power rails are monitored by the
TPS99001-Q1 in order to detect power failures or glitches and request a proper power down of the DMD in case
of an error. The host processor can read diagnostics information from the TPS99001-Q1 using a dedicated SPI
bus, which enables independent monitoring. Additionally, the host can request the image to be turned on or off
using a PROJ_ON signal. Lastly, the TPS99001-Q1 has several general-purpose ADCs that can be used to
implement system level monitoring functions.
The outputs of the TPS99001-Q1 are diagnostic information and error alerts to the DLPC230-Q1, and control
signals to the LED or laser driver. The TPS99001-Q1 can output diagnostic information to the host and the
DLPC230-Q1 over two SPI buses. In case of critical system errors, such as power loss, it outputs signals to the
DLPC230-Q1 that trigger power down or reset sequences. It also has output signals that can be used to
implement various LED or laser driver topologies.
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The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video
data), and produces a mechanical output (mirror position). The electrical interface to the DMD is a subLVDS
interface with the DLPC230-Q1. The mechanical output is the state of more than 0.9 million mirrors in the DMD
array that can be tilted ±12°. In a projection system the mirrors are used as pixels in order to display an image.
8.2.2 Reference Design
For information about connecting together the DLP4621-Q1 DMD, DLPC230-Q1 controller, and TPS99001-Q1,
please contact the TI Application Team for additional information about the DLP4621-Q1 evaluation module
(EVM). TI has optical-mechanical reference designs available, see the TI Application team for more information.
8.2.3 Application Mission Profile Consideration
Each application is anticipated to have different mission profiles, or number of operating hours at different
temperatures. To assist in evaluation an Application Report may be provided in the future. See the TI Application
team for more information.
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9 Power Supply Recommendations
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET.
All VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the
TPS99001-Q1 device.
CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to the prescribed power-up and power-down procedures may affect
device reliability.
VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-
up and power-down operations. Failure to meet any of the below requirements will result in a
significant reduction in the DMD’s reliability and lifetime. VSS must also be connected.
9.1 Power Supply Power-Up Procedure
• During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET
voltages are applied to the DMD.
• During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in the Recommended Operating Conditions.
• During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have
settled at operating voltage.
• During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow
the requirements listed previously and in 图9-1.
9.2 Power Supply Power-Down Procedure
• The power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be
supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
• During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement
that the delta between VBIAS and VOFFSET must be within the specified limit shown in the Recommended
Operating Conditions (refer to Note 2 in 节9.3).
• During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in the
Recommended Operating Conditions.
• During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed previously and in 节9.3.
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9.3 Power Supply Sequencing Requirements
TPS9900x initiates DMD power-
down sequence. DLPC231
executes critical commands.
DLPC231 and TPS9900x
control start of DMD
operation
DLPC231 and TPS9900x
disables VBIAS, VOFFSET, and
VRESET
Mirror Park Sequence(4)
Power off
VDD / VDDI
VDD / VDDI
VDD / VDDI
VSS
VSS
VBIAS
VBIAS
VBIAS
VBIAS < 4 V
V < Specification(1)(2)
V < Specification(3)
VSS
VSS
V < Specification(2)
VOFFSET
VOFFSET
VOFFSET
VSS
VOFFSET < 4 V
VSS
VRESET < 0.5 V
VSS
VSS
VRESET > - 4 V
VRESET
VRESET
VRESET
VDD
VDD
DMD_DEN_ARSTZ
VSS
VSS
VSS
Initialization
LS_CLK_P
LS_CLK_N
VSS
LS_WDATA_P
LS_WDATA_N
D_AP(7:0) , D_AN(7:0)
D_BP(7:0) , D_BN(7:0) VSS
DCLK_AP , DCLK_AN
DCLK_BP , DCLK_BN
VSS
A. To prevent excess current, the supply voltage delta |VBIAS –VOFFSET| must be less than specified in the Recommended Operating
Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to
remove VBIAS prior to VOFFSET during power-down. Also, the TPS99001-Q1 is capable of managing the timing between VBIAS and
VOFFSET.
B. To prevent excess current, the supply voltage delta |VBIAS –VRESET| must be less than specified than the limit shown in the
Recommended Operating Conditions.
C. When system power is interrupted, the TPS99001-Q1 initiates hardware power-down that disables VBIAS, VRESET, and VOFFSET
after the Micromirror Park Sequence.
D. The drawing is not to scale and details are omitted for clarity.
图9-1. Power Supply Sequencing Requirements (Power Up and Power Down)
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10 Layout
10.1 Layout Guidelines
Please refer to the DLPC230-Q1 and TPS99001-Q1 data sheets for specific PCB layout and routing guidelines.
For specific DMD PCB guidelines, use the following:
• Match lengths for the LS_WDATA and LS_CLK signals
• Minimize vias, layer changes, and turns for the HS bus signals
• Minimum of two 220-nF decoupling capacitors close to VBIAS
• Minimum of two 220-nF decoupling capacitors close to VRESET
• Minimum of two 220-nF decoupling capacitors close to VOFFSET
• Minimum of four 100-nF decoupling capacitors close to VDDI and VDD
• Temperature diode pins
The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411
temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411 are sensitive to
noise. See the TMP411 ±1°C Remote and Local Temperature Sensor with N-Factor and Series Resistance
Correction Data Sheet for specific routing recommendations.
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11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Device Support
11.2.1 Device Nomenclature
DLP4621 A FQX Q1
Automotive Qualified
Package Type
Temperature Range
Device Descriptor
图11-1. Part Number Description
11.2.2 Device Markings
The device marking includes the legible character string GHJJJJK DLP4621AFQXQ1. GHJJJJK is the lot trace
code. DLP4621AFQXQ1 is the part number.
Lot Trace Code
Part Marking
Two-Dimensional Matrix Code
(DMD part number and lot trace code)
图11-2. DMD Marking
11.3 Trademarks
DLP® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
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11.5 DMD Handling
The DMD is an optical device so precautions should be taken to avoid damaging the glass window. Please see
the application note DLPA019 DMD Handling for instructions on how to properly handle the DMD.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XDLP4621AFQXQ1
ACTIVE
CLGA
FQX
120
72
RoHS & Green
Call TI
N / A for Pkg Type
-40 to 105
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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19-Jul-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
XDLP4621AFQXQ1
FQX
CLGA
120
72
8 x 7
150
315 135.9 12190 21.9 15.15 16.95
Pack Materials-Page 1
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