ULN2004AIDRG4 [TI]
0.5A, 50V, 7 CHANNEL, NPN, Si, POWER TRANSISTOR, MS-012AC, GREEN, PLASTIC, SOIC-16;
| 型号： | ULN2004AIDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.5A, 50V, 7 CHANNEL, NPN, Si, POWER TRANSISTOR, MS-012AC, GREEN, PLASTIC, SOIC-16 开关 光电二极管 晶体管 |
| 文件： | 总17页 (文件大小：645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃꢄꢄ ꢅꢆ ꢇ
ꢈꢇ ꢉꢈ ꢊꢋꢌ ꢁꢍꢆꢉ ꢎ ꢈꢇ ꢉꢈ ꢊꢏꢀꢐꢐꢎ ꢂꢍ ꢑꢆꢐ ꢁꢇ ꢂꢉ ꢍꢌ ꢂ
ꢍ ꢐꢆꢂꢒ ꢇꢒꢍꢌꢐ ꢆ ꢐꢐ ꢆꢓ
SLRS055 − APRIL 2004
D, N, OR NS PACKAGE
(TOP VIEW)
D
500-mA-Rated Collector Current
(Single Output)
D
D
D
D
High-Voltage Outputs . . . 50 V
Output Clamp Diodes
1B
2B
3B
4B
5B
6B
7B
E
1
2
3
4
5
6
7
8
16 1C
15 2C
14 3C
Inputs Compatible With Various Types of
Logic
13
12
11
10
9
4C
5C
6C
7C
Relay-Driver Applications
description/ordering information
COM
The ULN2004AI is a high-voltage, high-current
Darlington transistor array. This device consists
of seven npn Darlington pairs that feature
high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current
rating of a single Darlington pair is 500 mA. The Darlington pairs can be paralleled for higher-current capability.
Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line
drivers, and logic buffers.
The ULN2004AI has a 10.5-kΩ series base resistor for each Darlington pair for operation directly with TTL or
5-V CMOS devices.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP (N)
SOIC (D)
SOP (NS)
Tube of 25
Tube of 40
Reel of 2500
Reel of 2000
ULN2004AIN
ULN2004AID
ULN2004AIDR
ULN2004AINSR
ULN2004AIN
ULN2004AI
ULN2004AI
−40°C to 105°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ
ꢈ ꢇꢉ ꢈꢊꢋ ꢌꢁꢍꢆ ꢉꢎ ꢈꢇ ꢉ ꢈꢊꢏ ꢀꢐꢐ ꢎꢂꢍ ꢑꢆ ꢐꢁꢇ ꢂꢉ ꢍꢌ ꢂ
ꢍ ꢐꢆꢂ ꢒꢇ ꢒꢍꢌꢐ ꢆꢐ ꢐꢆꢓ
SLRS055 − APRIL 2004
logic diagram
9
COM
1C
1
16
1B
2B
3B
4B
5B
6B
7B
2
3
4
5
6
7
15
14
13
12
11
10
2C
3C
4C
5C
6C
7C
schematics (each Darlington pair)
COM
Output
C
10.5 kΩ
Input
B
7.2 kΩ
3 kΩ
E
All resistor values shown are nominal.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢄ ꢅꢆ ꢇ
ꢈꢇ ꢉꢈ ꢊꢋꢌ ꢁꢍꢆꢉ ꢎ ꢈꢇ ꢉꢈ ꢊꢏꢀꢐꢐꢎ ꢂꢍ ꢑꢆꢐꢁ ꢇꢂ ꢉ ꢍꢌ ꢂ
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SLRS055 − APRIL 2004
†
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)
Collector-emitter voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
Clamp diode reverse voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V
Input voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
I
Peak collector current (see Notes 2 and 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
Output clamp current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
OK
Total emitter-terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2.5 A
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C
A
Package thermal impedance, θ (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
2. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable
J
JA
A
ambient temperature is P = (T (max) − T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.
D
J
A
JA
J
3. The package thermal impedance is calculated in accordance with JESD 51-7.
electrical characteristics, T = 25°C
A
TEST
FIGURE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
= 125 mA
= 200 mA
= 275 mA
= 350 mA
= 100 mA
= 200 mA
= 350 mA
5
6
C
C
C
C
C
C
C
V
V
On-state input voltage
6
V
= 2 V
V
I(on)
CE
7
8
I = 250 µA,
I
0.9
1
1.1
1.3
1.6
50
2
I = 350 µA,
I
Collector-emitter saturation voltage
5
V
CE(sat)
I = 500 µA,
I
1.2
I
Collector cutoff current
Clamp forward voltage
1
8
V
= 50 V,
I = 0
I
µA
CEX
CE
= 350 mA
F
V
F
I
1.7
0.35
1
V
V = 5 V
I
0.5
1.45
50
25
I
I
Input current
4
7
mA
I
V = 12 V
I
Clamp reverse current
Input capacitance
V
R
= 50 V
µA
R
C
V = 0,
I
f = 1 MHz
15
pF
i
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ
ꢈ ꢇꢉ ꢈꢊꢋ ꢌꢁꢍꢆ ꢉꢎ ꢈꢇ ꢉ ꢈꢊꢏ ꢀꢐꢐ ꢎꢂꢍ ꢑꢆ ꢐꢁꢇ ꢂꢉ ꢍꢌ ꢂ
ꢍ ꢐꢆꢂ ꢒꢇ ꢒꢍꢌꢐ ꢆꢐ ꢐꢆꢓ
SLRS055 − APRIL 2004
electrical characteristics, T = −40°C to 105°C
A
TEST
PARAMETER
FIGURE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
= 125 mA
= 200 mA
= 275 mA
= 350 mA
= 100 mA
= 200 mA
= 350 mA
5
6
C
C
C
C
C
C
C
V
On-state input voltage
6
V
= 2 V
V
I(on)
CE
7
8
I = 250 µA,
I
0.9
1
1.1
1.3
1.6
50
100
500
2
I = 350 µA,
I
V
I
Collector-emitter saturation voltage
Collector cutoff current
5
V
CE(sat)
I = 500 µA,
I
1.2
1
2
V
CE
= 50 V,
I = 0
I
I = 0
I
µA
CEX
V
CE
= 50 V
V = 1 V
I
V
F
Clamp forward voltage
Off-state input current
8
3
I
F
= 350 mA
1.7
65
V
I
V
= 50 V,
I = 500 µA
C
50
µA
I(off)
CE
V = 5 V
0.35
1
0.5
1.45
100
25
I
I
I
Input current
4
7
mA
V = 12 V
I
I
R
Clamp reverse current
Input capacitance
V
R
= 50 V
µA
C
V = 0,
I
f = 1 MHz
15
pF
i
switching characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
MIN
TYP
0.25
0.25
MAX
UNIT
µs
t
t
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
See Figure 8
See Figure 8
= 50 V,
1
1
PLH
µs
PHL
V
S
I
O
≈ 300 mA,
V
OH
High-level output voltage after switching
V
S
− 20
mV
See Figure 9
switching characteristics, T = −40°C to 105°C
A
PARAMETER
TEST CONDITIONS
See Figure 8
See Figure 8
= 50 V, ≈ 300 mA,
O
MIN
TYP
1
MAX
10
UNIT
µs
t
t
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
PLH
1
10
µs
PHL
V
I
S
V
OH
High-level output voltage after switching
V
S
− 500
mV
See Figure 9
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢄ ꢅꢆ ꢇ
ꢈꢇ ꢉꢈ ꢊꢋꢌ ꢁꢍꢆꢉ ꢎ ꢈꢇ ꢉꢈ ꢊꢏꢀꢐꢐꢎ ꢂꢍ ꢑꢆꢐꢁ ꢇꢂ ꢉ ꢍꢌ ꢂ
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SLRS055 − APRIL 2004
PARAMETER MEASUREMENT INFORMATION
Open
Open
V
CE
V
CE
I
I
CEX
CEX
Open
V
I
Figure 1. I
Test Circuit
Figure 2. I
Test Circuit
CEX
CEX
Open
V
CE
Open
I
I
C
I(off)
I
I(on)
V
I
Open
Figure 3. I
Test Circuit
Figure 4. I Test Circuit
I
I(off)
Open
Open
I
C
h
FE
=
I
I
V
CE
I
I
I
C
V
I(on)
V
CE
I
C
NOTE: I is fixed for measuring V
, variable for
I
CE(sat)
measuring h
.
FE
Figure 5. h , V
Test Circuit
Figure 6. V
Test Circuit
I(on)
FE CE(sat)
V
R
I
R
V
F
I
F
Open
Open
Figure 7. I Test Circuit
Figure 8. V Test Circuit
F
R
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ
ꢈ ꢇꢉ ꢈꢊꢋ ꢌꢁꢍꢆ ꢉꢎ ꢈꢇ ꢉ ꢈꢊꢏ ꢀꢐꢐ ꢎꢂꢍ ꢑꢆ ꢐꢁꢇ ꢂꢉ ꢍꢌ ꢂ
ꢍ ꢐꢆꢂ ꢒꢇ ꢒꢍꢌꢐ ꢆꢐ ꢐꢆꢓ
SLRS055 − APRIL 2004
PARAMETER MEASUREMENT INFORMATION
Input
50%
50%
t
t
PHL
PLH
50%
50%
Output
VOLTAGE WAVEFORMS
Figure 9. Propagation Delay-Time Waveforms
V
S
Input
2 mH
Open
1N3064
200 Ω
Pulse
Generator
(see Note A)
Output
= 15 pF
C
L
(see Note B)
TEST CIRCUIT
≤5 ns
90%
≤10 ns
V
IH
90%
(see Note C)
Input
1.5 V
1.5 V
10%
10%
0 V
40 µs
V
V
OH
Output
OL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, Z = 50 Ω.
O
B.
C includes probe and jig capacitance.
L
C. For testing, V = 3 V
IH
Figure 10. Latch-Up Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢄ ꢅꢆ ꢇ
ꢈꢇ ꢉꢈ ꢊꢋꢌ ꢁꢍꢆꢉ ꢎ ꢈꢇ ꢉꢈ ꢊꢏꢀꢐꢐꢎ ꢂꢍ ꢑꢆꢐꢁ ꢇꢂ ꢉ ꢍꢌ ꢂ
ꢍ ꢐꢆꢂꢒ ꢇꢒꢍꢌ ꢐ ꢆ ꢐꢐ ꢆꢓ
SLRS055 − APRIL 2004
TYPICAL CHARACTERISTICS
COLLECTOR-EMITTER
SATURATION VOLTAGE
vs
COLLECTOR-EMITTER
SATURATION VOLTAGE
vs
TOTAL COLLECTOR CURRENT
(TWO DARLINGTONS IN PARALLEL)
COLLECTOR CURRENT
(ONE DARLINGTON)
2.5
2
2.5
2
T
A
= 25°C
T
A
= 25°C
I = 250 µA
I
I = 350 µA
I
I = 250 µA
I
I = 350 µA
I
I = 500 µA
I
1.5
1
1.5
1
I = 500 µA
I
0.5
0
0.5
0
0
100 200 300 400 500 600 700 800
0
100 200 300 400 500 600 700 800
I
− Total Collector Current − mA
I
C
− Collector Current − mA
C(tot)
Figure 12
Figure 11
COLLECTOR CURRENT
vs
INPUT CURRENT
500
R
T
A
= 10 Ω
= 25°C
L
450
400
350
300
250
200
150
100
50
V
S
= 10 V
V
S
= 8 V
0
0
25
50
75
100 125 150 175 200
I − Input Current − µA
I
Figure 13
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ
ꢈ ꢇꢉ ꢈꢊꢋ ꢌꢁꢍꢆ ꢉꢎ ꢈꢇ ꢉ ꢈꢊꢏ ꢀꢐꢐ ꢎꢂꢍ ꢑꢆ ꢐꢁꢇ ꢂꢉ ꢍꢌ ꢂ
ꢍ ꢐꢆꢂ ꢒꢇ ꢒꢍꢌꢐ ꢆꢐ ꢐꢆꢓ
SLRS055 − APRIL 2004
APPLICATION INFORMATION
V
CC
V
V
CC
V
1
16
15
14
1
2
16
15
14
2
3
4
5
R
P
3
4
13
12
11
10
9
13
12
11
10
9
5
6
6
7
8
7
8
Lamp
Test
TTL
Output
TTL
Output
Figure 15. Use of Pullup Resistors
to Increase Drive Current
Figure 14. TTL to Load
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
ULN2004AID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ULN2004AIDE4
ULN2004AIDG4
ULN2004AIDR
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ULN2004AIDRE4
ULN2004AIDRG4
ULN2004AIN
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
ULN2004AINE4
ULN2004AINSR
ULN2004AINSRE4
ULN2004AINSRG4
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ULN2004AIDR
SOIC
SO
D
16
16
2500
2000
330.0
330.0
16.4
16.4
6.5
8.2
10.3
10.5
2.1
2.5
8.0
16.0
16.0
Q1
Q1
ULN2004AINSR
NS
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ULN2004AIDR
SOIC
SO
D
16
16
2500
2000
333.2
346.0
345.9
346.0
28.6
33.0
ULN2004AINSR
NS
Pack Materials-Page 2
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相关型号：
ULN2004ANS
TRANSISTOR 50 V, 7 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR, PLASTIC, SO-16, BIP General Purpose Small Signal
TI
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