UCD3138128APFCR [TI]
适用于隔离电源的高集成度数字控制器 | PFC | 80 | -40 to 125;型号: | UCD3138128APFCR |
厂家: | TEXAS INSTRUMENTS |
描述: | 适用于隔离电源的高集成度数字控制器 | PFC | 80 | -40 to 125 时钟 控制器 功率因数校正 外围集成电路 |
文件: | 总85页 (文件大小:2494K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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UCD3138128A
SLUSC99A –JULY 2016–REVISED JANUARY 2017
UCD3138128A Highly-Integrated Digital Controller For Isolated Power
1 Features
– Constant Current, Constant Power
•
•
Configurable FM, Phase Shift Modulation and
PWM
1
•
128 kB Program Flash Derivative of UCD3138xA
Family
Fast, Automatic and Smooth Mode Switching
–
–
4-32 kB Program Flash Memory Banks
–
–
Frequency Modulation and PWM
Phase Shift Modulation and PWM
Supports Execution From 1 Bank, While
Programming Another
–
–
–
Capability to Update Firmware Without
Shutting Down the Power Supply
•
High Efficiency and Light Load Management
–
–
–
Burst Mode and Ideal Diode Emulation
Synchronous Rectifier Soft On/Off
Low IC Standby Power
Additional Communication Ports Compared to
the UCD3138xA (+1 SPI, +1 I2C)
Boot Flash Based Dual Memory Image
Support for ‘On the Fly’ Firmware Updates
•
•
•
Primary Side Voltage Sensing
Current Share (Average and Master/Slave)
Feature Rich Fault Protection Options
•
•
Synchronous Rectifier Dead Time Optimization
Peripheral to Use with UCD7138 Synchronous
Rectifier Driver
–
–
–
7 Analog / 4 Digital Comparators,
Cycle-by-Cycle Current Limiting
Digital Control of up to 3 Independent Feedback
Loops
Programmable Blanking Time and Fault
Counting
–
–
Dedicated PID Based Hardware
–
External Fault Inputs
2-pole/2-zero Configurable, Non-Linear Control
•
•
Synchronization of DPWM Waveforms Between
Multiple UCD3138x Devices
•
•
Up to 16 MSPS Error A/D Converter (EADC)
–
–
Configurable Resolution (min: 1 mV/LSB)
15 channel, 12 bit, 539 ksps General Purpose
ADC
Up to 8x Oversampling and Adaptive Sample
Positioning
•
•
Internal Temperature Sensor
–
–
Hardware Based Averaging (up to 8x)
14 bit Effective Reference DAC
Fully Programmable High-Performance 31.25
MHz, 32-bit ARM7TDMI-S Processor
Up to 8 High Resolution Digital Pulse Width
Modulated (DPWM) Outputs
–
–
–
–
128 kB Program Flash (4-32 kB Banks)
2 kB Data Flash with ECC
–
–
–
–
–
250 ps Pulse Width Resolution
8 kB Data RAM
4 ns Frequency and Phase Resolution
Adjustable Phase Shift and Dead-bands
Cycle-by-Cycle Duty Cycle Matching
Up to 2 MHz Switching Frequency
8 kB Boot ROM Enables Firmware Boot-Load\
•
Communication Peripherals,
–
–
2 - I2C/PMBus interfaces
2 - UARTs, 1 - SPI
•
Configurable Trailing/Leading/Triangular
Modulation
•
•
•
•
•
UART Auto Baud Rate Adjustment
Timer Capture with Selectable Input Pins
80-pin QFP Package
•
•
•
RTC Support
External Crystal Interface
Configurable Feedback Control
Operating Temperature: –40°C to 125°C
Debug Interface
–
Voltage, Average Current and Peak Current
Mode Control
–
–
Code Composer Studio with JTAG Interface
Fusion Digital Power Designer GUI Support
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCD3138128A
SLUSC99A –JULY 2016–REVISED JANUARY 2017
www.ti.com
2 Applications
•
•
•
•
Power Supplies and Telecom Rectifiers
Power Factor Correction
Isolated DC-DC Modules
Phase Shifted Full Bridge with Peak Current Mode
Control, LLC, HSFB, Forward
Typical Applications and Tools
Best in Class Firmware
Development Tools
UCD3138128A
Advanced Configuration &
Advanced Topology Control
Debug Tools
VIN
Q1
Q3
Transformer
LK
LR
Q2
VIN
LM
CO
esr
Q1
Q2
Q4
SR2
n2
n2
CR
L0
L
n
M
1
C0
+ Forward, Flyback,
Half-bridge, etc...
Q3
Q4
SR1
Copyright
© 2016, Texas Instruments Incorporated
3 Description
The UCD3138xA is a digital power supply controller from Texas Instruments offering superior levels of integration
and performance in a single chip solution. The UCD3138128A offers 128 kB of program flash memory in
comparison to 32 kB in UCD3138A. and it also provides additional options for communication such as SPI and a
second I2C/PMBus port. The availability of of program Flash memory in multiple 32 kB banks enables designers
to implement dual images of firmware (that is, one main image + one back-up image) in the device and provides
the option to execute from either of the banks using appropriate algorithms. It also creates the unique opportunity
for the processor to load a new program and subsequently execute that program without interrupting power
delivery. This feature allows the end user to add new features to the power supply in the field while eliminating
any down-time required to load the new program.
The flexible nature of the UCD3138xA family makes it suitable for a wide variety of power conversion
applications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the
performance of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and
network infrastructure space. The UCD3138xA family is a fully programmable solution offering customers
complete control of their application, along with ample flexibility for many solutions. At the same time, TI is
committed to simplifying our customer’s development effort through offering best in class development tools,
including application firmware, Code Composer StudioTM software development environment, and TI’s Fusion
Power Development GUI which enables customers to configure and monitor key system parameters.
At the core of the controller are the Digital Power Peripherals (DPP). Each DPP implements a high speed digital
control loop consisting of a dedicated Error Analog to Digital Converter (EADC), a PID based 2 pole - 2 zero
digital compensator and DPWM outputs with 250 ps pulse width resolution. The device also contains a 12-bit,
539 ksps general purpose ADC with up to 15 channels, timers, interrupt control, PMBus, I2C, SPI and UART
communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-
time monitoring, configures peripherals and manages communications. The ARM microcontroller executes its
program out of programmable flash memory as well as on chip RAM and ROM.
In addition to the DPP, specific power management peripherals have been added to enable high efficiency
across the entire operating range, high integration for increased power density, reliability, and lowest overall
system cost and high flexibility with support for the widest number of control schemes and topologies. Such
peripherals include: light load burst mode, synchronous rectification, LLC and phase shifted full bridge mode
switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current
constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing,
secondary side input voltage sensing, high resolution current sharing, hardware configurable soft start with pre
bias, as well as several other features. Topology support has been optimized for voltage mode and peak current
mode controlled phase shifted full bridge, single and dual phase PFC, bridgeless PFC, hard switched full bridge
and half bridge, active clamp forward converter, two switch forward converter and LLC half bridge and full bridge.
2
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SLUSC99A –JULY 2016–REVISED JANUARY 2017
The UCD3138128A is a functional variant of the UCD3138 Digital Power Controller that includes significant
improvements over the UCD3138. For a description of the complete changes made in the UCD3138128A, refer
to UCD3138128A Migration Guide. The major improvements are:
•
The General Purpose ADC has been improved for better accuracy and performance at extreme cold
temperatures (–40°C).
•
•
The UART peripheral has been modified to include a hardware based auto-baud rate adjustment feature.
A new Synchronous Rectifier Dead Time Optimization hardware peripheral has been added. Benefits include:
–
–
–
Improved efficiency
Reduced synchronous rectifier voltage stresses
Shorter development cycle
•
A Duty Cycle Read Function has been added to improve use in peak current mode.
Device Information(1)
PART NUMBER
UCD3138128A
PACKAGE
BODY SIZE (NOM)
12.00 mm × 12.00 mm
TQFP (80)
(1) For detailed ordering information please check the Mechanical, Packaging, and Orderable Information section at the end of this
datasheet.
Copyright © 2016–2017, Texas Instruments Incorporated
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SLUSC99A –JULY 2016–REVISED JANUARY 2017
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Table of Contents
9.2 Functional Block Diagram ....................................... 21
9.3 Feature Description................................................. 22
9.4 Device Functional Modes........................................ 50
9.5 Register Maps......................................................... 57
10 Applications and Implementation...................... 60
10.1 Application Information.......................................... 60
10.2 Typical Application ............................................... 61
11 Power Supply Recommendations ..................... 72
12 Layout................................................................... 72
12.1 Device Grounding and Layout Guidelines ............ 72
12.2 Layout Examples................................................... 73
13 Device and Documentation Support ................. 74
13.1 Device Support...................................................... 74
13.2 Documentation Support ........................................ 74
13.3 Receiving Notification of Documentation Updates 76
13.4 Trademarks........................................................... 76
13.5 Electrostatic Discharge Caution............................ 76
13.6 Glossary................................................................ 76
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 2
Description ............................................................. 2
Revision History..................................................... 4
Device Comparison ............................................... 5
Pin Configuration and Functions......................... 7
Specifications......................................................... 9
7.1 Absolute Maximum Ratings ...................................... 9
7.2 ESD Ratings.............................................................. 9
7.3 Recommended Operating Conditions..................... 10
7.4 Thermal Information................................................ 10
7.5 Electrical Characteristics......................................... 10
7.6 Timing Characteristics............................................. 13
7.7 PMBus/SMBus/I2C Timing...................................... 14
7.8 Typical Characteristics............................................ 15
7.9 Timing Diagrams..................................................... 16
Parametric Measurement Information ............... 17
8.1 Typical Clock Gating Power Savings...................... 18
Detailed Description ............................................ 19
9.1 Overview ................................................................. 19
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 76
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2016) to Revision A
Page
•
•
•
•
•
•
•
Added two temperature ranges to the Internal oscillator frequency section. ....................................................................... 13
Changed Figure 15 .............................................................................................................................................................. 29
Changed Figure 35 to include DTC Adjustment .................................................................................................................. 51
Changed capacitor from RESET to ground value from 0.22 µF to 2.2 µF. ......................................................................... 72
Added updated V33 slew rate values in the Device Grounding and Layout Guidelines section. ........................................ 72
Added bullet on unused GPIO pins ..................................................................................................................................... 72
Changed "A" to part number ............................................................................................................................................... 73
4
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SLUSC99A –JULY 2016–REVISED JANUARY 2017
5 Device Comparison
Table 1. Product Family Comparison
UCD
3138
3138A
RHA/RMH
3138064
3138064A
RMH
3138
3138A
RGC
3138064
3138064A
RGC
3138128
3138A64
3138128A
PFC
3138064
RGZ
FEATURE
PFC
80 Pin QFP
(14mm x 14mm)
(Includes leads)
80 Pin QFP
(14mm x 14mm)
(Includes leads)
40 Pin QFN
(6mm x 6mm)
40 Pin QFN
(6mm x 6mm)
64 Pin QFN
( 9mm x 9mm)
64 Pin QFN
(9mm x 9mm)
48 Pin QFN
(7mm x 7mm)
Package Offering
ARM7TDMI-S Core Processor
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
High Resolution DPWM Outputs (250ps Resolution)
Number of High Speed Independent Feedback Loops
(# Regulated Output Voltages
3
3
3
3
3
3
3
12-bit, 256kps, General Purpose ADC Channels
Digital Comparators at ADC Outputs
Flash Memory (Program)
7
4
7
4
14
4
14
4
9
4
15
4
15
4
32 kB
64 kB
32 kB
64 kB
64 kB
128 kB
64 kB
Only 1 bank of 64 kB
Flash available
Number of Memory 32kB Flash Memory Banks
1
2
1
2
2
4
Flash Memory (Data)
RAM
2 kB
4 kB
2 kB
4 kB
2 kB
4 kB
4
2 kB
4 kB
2 kB
4 kB
2 kB
8 kB
4
2 kB
8 kB
4
Programmable Fault Inputs
1 + 2(1)
1 + 2(1)
2 + 2(1)
1 + 2(1)
High Speed Analog Comparators with Cycle-by-Cycle
Current Limiting
6
6
7
7
6
7
7
UART (SCI)
PMBus/I2C
1(1)
1
1(1)
1
2
1
2
1
2
1
2
1
2
1
Additional I2C
SPI
0
0
0
0
0
0
1(1)
1(1)
1(1)
1(1)
1
1
1
1
4 (16 bit) and
1 (24 bit)
4 (16 bit) and
1 (24 bit)
4 (16 bit) and
1 (24 bit)
4 (16 bit) and
1 (24 bit)
4 (16 bit) and
1 (24 bit)
4 (16 bit) and
2 (24 bit)
4 (16 bit) and
2 (24 bit)
Timers
Timer PWM Outputs
1(1)
1(1)
2
2
1(1)
4
4
Timer Capture Inputs
Total Digital GPIOs
2(1)
2(1)
1 + 3(1)
1 + 3(1)
2(1)
2 + 2(1)
2 + 2(1)
18
18
30
30
24
43
43
External Interrupts
0
no
0
no
1
no
1
no
0
no
1
1
External Crystal Clock Support
Peak Current Mode Control
Yes (pins #61, 62)
All EADC Channels
Yes (pins #61, 62)
All EADC Channels
EADC2 Only
All EADC channels
EADC Only
All EADC channels
All EADC Channels
(1) Represents an alternate pin out that is programmable via firmware.
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Table 2. Device Feature Information
FEATURE
UCD3138128A 80 PIN
ARM7TDMI-S Core Processor
31.25 MHz
High Resolution DPWM Outputs (250ps Resolution)
8
Number of High Speed Independent Feedback Loops (# Regulated Output Voltages)
3
12-bit, 539 ksps, General Purpose ADC Channels
15
Digital Comparators at ADC Outputs
4
Flash Memory (Program)
128 kB
Flash Memory (Data)
2 kB
Flash Security
√
RAM
8 kB
DPWM Switching Frequency
up to 2 MHz
Programmable Fault Inputs
4
High Speed Analog Comparators with Cycle-by-Cycle Current Limiting
7
UART (SCI)
2
PMBus
1
I2C
1
SPI
1
Timers
4 (16 bit) and 2 (24 bit)
Timer PWM Outputs
4
2
Timer Capture Inputs
Watchdog
√
On Chip Oscillator
√
Power-On Reset and Brown-Out Detector
√
Sync IN and Sync OUT Functions
√
Total GPIO (includes all pins with multiplexed functions such as, DPWM, Fault Inputs, SCI, etc.)
External Interrupts
43
1
6
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6 Pin Configuration and Functions
PFC Package
80 Pins (TQFP)
Top View
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
!ꢀ13
!ꢀ12
ꢀDbꢀ
ë33ꢀ
3
!ꢀ10
.t18
4
!ꢀ07
ë33ꢀLh
5
!ꢀ06
ꢀDbꢀ
6
!ꢀ04
C!Ü[Ç3
7
!ꢀ03
C!Ü[Ç2
8
ë33ꢀLh
{tL_aL{h
{tL_ah{L
{tL_ꢂ[Y
9
ꢀDbꢀ
10
11
12
13
14
15
16
17
18
19
20
/wꢁ{ꢁÇ
tía2
{tL_ꢂ{
tía3
Çꢂ!t0/Çꢂ!t1
Ça{
Çꢂ!t1/Çꢂ!t0
!ꢀꢂ_ꢁóÇ_ÇwLD
ta.Ü{_ꢂ[Y
ta.Ü{_ꢀ!Ç!
ta.Ü{_![ꢁwÇ
ta.Ü{_ꢂÇw[
L2ꢂ_ꢂ[Y
ÇꢀL/Çꢂ!t0/Çꢂ!t1
Çꢀh/Çꢂ!t0/Çꢂ!t1
ÇꢂY/wÇꢂ_Lb/óÇ![_ꢂ[Y_hÜÇ
C!Ü[Ç1
C!Ü[Ç0
ꢁóÇ_LbÇ
L2ꢂ_ꢀ!Ç!
ꢀDbꢀ
Additional pin functionality is specified in the following table.
Pin Functions
ALTERNATE ASSIGNMENT
CONFIGURABLE
AS A GPIO?
PIN
NAME
PRIMARY ASSIGNMENT
NO. 1
NO. 2
1
2
3
AD13
AD12
AD10
12-bit ADC, Ch 13, comparator E, I-share
12-bit ADC, Ch 12
DAC output
12-bit ADC, Ch 10
12-bit ADC, Ch 7, Connected to comparator F and reference to
comparator G
4
AD07
DAC output
5
6
7
8
AD06
12-bit ADC, Ch 6, Connected to comparator F
12-bit ADC, Ch 4, Connected to comparator D
12-bit ADC, Ch 3, Connected to comparator B and C
Digital I/O 3.3V core supply
DAC output
DAC output
AD04
AD03
V33DIO
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Pin Functions (continued)
ALTERNATE ASSIGNMENT
CONFIGURABLE
AS A GPIO?
PIN
NAME
PRIMARY ASSIGNMENT
NO. 1
NO. 2
9
DGND
RESET
PWM2
PWM3
TCAP1
Digital ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Device Reset Input, active low
General purpose PWM 2
General purpose PWM 3
Timer Capture Input
ADC conversion external trigger input
PMBUS Clock (Open Drain)
PMBus data (Open Drain)
PMBus Alert (Open Drain)
PMBus Control (Open Drain)
I2C Clock
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TCAP0
ADC_EXT_TRIG
PMBUS_CLK
PMBUS_DATA
PMBUS_ALERT
PMBUS_CTRL
I2C_CLK
I2C_DATA
DGND
I2C Data
Digital ground
DPWM0A
DPWM0B
DPWM1A
DPWM1B
DPWM2A
DPWM2B
DPWM3A
DPWM3B
DTC0
DPWM 0A output
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DPWM 0B output
DPWM 1A output
DPWM 1B output
DPWM 2A output
DPWM 2B output
DPWM 3A output
DPWM 3B output
Synchronous Rectifier dead time optimization control input 0
Synchronous Rectifier dead time optimization control input 1
General purpose IO C
General purpose IO D
DPWM Synchronize pin
SCI TX 0
GPIOA
GPIOB
DTC1
GPIOC
GPIOD
SYNC
SCI_TX0
SCI_RX0
SCI_TX1
SCI_RX1
PWM0
SCI RX 0
SCI TX 1
SCI RX 1
General purpose PWM 0
General purpose PWM 1
Digital ground
SYNC
PWM1
DGND
EXT_INT
FAULT0
External Interrupt
Yes
Yes
Yes
External fault input 0
External fault input 1
FAULT1
JTAG test clock. It is recommended that this pin is pulled LOW
on the target.
45
46
47
TCK(1)
TDO(1)
TDI(1)
RTC_IN
TCAP0
TCAP0
XTAL_CLK_OUT
TCAP1
Yes
Yes
Yes
JTAG test data output. It is recommended that this pin is pulled
HIGH on the target.
JTAG test data input. It is recommended that this pin is pulled
HIGH on the target.
TCAP1
JTAG test mode select. This pin must be pulled HIGH on the
target so that the effect of any spurious TCKs when there is no
connection is benign.
48
TMS(1)
Yes
49
50
51
52
53
54
55
56
57
58
59
TCAP0
Timer Capture Input
TCAP1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SPI_CS
SPI_CLK
SPI_MOSI
SPI_MISO
FAULT2
FAULT3
DGND
SPI Chip Select
SPI Clock
SPI Master Output Slave Input
SPI Master Input Slave Output
External fault input 2
External fault input 3
Digital ground
V33DIO
BP18
Digital I/O 3.3-V core supply
1.8V Bypass (For internal use only, do not load)
Digital 3.3-V core supply
V33D
(1) Fusion Digital Power based debug tools are recommended instead of JTAG.
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Pin Functions (continued)
ALTERNATE ASSIGNMENT
NO. 1 NO. 2
CONFIGURABLE
AS A GPIO?
PIN
NAME
PRIMARY ASSIGNMENT
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
DGND
Digital ground
XTAL_OUT
XTAL_IN
AGND
EAP0
EAN0
EAP1
EAN1
EAP2
EAN2
AGND
V33A
Crystal oscillator input
Crystal oscillator output
Analog ground
Channel #0, differential analog voltage, positive input
Channel #0, differential analog voltage, negative input
Channel #1, differential analog voltage, positive input
Channel #1, differential analog voltage, negative input
Channel #2, differential analog voltage, positive input
Channel #2, differential analog voltage, negative input
Analog ground
Analog 3.3V supply
AD00
12-bit ADC, Ch 0, Connected to current source
12-bit ADC, Ch 1, Connected to current source
12-bit ADC, Ch 2, Connected to comparator A, I-share
12-bit ADC, Ch 5
AD01
AD02
AD05
AD14
12-bit ADC, Ch 14
AD08
12-bit ADC, Ch 8
AD09
12-bit ADC, Ch 9
AD11
12-bit ADC, Ch 11
AGND
Analog ground
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
-0.3
MAX
3.8
V33D to DGND
V
V
V33DIO to DGND
3.8
V33A to AGND
3.8
V
Voltage
BP18 to DGND
2.5
V
Ground difference, |DGND – AGND|
Voltage applied to any pin, excluding AGND(2)
Junction Temperature, TJ
0.3
V
–0.3
–40
–55
3.8
V
125
150
°C
°C
Storage temperature range, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Referenced to DGND
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
3.0
3
TYP
3.3
3.3
3.3
1.8
MAX
3.6
3.6
3.6
2
UNIT
V
Digital power
V33D
V33DIO
V33A
Digital I/O power
Analog power
V
3
V
Digital power
BP18
1.6
–40
V
Junction temperature, TJ
125
°C
7.4 Thermal Information
TQFP (QFN)
80-PIN
47.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
7.8
24.4
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
24.0
RθJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, .
7.5 Electrical Characteristics
V33A = V33D = V33DIO = 3 V to 3.6 V; 1 μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITION
MIN
TYP
MAX
UNIT
Measured on V33A. The device is
powered up but all ADC12 and EADC
sampling is disabled
I33A(1)
7.5
mA
All GPIO and communication pins are
open
I33DIO(1)
I33D(1)
0.35
69
mA
mA
ROM program execution
The device is in ROM mode with all
DPWMs enabled and switching at 2
MHz. The DPWMs are all unloaded.
I33
90
100
mA
ERROR ADC INPUTS EAP, EAN
EAP – AGND(1)
–0.15
–0.256
–256
0.8
1.998
1.848
248
V
EAP – EAN(1)
Typical error range(1)
V
AFE = 0
AFE = 3
AFE = 2
AFE = 1
AFE = 0
mV
mV
mV
mV
mV
1
2
4
8
1.25
2.4
1.7
EAP – EAN Error voltage digital resolution
3.55
4.5
6.90
9.10
Input impedance(1)
(See Figure 11)
Input offset current(1)
(See Figure 11)
REA
AGND reference
0.5
–5
MΩ
μA
IOFFSET
EADC is in idle state
5
Input voltage = 0 V at AFE = 0
Input voltage = 0 V at AFE = 1
Input voltage = 0 V at AFE = 2
Input voltage = 0 V at AFE = 3
–20
–10
–6
20
10
6
mV
mV
mV
mV
EADC Offset
–4
4
(1) Characterized by design and not production tested.
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Electrical Characteristics (continued)
V33A = V33D = V33DIO = 3 V to 3.6 V; 1 μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
Sample Rate(1)
TEST CONDITION
MIN
TYP
MAX
UNIT
15.62
5
MHz
Analog Front End Amplifier Bandwidth(1)
Gain(1)
100
1
MHz
V/V
mV
See Figure 12
A0
Minimum output voltage
25
EADC DAC
DAC range
0
1.6
V
VREF DAC reference resolution
VREF DAC reference resolution(1)
10 bit, No dithering enabled
With 4 bit dithering enabled
Ensured INL
1.56
97.6
mV
μV
–1.5
–2.0
1.58
1.5
1
LSB
INL
Typical INL (TJ =25°C, V33A = V33D =
V33DIO = 3.3 V)
–0.4/+0.7
–0.4/+0.3
LSB
LSB
LSB
V
Guaranteed DNL
DNL
Typical DNL (TJ = 25°C, V33A = V33D =
V33DIO = 3.3 V)
DAC reference voltage
1.61
ADC12
IBIAS
Bias current for PMBus address pins
Measurement range for voltage monitoring
Internal ADC reference voltage
9.5
0
10.5
2.5
μA
V
2.475
2.500 2.525
–2.36
V
25°C to –40°C
25°C to 125°C
Change in Internal ADC reference from
25°C reference voltage(1)
mV
–5.45
ADC12 INL integral nonlinearity, end
point(1)
–3.9 –2.5/2.2
–2.4 –1.6/1.7
4.5
2.9
LSB
LSB
ADC12 INL integral nonlinearity, best fit
line(1)
ADC_SAMPLING_SEL = 0 or 7 for all
ADC12 data
ADC12 DNL differential nonlinearity(1)
ADC Zero Scale Error
ADC Full Scale Error
Input bias
–1.0 –0.6/+2.6
3.8
5
LSB
mV
mV
nA
–5
–30
30
2.5 V applied to pin
200
ADC_SAMPLING_SEL = 0
ADC_SAMPLING_SEL = 7
2
1
MΩ
MΩ
pF
Input leakage resistance(1)
Input Capacitance(1)
10
DIGITAL INPUTS/OUTPUTS(2)
DGND
+ 0.25
VOL
VOH
Low-level output voltage(3)(4)
IOH = 4 mA, V33DIO = 3 V
IOH = –4 mA, V33DIO = 3 V
V
V
V33DIO
(3)
High-level output voltage
– 0.6
VIH
VIL
IOH
IOL
High-level input voltage
Low-level input voltage
Output sinking current
Output sourcing current
V33DIO = 3 V
V33DIO = 3 V
2.1
V
V
1.1
4
mA
mA
–4
SYSTEM PERFORMANCE
Current share current source (See
Figure 34)
ISHARE
238
259
μA
(2) On the 40 pin package V33DIO is connected to V33D internally.
(3) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop
specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH
.
(4) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
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Electrical Characteristics (continued)
V33A = V33D = V33DIO = 3 V to 3.6 V; 1 μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
RSHARE Current share resistor (See Figure 34)
POWER ON RESET AND BROWN OUT (V33A PIN)
9.6
10.4
kΩ
VGH
VGL
Vres
Voltage good High
See Figure 9
2.302
2.248
0.8
2.53 2.836
2.48 2.781
V
V
V
Voltage good Low
Voltage at which IReset signal is valid(1)
Internal signal warning of brownout
conditions
Brownout
2.774
2.9 3.077
V
TEMPERATURE SENSOR
VTEMP
Voltage range of sensor(1)
Voltage resolution(1)
1.46
2.44
6.3
V
mV/ºC
ºC/LSB
ºC
Volts/°C
Temperature resolution(1)
Accuracy(1)(5)
Temperature range(1)
Current draw of sensor when active(1)
Ambient temperature
Degree C per bit
–40°C to 125°C
–40°C to 125°C
0.0969
±5
–10
–40
10
125
ºC
ITEMP
VAMB
30
μA
Trimmed 25°C reading
1.858
1.9 1.954
V
ANALOG COMPARATOR
DAC
Reference DAC Range(1)
0.019
2.478
2.5
V
Reference voltage
2.5 2.513
V
Bits
INL(1)
DNL(1)
7
bits
LSB
LSB
mV
mA
mV
mV
–0.5
0.06
–5.5
–0.5
–10
0.21
0.12
19.5
1
Offset
Reference DAC buffered output load(6)
Buffer offset (–0.5 mA)
Buffer offset (1.0 mA)
0.156 V < DAC < 2.363 V
0.059 V < DAC < 2.305 V
10
–10
10
RTC INTERFACE
fRTC RTC external input frequency
(7)
10
MHz
(5) Ambient temperature offset value from the TEMPSENCTRL register should be used to meet accuracy.
(6) Available from reference DACs for comparators D, E, F and G.
(7) Performance dependent on selected external components. The maximum frequency should be no more than 12 MHz.
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7.6 Timing Characteristics
V33A = V33D = V33DIO = 3.0 V to 3.6 V; 1 μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
EADC DAC
t
Settling Time(1)
From 10% to 90%
250
ns
ADC12
ADC single sample conversion time(1)
ADC single sample conversion time(1)
ADC_SAMPLING_SEL= 0
ADC_SAMPLING_SEL= 7
3.9
μs
μs
1..9
SYSTEM PERFORMANCE
Processor master clock (MCLK)
Digital filter delay(2)
31.25
MHz
MCLKs
MHz
tDelay
6
260
–40°C to +125°C
240
245
250
250
f(PCLK)
TWD
Internal oscillator frequency
Watchdog time out range(1)
–5°C to +85°C
255
MHz
Total time is: TWD x (WDCTRL.PERIOD+1)
12.02
13.08
13.65
ms
Time to disable DPWM output based on active
FAULT pin signal(1)
High level on FAULT pin
TJ = 25°C
80
1
ns
Flash Read
MCLKs
years
Retention period of flash content (data retention
and program)
100
Program time to erase one page or block in data
flash or program flash
20
ms
Program time to write one word in program flash
Program time to write one word in data flash
Sync-in/sync-out pulse width(1)
50
40
µs
µs
ns
Sync pin
256
POWER ON RESET AND BROWN OUT (V33A pin, See Figure 9)
Time delay after power is good or RESET*
(1)
tPOR
1
ms
ms
relinquished
IRESET goes from a low state to a high state.
This is approximately equivalent to toggling
the external reset pin from low to high state.
The time it takes from the device to exit a reset
state and begin executing the boot flash.(1)
tEXC1
tEXC2
tEXCT
0.5
The time it takes from the device to exit a reset
state and begin executing program flash bank 0
(32 kB).(1)
IRESET goes from a low state to a high state.
This is approximately equivalent to toggling
the external reset pin from low to high state.
3
6
ms
ms
The time it takes from the device to exit a reset
IRESET goes from a low state to a high state.
state and begin executing the total program flash This is approximately equivalent to toggling
(64 kB).(1)
the external reset pin from low to high state.
TEMPERATURE SENSOR(1)
(1)
tON
Turn on time / settling time of sensor
100
90
μs
ANALOG COMPARATOR
Time to disable DPWM output based on 0 V to
150
ns
2.5 V step input on the analog comparator.(1)
(1) Characterized by design and not production tested.
(2) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which
has no variation associated with it, must be accounted for when calculating the system dynamic response.
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7.7 PMBus/SMBus/I2C Timing
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in
Slave or Master mode are shown in PMBus/SMBus/I2C Timing, Figure 6, and Figure 7. The numbers in PMBus/SMBus/I2C
(1)
Timing shows that the device supports standard (100 kHz), fast (400 kHz), and fast-mode plus (1 MHz) speeds.
100 kHz Class
MIN MAX
400 kHz Class
1 MHz Class(2)
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
Typical values at TA = 25 °C and VCC = 3.3 V (unless otherwise noted)
SMBus/PMBus
operating
frequency
Slave mode, SMBC 50%
duty cycle
fSMB
10
10
100
100
10
10
400
400
10
10
1000
1000
kHz
kHz
µs
I2C operating
frequency
Slave mode, SCL 50% duty
cycle
fI2C
Bus free time
between start and
stop
t(BUF)
4.7
1.3
0.5
Hold time after
(repeated) start
t(HD:STA)
t(SU:STA)
4
0.6
0.6
0.26
0.26
µs
µs
Repeated start
setup time
4.7
t(SU:STO)
t(HD:DAT)
t(SU:DAT)
Stop setup time
Data hold time
Data setup time
4
0
0.6
0
0.26
0
µs
ns
ns
ms
µs
µs
Receive mode
250
25
4.7
4
100
25
50
t(TIMEOUT) Error signal/detect
35
35
25
35
t(LOW)
t(HIGH)
Clock low period
Clock high period
Cumulative clock
1.3
0.6
0.5
0.26
50
25
50
25
50
25
t(LOW:SEXT) low slave extend
time
ms
Rise time tr = (VILmax
0.15) to (VIHmin + 0.15)
–
20
+ 0.1 Cb
20
+ 0.1 Cb
20
+ 0.1 Cb
tr
Clock/data fall time
300
300
300
400
120
120
ns
ns
pF
Clock/data rise
time
Fall time tf = 0.9 VDD to
(VILmax – 0.15)
20
+ 0.1 Cb
20
+ 0.1 Cb
20
+ 0.1 Cb
tf
1000
Total capacitance
of one bus line
Cb
(1) Values dependent on bus pull up resistor selection and are not ATE tested.
(2) Characterized by design and not production tested.
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7.8 Typical Characteristics
ADC12 Measurement Temperature Sensor Voltage
2.1
2.6
2.4
2.2
2.0
1.8
1.6
1.4
2
1.9
1.8
1.7
1.6
−60 −40 −20
0
20 40 60 80 100 120 140 160
Temperature (°C)
−40
−20
0
20
40
60
Temperature (°C)
80
100
120
G006b
G005a
Figure 2. ADC12 Measurement Temperature Sensor Voltage
vs. Temperature
Figure 1. EADC LSB Size With 4x Gain (Mv) vs. Temperature
ADC12 2.5-V Reference
ADC12 Temperature Sensor Measurement Error
8
2.515
2.510
2.505
2.500
6
4
2
2.495
2.490
2.485
0
−2
−4
2.480
2.475
−40
−20
0
20
40
60
Temperature (°C)
80
100
120
−40
−20
0
20
40
60
80
100
120
G002b
Temperature (°C)
G003b
Figure 4. ADC12 Temperature Sensor Measurement Error
vs. Temperature
Figure 3. ADC12 2.5-V Reference vs. Temperature
2.08
2.06
3 σ
1 σ
AVG
-1 σ
-3 σ
2.04
2.02
2
1.98
1.96
1.94
1.92
-100
-50
0
50
100
150
200
Temperature (°C)
2 MHz Reference, Divided Down From 250 MHz
Figure 5. Oscillator Frequency vs. Temperature
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7.9 Timing Diagrams
Figure 6. IC/SMBUS/PMBUS Timing Diagram2
Figure 7. Bus Timing In Extended Mode
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8 Parametric Measurement Information
INL best fit
INL end point
Actual ADC transfer function
Best fit line
Line connecting actual zero-scale point and actual full-scale point
ADC Input Voltage
Figure 8. Best Fit INL and End Point INL
V33D
3.3 V
Brown Out
VGH
VGL
Vres
t
tPOR
tPOR
IReset
t
undefined
Figure 9. Power On Reset (POR) / Brown Out Reset (BOR)
VGH –
VGL –
This is the V33A threshold where the internal power is declared good. The UCD3138xA comes
out of reset when above this threshold.
This is the V33A threshold where the internal power is declared bad. The device goes into reset
when below this threshold.
Vres
–
This is the V33A threshold where the internal reset signal is no longer valid. Below this threshold
the device is in an indeterminate state.
IReset
–
This is the internal reset signal. When low, the device is held in reset. This is equivalent to holding
the reset pin on the IC low.
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tPOR
–
The time delay from when VGH is exceeded to when the device comes out of reset.
Brown
Out –
This is the V33A voltage threshold at which the device sets the brown out status bit. In addition an
interrupt can be triggered if enabled.
8.1 Typical Clock Gating Power Savings
6.00
5.31
5.00
4.00
3.00
2.50
2.00
1.00
0.52
DTC
0.35
0.36
Filter
0.33
SPI
0.21
0.02
0.20
I2C
0.12
0.07
RTC
0.05
GIO
0.00
DPWM
ADC12
Front-end Peak Current Timer
Control
Constant
Power/Constant
Current
Mode
Module
The CLKGATECTRL register provides control bits that can enable or disable the clock to several peripherals
such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.
By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in
order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current
consumption of the device. The power savings chart displays the power savings per module. For example there
are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved.
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9 Detailed Description
9.1 Overview
The UCD3138xA family is a digital power supply controller from Texas Instruments offering superior levels of
integration and performance in a single chip solution. The UCD3138128A, in comparison to Texas Instruments
UCD3138A digital power controller offers 128 kB of program Flash memory. The flexible nature of the
UCD3138xA family makes it suitable for a wide variety of power conversion applications.
In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance
of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and network
infrastructure space. The UCD3138xA family is a fully programmable solution offering customers complete
control of their application, along with ample ability to differentiate their solution. At the same time, TI is
committed to simplifying our customer’s development effort through offering best in class development tools,
including application firmware, Code Composer Studio™ software development environment, and TI’s Fusion
Power Development GUI which enables customers to configure and monitor key system parameters.
9.1.1 ARM Processor
The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit
microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where
two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The
Thumb instructions allow for higher code density equivalent to a 16-bit microprocessor, with the performance of
the 32-bit microprocessor.
The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocks in
the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter.
9.1.2 Memory
The UCD3138xA (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of
the memory modules. All of the memory module addresses are sequentially aligned along the same address
range. This applies to program flash, data flash, ROM and all other peripherals.
Within the UCD3138xA family architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware
startup routines for PMBus communication and non-volatile (FLASH) memory download. This boot ROM is
executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is present, the
ROM code branches to the main FLASH-program execution. If there is no valid program, the device waits for a
program download through the PMBus.
The UCD3138xA family also supports customization of the boot program by allowing an alternative boot routine
to be executed from program FLASH. This feature enables assignment of a unique address to each device;
therefore, enabling firmware reprogramming even when several devices are connected on the same
communication bus.
There are three separate flash memory areas present inside the device. There are 4-32 kB program flash blocks
and 1-2 kB data flash area. The 32 kB program areas are organized as 8 k x 32 bit memory blocks and are
intended to be for the firmware programs. The blocks are configured with page erase capability for erasing blocks
as small as 1 kB per page, or with a mass erase for erasing the entire 32 kB array. The flash endurance is
specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data flash array is
organized as a 512 x 32 bit memory (32 byte page size). The data flash is intended for firmware data value
storage and data logging. Thus, the Data flash is specified as a high endurance memory of 20 k cycles with
embedded error correction code (ECC).
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Overview (continued)
For run time data storage and scratchpad memory, a 8 kB RAM is available. The RAM is organized as a 2 k x 32
bit array.
The availability of 128 kB of program Flash memory in 4-32 kB banks, respectively enables the designers to
implement multiple images of firmware (e.g. one main image + one back-up image) in the device and the
flexibility to execute from either of the banks using appropriate algorithms. It also creates the unique opportunity
for the processor to load a new program and subsequently execute that program without interrupting power
delivery. This feature allows the end user to add new features to the power supply while eliminating any down-
time required to load the new program.
On the UCD3138128A, the boot ROM supports a dual image configuration where each image contains 64 kB. If
the first 64kB has an invalid program, the boot ROM will check for a valid program in the second 64kB and jump
there. The boot ROM also supports a configuration with a single program occupying the entire 128 kB.
For the UCD3138128A, on the fly updates are supported through boot ROM. Detailed procedures can be found
in SLUUB54
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9.2 Functional Block Diagram
Loop MUX
DPWM0A
DPWM0
EAP0
PID Based
Filter 0
Front End 0
EAN0
DPWM0B
DPWM1A
DPWM1
EAP1
PID Based
Filter 1
Front End 1
EAN1
DPWM1B
DPWM2A
DPWM2
PID Based
Filter 2
Front End 2
AFE
DPWM2B
DPWM3A
DPWM3B
SYNC
Constant Power Constant
Current
DPWM3
23-AFE
EAP2
EAN2
Front End Averaging
Digital Comparators
EADC
2AFE
X
Avg()
SAR/Prebias
Ramp
DAC0
Input Voltage Feed Forward
A0
Filter x
CPCC
ꢀ
Value
Dither
Abs()
Peak Current Mode
Control Comparator
PMBUS_ALERT
PMBUS_CTRL
PMBUS_DATA
PMBUS_CLK
PWM0
Advanced Power Control
Mode Switching, Burst Mode, IDE,
Synchronous Rectification soft on & off
PMBus
ADC_EXT
AD[14:0]
ADC12 Control
Sequencing, Averaging,
Digital Compare, Dual
Sample and hold
PWM1
ADC12
Timers
PWM2
AD00
AD01
4 œ 16 bit (PWM)
2 œ 24 bit (TCAP)
PWM3
Internal Temperature
Sensor
TCAP0
TCAP1
AD02
AD13
Current Share
Analog, Average, Master/Slave
AGND
Oscillator
SCI_TX1
SCI_RX0
SCI_TX1
SCI_RX1
UART0
UART1
ARM7TDMI-S
32 bit, 31.25 MHz
Analog
Comparators
AD02
AD03
A
B
Memory
DFLASH 2 kB
RAM 8 kB
EXT_INT
FAULT[0..3]
GPIOD
GPIO
Control
ROM 8 kB
GPIOC
C
PFLASH 128 kB
Bank 0
32 kB
Bank 1
32 kB
AD04
AD13
AD06
AD07
Fault MUX &
Control
DTC0/GPIOA
D
DTC
V33D
V33DIO
BP18
DTC1/GPIOB
/RESET
Cycle by Cycle
Current Limit
Bank 2
32 kB
Bank 3
32 kB
E
Power and
Digital
Comparators
TCK
F
1.8 V Voltage
Regulator
DGND
V33A
Power On Reset
JTAG
TDI
G
TMS
Brown Out Detection
AGND
TDO
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CS
I2C_DATA
I2C_CLK
Real Time
Clock
XTAL_IN
SPI
I2C
Crystal
Interface
XTAL_OUT
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9.3 Feature Description
9.3.1 System Module
The System Module contains the interface logic and configuration registers to control and configure all the
memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address decoder,
memory management controller, system management unit, central interrupt unit, and clock control unit.
9.3.1.1 Address Decoder (DEC)
The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map
addresses are selectable through configurable register settings. These memory selects can be configured from 1
kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is then
configured by the ROM code to the application setup. During access to the DEC registers, a wait state is
asserted to the CPU. DEC registers are only writable in the ARM privilege mode for user mode protection.
9.3.1.2 Memory Management Controller (MMC)
The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and
write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of address space
decoding.
9.3.1.3 System Management (SYS)
The SYS unit contains the software access protection by configuring user privilege levels to memory or
peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or
access conditions. A clock control setup for the processor clock (MCLK) speed, is also available.
9.3.1.4 Central Interrupt Module (CIM)
The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports
two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of
interrupts by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index
value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector
address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31
has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first
action in the interrupt service routine. The request channels are maskable, allowing individual channels to be
selectively disabled or enabled.
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Feature Description (continued)
Table 3. Interrupt Priority Table
MODULE COMPONENT OR
REGISTER
NAME
DESCRIPTION
PRIORITY
BRN_OUT_INT
EXT_INT
Brownout
Brownout interrupt
0 (Lowest)
1
External Interrupts
Watchdog Control
Interrupt on external input pin
WDRST_INT
Interrupt from watchdog exceeded (reset)
Wake-up interrupt when watchdog equals half of set watch
time
2
WDWAKE_INT
Watchdog Control
3
SCI_ERR_INT
SCI_RX_0_INT
SCI_TX_0_INT
SCI_RX_1_INT
SCI_TX_1_INT
PMBUS_INT
UART or SCI Control
UART or SCI Control
UART or SCI Control
UART or SCI Control
UART or SCI Control
PMBus
UART or SCI error Interrupt. Frame, parity or overrun
UART0 RX buffer has a byte
UART0 TX buffer empty
4
5
6
UART1 RX buffer has a byte
UART1 TX buffer empty
7
8
PMBus related interrupt
9
DIG_COMP_SPI_I2C_INT 12-bit ADC Control, SPI, I2C
Digital comparator, SPI and I2C interrupt
10
“Prebias complete”, “Ramp Delay Complete”, “Ramp
Complete”, “Load Step Detected”,
“Over-Voltage Detected”, “EADC saturated”
FE0_INT
FE1_INT
FE2_INT
Front End 0
Front End 1
Front End 2
11
12
13
“Prebias complete”, “Ramp Delay Complete”, “Ramp
Complete”, “Load Step Detected”,
“Over-Voltage Detected”, “EADC saturated”
“Prebias complete”, “Ramp Delay Complete”, “Ramp
Complete”, “Load Step Detected”,
“Over-Voltage Detected”, “EADC saturated”
PWM3_INT
16-bit Timer PWM 3
16-bit Timer PWM 2
16-bit Timer PWM 1
16-bit timer PWM 0
24-bit Timer Control
24 bit Timer Control or DTC
24-bit Timer Control
24-bit Timer Control
24-bit Timer Control
16-bit Timer PWM3 counter overflow or compare interrupt
16-bit Timer PWM2 counter Overflow or compare interrupt
16-bit Timer PWM1 counter overflow or compare interrupt
16-bit Timer PWM0 counter overflow or compare interrupt
24-bit Timer counter overflow interrupt
14
15
16
17
18
19
20
21
22
PWM2_INT
PWM1_INT
PWM0_INT
OVF24_INT
CAPTURE1_DTC_INT
COMP_1_INT
CAPTURE_0_INT
COMP_0_INT
24 bit Timer capture 1 interrupt or DTC fault interrupt
24-bit Timer compare 1 interrupt
24-bit Timer capture 0 interrupt
24-bit Timer compare 0 interrupt
Constant Power Constant Current Mode switched in CPCC module Flag needs to be read for
CPCC_RTC_INT
ADC_CONV_INT
23
24
or Real Time Clock Output
details. RTC timer output generates an interrupt.
12-bit ADC Control
ADC end of conversion interrupt
Analog comparator interrupts, Over-Voltage detection,
Under-Voltage detection,
FAULT_INT
Fault Mux Interrupt
25
LLM load step detection
DPWM3
DPWM2
DPWM3
DPWM2
Same as DPWM1
Same as DPWM1
26
27
1) Every (1-256) switching cycles
2) Fault Detection
DPWM1
DPWM1
28
3) Mode switching
DPWM0
DPWM0
Same as DPWM1
29
30
EXT_FAULT_INT
SYS_SSI_INT
External Faults
System Software
Fault pin interrupt
System software interrupt
31 (highest)
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9.3.2 Peripherals
9.3.2.1 Digital Power Peripherals (DPPs)
At the core of the UCD3138xA controller are three DDPs. Each DPP can be configured to drive from one to eight
DPWM outputs. Each DPP consists of:
•
•
•
Differential input error ADC (EADC) with sophisticated controls
Hardware accelerated digital 2-pole/2-zero PID based compensator
Digital PWM module with support for a variety of topologies
These can be connected in many different combinations, with multiple filters and DPWMs. They are capable of
supporting functions like input voltage feed forward, current mode control, and constant current/constant power,
and so on. The simplest configuration is shown in Figure 10.
EAP
DPWMA
Digital
PWM
Error ADC
(Front End)
Filter
DPWMB
EAN
Figure 10. Multiple Filters and DPWMs
9.3.2.1.1 Front End
Figure 11 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable
gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging filters and a precision
high resolution set point DAC reference. The programmable gain amplifier in concert with the EADC and the
adjustable digital gain on the EADC output work together to provide 9 bits of range with 6 bits of resolution on the
EADC output. The output of the Front End module is a 9-bit sign extended result with a gain of 1 LSB / mV.
Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or 8 LSBs. In
addition each EADC has the ability to automatically select the AFE value such that the minimum resolution is
maintained that still allows the voltage to fit within the range of the measurement. The EADC control logic
receives the sample request from the DPWM module for initiating an EADC conversion. EADC control circuitry
captures the EADC-9-bit-code and strobes the digital compensator for processing of the representative error. The
set point DAC has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This
DAC can be driven from a variety of sources to facilitate things like soft start, nested loops, and so on. Some
additional features include the ability to change the polarity of the error measurement and an absolute value
mode which automatically adds the DAC value to the error.
It is possible to operate the controller in a peak current mode control configuration; an EADC is recommended for
implementing peak current mode control. In this mode, topologies like a phase shifted full bridge converter can
be controlled to maintain transformer flux balance. The internal DAC can be ramped at a synchronously
controlled slew rate to achieve a programmable slope compensation. This eliminates the sub-harmonic oscillation
as well as improves input voltage feed-forward performance. A0 is a unity gain buffer used to isolate the peak
current mode comparator. The offset of this buffer is specified in Electrical Characteristics.
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EAP
Front End Differential
Amplifier
REA
IOFFSET
AGND
EAN
REA
IOFFSET
AGND
Figure 11. Input Stage of EADC Module
AFE_GAIN
3-AFE_GAIN
2
6 bit ADC
8 mV/LSB
EAP0
EAN0
Signed 9 bit result
(error) 1 mV /LSB
AFE_GAIN
EADC
X
Averaging
2
SAR/Prebias
Ramp
Filter x
CPCC
DAC0
A
0
10 bit DAC
1.5625 mV/LSB
Value
S
Dither
4 bit dithering gives 14 bits of effective resolution
97.65625 µV/LSB effective resolution
Absolute Value
Calculation
10 bit result
1.5625 mV/LSB
Peak Current
Detected
Peak Current Mode
Comparator
Figure 12. Front End Module
(Front End 2 Recommended for Peak Current Mode Control)
9.3.2.1.2 DPWM Module
The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple
DPWM modules within the UCD3138xA system can be configured to support all key power topologies. DPWM
modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It
can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to
control power supply outputs with multiphase or interleaved DPWM configurations.
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The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width
modulated outputs for the power stage switches. The compensator calculates the duty ratio as a 24-bit number in
Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This
duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON
time is 250 psec.
Each DPWM module can be synchronized to another module or to an external sync signal. An input SYNC signal
causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM modules—occur
when the ramp timer crosses a programmed threshold. In this way the phase of the DPWM outputs for multiple
power stages can be tightly controlled.
The DPWM logic is probably the most complex of the Digital Peripherals. It receives the output of the
compensator and converts it into the correct DPWM output for several power supply topologies. It provides for
programmable dead times and cycle adjustments for current balancing between phases. It controls the triggering
of the EADC. It can synchronize to other DPWMs or to external sources. It can provide synchronization
information to other DPWMs or to external recipients. In addition, it interfaces to several fault handling circuits.
Some of the control for these fault handling circuits is in the DPWM registers. Fault handling is covered in the
Fault Mux section.
Each DPWM module supports the following features:
•
•
•
Dedicated 14 bit time-base with period and frequency control
Shadow period register for end of period updates.
Quad-event control registers (A and B, rising and falling) (Events 1 to 4)
–
Used for on/off DPWM duty ratio updates.
•
•
•
•
•
•
•
•
Phase control relative to other DPWM modules
Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
Support for two independent edge placement DPWM outputs (same frequency or period setting)
Dead-time between DPWM A and B outputs
High Resolution capabilities – 250 ps
Pulse cycle adjustment of up to ±8.192 µs (32768 × 250 ps)
Active high/ active low output polarity selection
Provides events to trigger both CPU interrupts and start of ADC12 conversions.
The DPWM is a complex logic system which is highly configurable to support different power supply topologies.
For details about the DPWM operation modes, refer to Device Functional Modes.
9.3.2.1.3 DPWM Events
Each DPWM can control the following timing events:
1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in relationship
to the DPWM period. The programmed value set in the register should be one fourth of the value calculated
based on the DPWM clock. The clock controlling the circuitry runs at one fourth of the DPWM clock (PCLK =
250 MHz max). When this sample trigger count is equal to the DPWM Counter, it initiates a front end
calculation by triggering the EADC, resulting in a CLA calculation, and a DPWM update. Oversampling can
be set for 2, 4, or 8 times the sampling rate.
2. Phase Trigger Count – count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
3. Period – low resolution switching period count. (count of PCLK cycles)
4. Event 1 – count offset for rising DPWM A event. (PCLK cycles)
5. Event 2 – DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are for
high resolution control. Upper 14 bits are the number of PCLK cycle counts.
6. Event 3 – DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution control.
Upper 14 bits are the number of PCLK cycle counts.
7. Event 4 – DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution control.
Upper 14 bits are the number of PCLK cycle counts.
8. Cycle Adjust – Constant offset for Event 2 and Event 4 adjustments.
Basic comparisons between the programmed registers and the DPWM counter can create the desired edge
placements in the DPWM. High resolution edge capability is available on Events 2, 3, and 4.
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Figure 13 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own
registers, not by the filter output. In other words, the power supply control loop is not closed.
The Sample Trigger signals are used to trigger the front end to sample input signals. The Blanking signals are
used to blank fault measurements during noisy events, such as FET turn on and turn off.
Start of Period
Period
Start of Period
Period Counter
DPWM Output A
Event 1
Event 2 (High Resolution)
Cycle Adjust A (High Resolution)
Sample Trigger 1
To Other
Modules
Blanking A Begin
Blanking A End
DPWM Output B
Event 3 (High Resolution)
Event 4 (High Resolution)
Cycle Adjust B (High Resolution)
Sample Trigger 2
Blanking B Begin
To Other
Modules
Blanking B End
Phase Trigger
Events which change with DPWM mode:
•
•
•
•
•
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 2 + Cycle Adjust A
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 4 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
•
•
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 13. Multi Mode Open Loop
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9.3.2.1.4 High Resolution DPWM
Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM
edges, the UCD3138xA DPWM can generate waveforms with resolutions as small as 250 ps. This is 16× the
resolution of the clock driving the DPWM module.
This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz. The high
resolution section of DPWM can be enabled or disabled, and the resolution can be defined in several steps
between 4 ns to 250 ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN and HIRES_SCALE
inside the DPWM Control register 1. See the Power Peripherals programmer’s manual for details.
9.3.2.1.5 Oversampling
The DPWM module has the capability to trigger an oversampling event by initiating the EADC to sample the error
voltage. The default 00 configuration has the DPWM trigger the EADC once based on the sample trigger register
value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period. Thus the
time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The 01 setting
triggers 2X oversampling, the 10 setting triggers 4X over sampling, and the 11 triggers oversampling at 8X.
9.3.2.1.6 DPWM Interrupt Generation
The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the
period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt
service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for sequence
synchronization. Table 4 outlines the divide ratios that can be programmed.
9.3.2.1.7 DPWM Interrupt Scaling/Range
Table 4. DPWM Interrupt Divide Ratio
Switching Period
Frames (Assume 1-MHz
Loop)
Interrupt Divide Interrupt Divide Interrupt Divide
Number of 32-MHz
Processor Cycles
Setting
Count
Count (hex)
1
2
0
1
00
01
03
07
0F
1F
2F
3F
4F
5F
7F
9F
BF
DF
FF
1
2
32
64
3
3
4
128
4
7
8
256
5
15
31
47
63
79
95
127
159
191
223
255
16
32
48
64
80
96
128
160
192
224
256
512
6
1024
1536
2048
2560
3072
4096
5120
6144
7168
8192
7
8
9
10
11
12
13
14
15
9.3.2.1.8 Synchronous Rectifier Dead Time Optimization Peripheral
The UCD3138xA has an advanced dead time control interface where it can accept UCD7138 output signals and
optimize SR gate driver signals accordingly. The UCD7138 low-side MOSFET driver is a high-performance driver
for secondary-side synchronous rectification (SR) with body diode conduction sensing. The device is suitable for
high power high efficiency isolated converter applications where dead-time optimization is desired. The UCD7138
gate driver is a companion device to UCD3138xA highly integrated digital controller for isolated power.
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UCD3138xA
Rising edge
optimization
control
UCD7138
CTRL
IN
SR1 DPWM
SR2 DPWM
6
4
5
1
2
3
DPWM
module
Thermal Pad
(GND)
DTC
VCC
OUT
VD
SR1
Dead Time
Control
Computation
Engine
Rising edge
optimization
control
UCD7138
IN
CTRL
OUT
6
4
5
1
2
3
DTC0
DTC1
Thermal Pad
(GND)
SR2
DTC
VCC
Decoder
VD
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Figure 14. Synchronous Rectifier Peripheral use with Synchronous Rectifier Driver
DTC0 and DTC1 are received body diode conduction inputs from UCD7138. SR0_DPWM and SR1_DPWM are
the DPWM waveforms for the SRs. The red and green edges are moving edges controlled by both the filter
output and the DTC interface. In each cycle, right after the falling edge of the SR DPWM waveform, a body diode
conduction time detection window is generated. The detection window is defined by both DETECT_BLANK and
DETECT_LEN registers. During this detection window, a 4-ns timer capture counts how long the body diode
conducts. Then the DPWM turn off edge of the next cycle is adjusted accordingly.
{w0_ 5tía
!5WÜ{Ç
{w1_ 5tía
!5WÜ{Ç
59Ç9/Ç
59Ç9/Ç
5Ç/0
5Ç/1
59Ç9/Ç
59Ç9/Ç
59Ç9/Ç_ .[!bY
59Ç9/Ç_[9b
Figure 15. Timing Diagram of the DTC Interface
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Figure 16 shows how the turn off edge is adjusted based on the DTC measurement of the previous cycle. The
A_ADJ and B_ADJ registers in DTCMONITOR are signed accumulators; default value is 0.
!_/bÇ or ._/bÇ vꢀlue
127
Lf in aꢀnuꢀl /onꢁrol aode
P = aꢀnuꢀl /onꢁrol regisꢁer vꢀlue
P = 1
9lse if !_/bÇ or ._/bÇ < C[Ç_ÇIw9{I
P = C[Ç_{Ç9t
Ç!wD9Ç_hCC{9Ç
9lse if !_/bÇ or ._/bÇ < Ç!wD9Ç_[hí
P = 0
Ç!wD9Ç_[hí
P = - 1
9lse if !_/bÇ or ._/bÇ > Ç!wD9Ç_[hí + Ç!wD9Ç_hCC{9Ç
P = 1
P = - 1
9lse
P = 0
C[Ç_ÇIw9{I
P = C[Ç_{Ç9t
Figure 16. DTC Interface Principle
Based on the DTC measured, in the next cycle:
•
•
A_ADJ = A_ADJ + A_∆
A_ADJ = A_ADJ + B_∆
In each cycle, the A_ADJ and B_ADJ accumulator values are dynamically adjust the dead time. The ∆ value
changes after the measured body diode conduction time. A_ADJ and B_ADJ have been measured and
compared to the threshold values in automatic control mode. A_ADJ and B_ADJ can be controlled by firmware
while in manual control mode.
Other figures of this peripheral include negative current fault protection, consecutive fault counter, DTC input
multiplexor, etc. For details, refer to the programmer's manual.
9.3.3 Automatic Mode Switching
Automatic Mode switching enables the DPWM module to switch between modes automatically, with no firmware
intervention. This is useful to increase efficiency and power range. The following paragraphs describe phase-
shifted full bridge and LLC examples.
9.3.3.1 Phase Shifted Full Bridge Example
In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather than
phase shift, at light load. This is shown below:
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DPWM3A
(QB1)
DPWM3B
(QT1)
DPWM2A
(QT2)
DPWM2B
(QB2)
VTrans
DPWM1B
(QSYN1,3)
DPWM0B
(QSYN2,4)
IPRI
Figure 17. Phase-Shifted Full Bridge Waveforms
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L1
T1
Q7
+12V
Q6
C1
RL
VBUS
I_pri
PRIM
CURRENT
ORING
CTL
Q5
T2
VOUT
C2
R2
D1
T1
QT2
QB2
QT1
VA
Lr
Current
Sensing
QB1
D2
DPWM0B
DPWM1B
Vref
DPWM0
Duty for mode
switching
Vout
Iout
CPCC
<
EADC0
EADC1
CLA0
DPWM1
DPWM2
CLA1
DPWM2A
DPWM2B
Load Current
DPWM3A
DPWM3B
I_pri
EADC2
DPWM3
PCM
AD00
AD01
ISOLATED
GATE Transformer
ACFAIL_IN
FAULT 0
FAULT 1
FAULT 2
SYNCHRONOUS
GATE DRIVE
ACFAIL_OUT
FAILURE
AD02/CMP0
AD03/CMP1/CMP2
AD04/CMP3
AD05/CMP4
AD06/CMP5
AD07/CMP6
AD08
I_SHARE
Vout
FAULT
GPIO1
GPIO2
GPIO3
ORING_CRTL
ON/OFF
Iout
I_pri
CBC
temp
P_GOOD
Vin
VA
WD
ARM7
AD09
PMBus
UART0
RST
OSC
Primary
UART1
Memory
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Figure 18. Secondary-Referenced Phase-Shifted Full Bridge Control With Synchronous Rectification
9.3.3.2 LLC Example
In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As
the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET
drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle-by-
cycle current limiting. This protection function operates by a comparator monitoring the maximum current during
the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the pulse is
immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also possible
to force DPWMB to match the truncated pulse width of DPWMA. Here are the waveforms for the LLC:
PWM
Mode
LLC Mode
fr
fs= fr_max
fs< fr
fs> fr
Q1T
Q1B
QSR1
QSR2
Tr= 1/fr
Tr= 1/fr
ISEC(t)
Figure 19. LLC Waveforms
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VBUS
Q1T
ILR(t)
Transformer
QSR2
LRES
LK
NS
NS
Driver
DPWM1B
ISEC(t)
Oring Circuitry
RLRES
Q1B
ILM(t)
LM
VOUT
NP
RF1
RF2
AD03
EAP0
COUT1
COUT2
VOUT(t)
VBUS
ESR1
ESR2
CF
QSR1
EAN0
AD04
CRES
RS
Driver
DPWM1A
CS
CRES
VCR(t)
RS1
RS2
ADC13
EAP1
Driver
Driver
DPWM0B
DPWM0A
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Figure 20. Secondary-Referenced Half-Bridge Resonant LLC Control With Synchronous Rectification
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9.3.3.3 Mechanism For Automatic Mode Switching
The UCD3138xA allows the customer to enable up to two distinct levels of automatic mode switching. These
different modes are used to enhance light load operation, short circuit operation and soft start. Many of the
configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching, some
of these parameters are duplicated in the Auto Config Mid and Auto Config High registers.
If automatic mode switching is enabled, the filter duty signal is used to select which of these three registers is
used. There are 4 registers which are used to select the points at which the mode switching takes place. They
are used as shown below.
Automatic Mode Switching
With Hysteresis
Filter Duty
Full Range
Auto Config High
High – Upper Threshold
High – Lower Threshold
Auto Config Mid
Low – Upper Threshold
Low – Lower Threshold
Control
Register 1
0
Figure 21. Automatic Mode Switching
As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config
Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Auto
Config Mid until the Low Lower Threshold is passed. This prevents oscillation between modes if the filter duty is
close to a mode switching point.
9.3.4 DPWMC, Edge Generation, Intramux
The UCD3138xA has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB
waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux.
DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the Blanking A
end time.
The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and uses
them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next DPWM. Each
edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it.
The options are:
0 = DPWM(n) A Rising edge
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1 = DPWM(n) A Falling edge
2 = DPWM(n) B Rising edge
3 = DPWM(n) B Falling edge
4 = DPWM(n+1) A Rising edge
5 = DPWM(n+1) A Falling edge
6 = DPWM(n+1) B Rising edge
7 = DPWM(n+1) B Falling edge
Where “n" is the numerical index of the DPWM module of interest. For example n=1 refers to DPWM1.
The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit.
The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The IntraMux
takes signals from multiple DPWMs and from the Edge Gen and combines them logically to generate DPWMA
and DPWMB signals This is useful for topologies like phase-shifted full bridge, especially when they are
controlled with automatic mode switching. Of course, it can all be disabled, and DPWMA and DPWMB will be
driven as described in the sections above. If the Intra Mux is enabled, high resolution must be disabled, and
DPWM edge resolution goes down to 4 ns.
Here is a drawing of the Edge Gen/Intra Mux:
A/B/C (N)
A/B/C (N+1)
INTRAMUX
C (N+2)
C (N+3)
PWM A
PWM B
EDGE GEN
A(N)
B(N)
EGEN A
EGEN B
A(N+1)
B(N+1)
B SELECT
A SELECT
A ON SELECT
A OFF SELECT
B ON SELECT
B OFF SELECT
Figure 22. Edge Generation / IntraMux
Here is a list of the IntraMux modes for DPWMA:
0 = DPWMA(n) pass through (default)
1 = Edge-gen output, DPWMA(n)
2 = DPWNC(n)
3 = DPWMB(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
and for DPWMB:
0 = DPWMB(n) pass through (default)
1 = Edge-gen output, DPWMB(n)
2 = DPWNC(n)
3 = DPWMA(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
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6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:
DPWM(n)
DPWM3
DPWM0
DPWM1
DPWM2
DPWM(n+1)
DPWM(n+2)
DPWM(n+3)
9.3.5 Synchronous Rectifier MOSFET Ramp And IDE Calculation
The device has built in logic for optimizing the performance of the synchronous rectifier MOSFETs. This comes in
two forms:
•
•
Synchronous Rectifier MOSFET ramp for softly turning on and off the MOSFETs
Ideal Diode Emulation (IDE) calculation
When starting up a power supply, It is not uncommon for there to already be a voltage present on the output –
this is called pre-bias. It can be very difficult to calculate the ideal synchronous rectifier MOSFET on-time for this
case. If it is not calculated correctly, it may pull down the pre-bias voltage, causing the power supply to sink
current. To avoid this, the synchronous rectifier MOSFETs are not turned on until after the power supply has
ramped up to the nominal output voltage. The synchronous rectifier MOSFETs are then turned on slowly in order
to avoid an output voltage glitch. The synchronous rectifier MOSFET ramp logic can be used to turn them on at a
rate well below the bandwidth of the filter.
In discontinuous mode, the ideal on-time for the synchronous rectifier MOSFETs is a function of Vin, Vout, and the
primary side duty cycle (D). The IDE logic in the UCD3138xA takes Vin and Vout data from the firmware and
combines it with D data from the filter hardware. It uses this information to calculate the ideal on-time for the
synchronous rectifier MOSFETs.
9.3.6 Filter
The UCD3138xA filter is a PID filter with many enhancements for power supply control. Some of its features
include:
•
•
•
•
•
•
•
•
•
•
•
Traditional PID Architecture
Programmable non-linear limits for automated modification of filter coefficients based on received EADC error
Multiple coefficient sets fully configurable by firmware
Full 24-bit precision throughout filter calculations
Programmable clamps on integrator branch and filter output
Ability to load values into internal filter registers while system is running
Ability to stall calculations on any of the individual filter branches
Ability to turn off calculations on any of the individual filter branches
Duty cycle, resonant period, or phase shift generation based on filter output.
Flux balancing
Voltage feed forward
Here is the first section of the Filter :
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Limit Comparator
Limit 6
Limit 5
…..
PID Filter Branch Stages
Limit 0
Coefficient
select
EADC_DATA
Xn
16
24
9
24
X
P
9
9
24
16
24
24
9
9
24
24
9
+
+
X
I
24
24
Ki Low
9
24
24
X
32
9
Round
24
16
24
X –X
9
n
n-1
9
24
24
-
X
Clamp
+
D
Figure 23. First Section of the Filter
The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note that the D
branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D alpha pole.
The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected depending
on the magnitude of the error input Xn. This can be used to increase the filter gain for higher errors to improve
transient response.
Here is the output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional bits).
Filter Yn
Clamp High
Yn Scale
Shifter
24
24
24
P
I
24
24
24
S0.23
26
Filter Yn
Saturate
Yn
Clamp
+
D
S2.23
S0.23
S0.23
Filter Yn
Clamp Low
All are S0.23
Figure 24. Output Section of the Filter
This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping.
There is a final section for the filter, which permits its output to be matched to the DPWM:
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Filter Output
Clamp High
Round to
18 bits,
Clamp to
Positive
Truncate
low 4 bits
Filter Period
Bits [17:4]
Filter YN
38
18
14
X
Round to
18 bits,
S14.23
24
S0.23
14.4
14.0
Filter YN (Duty %)
18
Filter Duty
14.4
38
18
Clamp
X
Clamp to
Positive
24
S0.23
S14.23
14.4
KCompx 14.0
14
14.0
14.0
KCompx
DPWMx Period
Loop_VFF
14
DPWMx Period 14.0
Filter Output
Clamp Low
14.0
14.0
14.0
14.0
PERIOD_MULT_SEL
Resonant Duty
OUTPUT_MULT_SEL
Figure 25. Final Section for the Filter
This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period, to
provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant mode,
the filter can be used to generate both period and duty cycle.
9.3.6.1 Loop Multiplexer
The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end, and
DPWM can be combined in a variety of configurations.
It also controls the following connections:
•
•
•
•
•
DPWM to Front End
Front End DAC control from Filters or Constant Current/Constant Power Module
Filter Special Coefficients and Feed Forward
DPWM synchronization
Filter to DPWM
The following control modules are configured in the Loop Mux:
•
•
•
•
•
Constant Power/Constant Current
Cycle Adjustment (Current and flux balancing)
Global Period
Light Load (Burst Mode)
Analog Peak Current Mode
9.3.6.2 Fault Multiplexer
In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the
UCD3138xA provides an extensive array of multiplexers that are united under the name Fault Mux module.
The Fault Mux Module supports the following types of mapping between all the sources of fault and all the
different fault response mechanisms inside each DPWM module.
•
Many fault sources may be mapped to a single fault response mechanism. For instance an analog
comparator in charge of over voltage protection, a digital comparator in charge of over current protection and
an external digital fault pin can be all mapped to a Fault-A signal connected to a single FAULT MODULE and
shut down DPWM1-A.
•
•
A single fault source can be mapped to many fault response mechanisms inside many DPWM modules. For
instance an analog comparator in charge of over current protection can be mapped to DPWM-0 through
DPWM-3 by way of several fault modules.
Many fault sources can be mapped to many fault modules inside many DPWM modules.
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CBC_PWM_AB_EN
FAULT MUX
DPWM
Bit20 in DPWMCTRL0
CYCLE BY CYCLE
ANALOG PCM
FAULT- CBC
AB FLAG
FAULT MODULE
DISABLE PWM A AND B
CBC_FAULT_EN
Bit30 in DPWMFLTCTRL
FAULT- AB
FAULT-A
FAULT-B
AB FLAG
FAULT MODULE
DISABLE PWM A AND B
DCOMP– 4X
EXT GPIO– 4X
ACOMP – 7X
A FLAG
FAULT MODULE
DISABLE PWM A ONLY
B FLAG
FAULT MODULE
DISABLE PWM B ONLY
ALL_FAULT_EN
DPWM_EN
Bit 31 in DPWMFLTCTRL
Bit0 in DPWMCTRL0
Figure 26. Fault Mux Module
The Fault Mux Module provides a multitude of fault protection functions within the UCD3138xA high-speed loop
(Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly configurable
fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of
the fault inputs to the DPWM modules can be configured to one or any combination of the fault events provided
in the Fault Mux Module.
Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB fault
module, A fault module and B fault module.
The internal circuitry in all the four fault modules is identical, and the difference between the modules is limited to
the way the modules are attached to the DPWMs.
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FAULT FLAG
FAULT IN
FAULT MODULE
Figure 27. Fault Module
All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of the
fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle fault count
exceeds max_count.
Once the fault flag is set, DPWMs need to be disabled by DPWM_EN going low in order to clear the fault flags.
Please note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault Modules)
will be cleared simultaneously.
All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module cannot be
enabled/ disabled separately.
FAULT - CBC
CLIM
CYCLE BY CYCLE
Figure 28. Cycle-By-Cycle Block
Unlike Fault Modules, only one Cycle by Cycle block is available in each DPWM module.
The Cycle by Cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to signals
arriving from the Analog Peak current mode (PCM) module.
The Fault Mux Module supports the following basic functions:
•
•
•
•
4 digital comparators with programmable thresholds and fault generation
Configuration for 7 high speed analog comparators with programmable thresholds and fault generation
External GPIO detection control with programmable fault generation
Configurable DPWM fault generation for DPWM Current Limit Fault, DPWM Over-Voltage Detection Fault,
DPWM A External Fault, DPWM B External Fault and DPWM IDE Flag
•
•
Clock Failure Detection for High and Low Frequency Oscillator blocks and XTAL failure
Discontinuous Conduction Mode Detection
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HFO/LFO
Fail Detect
DCM Detection
Analog Comparator 0
Control
Analog
Comparator 0
Digital Comparator 0
Control
Front End
Control 0
Analog Comparator 1
Control
Analog
Comparator 1
Digital Comparator 1
Control
Front End
Control 1
Analog Comparator 2
Control
Analog
Comparator 2
Digital Comparator 2
Control
Analog Comparator 3
Control
Analog
Comparator 3
Front End
Control 2
Digital Comparator 3
Control
Analog Comparator 4
Control
Analog
Comparator 4
fault[2:0]
External GPIO
Detection
Analog Comparator 5
Control
Analog
Comparator 5
DPWM 0
Fault Control
DPWM 1
Fault Control
DPWM 2
Fault Control
DPWM 3
Fault Control
Analog Comparator 6
Control
Analog
Comparator 6
DPWM 0
DPWM 1
DPWM 2
DPWM 3
Analog Comparator
Automated Ramp
Figure 29. Fault Mux Block Diagram
9.3.7 Communication Ports
9.3.7.1 SCI (UART) Serial Communication Interface
maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous
A
Receiver/Transmitter (UART) interfaces are included within the device for asynchronous start-stop serial data
communication (see the pin out sections for details). Each interface has a 24 bit pre-scaler for supporting
programmable baud rates, a programmable data word and stop bit options. Half or full duplex operation is
configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX
and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used.
9.3.7.2 PMBUS/I2C
The UCD3138xA has two independent interfaces which both support PMBus and I2C in master and slave modes.
Only one of the interfaces has control of the address pin current sources as well as support for the optional
Control and Alert lines described in the PMBus specification. Other than these differences, the interfaces are
identical.
The PMBus/I2C interface is designed to minimize the processor overhead required for interface. It can
automatically detect and acknowledge addresses. It handles start and stop conditions automatically, and can
clock stretch until the processor has time to poll the PMBus status. It will automatically receive and send up to 4
bytes at a time. It can automatically verify and generate a PEC. This means that a write byte command can be
received by the processor with only one function call.
The interface also supports automatic ACK of two independent addresses. If both PMBus/I2C interfaces are used
at the same time a total of 4 independent addresses can be automatically detected.
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9.3.7.2.1 Example: PMBus Address Decode via ADC12 Reading
The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding.
At power-up the device applies IBIAS to each address detect pin and the voltage on that pin is captured by the
internal 12-bit ADC.
Vdd
AD00,
AD01
pin
On/Off Control
I
BIAS
Resistor to
set PMBus
Address
To ADC Mux
Figure 30. PMBUS Address Detection Method
PMBus/I2C address 0x7E is a reserved address and should not be used in a system using the UCD3138xA. This
address is used for manufacturing test.
9.3.7.3 SPI
The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length
(1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used
for communication between the UCD3138xA and external peripherals. Typical applications include an interface to
external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EPROMs and
analog-to-digital converters. The SPI allows serial communication with other SPI devices through a 3-pin or 4-pin
mode interface. A typical use case of SPI is to be configured as a master for communicating to external
EEPROM.
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SCS
tCSS
tWH
tWL
tCSH
SCK
tSU
tH
MISO
MOSI
VALID IN
tV
tHO
VALID OUT
PSCK
tWH
tWL
tSU
tH
tV
tHO
tCSS
Period SCK
2 ICLK
1/2 PSCK
1/2 PSCK
2 ns (typical)
4 ns (typical)
4 ns (typical)
2 ns (typical)
1 PSCK
SCK High Time
SCK Low Time
Data in setup
Data in hold
Ouput Valid
Ouput Data Hold
Chip Select Setup
tCSH
Chip Select Hold
1 PSCK
Figure 31. SPI Timing Diagram
9.3.7.4 JTAG Standard Interface
The UCD31xx family provides an On-Chip Scan-Base Emulation Logic, IEEE standard 1149.1 JTAG interface
which requires four signals for debugging and flash programming purposes. The JTAG pins are shared with other
function specific or general purpose I/O. The IOMUX register controls the JTAG pin sharing mechanism. The Pin
Functions table in Pin Configuration and Functions lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the UCD31xx Technical reference Manual
(SLUSAP2).
9.3.8 Real Time Clock
The UCD3138xA has an internal real time clock (RTC) function that can track time in seconds, minutes, hours
and days. This function requires an external precision 10 MHz clock.
•
Firmware writable time/day register which tracks the total number of days.
–
–
The day counter will be able to count 4 years worth of days.
Years and months and leap year calculation must be calculated in firmware.
•
•
•
•
Firmware programmable frequency correction of ±200 ppm in 0.8 ppm steps
The RTC function can provide interrupts to the IRQ or FIQ at 1, 10, 30, and 60 second intervals.
The clock from the RTC driver can be driven to an external pin through an internal multiplexor
The clock for the RTC function can come from an external clock through a dedicated GPIO pin.
9.3.9 External Crystal Interface
The UCD3138128A supports a 10-MHz external crystal. The external crystal can be used for the Real Time
Clock or synthesized to be the system clock.
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The crystal circuit biasing should be optimized depending on the total Cload on the crystal. Refer to Table 5 for
recommended bias settings based on Cload
.
Table 5. Recommended Bias Settings
Cload
0~4pF
BIAS_R SETTING
0
1
2
3
4
5~7pF
8~11pF
12~15pF
16~20pF
9.3.10 Timers
External to the Digital Power Peripherals there are 3 different types of timers in UCD3138xA. They are the 24-bit
timer, 16-bit timer and the watchdog timer
9.3.10.1 24-Bit Timer
There is one 24 bit timer which runs off the Interface Clock. It can be used to measure the time between two
events, and to generate interrupts after a specific interval. Its clock can be divided down by an 8-bit pre-scalar to
provide longer intervals. The timer has two compare registers (Data Registers). Both can be used to generate an
interrupt after a time interval. . Additionally, the timer has a shadow register (Data Buffer register) which can be
used to store CPU updates of the compare events while still using the timer. The selected shadow register
update mode happens after the compare event matches.
The two capture pins TCAP0 and TCAP1 are inputs for recording a capture event. A capture event can be set
either to rising, falling, or both edges of the capture pin signal. Upon this event, the counter value is stored in the
corresponding capture data register. Five Interrupts from the 24 bit timer can be set, which are the counter
rollover event (overflow), capture events 0 and 1, and the two comparison match events. Each interrupt can be
disabled or enabled.
9.3.10.2 16-Bit PWM Timers
There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by a
8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers) for
generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register)
which can be used to store CPU updates of compare events while still using the timer. The selected shadow
register update mode happens after the compare event matches.
The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a software
controlled register. Interrupts from the PWM timer can be set due to the counter rollover event (overflow) or by
the two comparison match events. Each comparison match and the overflow interrupts can be disabled or
enabled.
Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the output.
The value of PWM pin output can be read for status or simply configured as General Purpose I/O for reading the
value of the input at the pin.
9.3.10.3 Watchdog Timer
A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is clocked off
of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is issued to the ARM
processor. The watchdog is reset by a simple CPU write bit to the watchdog key register by the firmware routine.
On device power-up the watchdog is disabled. Yet after it is enabled, the watchdog cannot be disabled by
firmware. Only a device reset can put this bit back to the default disabled state. A half timer flag is also provided
for status monitoring of the watchdog.
9.3.11 General Purpose ADC12
The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:
•
•
Typical conversion speed of 539 ksps
Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence
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•
•
Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples
Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge,
ADC_EXT_TRIG pin or Analog Comparator results
•
•
Interrupt capability to embedded processor at completion of ADC conversion
Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data or
averaged ADC data
•
•
•
Two 10 µA current sources for excitation of PMBus addressing resistors
Dual sample and hold for accurate power measurement
Internal temperature sensor for temperature protection and monitoring
The control module (ADC12 Contol Block Diagram) contains the control and conversion logic for auto-
sequencing a series of conversions. The sequencing is fully configurable for any combination of 16 possible ADC
channels through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel
value is stored in the result register associated with the sequence number. Input channels can be sampled in any
desired order or programmed to repeat conversions on the same channel multiple times during a conversion
sequence. Selected channel conversions are also stored in the result registers in order of conversion, where the
result 0 register is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a
16-channel sequence. The number of channels converted in a sequence can vary from 1 to 16.
Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the
ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster
conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best
suited for monitoring and detection of currents, voltages, temperatures and faults. Please see the Typical
Characteristics plots for the temperature variation associated with this function.
ADC12 Block
ADC12 Registers
ADC
Averaging
12-bit SAR
S/H
ADC
ADC
Channels
ADC12
Control
Digital
Comparators
ADC Channel
ADC External Trigger (from pin)
Analog
Comparators
DPWM
Modules
Figure 32. ADC12 Control Block Diagram
9.3.12 Miscellaneous Analog
The Miscellaneous Analog Control (MAC) Registers control and monitor a wide variety of functions. These
functions include device supervisory features such as Brown-Out and power saving configuration, general
purpose input/output configuration and interfacing, internal temperature sensor control and current sharing
control.
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The MAC module also provides trim signals to the oscillator and AFE blocks. These controls are usually used at
the time of trimming at manufacturing; therefore this document will not cover these trim controls.
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9.3.13 Brownout
Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a condition
that may be considered unsafe for proper operation of the device.
The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is lower
than brownout threshold, it still does not necessarily trigger a device reset.
The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by an
interrupt service routine. Please see the Power On Reset (POR) / Brown Out Reset (BOR) section.
9.3.14 Global I/O
Up to 32 pins in UCD3138xA can be configured in the Global I/O register to serve as a general purpose input or
output pins (GPIO). This includes all digital input or output pins except for the RESET pin.
The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input pins,
EADC analog input pins and the RESET pin. Additional digital pins not listed in this register can be configured
through their local configuration registers.
There are two ways to configure and use the digital pins as GPIO pins:
1. Through the centralized Global I/O control registers.
2. Through the distributed control registers in the specific peripheral that shares it pins with the standard GPIO
functionality.
The Global I/O registers offer full control of:
1. Configuring each pin as a GPIO.
2. Setting each pin as input or output.
3. Reading the pin’s logic state, if it is configured as an input pin.
4. Setting the logic state of the pin, if it is configured as an output pin.
5. Connecting pin/pins to high rail through internal push/pull drivers or external pull up resistors.
The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain Control
Register, Global I/O Value Register and Global I/O Read Register.
Table 6 shows the format of Global I/O EN Register (GLBIOEN) as an example:
Table 6. Global I/O EN Register (GLBIOEN)
BIT NUMBER
Bit Name
Access
31:0
GLOBAL_IO_EN
R/W
Default
0000_0000_0000_0000_0000_0000_0000_0000
Bits 31-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins
0 = Control of IO is done by the functional block assigned to the IO (Default)
1 = Control of IO is done by Global IO registers.
PIN NUMBER
BIT
PIN_NAME
UCD3138xA
31
30
29
28
27
26
25
24
23
22
PWM2
PWM3
11
12
55
14
45
46
48
47
37
35
FAULT3
ADC_EXT_TRIG
TCK
TDO
TMS
TDI
SCI_TX1
SCI_TX0
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PIN NUMBER
BIT
PIN_NAME
UCD3138xA
21
20
19
18
17
16
15
14
13
12
11
10
9
SCI_RX1
SCI_RX0
TCAP0
38
36
49
40
39
13
20
18
17
42
54
44
43
34
29
28
27
26
25
24
23
22
PWM1
PWM0
TCAP1
I2C_DATA
PMBUS_CTRL
PMBUS_ALERT
EXT_INT
FAULT2
FAULT1
FAULT0
8
SYNC
7
DPWM3B
DPWM3A
DPWM2B
DPWM2A
DPWM1B
DPWM1A
DPWM0B
DPWM0A
6
5
4
3
2
1
0
9.3.15 Temperature Sensor Control
Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities. The
internal temperature sensor is disabled by default.
Temperature
Calibration
ADC 12
Temperature
Sensor
CH15
Figure 33. Internal Temp Sensor
Temperature sensor is calibrated at room temperature (25 °C) via a calibration register value.
The temperature sensor is measured using ADC12 (via Ch15). The temperature is then calculated using a
mathematical formula involving the calibration register (this effectively adds a delta to the ADC measurement).
The temperature sensor can be enabled or disabled.
9.3.16 I/O Mux Control
I/O Mux Control register may be used in order to choose a single specific functionality that is desired to be
assigned to a physical device pin for your application. See the UCD3138xA programmer's manual for details on
the available configurations.
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9.3.17 Current Sharing Control
UCD3138xA provides three separate modes of current sharing operation.
•
•
•
•
Analog bus current sharing
PWM bus current sharing
Master/Slave current sharing
AD02 has a special ESD protection mechanism that prevents the pin from pulling down the current-share bus
if power is missing from the UCD3138xA
The simplified current sharing circuitry is shown in the drawing below. The digital pulse connected to SW3
transforms SW3 into a pulse-width-modulated current source. Details on the frequency and resolution of this
feature are in the digital power fusion peripherals manual.
3.3 V
ISHARE
SW3
Digital
3.3 V
3.3V
ESD
3.2 kΩ
SW1
400 Ω
250 Ω
AD02
ESD
AD13
ESD
SW2
250 Ω
EXT CAP
RSHARE
ADC12 and
CMP
ADC12 and
CMP
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Figure 34. Simplified Current Sharing Circuitry
FOR TEST ONLY,
ALWAYS KEEP 00
CURRENT SHARING MODE
CS_MODE
EN_SW1
EN_SW2
DPWM
Off or Slave Mode (3-state)
PWM Bus
00
00
00
00
00 (default)
0
1
0
0
0
0
0
1
0
01
10
11
ACTIVE
Off or Slave Mode (3-state)
Analog Bus or Master
0
0
The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be
controlled through the current sharing control register (CSCTRL).
9.3.18 Temperature Reference
The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the internal
temperature sensor (channel 15) during the factory trim and calibration.
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This information can be used by different periodic temperature compensation routines implemented in the
firmware. But it should not be overwritten by firmware, otherwise this factory written value will be lost until the
device is reset.
9.4 Device Functional Modes
9.4.1 DPWM Modes of Operation
The DPWM is a complex logic system which is highly configurable to support several different power supply
topologies. The discussion below will focus primarily on waveforms, timing and register settings, rather than on
logic design.
The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts over
again.
The DPWM logic causes transitions in many digital signals when the period counter hits the target value for that
signal.
9.4.1.1 Normal Mode
In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of the
switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck topologies. The
drawing of the Normal Mode waveforms is shown in Figure 35.
Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can be
used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the middle of
the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The Adaptive Sample
Register provides an offset from the center of the on-time. This can compensate for external delays, such as
MOSFET and gate driver turn on times.
Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the beginning
of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB. The other edges
are dynamic, so blanking is more difficult.
Cycle Adjust B has no effect in Normal Mode.
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Device Functional Modes (continued)
Start of Period
Start of Period
Period
Period Counter
Filter controlled edge
DPWM Output A
Event 1
Filter Duty (High Resolution)
Cycle Adjust A (High Resolution)
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
Event 3 œ Event 2 (High Res)
Event 4 (High Res)
DTC Adjustment
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
•
•
•
•
•
•
•
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 1 + Filter Duty + Cycle Adjust A + (Event 3 – Event 2)
DPWM B Falling Edge = Event 4 + DTC Adjustment
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
•
•
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 35. Normal Mode Closed Loop
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Device Functional Modes (continued)
9.4.1.2 DPWM Multiple Output Mode
Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM peripheral
to drive two phases with the same pulse width, but with a time offset between the phases, and with different
cycle adjusts for each phase.
The diagram for Multi-Mode is shown in Figure 36.
Event 2 and Event 4 are not relevant in Multi mode.
DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100% pulse
width operation is possible. DPWMA cannot cross over the period boundary.
Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for blanking
this rising edge.
Cycle Adjust B is usable on DPWM B.
Start of Period
Period
Start of Period
Period Counter
Filter controlled edge
DPWM Output A
Event 1
Filter Duty (High Resolution)
Cycle Adjust A (High Resolution)
DTC Adjustment
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
To Other
Modules
Blanking A Begin
Blanking A End
DPWM Output B
Event 3 (High Resolution)
Filter Duty (High Resolution)
Cycle Adjust B (High Resolution)
DTC Adjustment
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
•
•
•
•
•
•
•
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A + DTC Adjustment
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B + DTC Adjustment
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
•
•
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 36. Multi Mode Closed Loop
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Device Functional Modes (continued)
9.4.1.3 DPWM Resonant Mode
This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As the
switching frequency changes, the dead times between the pulses remain the same.
The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as
described in LLC Example. The diagram of this mode is shown in Figure 37.
The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the Filter
Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half of the
period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty for both
DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed regardless of the
period. The only edge which is fixed relative to the start of the period is the rising edge of DPWM A. This is the
only edge for which the blanking signals can be used easily.
Start of Period
Filter Period
Start of Period
Period Counter
Filter controlled edge
DPWM Output A
Event 1
Filter Duty œ 2 x Event 1
DTC Adjustment
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
2 x Event 1
Event 1
DTC Adjustment
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
•
•
•
•
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Filter Duty - Event 1 + DTC Adjustment
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
•
•
•
DPWM B Rising Edge = Filter Duty + Event 1
DPWM B Falling Edge = Filter Duty - Event 1 + DTC Adjustment
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
•
•
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 37. Resonant Symmetrical Closed Loop
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Device Functional Modes (continued)
9.4.1.4 Triangular Mode
Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the PWM
pulse is centered in the middle of the period, rather than starting at one end or the other. In Triangular Mode,
only DPWM-B is available. The diagram for Triangular Mode is shown in Figure 38.
All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger is not
needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time, because the center
of the on-time does not move in this mode.
Start of Period
Period
Start of Period
Period Counter
DPWM Output A
Sample Trigger 1
Blanking A Begin
Blanking A End
To Other
Modules
Filter controlled edge
DPWM Output B
Cycle Adjust A (High Resolution)
Cycle Adjust B (High Resolution)
Filter Duty/2 (High Resolution)
Period/2
Sample Trigger 2
Blanking B Begin
Blanking B End
To Other
Phase Trigger
Modules
Events which change with DPWM mode:
•
•
•
•
•
•
DPWM A Rising Edge = None
DPWM A Falling Edge = None
Adaptive Sample Trigger = None
DPWM B Rising Edge = Period / 2 - Filter Duty / 2 + Cycle Adjust A
DPWM B Falling Edge = Period / 2 + Filter Duty / 2 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
•
•
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 38. Triangular Mode Closed Loop
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Device Functional Modes (continued)
9.4.1.5 Leading Edge Mode
Leading edge mode is very similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the
rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling edge
stays ahead of the DPWMA rising edge by a fixed dead time. The diagram of the Leading Edge Mode is shown
in Figure 39.
As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking intervals are
mainly useful for the edges at the beginning and end of the period.
Start of Period
Period
Start of Period
Period Counter
DPWM Output A
Event 1
Filter Duty (High Resolution)
Cycle Adjust A (High Resolution)
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
Event 2 - Event 3 (High Resolution)
Event 4 (High Resolution)
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
•
•
•
•
•
•
•
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = = Event 1 - Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 - Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 - Filter Duty / 2 + Adaptive Sample Register
DPWM B Rising Edge = Event 4
DPWM B Falling Edge = Event 1 - Filter Duty + Cycle Adjust A - ( Event 2 – Event 3 )
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
•
•
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 39. Leading Edge Closed Loop
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Device Functional Modes (continued)
9.4.1.6 Phase Shifting
In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The phase
shift signal has two possible sources. It can come from the Phase Trigger Register. This provides a fixed value,
which is useful for an application like interleaved PFC.
The phase shift value can also come from the filter output. In this case, the changes in the filter output causes
changes in the phase relationship of two DPWM modules. This is useful for phase shifted full bridge topologies.
The following figure shows the mechanism of phase shift:
Phase Shift
DPWM0 Start of Period
DPWM0 Start of Period
Period Counter
DPWM1 Start of Period
DPWM1 Start of Period
Period Counter
Phase Trigger = Phase Trigger Register value or Filter Duty
Figure 40. Phase Shifting
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9.5 Register Maps
9.5.1 CPU Memory Map And Interrupts
When the device comes out of power-on-reset, the data memories are mapped to the processor as follows:
9.5.1.1 Memory Map (After Reset Operation)
ADDRESS
SIZE (BYTES)
MODULE
0x0000_0000 – 0x0003_FFFF
In 32 repeated blocks of 8 k each
32 X 8 k
Boot ROM
0x0004_0000 – 0x0004_7FFF
0x0004_8000 – 0x0004_FFFF
0x0005_0000_0x0005_7FFF
0x0005_0000_0x0005_7FFF
0x0006_9800 – 0x0006_9FFF
0x0006_A000 – 0x0006_BFFF
32 k
32 k
32 k
32 k
2 k
Program Flash 0
Program Flash 1
Program Flash 2
Program Flash 3
Data Flash
8 k
Data RAM
9.5.1.2 Memory Map (Normal Operation)
Just before the boot ROM program gives control to flash program, the ROM configures the memory as follows:
ADDRESS
SIZE (BYTES)
MODULE
Boot ROM
0x0002_0000 – 0x0002_1FFF
0x0000_0000 – 0x00000_07FFF
0x0000_8000 – 0x00000_0FFFF
0x0001_8000 - 0x0001_07FFF
0x0001_8000 - 0x0001_FFF
0x0006_9800 – 0x0006_9FFF
0x0006_A000 – 0x0006_BFFF
8 k
32 k
32 k
32 k
32 k
2 k
Program Flash 0 (or 2)
Program Flash 1 (or 3)
Program Flash 2 (or 0)
Program Flash 3 (or 1)
Data Flash
8 k
Data RAM
9.5.1.3 Memory Map (System And Peripherals Blocks)
ADDRESS
SIZE
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
MODULE
0x0012_0000 - 0x0012_00FF
0x0013_0000 - 0x0013_00FF
0x0014_0000 - 0x0014_00FF
0x0015_0000 - 0x0015_00FF
0x0016_0000 - 0x0016_00FF
0x0017_0000 - 0x0017_00FF
0x0018_0000 - 0x0018_00FF
0x0019_0000 - 0x0019_00FF
0x001A_0000 - 0x001A_00FF
0x001B_0000 – 0x001B_00FF
0x001C_0000 - 0x001C_00FF
0x001D_0000 - 0x001D_00FF
0x001E_0000 - 0x001E_00FF
0xFFF7_E400 - 0xFFF7_E4FF
0xFFF7_E800-0xFFF7_E8FF
0xFFF7_EC00 - 0xFFF7_ECFF
0xFFF7_ED00 - 0xFFF7_EDFF
0xFFF7_F000 - 0xFFF7_F0FF
0xFFF7_F600 - 0xFFF7_F6FF
Loop Mux
Fault Mux
ADC
DPWM 3
Filter 2
DPWM 2
Front End/Ramp Interface 2
Filter 1
DPWM 1
Front End/Ramp Interface 1
Filter 0
DPWM 0
Front End/Ramp Interface 0
RTC
SPI
UART 0
UART 1
Miscellaneous Analog Control
PMBus/I2C Interface (1)
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ADDRESS
SIZE
256
256
256
256
256
23
MODULE
PMBus/I2C Interface (2)
0xFFF7_F700 - 0xFFF7_F7FF
0xFFF7_FA00 - 0xFFF7_FAFF
0xFFF7_FD00 - 0xFFF7_FDFF
0xFFFF_FD00 - 0xFFFF_FDFF
0xFFFF_FE00 - 0xFFFF_FEFF
0xFFFF_FF20 - 0xFFFF_FF37
0xFFFF_FFD0 - 0xFFFF_FFEC
GIO
Timer
MMC
DEC
CIM
28
SYS
The registers and bit definitions inside the System and Peripheral blocks are detailed in the programmer’s
manuals.
9.5.2 Boot ROM
The device incorporates a 8 kB boot ROM. This boot ROM includes support for:
•
•
•
•
•
•
Program download through the PMBus
Device initialization
Examining and modifying registers and memory
Verifying and executing program flash automatically
Jumping to a customer defined boot program
Checksum evaluation to support using the program flash as a single 64 kB block or as 2-32 kB blocks.
The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on
the program flash. If the first 2 kB of program FLASH 0 has a valid checksum, the program branches to location
0 in Program FLASH 0. This permits the use of a custom boot program. If the first checksum fails, it performs
some additional checksum calculations to determine where the valid program is located. This permits full
automated program memory checking, when there is no need for a custom boot program. The complete decision
tree is located in Pseudo Code for ROM. Additionally, the part can support two separate programs in block 0 and
block 1 through a custom boot-flash routine.
If none of the checksums are valid, the Boot ROM stays in control, and accepts commands via the PMBus
interface. These functions can be used to read and write to all memory locations in the device. Typically they are
at address 11 and are used to download a program to Program Flash, and to command its execution.
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9.5.2.1 Pseudo Code for ROM
-> If PFLASH[0], location 0 = 0xEA
-> If PFLASH[0] 2K/32K checksum is valid ==> Execute PFLASH[0}
-> Else,
-> If PFLASH[0-1] 64K checksum is valid ==> Execute PFLASH[0]
-> If PFLASH[0-3] 128K checksum is valid ==> Execute PFLASH[0]
-> If PFLASH[2], location 0 = 0xEA
-> If PFLASH[2], location 0 = 0xEA
-> Else If PFLASH[2], location 0 = 0xEA
-> PFLASH[2-3] 64K checksum is valid ==> Execute PFLASH[2]
-> Else
-> Stay in ROM mode
9.5.3 Customer Boot Program
As described above, it is possible to generate a user boot program using 2 kB or more of the Program Flash.
This can support things which the Boot ROM does not support, including:
•
Program download via UART – useful especially for applications where the UCD3138128A is isolated from
the host (that is, PFC)
•
•
•
Encrypted download – useful for code security in field updates.
PMBus download at different addresses
Different command formats
9.5.4 Flash Management
The device offers a variety of features providing for easy prototyping and easy flash programming. At the same
time, high levels of security are possible for production code, even with field updates. Standard firmware will be
provided for storing multiple copies of system parameters in data flash. This minimizes the risk of losing
information if data-flash programming is interrupted.
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The UCD3138xA has an extensive set of fully-programmable, high-performance peripherals that make it suitable
for a wide range of power supply applications. In order to make the part easier to use, TI has prepared an
extensive set of materials to demonstrate the features of the device for several key applications. In each case the
following items are available:
1. Full featured EVM hardware that demonstrates classic power supply functionality.
2. An EVM user guide that contains schematics, bill-of-materials, layout guidance and test data showcasing the
performance and features of the device and the hardware.
3. A firmware programmers manual that provides a step-by-step walk through of the code.
Table 7. Application Information
APPLICATION
EVM DESCRIPTION
This EVM demonstrates a PSFB DC-DC power converter with digital control using the UCD3138xA device. Control is
implemented by using PCMC with slope compensation. This simplifies the hardware design by eliminating the need
for a series blocking capacitors and providing the inherent input voltage feed-forward that comes from PCMC. The
controller is located on a daughter card and requires firmware in order to operate. This firmware, along with the entire
source code, is made available through TI. A free, custom function GUI is available to help the user experiment with
the different hardware and software enabled features. The EVM accepts a DC input from 350 VDC to 400 VDC, and
outputs a nominal 12 VDC with full load output power of 360 W, or full output current of 30 A.
Phase shifted full
bridge
This EVM demonstrates an LLC resonant half-bridge DC-DC power converter with digital control using the
UCD3138xA device. The controller is located on a daughter card and requires firmware in order to operate. This
firmware, along with the entire source code, is made available through TI. A free, custom function GUI is available to
help the user experiment with the different hardware and software enabled features. The EVM accepts a DC input
from 350 VDC to 400 VDC, and outputs a nominal 12 VDC with full load output power of 340 W, or full output current
of 29 A.
LLC resonant
converter
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10.2 Typical Application
This section summarizes the PSFB EVM DC-DC power converter.
L1
T1
Q7
+12V
Q6
Q5
C1
RL
VBUS
I_pri
PRIM
ORING
CTL
CURRENT
T2
VOUT
C2
R2
D1
T1
QT2
QB2
QT1
VA
Lr
Current
Sensing
QB1
D2
Vref
DPWM0
DPWM0B
DPWM1B
Duty for mode
switching
Vout
CPCC
<
EADC0
EADC1
CLA0
DPWM1
DPWM2
Iout
CLA1
DPWM2A
DPWM2B
Load Current
DPWM3A
DPWM3B
I_pri
EADC2
PCM
DPWM3
AD00
ISOLATED
GATE Transformer
ACFAIL_IN
FAULT0
FAULT1
FAULT2
SYNCHRONOUS
GATE DRIVE
AD01
AD02/CMP0
AD03/CMP1/CMP2
AD04/CMP3
AD05/CMP4
AD06/CMP5
AD07/CMP6
AD08
ACFAIL_OUT
FAILURE
I_SHARE
Vout
FAULT
UCD3138
GPIO1
GPIO2
GPIO3
ORING_CRTL
ON/OFF
Iout
I_pri
CBC
temp
P_GOOD
Vin
VA
WD
ARM7
AD09
PMBus
UART0
RST
OSC
Primary
UART1
Memory
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Figure 41. Phase-Shifted Full-Bridge
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Typical Application (continued)
10.2.1 Design Requirements
Table 8. Input Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.
Vin
Input voltage range
Max input voltage
Input current
Normal Operating
Continuous
350
385
420
420
V
V
Vinmax
Iin
Vin=350V, Full Load
1.15
30
A
Istby
Von
Vhys
Input no load current Output current is 0A
mA
V
Vin Decreasing (input voltage is detected on secondary side)
340
360
Under voltage lockout
Vin Increasing
V
Table 9. Output Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.
VO
Output voltage setpoint
Line regulation
No load on outputs
12
V
Regline
All outputs; 360 ≤ Vin ≤ 420; IO = IOmax
All outputs; 0 ≤ IO ≤ IOmax; Vin = 400 V
5Hz to 20 MHz
0.5
1
%
%
Regload
Load regulation
Ripple and noise(1)
Vn
IO
η
100
mVpp
A
Output current
0
30
Efficiency at phase-shift mode
Efficiency at PWM ZVS mode
Efficiency at hard switching mode
Output adjust range
Vo = 12 V, Io = 15 A
Vo = 12 V, Io = 15 A
Vo = 12 V, Io = 15 A
93%
93%
90%
η
η
Vadj
11.4
12.6
V
V
Transient response
overshoot/undershoot
Vtr
50% Load Step at 1AµS, min load at 2A
±0.36
tsettling
tstart
Transient response settling time
Output rise time
100
50
µS
mS
%
10% to 90% of Vout
At Startup
Overshoot
2
fs
Switching frequency
Current sharing accuracy
Loop phase margin
Loop gain margin
Over Vin and IO ranges
50% - full load
150
±5
kHz
%
Ishare
φ
10% - Full load
10% - Full load
45
degree
dB
G
10
(1) Ripple and noise are measured with 10µF Tantalum capacitor and 0.1µF ceramic capacitor across output.
10.2.2 Detailed Design Procedure
10.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration
Overview
The hardware configuration of the UCD3138xA PCMC PSFB converter contains two critical elements that are
highlighted in the subsequent sections.
•
DPWM initialization - This section will highlight the key register settings and considerations necessary for the
UCD3138xA to generate the correct MOSFET waveforms for this topology. This maintains the proper phase
relationship between the MOSFETs and synchronous rectifiers as well as the proper set up required to
function correctly with PCMC.
•
PCMC initialization - This section will discuss the register settings and hardware considerations necessary to
modulate the DPWM pins with PCMC and internal slope compensation.
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10.2.2.2 DPWM Initialization for PSFB
The UCD3138xA DPWM peripheral provides flexibility for a wide range of topologies. The PSFB configuration
utilizes the Intra-Mux and Edge Generation Modules of the DPWM. For a diagram showing these modules, see
the UCD3138xA Digital Power Peripherals Manual.
Here is a schematic of the power stage of the PSFB:
L1
T1
VOUT
Q6
VBUS
I_pri
PRIM
CURRENT
Q5
T2
R2
D1
D2
QT2
QB2
QT1
QB1
Lr
T1
ISOLATED
GATE Transformer
SYNCHRONOUS
GATE DRIVE
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Figure 42. Schematic – PSFB Power Stage
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Here is an overview of the key PSFB signals:
3 A – QB1
( DPWM1C)
3 B – QT1
( DPWM2C)
2 A – QT2
( EDGEGEN)
X1
Y3
2 B – QB2
( EDGEGEN)
X3
Y2
Transformer
Voltage
X2
1 B –
QSYN 1,3
Y1
0 B –
QSYN 2,4
DPWM3AF
DPWM3BF
DPWM 2AF
DPWM 2BF
Current
Peak Level
X1, X2 ,X3 and Y1 , Y2 , Y3 are sets of moving edges
All other edges are fixed .
Figure 43. Key PSFB Signals
10.2.2.3 DPWM Synchronization
DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to
DPWM2, ½ period out of phase using these commands:
Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave
Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave
Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave
Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;
Dpwm1Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;
Dpwm2Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;
LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0; // Slave to dpwm-0
LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL = 1; // Slave to dpwm-1
LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL = 2; // Slave to dpwm-2
If the event registers on the DPWMs are the same, the two pairs of signals will be symmetrical. All code
examples are taken from the PSFB EVM code, unless otherwise stated.
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10.2.2.4 Fixed Signals to Bridge
The two top signals in the above drawing have fixed timing. The DPWM1CF and DPWM2CF signals are used for
these pins. DPWMCxF refers to the signal coming out of the fault module of DPWMx, as shown inFigure 44.
Figure 44. Fixed Signals to Bridge
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These signals are actually routed to pins DPWM3A and 3B using the Intra Mux with these statements:
Dpwm3Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 7; // Send DPWM1C
Dpwm3Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 8; // Send DPWM2C
Since these signals are really being used as events in the timer, the #defines are called EV5 and EV6. Here are
the statements which initialize them:
// Setup waveform for DPWM-C (re-using blanking B regs)
Dpwm2Regs.DPWMBLKBBEG.all = PWM2_EV5 + (4 x 16);
Dpwm2Regs.DPWMBLKBEND.all = PWM2_EV6;
Period End
Period Start
Controlled by DPWM 1 Blanking register
Blank B Begin
Blank B End
3 A – QB1
Event 6
Event 5
( DPWM1C)
3 B – QT1
Event 6
Event 6
Event 5
( DPWM 2C)
Blank B Begin
Blank B End
Controlled by DPWM 2 Blanking register
Figure 45. Blank B Timing Information
The statements for DPWM1 are the same. Remember that DPWMC reuses the Blank B registers for timing
information.
10.2.2.5 Dynamic Signals to Bridge
DPWM0 and 1 are set at normal mode. PCMC triggering signal (fault) chops DPWM0A and 1A cycle by cycle.
The corresponding DPWM0B and 1B are used for synchronous rectifier MOSFET control. The same PCMC
triggering signal is applied to DPWM2 and DPWM3. Both of these are set to normal mode as well. DPWM2 and
3 are chopped and their edges are used to generate the next two dynamic signals to the bridge. They are
generated using the Edge Generator Module in DPWM2. The Edge Generator sources are DPWM2 and
DPWM3. The edges used are:
DPWM2A turned on by a rising edge on DPWM2BF
DPWM2A turned off by a falling edge on DPWM3AF
DPWM2B turned on by a rising edge on DPWM3BF
DPWM2B turned off by a falling edge on DPWM2AF
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Period Start
Period End
3 A – QB1
( DPWM 1C)
3 B – QT1
( DPWM 2C)
2 A – QT2
( EDGEGEN )
2 B – QB2
( EDGEGEN )
Y3
X3
1A
1 B –
QSYN 1,3
Y2
Y1
X2
0A
0 B –
QSYN 2,4
X1
DPWM 3AF
DPWM 3BF
DPWM 2AF
DPWM 2BF
Current
Peak Level
Chopping point
Chopping point
X1 , X2 , X3 and Y1 , Y2 , Y3 are sets of moving edges
All other edges are fixed .
Figure 46. Dynamic Signals to Bridge
The Edge Generator is configured with these statements:
Dpwm2Regs.DPWMEDGEGEN.bit.A_ON_EDGE = 2;
Dpwm2Regs.DPWMEDGEGEN.bit.A_OFF_EDGE = 5;
Dpwm2Regs.DPWMEDGEGEN.bit.B_ON_EDGE = 6;
Dpwm2Regs.DPWMEDGEGEN.bit.B_OFF_EDGE = 1;
Dpwm2Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 1; // EDGEGEN-A out the A output
Dpwm2Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 1; // EDGEGEN-B out the B output
Dpwm2Regs.DPWMEDGEGEN.bit.EDGE_EN = 1;
The EDGE_EN bits are set for all 4 DPWMs. This is done to ensure that all signals have the same timing delay
through the DPWM.
The finial 6 gate signals are shown in Figure 47.
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Period Start
Period End
3 A – QB1
( DPWM 1C)
3 B – QT1
( DPWM 2C)
2 A – QT2
( EDGEGEN )
2 B – QB2
( EDGEGEN )
Y3
X3
1 B –
QSYN 1,3
X2
Y2
Y1
0 B –
QSYN 2,4
X1
Peak Level
Current
Chopping point
Chopping point
Figure 47. Final 6 Gate Signals
Note how the falling edge of DPWM2AF aligns with the X1 edge, and how the rising edge of DPWM2BF aligns
with the X3 edge. The falling edges on DPWM2AF and DPWM3AF are caused by the peak detection logic. This
is fed through the Cycle By Cycle logic. The Cycle By Cycle logic also has a special feature to control the rising
edges of DPWM2BF (X1 and X3) and DPWM3BF (Y1 and Y3). It uses the value of Event3 – Event2 to control
the time between the edges. The same feature is used with DPWM0 and DPWM1 to control the X2 and Y2
signals. Using the other 2 DPWMs permits these signals to have a different dead time.
The same setup can be used for voltage mode control. In this case, the Filter output sets the timing of the falling
edge on DPWMxAF.
All DPWMs are configured in Normal mode, with CBC enabled. If external slope compensation is used,
DPWM1A and DPWM1B are used to reset the external compensator at the beginning of each half cycle. If no
PCMC event occurs, the values of Events 2 and 3 determine the locations of the edges, just as in open loop
mode.
10.2.3 System Initialization for PCM
PCM (Peak Current Mode) is a specialized configuration for the UCD3138xA which involves several peripherals.
This section describes how it works across the peripherals.
10.2.3.1 Use of Front Ends and Filters in PSFB
All three front ends are used in PSFB. The same signals are used in the same places for both PCMC and
voltage mode. The same hardware can be used for both control modes, with the mode determined by which
firmware is loaded into the device. FE0 and FE1 are used with their associated filters, but Filter 2 is not used at
all.
FE0 – Vout – voltage loop
FE1 – Iout – current loop
FE2 – Ipri – PCM
In PCMC mode, FE2 is used for PCMC, and the voltage loop is normally used to provide the start point for the
compensation ramp. If the CPCC firmware detects a need for constant current mode, it switches to the current
loop for the start point.
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10.2.3.2 Peak Current Detection
Peak current detection involves all the major modules of the DPPs, the Front End, Filter, Loop Mux, Fault Mux
and the DPWMs. A drawing of the major elements is shown in Figure 48.
Ipri
PCM
Comparator
Loop
Mux
Fault
Mux
DPWM
Voltage Loop
Filter
Loop
Mux
Ramp
Module
Loop
Mux
Vout
Front
End
Figure 48. Peak Current Detection Function
All signals without arrows flow from left to right. The voltage loop is used to select a peak current level. This level
is fed to the Ramp module to generate a compensation ramp. The compensation ramp is compared to the
primary current by the PCMC comparator in the Front End. When the ramp value is greater than the primary
current, the APCMC signal is sent to the DPWM, causing the events described in the previous sections.
The DPWM frame start and output pin signals can be used to trigger the Ramp Module. In this case, unlike in the
case of other ramp module functions, each DPWM frame triggers the start of the ramp. The ramp steps every 32
ns.
The Filter is configured normally, there is no real difference for PCMC. The PCM_FILTER_SEL bits in the
LoopMux.PCMCTRL register are used to select which filter is connected to the ramp module:
LoopMuxRegs.APCMCTRL.bit.PCM_FILTER_SEL = 0; //select filter0
With Firmware Constant Power/Constant current, Filter 1 and Front End 1 are used as a current control loop,
with the EADCDAC set to high current. If the voltage loop value becomes higher than the current loop value,
then Filter 1 is used to control the PCM ramp start value:
LoopMuxRegs.APCMCTRL.bit.PCM_FILTER_SEL = 1;
//select filter1 for slope compensation source
S P A C E
In the ramp module, there are 2 bitfields in the RAMPCTRL register which must be configured. The
PCM_START_SEL must be set to a 1 to enable the Filter to be used as a ramp start source. The RAMP_EN bit
must be set, of course.
The DAC_STEP register sets the slope of the compensation ramp. The DAC value is in volts, of course, so it is
necessary to calculate the slope after the current to voltage conversion. Here is the formula for converting from
millivolts per microsecond to DACSTEP.
m = compensation slope in millivolts per microsecond
ACSTEP = 335.5 × M
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In C, this can be written:
#define COMPENSATION_SLOPE 150 //compensation slope in millivolts per microsecond
#define DACSTEP_COMP_VALUE ((int) (COMPENSATION_SLOPE*335.5) )
//value in DACSTEP for desired compensation slope
FeCtrl0Regs.DACSTEP.all = DACSTEP_COMP_VALUE;
It may also be necessary to set a ramp ending value in the RAMPDACEND register.
In addition, it is necessary to set the D2S_COMP_EN bit in the EADCCTRL register. This is for enabling the
differential to single ended comparator function. The front end diagram leaves it out for simplicity, but the
connection between the DAC and the EADC amplifier is actually differential. The PCMC comparator, however, is
single ended. So a conversion is necessary as shown in Figure 49.
AFE_GAIN
23-AFE_GAIN
6 bit ADC
8mV/LSB
EAP0
2AFE_GAIN
EAN0
Signed 9 bit result
(error) 1 mV /LSB
EADC
X
Averaging
SAR/Prebias
Ramp
Filter x
CPCC
DAC0
10 bit DAC
1.5625mV/LSB
Σ
Value
Differential to
Single Ended
Dither
4 bit dithering gives 14 bits of effective resolution
97.65625μV/LSB effective resolution
Absolute Value
Calculation
10 bit result
1.5625mV/LSB
Peak Current
Detected
Peak Current Mode
Comparator
Figure 49. Differential to Single-Ended Comparator Function
The EADC_MODE bit in EADCCTRL should be set to a 5 for peak current mode.
The peak current detection signal next goes to the Loop Mux. The Fault Mux has only 1 APCM input, but there
are 3 front ends. So the PCM_FE_SEL bits in APCMCTRL must be used to select which front end is used:
LoopMuxRegs.APCMCTRL.bit.PCM_FE_SEL = 2; // use FE2 for PCM */
The PCM_EN bit must also be set.
LoopMuxRegs.APCMCTRL.bit.PCM_EN = 1; // Enable PCM
Next the Fault Mux is used to enable the APCM bit to the CLIM/CBC signal to the DPWM. There are 4
DPWMxCLIM registers, one for each DPWM. The ANALOG_PCM_EN bit must be set in each one to connect the
PCM detection signal to the CLIM/CBC signal on each DPWM. For the latest configuration information on all of
these bits, consult the appropriate EVM firmware. To avoid errors, it is best to configure your hardware design
using the same DPWMs, filters, and front ends for the same functions as the EVM.
DPWM timing is used to trigger the start of the ramp. This is selected by the FECTRLxMUX registers in the Loop
Mux. DPWMx_FRAME_SYNC_EN bits, when set, cause the ramp to be triggered at the start of the DPWM
period.
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10.2.3.3 Peak Current Mode (PCM)
There is one peak current mode control module in the device however any front end can be configured to use
this module.
10.2.4 Application Curves
30A Load
syncFETs off
1A-16A-1A
Vin =385V
Figure 51. VOUT Soft Start
Figure 50. Load Transient
Kp =14000
Ki =300
Kd =2000
Alpha = –2
Figure 52. Bode Plot
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11 Power Supply Recommendations
•
Both 3.3 VD and 3.3 VA should have a local capacitor of at least 4.7-µF in parallel with a 10-nF capacitor
placed as close as possible to the device pins.
•
BP18 should have a 1-µF capacitor in parallel with a 10-nF capacitor to ground.
For detailed practical design guidelines, refer to (SLUA779).
12 Layout
12.1 Device Grounding and Layout Guidelines
•
•
•
•
Single ground is recommended: SGND. A multilayer such as 4 layers board is recommended so that one
solid SGND is dedicated for return current path, referred to the layout example.
Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor has
different ESL, Capacitance and ESR, and they have different frequency response.
Avoid long traces close to radiation components, and place them into an internal layer, and it is preferred to
have grounding shield.
Analog circuits and digital circuits should have separate return to ground; although with a single plane, still try
to avoid mixing analog current and digital current.
•
•
Do not use a ferrite bead or larger than 3-Ω resistor to connect between V33A and V33D.
Both 3.3VD and 3.3VA should have local decoupling capacitors close to the device power pins, add vias to
connect decoupling caps directly to SGND.
•
Avoid negative current/negative voltage on all pins, so Schottky clamping diodes may be needed to limit the
voltage; avoid more than 3.8 V or less than –0.3 V voltage spikes on all pins; add Schottky diodes on the pins
which could have voltage spikes during surge test; be aware that a Schottky has relatively higher leakage
current, which can affect the voltage sensing at high temperature.
•
If V33 slew rate is less than 2.5 V/ms the RESET pin should have a 2.21-kΩ resistor between the reset pin
and V33D and a 2.2-µF capacitor from RESET to ground. For more details please refer to the UCD3138
Family - Practical Design Guideline This capacitor must be located close to the device RESET pin.
•
•
If the XTAL_IN (Pin 61) and XTAL_OUT (Pin 62) are not used for external clock, tie them to 1.8 V (Pin BP18)
through a 1-kΩ resistor respectively.
Configure unused GPIO pins to be inputs or connect them to the ground (DGND or SGND); when an external
pull-up resistor is used for GPIO, the pull-up resistor needs to be 1 kΩ or higher.
For detailed practical design guidelines, refer to (UCD3138 Family - Practical Design Guideline).
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12.2 Layout Examples
Figure 53. Layout Example for UCD3138128A Top Layer
Figure 54. Layout Example for UCD3138128A Internal Ground Layer
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
The application firmware for the UCD3138xA is developed on Texas Instruments Code Composer Studio (CCS)
integrated development environment.
Device programming, real time debug and monitoring/configuration of key device parameters for certain power
topologies are all available through Texas Instruments’ FUSION_DIGITAL_POWER_DESIGNER Graphical User
Interface (http://www.ti.com/tool/fusion_digital_power_designer). The FUSION_DIGITAL_POWER_DESIGNER
software application uses the PMBus protocol to communicate with the device over a serial bus using an
interface adaptor known as the USB-TO-GPIO, available as an EVM from Texas Instruments
(http://www.ti.com/tool/usb-to-gpio). PMBUS-based real-time debug capability is available through the ‘Memory
Debugger’ tool within the Device GUI module of the FUSION_DIGITAL_POWER_DESIGNER GUI, which
represents a powerful alternative over traditional JTAG-based approaches’.
The software application can also be used to program the devices, with a version of the tool known as
FUSION_MFR_GUI optimized for manufacturing environments (http://www.ti.com/tool/fusion_mfr_gui). The
FUSION_MFR_GUI tool supports multiple devices on a board, and includes built-in logging and reporting
capabilities.
13.2 Documentation Support
13.2.1 Related Documentation
In terms of reference documentation, the following programmer’s manuals are available offering detailed
information regarding the application and usage of UCD3138xA digital controller:
1. UCD3138064A or UCD3138128A Programmer's Manual
2. UCD3138 Digital Power Peripheral Programmer's Manual Key Tpics Covered in This Manual Include:
–
Digital Pulse Width Modulator (DPWM)
–
–
–
Modes of Operation (Normal/Multi/Phase-shift/Resonant etc)
Automatic Mode Switching
DPWMC, Edge Generation and Intra-Mux
–
Front End
–
–
–
–
–
Analog Front End
Error ADC or EADC
Front End DAC
Ramp Module
Successive Approximation Register Module
–
–
Filter
–
Filter Math
Loop Mux
–
–
–
Analog Peak Current Mode
Constant Power/Constant Current (CPCC)
Automatic Cycle Adjustment
–
–
Fault Mux
–
–
–
–
–
–
Analog Comparators
Digital Comparators
Fault Pin functions
DPWM Fault Action
Ideal Diode Emulation (IDE), DCM Detection
Oscillator Failure Detection
Register Map for all of the above peripherals in UCD3138A64 or UCD3138128
74
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Copyright © 2016–2017, Texas Instruments Incorporated
Product Folder Links: UCD3138128A
UCD3138128A
www.ti.com
SLUSC99A –JULY 2016–REVISED JANUARY 2017
Documentation Support (continued)
3. UCD3138 Monitoring and Communications Programmer’s Manual
Key Topics Covered in This Manual Include:
–
ADC12
–
–
–
–
–
Control, Conversion, Sequencing & Averaging
Digital Comparators
Temperature Sensor
PMBUS Addressing
Dual Sample and Hold
–
–
–
–
–
–
Miscellaneous Analog Controls (Current Sharing, Brown-Out, Clock-Gating)
PMBUS Interface
General Purpose Input Output (GPIO)
Timer Modules
PMBus
Register Map for all of the Above Peripherals in UCD3138A64
4. UCD3138 ARM and Digital System Programmer’s Manual
Key topics covered in this manual include:
–
Boot ROM and Boot Flash
–
–
–
–
–
BootROM Function
Memory Read/Write Functions
Checksum Functions
Flash Functions
Avoiding Program Flash Lock-Up
–
ARM7 Architecture
–
–
–
–
Modes of Operation
Hardware/Software Interrupts
Instruction Set
Dual State Inter-working (Thumb 16-bit Mode/ARM 32-bit Mode)
–
–
Memory and System Module
–
–
–
Address Decoder, DEC (Memory Mapping)
Memory Controller (MMC)
Central Interrupt Module
Register Map for all of the above peripherals in UCD3138A64 or UCD3138128
5. FUSION_DIGITAL_POWER_DESIGNER for UCD31XX Isolated Power Applications – User Guide
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
75
Product Folder Links: UCD3138128A
UCD3138128A
SLUSC99A –JULY 2016–REVISED JANUARY 2017
www.ti.com
Documentation Support (continued)
13.2.1.1 References
1. UCD3138064 Programmer’s Manual (Literature Number: SLUUAD8 )
2. UCD3138 Digital Power Peripherals Programmer’s Manual (Literature Number:SLUU995)
3. UCD3138 Monitoring & Communications Programmer’s Manual (Literature Number:SLUU996)
4. UCD3138 ARM and Digital System Programmer’s Manual (Literature Number:SLUU994)
5. FUSION_DIGITAL_POWER_DESIGNER for Isolated Power Applications (Literature Number: SLUA676)
6. Code Composer Studio Development Tools v3.3 – Getting Started Guide, (Literature Number: SPRU509H)
7. ARM7TDMI-S Technical Reference Manual
8. System Management Bus (SMBus) Specification
9. PMBus™ Power System Management Protocol Specification
10. UCD3138128 Programmers Manual (Literature Number: SLUUB54)
11. UCD3138 Family - Practical Design Guideline (Literature Number: SLUA779)
In addition to the tools and documentation described above, for the most up to date information regarding
evaluation modules, reference application firmware and application notes/design tips, please visit
http://www.ti.com/product/UCD3138A64.
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Trademarks
PMBus is a trademark of SMIF, Inc.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
76
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Product Folder Links: UCD3138128A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCD3138128APFC
UCD3138128APFCR
ACTIVE
ACTIVE
TQFP
TQFP
PFC
PFC
80
80
96
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
UCD3138128A
UCD3138128A
1000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCD3138128APFCR
TQFP
PFC
80
1000
330.0
24.4
15.0
15.0
1.5
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PFC 80
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
UCD3138128APFCR
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2022
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
UCD3138128APFC
PFC
TQFP
80
96
6 x 16
150
315 135.9 7620 18.7 17.25 18.3
Pack Materials-Page 3
PACKAGE OUTLINE
PFC0080A
TQFP - 1.2 mm max height
SCALE 1.250
PLASTIC QUAD FLATPACK
12.2
11.8
B
PIN 1 ID
80
61
A
1
60
12.2
11.8
14.2
TYP
13.8
20
41
40
21
76X 0.5
0.27
80X
0.17
4X 9.5
0.08
C A B
1.2 MAX
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1)
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215165/B 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PFC0080A
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
SYMM
80
61
80X (1.5)
1
60
80X (0.3)
SYMM
(13.4)
76X (0.5)
(R0.05) TYP
20
41
21
40
(13.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215165/B 06/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PFC0080A
TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
SYMM
80
61
80X (1.5)
1
60
80X (0.3)
SYMM
(13.4)
76X (0.5)
(R0.05) TYP
20
41
21
40
(13.4)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:6X
4215165/B 06/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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