UCC5871QDWJRQ1 [TI]
具有高级保护功能的汽车类 30A 隔离式 5.7kV VRMS IGBT/SiC MOSFET 栅极驱动器 | DWJ | 36 | -40 to 125;
| 型号： | UCC5871QDWJRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有高级保护功能的汽车类 30A 隔离式 5.7kV VRMS IGBT/SiC MOSFET 栅极驱动器 | DWJ | 36 | -40 to 125 栅极驱动 双极性晶体管 驱动器 |
| 文件： | 总30页 (文件大小：1851K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC5871-Q1
ZHCSRA0 –DECEMBER 2022
UCC5871-Q1 具有高级保护功能、适用于汽车应用的30A 隔离式IGBT/SiC
MOSFET 栅极驱动器
1 特性
2 应用
• 分离输出驱动器，以提供峰值为30A 的拉电流和峰
值为30A 的灌电流
• 混合动力汽车和电动汽车牵引逆变器
• 混合动力汽车和电动汽车电源模块
• 具有150ns（最大值）传播延迟和可编程最小脉冲
抑制的互锁和击穿保护
3 说明
UCC5871-Q1 器件是一款高度可配置的隔离式单通道
栅极驱动器，专用于驱动 EV/HEV 应用中的大功率
SiC MOSFET 和IGBT。该器件提供功率晶体管保护，
例如基于分流电阻器的过流保护、基于 NTC 的过热保
护以及 DESAT 检测，还在这些故障期间提供可选的软
关断或两级关断。为了进一步缩小应用尺寸，
UCC5871-Q1 可在开关期间提供 4A 有源米勒钳位，
在驱动器未通电时提供有源栅极下拉。集成的 10 位
ADC 可用于监控多达六个模拟输入以及栅极驱动器温
度，从而增强系统管理。集成的诊断和检测功能可简化
系统设计。这些功能的参数和阈值可使用 SPI 接口进
行配置，因此该器件几乎可与任何 SiC MOSFET 或
IGBT 一同使用。
• 支持初级侧和次级侧主动短路(ASC)
• 可配置功率晶体管保护
– 基于DESAT 的短路保护
– 基于分流电阻器的过流和短路保护
– 基于NTC 的过热保护
– 在功率晶体管发生故障时提供可编程软关断
(STO) 和两级关断(2LTOFF) 保护
• 功能安全合规型
– 专为功能安全应用开发
– 可帮助使ISO 26262 系统设计符合ASIL D 要求
的文档
• 集成型诊断：
– 针对保护比较器的内置自检(BIST)
– IN+ 至晶体管栅极路径完整性
– 功率晶体管阈值监测
器件信息
器件型号(1)
封装尺寸（标称值）
封装
– 内部时钟监测
UCC5871-Q1
SSOP (36)
12.8mm × 7.5mm
– 故障警报(nFLT1) 和警告(nFLT2) 输出
• 用于米勒钳位晶体管的集成式4A 有源米勒钳位或
可选的外部驱动器
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 高级高压钳位控制
VI/O
15V to 30V
• 内部和外部电源欠压和过压保护
• 有源输出下拉特性，在低电源或输入悬空的情况下
默认输出低电平
• 驱动器内核温度检测和过热保护
• 在VCM = 1000V 时，共模瞬态抗扰度(CMTI) 的最
小值为100kV/μs
VCC1
VCC2
GND2
GND1
MCU
DESAT
nFLT1
GND2
nFLT2/DOUT
VCECLP
IN+
IN-
VBST
OUTH
OUTL
VEE2
nCS
CLK
SDI
• 可通过SPI 对器件进行重新配置、验证、监控和诊
断
CLAMP
SDO
Safety
ASC
GND2
• 用于功率晶体管温度、电压、电流监测的集成式10
位ADC
ASC_EN
Controller
GND2
AIx[1:6]
VREF
VREG1
GND1
VREG2
VEE2
GND2
-12V to 0V
GND1
GND2
VEE2
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSF42
UCC5871-Q1
ZHCSRA0 –DECEMBER 2022
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Table of Contents
6.10 Switching Characteristics........................................16
6.11 Typical Characteristics............................................ 18
7 Layout.............................................................................22
7.1 Layout Guidelines..................................................... 22
7.2 Layout Example........................................................ 23
8 Device and Documentation Support............................24
8.1 Device Support......................................................... 24
8.2 Documentation Support............................................ 24
8.3 Receiving Notification of Documentation Updates....24
8.4 支持资源....................................................................24
8.5 Trademarks...............................................................24
8.6 Electrostatic Discharge Caution................................24
8.7 术语表....................................................................... 24
9 Mechanical, Packaging, and Orderable Information..24
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Power Ratings.............................................................7
6.6 Insulation Specifications............................................. 7
6.7 Safety Limiting Values.................................................8
6.8 Electrical Characteristics.............................................9
6.9 SPI Timing Requirements......................................... 16
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Pin Configuration and Functions
图5-1. DWJ 36-Pin SOIC Top View
表5-1. Pin Functions
PIN
NAME
I/O(1)
DESCRIPTION
NO.
1
GND1
NC
G
Primary Side Ground. Connect all GND1 pins together and to the PCB ground plane on the primary side.
No internal connection. Connect to GND1.
2
—
—
—
—
3
NC
No internal connection. Connect to GND1.
4
NC
No internal connection. Connect to GND1.
5
NC
No internal connection. Connect to GND1.
Active Short Circuit Enable Input. ASC_EN enables the ASC function and forces the output of the driver to
the state defined by the ASC input. If ASC is high, OUTH is pulled high. If ASC is low, OUTL is pulled low.
6
7
ASC_EN
nFLT1
I
Fault Indicator Output 1. nFLT1 is used to interrupt the host when a fault occurs. Faults that are unmasked
pull nFLT1 low when the fault occurs. nFLT1 is high when all faults are either non-existent or masked.
O
Fault Indicator Output 2. nFLT2 is used to interrupt the host when a fault occurs. Additionally, nFLT2 may
be configured as DOUT to provide the host controller a PWM signal with a duty cycle relative to the ADC
input of interest. Faults that are unmasked pull nFLT2 low when the fault occurs. nFLT2 is high when all
faults are either non-existent or masked.
8
nFLT2/DOUT
O
Primary Side Power Supply. Connect a 3V to 5.5V power supply to VCC1. Bypass VCC1 to GND1 with
ceramic bulk capacitance as close to the VCC1 pin as possible.
9
VCC1
ASC
IN–
P
I
Active Short Circuit Control Input. ASC sets the drive state when ASC_EN is high. If ASC is high, OUTH is
pulled high. If ASC is low, OUTL is pulled low.
10
11
Negative PWM Input. IN- is connected to the IN+ from the opposite arm of the half-bridge. If IN+ and IN-
overlap, the Shoot Through Protection (STP) fault is asserted.
I
Positive PWM Input. IN+ drives the state of the driver output. With the driver enabled, when IN+ is high,
OUTH is pulled high. When IN+ is low, OUTL is pulled low. Drive IN+ with a 1kHz to 50kHz PWM signal,
with a logic level determined by the VCC1 voltage. IN+ is connected to the IN- of the opposite arm of the
half-bridge. If IN+ and IN- overlap, the Shoot Through Protection (STP) fault is asserted.
12
IN+
I
SPI Clock. CLK is the clock signal for the main SPI interface. The SPI interface operates with clock rates
up to 4MHz.
13
14
15
CLK
nCS
SDI
I
I
I
SPI Chip Selection Input. nCS is an active low input used to activate the SPI peripheral device. Drive nCS
low during SPI communication. When nCS is high, the CLK and SDI inputs are ignored.
SPI Data Input. SDI is the data input for the main SPI interface. Data is sampled on the falling edge of CLK,
SDI must be in a stable condition to ensure proper communication.
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表5-1. Pin Functions (continued)
PIN
I/O(1)
DESCRIPTION
NO.
NAME
SPI Data Output. SDO is the data output for the main SPI interface. Data is clocked out on the falling edge
of CLK, SDO is changed with a rising edge of CLK.
16
SDO
O
Internal Voltage Regulator Output. VREG1 provides a 1.8V rail for internal primary-side circuits. Bypass
VREG1 to GND1 with at least 4.7µF of ceramic capacitance. Do not put any additional load on VREG1.
17
18
VREG1
GND1
P
G
Primary Side Ground. Connect all GND1 pins together and to the PCB ground plane on the primary side.
Secondary Negative Power Supply. Connect all VEE2 supply inputs together. Connect a -12V to 0V power
supply to VEE2. The total voltage rail from VCC2 to VEE2 must not exceed 30V. Bypass VEE2 to GND2
with at least 1uF of ceramic capacitance as close to the VEE1 pin as possible.
19
VEE2
P
Internal voltage regulator output. VREG2 provides a 1.8V rail for internal secondary-side circuits. Bypass
VREG2 to VEE2 with at least 4.7µF of ceramic capacitance. Do not put any additional load on VREG2.
20
21
22
23
24
25
26
VREG2
AI6
P
I
Analog Input 6. AI6 is a multi-function input. It is configurable as an input to the internal ADC, a power FET
current sense protection comparator input, and an ASC input for the secondary side.
Analog Input 5. AI5 is a multi-function input. It is configurable as an input to the internal ADC, a power FET
over temperature protection comparator input, and an ASC_EN input for the secondary side.
AI5
I
Analog Input 4. AI4 is a multi-function input. It is configurable as an input to the internal ADC and a power
FET current sense protection comparator input.
AI4
I
Analog Input 3. AI3 is a multi-function input. It is configurable as an input to the internal ADC and a power
FET current sense protection comparator input.
AI3
I
Analog Input 2. AI2 is a multi-function input. It is configurable as an input to the internal ADC and a power
FET current sense protection comparator input.
AI2
I
Analog Input 1. AI1 is a multi-function input. It is configurable as an input to the internal ADC and a power
FET current sense protection comparator input.
AI1
I
Internal ADC Voltage Regulator Output. VREF provides an internal 4V, reference for the ADC. Bypass
VREF to GND2 with at least 1uF of ceramic capacitance. If an external reference is desired, disable the
internal VREF using the SPI register, and connect a 4V reference supply to VREF. Loads up to 5mA on
VREF are allowed.
27
28
29
VREF
GND2
CLAMP
P
G
Gate Drive Common Input. Connect GND2 to the power FET source/ IGBT emitter. All AIx inputs, VREF,
and DESAT are referenced to GND2.
Miller Clamp Input. The CLAMP input is used to hold the gate of the power FET strongly to VEE2 while the
power FET is "off". CLAMP is configurable as an internal Miller clamp, or to drive an external clamping
circuit. When using the internal clamping function, connect CLAMP directly the power FET gate. When
configured as an external clamp, connect CLAMP to the gate of an external pulldown MOSFET.
IO
Secondary negative power supply. Connect all VEE2 supply inputs together. Connect a -12V to 0V power
supply to VEE2. The total voltage rail from VCC2 to VEE2 must not exceed 30V. Bypass VEE2 to GND2
with at least 1uF of ceramic capacitance as close to the VEE2 pin as possible. Additional capacitance may
be needed depending on the required drive current.
30
31
VEE2
P
Negative Gate Drive Voltage Output. When the driver is active, OUTL drives the gate of the power FET low
when INP is low. Connect OUTL to the gate of the power FET through a gate resistor. The value of the gate
resistor is chosen based on the slew rate required for the application.
OUTL
O
Positive Gate Drive Voltage Output. When the driver is active, OUTH drives the gate of the power FET high
when INP is high. Connect OUTH to the gate of the power FET through a gate resistor. The value of the
gate resistor is chosen based on the slew rate required for the application.
32
33
OUTH
VBST
O
P
Bootstrap Supply. VBST supplies power for the OUTH drive. Connect a 0.1µF ceramic capacitor between
VBST and OUTH.
VCE Clamp Input. VCECLP clamps to a diode above the VCC2 rail and indicates a fault when the voltage
at VCECLP is above the VCECLPth threshold. Bypass VCECLP to VEE2 with ceramic capacitor and, in
parallel, connect a resistor. Additionally, connect VCECLP to the anode of a zener diode to the collector of
the power FET.
34
35
VCECLP
I
Secondary Positive Power Supply. Connect a 15V to 30V power supply to VCC2. The total voltage rail from
VCC2 to VEE2 must not exceed 30V. Bypass VCC2 to GND2 and VCC2 to VEE2 with bulk ceramic
capacitance as close to the VCC2 pin as possible. Additional capacitance may be needed depending on
the required drive current.
VCC2
P
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PIN
表5-1. Pin Functions (continued)
I/O(1)
DESCRIPTION
NO.
NAME
Desaturation based Short Circuit Detection Input. DESAT is used to detect a short circuit in the power FET.
Bypass DESAT to GND2 with a ceramic capacitor to program the DESAT blanking time. In parallel, connect
a schottky diode with the cathode connected to the DESAT. Additionally, connect DESAT to a resistor to the
anode of a diode to the collector of the power FET to adjust the DESAT protection threshold. DESAT
detects a fault when the VCE voltage of the power FET exceeds the defined threshold while the power FET
is on.
36
DESAT
I
(1) P = Power, G = Ground, I = Input, O = Output, - = NA
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
VCC1
VCC2
VEE2
VSUP2
Supply voltage primary side referenced to GND1
6
33
V
V
V
V
V
Positive supply voltage secondary side referenced to GND2
Negative supply voltage output side referenced to GND2
–0.3
0.3
–15
Total supply voltage output side (VCC2 - VEE2
)
33
–0.3
VOUTH, VOUTL Voltage on the driver output pins referenced to GND2
VCC2+0.3
V
EE2–0.3
Voltage on IO pins (ASC, ASC_EN, CLK, IN+, IN-, nCS,
nFLTx, SDI, SDO) on primary side referenced to GND1
VIOP
VCC1+0.3
V
–0.3
VCLAMP
VDESAT
VCECLP
VREG1
VREG2
VREF
VBST
VAI
Voltage on the Miller clamp pin referenced to GND2
Voltage on DESAT referenced to GND2
Voltage on VCECLP referenced to GND2
Voltage on VREG1 referenced to GND1
Voltage on VREG2 referenced to VEE2
Voltage on VREF referenced to GND2
Voltage on VBST referenced to OUTH
Voltage on the analog inputs referenced to GND2
Junction temperature
VCC2 +0.3
V
V
V
V
EE2–0.3
–0.3
EE2–0.3
–0.3
–0.3
–0.3
-0.3
VCC2 +0.3
VCC2 +0.3
V
2
2
V
V
5.5
5.3
5.5
150
150
V
V
V
–0.3
–40
TJ
oC
oC
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Corner pins (GND1 and VEE2)
Other pins
V
Charged device model (CDM), per AEC
Q100-011
±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
VCC1
VCC2
VEE2
VSUP2
VIH
Supply voltage input side
3
15
5.5
Positive supply voltage secondary side (VCC2 - GND2)
Negative supply voltage output side (VEE2 - GND2)
30
V
0
V
–12
15
Total supply voltage output side (VCC2 - VEE2
)
30
V
High-level IO voltage (ASC, ASC_EN, IN+, IN-, nCS, SCLK, SDI)
Low-level IO voltage (ASC, ASC_EN, IN+, IN-, nCS, SCLK, SDI)
Source current for primary side outputs (nFLT2, SDO)
Sink current for primary side outputs (nFLTx, SDO)
Driver output source current from OUTH (1)
0.7*VCC1
0
VCC1
V
VIL
0.3*VCC1
V
IOHP
IOLP
IOH
5
5
mA
mA
A
15
15
IOL
Driver output sink current into OUTL (1)
A
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VAI*
Voltage on analog input (AI) pins referenced to GND2
Output voltage at VREG1 referenced to GND1 (2)
Output voltage at VREG2 referenced to VEE2(3)
Output voltage at VBST referenced to OUTH(4)
Voltage on the VREF pin vs GND2(5)
0
VREF+0.1
V
V
V
V
V
VVREG1
VVREG2
VVBST
VVREF
1.8
1.8
Vcc2 + 4.5
4
0
4.1
Common mode transient immunity rating (dV/dt rate across the isolation
barrier)
CMTI
100
kV/us
fPWM
fSPI
PWM input frequency (IN+ and IN- pins)
SPI clock frequency
50
4
kHz
MHz
TJ
Maximum junction temperature
PWM input pulse width (IN+ and IN- pins)
150
–40
℃
tPWM
250
ns
(1) External gate resistor needs to be used to limit the max drive current to be not more than 15A.
(2) Connect a decoupling capacitor of 0.1uF+4.7uF between VREG1 and GND1. Do not connect external supply.
(3) Connect a decoupling capacitor of 0.1uF+4.7uF between VREG2 and VEE2. Do not connect external supply.
(4) Connect a decoupling capacitor of 100nF between VBST and OUTH. Do not connect external supply.
(5) Connect a decoupling capacitor of 1.0uF on the VREF pin.
6.4 Thermal Information
UCC5870/UCC5871
THERMAL METRIC(1)
DWJ
UNIT
36 SOIC
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
50.6
17.5
21.3
5.3
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
20.2
N/A
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
500
50
UNIT
mW
mW
mW
PD
Maximum power dissipation (both sides) TA = 125C
PD1
PD2
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
TA = 125C
TA = 125C
450
6.6 Insulation Specifications
SPECIFIC
ATION
PARAMETER
TEST CONDITIONS
UNIT
PACKAGE SPECIFICATIONS
CLR
CPG
External clearance(1)
Shortest terminal-to-terminal distance through air
8
8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
External creepage(1)
DTI
CTI
Distance through the insulation
Comparative tracking index
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
> 17
600
µm
V
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6.6 Insulation Specifications (continued)
SPECIFIC
ATION
PARAMETER
TEST CONDITIONS
According to IEC60664-1
UNIT
Material group
I
I-IV
I-III
Rated mains voltage ≤600 VRMS
Rated mains voltage ≤1000 VRMS
Overvoltage category
Test 1
VIORM
Maximum repetitive peak isolation voltage
Maximum isolation working voltage
AC voltage (bipolar)
2121
1500
2121
VPK
VRMS
VDC
AC voltage (sine wave); time-dependent dielectric
breakdown (TDDB) test
VIOWM
DC voltage
VTEST = VIOTM
t=60s (qualification);
VTEST = 1.2 x VIOTM
,
VIOTM
Maximum transient isolation voltage
Maximum surge isolation voltage
8000
VPK
,
t=1s (100% production)
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM
VIOSM
8000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
≤5
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
qpd
Apparent charge
pC
Method b1: At routine test (100% production) and
preconditioning (type test),
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1s
Test 2
CIO
Barrier capacitance, input to output(2)
Insulation resistance, input to output(2)
2
pF
VIO = 0.4 × sin (2 πft), f = 1 MHz
VIO = 500 V, TA = 25°C
10^12
10^11
10^9
RIO
VIO = 500 V, 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
VTEST = VISO = VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = VRMS, t = 1 s (100%
production)
VISO
Withstand isolation voltage
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator onthe printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases.Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these
specifications.
(2) All pins on each side of the barrier tied together creating a two-pin device.
6.7 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
36-DWJ PACKAGE
R
θJA = 50.6°C/W, VVCC2 = 15V, TJ =
164
82
150°C, TA = 25°C
θJA = 50.6°C/W, VVCC2 = 30V, TJ =
150°C, TA = 25°C
IS
Safety output supply current
mA
R
PS
PS
PS
Safety input power
Safety output power
Safety total power
RθJA = 50.6°C/W, TJ = 150°C, TA = 25°C
RθJA = 50.6°C/W, TJ = 150°C, TA = 25°C
RθJA = 50.6°C/W, TJ = 150°C, TA = 25°C
83
2460
2543
mW
mW
mW
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Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TS
Maximum safety temperature
150
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the table is that of a
device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each
parameter:TJ = TA + RθJA × P, where P is the power dissipated in the device.TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the
maximum allowed junction temperature.PS = IS × VI, where VI is the maximum input voltage.
6.8 Electrical Characteristics
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIT+
UVLO threshold of VCC1 rising
UVLO threshold of VCC1 rising
UVLO threshold of VCC1 falling
UVLO threshold of VCC1 falling
UVOV1_LEVEL = 0
2.6
4.5
2.3
4.2
2.75
4.65
2.45
4.35
2.9
4.8
2.6
4.5
V
V
V
V
(UVLO1)
VIT+
UVOV1_LEVEL = 1
UVOV1_LEVEL = 0
UVOV1_LEVEL = 1
(UVLO1)
VIT-
(UVLO1)
VIT-
(UVLO1)
VHYS
UVLO threshold hysteresis of VCC1
VCC1 UVLO detection deglitch time
OVLO threshold of VCC1 falling
0.30
20
V
µs
V
(UVLO1)
tUVLO1
VIT-
UVOV1_LEVEL = 0
UVOV1_LEVEL = 1
UVOV1_LEVEL = 0
UVOV1_LEVEL = 1
3.7
5.2
4.0
5.5
3.85
4.0
5.5
4.3
5.8
(OVLO1)
VIT-
OVLO threshold of VCC1 falling
OVLO threshold of VCC1 rising
OVLO threshold of VCC1 rising
5.35
4.15
5.65
0.30
V
V
V
V
(OVLO1)
VIT+
(OVLO1)
VIT+
(OVLO1)
VHYS
OVLO threshold hysteresis of VCC1
VCC1 OVLO detection deglitch time
(OVLO1)
tOVLO1
20
16
14
12
10
15
13
11
9
µs
V
V
V
V
V
V
V
V
UVLO2TH = 00b
UVLO2TH = 01b
UVLO2TH = 10b
UVLO2TH = 11b
UVLO2TH = 00b
UVLO2TH = 01b
UVLO2TH = 10b
UVLO2TH = 11b
15.2
13.3
16.8
14.7
VIT+
UVLO threshold voltage of VCC2
rising with reference to GND2
(UVLO2)
11.4
12.6
9.5
10.5
14.25
12.35
10.45
8.55
15.75
13.65
11.55
9.45
VIT-
UVLO threshold voltage of VCC2
falling with reference to GND2
(UVLO2)
VHYS
UVLO threshold voltage hysteresis of
VCC2
1
V
(UVLO2)
tUVLO2
VCC2 UVLO detection deglitch time
20
23
21
19
17
µs
V
OVLO2TH = 00b
OVLO2TH = 01b
OVLO2TH = 10b
OVLO2TH = 11b
21.85
19.95
18.05
16.15
24.15
22.05
19.95
17.85
V
VIT-
OVLO threshold voltage of VCC2 falling
with reference to GND2
(OVLO2)
V
V
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
22.8
20.9
19
TYP
24
MAX
UNIT
OVLO2TH = 00b
OVLO2TH = 01b
OVLO2TH = 10b
OVLO2TH = 11b
25.2
23.1
21
V
V
V
V
22
VIT+
OVLO threshold voltage of VCC2 rising
with reference to GND2
(OVLO2)
20
17.1
18
18.9
VHYS
OVLO threshold voltage hysteresis of
VCC2
1
V
(OVLO2)
tOVLO2
VCC2 OVLO detection blanking time
20
–3
–5
–8
–10
–2
–4
–7
–9
µs
V
V
V
V
V
V
V
V
UVLO3TH = 00b
UVLO3TH = 01b
UVLO3TH = 10b
UVLO3TH = 11b
UVLO3TH = 00b
UVLO3TH = 01b
UVLO3TH = 10b
UVLO3TH = 11b
–3.15
–5.25
–8.4
–2.85
–4.75
–7.6
VIT-
UVLO threshold voltage of VEE2 falling
with reference to GND2
(UVLO3)
–10.5
–2.1
–9.5
–1.9
–4.2
–3.8
VIT+
UVLO threshold voltage of VEE2 rising
with reference to GND2
(UVLO3)
–7.35
–9.45
–6.65
–8.55
VHYS
UVLO threshold voltage hysteresis of
VEE2
1
V
(UVLO3)
tUVLO3
VEE2 UVLO detection blanking time
20
–5
µs
V
V
V
V
V
V
V
V
OVLO3TH = 00b
OVLO3TH = 01b
OVLO3TH = 10b
OVLO3TH = 11b
OVLO3TH = 00b
OVLO3TH = 01b
OVLO3TH = 10b
OVLO3TH = 11b
–5.25
–7.35
–10.5
–12.6
–6.3
–4.75
–6.65
–9.5
–7
VIT+
OVLO threshold voltage of VEE2 rising
with reference to GND2
(OVLO3)
–10
–12
–6
–11.4
–5.7
–8.4
–8
–7.6
VIT-
OVLO threshold voltage of VEE2
falling with reference to GND2
(OVLO3)
–11.55
–13.65
–11 –10.45
–13 –12.35
VHYS(OVL OVLO threshold voltage hysteresis of
1
V
VEE2
O3)
tOVLO3
IQVCC1
IQVCC2
IQVEE2
VEE2 OVLO detection blanking time
Quiescent Current of VCC1
Quiescent Current of VCC2
Quiescent Current of VEE2
20
µs
No switching, VCC1 = 5V
7.7
15
mA
No switching, VCC2 = 20V, VEE2 = -10V
No switching, VCC2 = 20V, VEE2 = -10V
mA
15
mA
tRP(VCC1) Slew rate of VCC1
tRP(VCC2) Slew rate of VCC2
tRP(VEE2) Slew rate of VEE2
LOGIC IO
0.1
0.1
0.1
V/µs
V/µs
V/µs
Input-high threshold voltage of primary
IO (IN+, IN-, ASC, and ASC_EN)
Input rising, VCC1 = 3.3V
Input rising, VREF=4V
VCC1 = 3.3V
0.7*VCC1
3.0
V
V
V
V
VIH
Input-high threshold voltage of
secondary IO in ASC mode (AI5, and
AI6)
Input-low threshold voltage of primary
IO (IN+, IN-, ASC, and ASC_EN)
0.3*VCC1
1.5
VIL
Input-low input-threshold voltage of
secondary IO in ASC mode (AI5 and
AI6)
Input falling
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input hysteresis voltage of primary IO
(IN+, IN-, ASC, and ASC_EN)
VCC1=3.3V
0.1*VCC1
V
VHYS(IN)
Input hysteresis voltage of secondary IO
in ASC mode (AI5, and AI6)
0.5
V
Leakage current on the input IO pins
ASC, ASC_EN, IN+, IN-, CLK, and SDI
VIO = GND1, VIO is the voltage on IO pins
VIO = VCC1, VIO is the voltage on IO pins
5
µA
ILI
Leakage current on nCS
Pullup resistance for nCS
5
µA
RPUI
40
40
100
kΩ
Pulldown resistance for ASC, ASC_EN,
IN+, IN-, CLK, and SDI
100
kΩ
RPDI
Pulldown resistance for AI5 and AI6 in
ASC mode
800
1200
kΩ
V
VOH
VOL
Output logic-high voltage (SDO)
4.5mA output current, VCC1 = 5V
4.5mA sink current, VCC1 = 5V
0.9*VCC1
Output logic-low voltage (nFLT1, nFLT2,
and SDO)
0.1*VCC1
V
FREQ_DOUT = 00b
FREQ_DOUT = 01b
FREQ_DOUT = 10b
FREQ_DOUT = 11b
VAI* = 0.36 V
13.9
27.8
55.7
111.4
10
kHz
kHz
kHz
kHz
%
fDOUT
Output frequency of DOUT pin
DDOUT
Duty of DOUT
VAI* = 1.8 V
50
%
VAI* = 3.24 V
90
%
Leakage current on pin nFLT*
Leakage current on pin SDO
Pullup resistance for pin nFLT*
nFLT* = HiZ, VCC1 on nFLT* pin
nCS = 1
5
5
µA
µA
–5
–5
40
ILO
RPUO
100
kΩ
DRIVER STAGE
High-level output voltage (OUT and
OUTH)
VCC2 –
VOUTH
VOUTL
IOUTH
IOUTL
IOUT = -100 mA
IOUT = 100 mA
V
mV
A
0.033
Low-level output voltage (OUT and
OUTL)
33
IN+= high, IN- = low, VCC2 - VOUTH = 5
V
Gate driver high output current
Gate driver low output current
15
15
IN- = low, IN + = high, VOUTL - VEE2 = 5
V
A
VOUTL - VEE2 = 6 V and STO_CURR =
00b, 100℃to 150℃
0.24
0.48
0.72
0.96
0.3
0.6
0.9
1.2
0.36
0.72
1.08
1.44
A
VOUTL - VEE2 = 6 V and STO_CURR =
01b, 100℃to 150℃
A
Driver low output current during SC and
OC faults
ISTO
VOUTL - VEE2 = 6 V and STO_CURR =
10b, 100℃to 150℃
A
VOUTL - VEE2 = 6 V and STO_CURR =
11b, 100℃to 150℃
A
ACTIVE MILLER CLAMP
Low-level clamp voltage (internal Miller
ICLP = 100 mA
100
mV
A
clamp)
VCLP
Miller clamp current
MCLPTH=11b, VCLAMP = VEE2+4 V
3.2
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
1.2
1.6
2.25
3
TYP
1.5
2
MAX
UNIT
MCLPTH = 00b
MCLPTH = 01b
MCLPTH = 10b
MCLPTH = 11b
1.8
2.5
3.75
5
V
V
V
V
Clamp threshold voltage with reference
to VEE2
VCLPTH
3
4
CLAMP output voltage in external Miller
clamp mode
VECLP
4.5
5
13
13
5.5
V
Ω
Ω
CLAMP pull-down resistance in external
Miller clamp mode
RECLP_PD
CLAMP pull-up resistance in external
Miller clamp mode
RECLP_PU
SHORT CIRCUIT CLAMPING
Clamping voltage (VOUTH - VCC2, VCLAMP IN+= high, IN- = low, tCLP = 10us, IOUTH or
VCLP-OUT
0.8
1.6
V
- VCC2
ACTIVE PULLDOWN
VOUTSD Active shut-down voltage on OUTL
VOUTSD Active shut-down voltage on OUTL
)
ICLAMP = 500 mA
IOUTL = 30mA, VCC2 = open
IOUTL = 0.1xIOUTL, VCC2 = open
1.55
2.5
V
V
DESAT SHORT-CIRCUIT PROTECTION
DESATTH = 0000b
DESATTH = 0001b
DESATTH = 0010b
DESATTH = 0011b
DESATTH = 0100b
DESATTH = 0101b
DESATTH = 0110b
DESATTH = 0111b
DESATTH = 1000b
DESATTH = 1001b
DESATTH = 1010b
DESATTH = 1011b
DESATTH = 1100b
DESATTH = 1101b
DESATTH = 1110b
DESATTH = 1111b
2.25
2.7
2.5
3
2.75
3.3
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3.15
3.6
3.5
4
3.85
4.4
4.05
4.5
4.5
5
4.95
5.5
4.95
5.4
5.5
6
6.05
6.6
DESAT detection threshold voltage with
respect to GND2
VDESATth
5.85
6.3
6.5
7
7.15
7.7
6.75
7.2
7.5
8
8.25
8.8
7.65
8.1
8.5
9
9.35
9.9
8.55
9
9.5
10
10.45
11
DESAT voltage with respect to GND2
VDESATL
1
0.645
0.7525
0.86
V
when OUTL is driven low
V(DESAT) - GND2 = 2 V,
DESAT_CHG_CURR = 00b
0.555
0.6475
0.74
0.6
0.7
0.8
1
mA
mA
mA
mA
V(DESAT) - GND2 = 2 V,
DESAT_CHG_CURR = 01b
ICHG
Blanking capacitor charging current
V(DESAT) - GND2 = 2 V,
DESAT_CHG_CURR = 10b
V(DESAT) - GND2 = 2 V,
DESAT_CHG_CURR = 11b
0.925
1.075
IDCHG
tLEB
tDESFLT
tDESFLT
Blanking capacitor discharging current
DESAT leading edge blanking time
DESAT pin glitch filter
V(DESAT) - GND2 = 6 V
14
127
90
mA
ns
158
158
316
250
190
401
DESAT_DEGLITCH=0
DESAT_DEGLITCH=1
ns
DESAT pin glitch filter
270
ns
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tDESAT
(90%)
DESAT protection reaction time from
event to action (includes deglitch time)
VDESAT>VDESATth to VOUTL 90% of VCC2
CLOAD = 1 nF, DESAT_DEGLITCH=0
,
160 +
tDESFLT
ns
OVERCURRENT PROTECTION
OCTH = 0000b
OCTH = 0001b
OCTH = 0010b
OCTH = 0011b
OCTH = 0100b
OCTH = 0101b
OCTH = 0110b
OCTH = 0111b
OCTH = 1000b
OCTH = 1001b
OCTH = 1010b
OCTH = 1011b
OCTH = 1100b
OCTH = 1101b
OCTH = 1110b
OCTH = 1111b
SCTH = 00b
170
220
270
315
360
410
460
520
570
610
660
710
760
807
855
902
460
700
945
1185
200
250
225
275
330
375
440
475
525
575
630
690
740
790
840
893
945
998
530
785
1050
1312
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
ns
300
350
400
450
500
550
VOCth
Over current detection threshold voltage
600
650
700
750
800
850
900
950
500
SCTH = 01b
750
VSCth
Short circuit protection threshold
SCTH = 10b
1000
1250
100
SCTH = 11b
SC_BLK = 00b
SC_BLK = 01b
SC_BLK = 10b
SC_BLK = 11b
OC_BLK = 000b
OC_BLK = 001b
OC_BLK = 010b
OC_BLK = 011b
OC_BLK = 100b
OC_BLK = 101b
OC_BLK = 110b
OC_BLK = 111b
200
ns
Short circuit protection blanking time with
reference to system clock
tSCBLK
400
ns
800
ns
500
ns
1000
1500
2000
2500
3000
5000
10000
150
ns
ns
ns
Over current protection blanking time
with reference to system clock
tOCBLK
ns
ns
ns
ns
tSCFLT
tOCFLT
Short circuit protection deglitch filter
Over current protection deglitch filter
50
50
200
200
ns
150
ns
Short circuit protection reaction time from VAIx > VSCth to VOUTL at 90% of VCC2,
175
+ tSCFLT
tSC(90%)
ns
ns
event to action (includes deglitch time)
CLOAD = 1nF, tSCBLK expired
Over current protection reaction time
from event to action (includes deglitch
time)
VAIx > VOCth to VOUTL at 90% of VCC2,
CLOAD = 1nF, tOCBLK expired
175 +
tOCFLT
tOC(90%)
TWO-LEVEL TURN-OFF PLATEAU VOLTAGE LEVEL
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
5
TYP
6
MAX
UNIT
V
2LOFF_VOLT = 000b
7
8
2LOFF_VOLT = 001b
6
7
V
2LOFF_VOLT = 010b
7
8
9
V
2LOFF_VOLT = 011b
8
9
10
11
12
13
14
V
Plateau voltage (with respect to GND2)
during two-level turnoff
V2 LOFF
2LOFF_VOLT = 100b
9
10
V
2LOFF_VOLT = 101b
10
11
12
11
V
2LOFF_VOLT = 110b
12
V
2LOFF_VOLT = 111b
13
V
2LOFF_TIME = 000b
150
300
450
600
1000
1500
2000
2500
0.3
0.6
0.9
1.2
ns
ns
ns
ns
ns
ns
ns
ns
A
2LOFF_TIME = 001b
2LOFF_TIME = 010b
2LOFF_TIME = 011b
Plateau voltage during two-level turnoff
hold time
t2 LOFF
2LOFF_TIME = 100b
2LOFF_TIME = 101b
2LOFF_TIME = 110b
2LOFF_TIME = 111b
0.24
0.48
0.72
0.96
0.36
0.72
1.08
1.44
2LOFF_CURR = 00b, 100℃to 150℃
2LOFF_CURR = 01b, 100℃to 150℃
2LOFF_CURR = 10b, 100℃to 150℃
2LOFF_CURR = 11b, 100℃to 150℃
A
Discharge current for transition to
plateau voltage level
I2 LOFF
A
A
HIGH VOLTAGE CLAMPING
VCE clamping threshold with respect to
VEE2
VCECLPTH
1.5
2.2
2.9
V
VCECLPHY
VCE clamping threshold hysteresis
VCE clamping intervention-time
200
mV
S
tVCECLP
30
ns
ns
ns
ns
ns
VCE_CLMP_HLD_TIME = 00b
VCE_CLMP_HLD_TIME = 01b
VCE_CLMP_HLD_TIME = 10b
VCE_CLMP_HLD_TIME = 11b
100
200
300
400
tVCECLP_H
VCE clamping hold on time
LD
OVERTEMPERATURE PROTECTION
TSD_SET Overtemperature protection set for driver
155
135
°C
°C
Overtemperature protection clear for
TSD_CLR
driver
TWN_SET Overtemperature warning set for driver
TWN_CLR Overtemperature warning clear for driver
130
110
°C
°C
THYS
Hysteresis for thermal comparators
20
0.1
0.3
0.6
1
°C
TEMP_CURR = 00b, Tj = 100C to 150C
TEMP_CURR = 01b, Tj = 100C to 150C
TEMP_CURR = 10b, Tj = 100C to 150C
TEMP_CURR = 11b, Tj = 100C to 150C
0.097
0.291
0.582
0.97
0.103
0.309
0.618
1.03
mA
mA
mA
mA
Bias current for temp sensing diode for
pins AI1, AI3, and AI5
ITO
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
0.95
TYP
1
MAX
1.05
UNIT
V
TSDTH_PS = 000b
TSDTH_PS = 001b
1.1875
1.425
1.6625
1.9
1.25
1.5
1.3125
1.575
1.8375
2.1
V
TSDTH_PS = 010b
V
TSDTH_PS = 011b
1.75
2
V
The threshold of power switch over
temperature protection.
VPS_TSDth
TSDTH_PS = 100b
V
TSDTH_PS = 101b
2.1375
2.375
2.6125
2.25
2.5
2.3625
2.625
2.8875
V
TSDTH_PS = 110b
V
TSDTH_PS = 111b
2.75
250
500
750
1000
V
PS_TSD_DEGLITCH = 00b
PS_TSD_DEGLITCH = 01b
PS_TSD_DEGLITCH = 10b
PS_TSD_DEGLITCH = 11b
ns
ns
ns
ns
tPS_TSDFL Power switch thermal shutdown deglitch
time
T
GATE VOLTAGE MONITOR
Gate monitor threshold value with
reference to VCC2
VGMH
IN+= high and IN- = low
IN + = low and IN- = high
V
V
–4
–3
–2
Gate monitor threshold value with
reference to VEE2
VGML
2
3
4
GM_BLK = 00b
GM_BLK = 01b
GM_BLK = 10b
GM_BLK = 11b
500
1000
2500
4000
250
ns
ns
Gate voltage monitor blanking time after
tGMBLK
driver receives PWM transition
ns
ns
tGMFLT
IVGTHM
Gate voltage monitor deglitch time
ns
Charge current for VGTH measurement VCC2 - VOUTH = 10V
2
mA
Delay time between VGTH measurement
control command to gate voltage
sampling point.
tdVGTHM
2300
µs
ADC
Full scale input voltage range for A1 to
A6
FSR
0
3.6
3.636
V
V
Accuracy of external reference directly
affects the accuracy of the ADC
Required voltage for external VREF
Internal VREF output voltage
4
4
VREF
V
External reference, VREF = 4V
Internal reference
-1.2
-4
1.2
9
LSB
LSB
LSB
LSB
INL
Integral non-linearity
External reference, VREF = 4V
Internal reference
-0.75
-0.75
0.75
0.75
DNL
Differential non-linearity
External ADC reference turn on delay
time from VCC2 > VIT-(UVLO2)
tADREFEXT
ITO2
VIT-(UVLO2) to 10% of VREF
10
µs
µA
ms
µs
Pull up current on AI2,4,6 pins
VAI2,4,6= VREF/2, ITO2_EN=H
ADC in hybrid mode configuration
10
0.4
5.1
7.5
15
IN+ hold time to cause switchover
between center mode and edge mode
thybrid
tCONV
tRR
Time to complete ADC conversion
Time between ADC conversions in Edge ADC in edge mode or hybrid mode (after
mode
µs
tHYBRID) configuration
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6.9 SPI Timing Requirements
MIN
NOM
MAX
UNIT
MHz
ns
fSPI
SPI clock frequency(1)
SPI clock period(1)
4
tCLK
250
90
90
50
30
45
tCLKH
tCLKL
CLK logic high duration(1)
CLK logic low duration(1)
ns
ns
tSU_NCS time between falling edge of nCS and rising edge of CLK(1)
ns
tSU_SDI
tHD_SDI
tD_SDO
setup time of SDI before the falling edge of CLK(1)
SDI data hold time (1)
ns
ns
time delay from rising edge of CLK to data valid at SDO(1)
60
ns
tHD_SDO SDO output hold time(1)
40
50
ns
tHD_NCS time between the falling edge of CLK and rising edge of nCS(1)
ns
tHI_NCS
tACC
SPI transfer inactive time(1)
250
ns
nCS low to SDO out of high impedance(1)
time between rising edge of nCS and SDO in tri-state(1)
60
30
80
50
ns
tDIS
ns
(1) Ensured by bench characterization.
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
OUTH rise time
OUTL fall time
TEST CONDITIONS
MIN
TYP
MAX
150
150
150
50
UNIT
ns
tr
tf
CLOAD = 10 nF
CLOAD = 10 nF
ns
tPLH, tPHL Propagation delay from INP to OUTx
CLOAD = 0.1 nF, tGLITCH_IO = 00b
CLOAD = 0.1 nF
ns
tsk(p)
tsk-pp
fmax
Pulse skew |tPHL - tPLH
|
20
20
ns
Part-to-part skew - same edge
Maximum switching frequency
CLOAD = 0.1 nF
50
ns
CLOAD = 0.1 nF, ADC disabled
50
kHz
Delay from fault detection to nFLT1 pin
goes LOW.
tdFLT1
tdFLT2
5
CLOAD = 100pF, REPU = 10kΩ
CLOAD = 100pF, REPU = 10kΩ
μs
μs
μs
Delay from fault detection to nFLT2 pin
goes LOW.
25
Required hold time for ASC after
ASC_EN transition
tASC_EN
1
tASC_DLY
ASC rising
ASC falling
AI6 rising
AI6 falling
2
μs
μs
μs
μs
Delay from the ASC edge to OUTx
transition (primary side)
0.1
1.8
0.3
tASC_DLY
Delay from the AI6 (ASC) edge to OUTx
transition (secondary side)
PWM input mute time in case of DESAT,
SC, and PS_TSD fault
tMUTE
PWM_MUTE_EN = 1
10
ms
IO_DEGLITCH = 00b
IO_DEGLITCH = 01b
IO_DEGLITCH = 10b
IO_DEGLITCH = 11b
TDEAD = 000000b
TDEAD = 000001b
TDEAD = 000010b
TDEAD = 000011b
TDEAD = 000100b
TDEAD = 111111b
0
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Deglitch time for the primary side IO pins
(exclude nCS, CLK, SDI, and SDO pins)
tGLITCH_IO
140
210
0
93
159
105
175
245
315
4445
154
228
tDEAD
Dead time for shoot through protection
225
302
291
376
4178.3
4748.8
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6.10 Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System start-up time (from power ready
to nFLTx pins go high)
tSTARTUP
tVREGxOV
5
ms
VREG1 and VREG2 overvoltage
detection deglitch time
30
μs
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6.11 Typical Characteristics
图6-1. IOUTH vs. Temperature
图6-2. IOUTL vs. Temperature
图6-3. Internal Miller Clamp Current vs. Temperature
图6-4. VCC1 Quiescent Current vs. Temperature
图6-5. VCC2 Quiescent Current vs. Temperature
图6-6. Propagation Delay vs. Temperature
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6.11 Typical Characteristics (continued)
图6-7. Rise/Fall Time vs. Temperature
图6-8. UVLO Threshold Error vs. Temperature
图6-9. UVLO2 Error vs. Temperature
图6-10. VEE2 UVLO Error vs. Temperature
图6-12. VCC2 OVLO Error vs. Temperature
图6-11. VCC1 OVLO Error vs. Temperature
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6.11 Typical Characteristics (continued)
图6-14. DESAT Threshold Error vs. Temperature
图6-13. VEE2 OVLO Error vs. Temperature
图6-15. OC Threshold Error vs. Temperature
图6-16. SC Threshold Error vs. Temperature
图6-18. VCECLP Intervention Time vs. Temperature
图6-17. Overcurrent Protection Response Time vs. Temperature
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6.11 Typical Characteristics (continued)
图6-19. nFLT1 Response Time vs Temperature
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7 Layout
7.1 Layout Guidelines
One must pay close attention to PCB layout in order to achieve optimum performance for the device.
7.1.1 Component Placement
• Low-ESR and low-ESL capacitors must be connected close to the device between the VCC1 and GND1 pins
and between the VCC2, VEE2 and GND2 pins to support high peak currents when turning on the external
power transistor.
• Place the VBST and VREF caps as close to the device as possible.
7.1.2 Grounding Considerations
• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This decreases the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
• Pay attention to high current path that includes the bootstrap capacitor. The bootstrap capacitor is recharged
on a cycle-by-cycle basis through the diode by the VCC2 bypass capacitor. This recharging occurs in a short
time interval and involves a high peak current. Minimizing this loop length and area on the circuit board is
important for ensuring reliable operation.
7.1.3 High-Voltage Considerations
• To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB
traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination
that may compromise the UCC51870’s isolation performance.
• For half-bridge, or high-side/low-side configurations, where the high-side and low-side drivers could operate
with a DC-link voltage up to 1000 VDC, one should try to increase the creepage distance of the PCB layout
between the high and low-side PCB traces.
7.1.4 Thermal Considerations
• The power dissipated by the device is directly proportional to the drive voltage, heavy capacitive loading,
and/or high switching frequency. Proper PCB layout helps dissipate heat from the device to the PCB and
minimize junction to board thermal impedance (θJB).
• Increasing the PCB copper connecting to VCC2 and VEE2 is recommended, with priority on maximizing the
connection to VEE2. However, high voltage PCB considerations mentioned above must be maintained.
• If there are multiple layers in the system, it is also recommended to connect the VCC2 and VEE2 to internal
ground or power planes through multiple vias of adequate size. However, keep in mind that there shouldn’t
be any traces/coppers from different high voltage planes overlapping.
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7.2 Layout Example
图7-1. Layout Example
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8 Device and Documentation Support
8.1 Device Support
8.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
8.2 Documentation Support
8.2.1 Related Documentation
For related documentation see the following:
• Digital Isolator Design Guide
• Isolation Glossary
• Documentation available to aid ISO 26262 system design up to ASIL D
8.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
8.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
8.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PUCC5871QDWJRQ1
UCC5871QDWJRQ1
ACTIVE
ACTIVE
SSOP
SSOP
DWJ
DWJ
36
36
750
750
TBD
Call TI
Call TI
-40 to 125
-40 to 125
Samples
Samples
RoHS & Green
NIPDAU
Level-3-260C-168 HR
UCC5871Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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