首页 |元器件品牌

UCC5350MCQDWVQ1 [TI]

适用于 IGBT/SiC 且具有米勒钳位或分离输出的汽车类 ±5A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125;
UCC5350MCQDWVQ1
型号： UCC5350MCQDWVQ1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

适用于 IGBT/SiC 且具有米勒钳位或分离输出的汽车类 ±5A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125

栅极驱动 双极性晶体管 驱动器
文件： 总47页 (文件大小：2371K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
UCC5350-Q1 适用于SiC/IGBT 器件和汽车应用的  
单通道隔离式栅极驱动器  
1 特性  
2 应用  
• 5kVRMS 和3kVRMS 单通道隔离式栅极驱动器  
• 符合面向汽车应用的AEC-Q100 标准  
• 车载充电器  
• 适用于电动汽车的牵引逆变器  
• 直流充电站  
• HVAC  
• 加热器  
– 温度等级1  
– HBM ESD 分类等级H2  
– CDM ESD 分类等级C6  
• 特性选项  
3 说明  
– 分离输出，8V UVLO (UCC5350SB-Q1)  
– 米勒钳位，12V UVLO (UCC5350MC-Q1)  
UCC5350-Q1 是一款单通道隔离式栅极驱动器，具有  
5A 最小峰值拉电流和 5A 最小峰值灌电流，专为驱动  
MOSFET 、IGBT 和 SiC MOSFET 而设计。  
UCC5350-Q1 具有米勒钳位或分离输出选项。CLAMP  
引脚除了可将晶体管栅极连接到输出端之外，还用于将  
栅极连接到内部 FET，以防止米勒电流造成假接通。  
借助分离输出选项，可以使用 OUTH 和 OUTL 引脚单  
独控制栅极电压的上升和下降时间。  
• ±5A 最小峰值电流驱动强度  
• 3V 至15V 输入电源电压  
• 驱动器电源电压高达33V  
– 8V 和12V UVLO 选项  
• 100V/ns 最小CMTI  
• 输入引脚具有负5V 电压处理能力  
• 100ns（最大值）的传播延迟和<25ns 的器件间延  
迟
• 8 引脚DWV（8.5mm 爬电）  
和D（4mm 爬电）封装  
• 隔离栅寿命> 40 年  
器件信息  
封装尺寸  
（标称  
值）  
封装(1)  
器件版本  
特性  
7.5mm ×  
5.85mm  
DWV SOIC-8  
D SOIC-8  
米勒钳位，12V  
• 安全相关认证：  
UCC5350MC-Q1  
UCC5350SB-Q1  
UVLO  
3.91mm x  
4.9mm  
– 符合UL 1577 标准且长达1 分钟的5000VRMS  
DWV 和3000VRMS  
隔离等级  
D
3.91mm x  
4.9mm  
分离输出，8V  
UVLO  
D SOIC-8  
• CMOS 输入  
• 工作结温：–40°C 至+150°C  
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附  
录。  
功能方框图（S 和M 版本）  
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问  
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。  
English Data Sheet: SLUSE29  
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
Table of Contents  
9 Detailed Description......................................................18  
9.1 Overview...................................................................18  
9.2 Functional Block Diagram.........................................18  
9.3 Feature Description...................................................19  
9.4 Device Functional Modes..........................................23  
10 Application and Implementation................................25  
10.1 Application Information........................................... 25  
10.2 Typical Application.................................................. 25  
11 Power Supply Recommendations..............................31  
12 Layout...........................................................................31  
12.1 Layout Guidelines................................................... 31  
12.2 Layout Example...................................................... 32  
12.3 PCB Material...........................................................34  
13 Device and Documentation Support..........................35  
13.1 Device Support....................................................... 35  
13.2 Documentation Support.......................................... 35  
13.3 Certifications........................................................... 35  
13.4 接收文档更新通知................................................... 35  
13.5 支持资源..................................................................35  
13.6 Trademarks.............................................................35  
13.7 Electrostatic Discharge Caution..............................35  
13.8 术语表..................................................................... 35  
1 特性................................................................................... 1  
2 应用................................................................................... 1  
3 说明................................................................................... 1  
4 Revision History.............................................................. 2  
5 说明（续）.........................................................................3  
6 Pin Configuration and Function.....................................4  
7 Specifications.................................................................. 5  
7.1 Absolute Maximum Ratings........................................ 5  
7.2 ESD Ratings............................................................... 5  
7.3 Recommended Operating Conditions.........................5  
7.4 Thermal Information....................................................5  
7.5 Power Ratings.............................................................6  
7.6 Insulation Specifications for D Package......................6  
7.7 Insulation Specifications for DWV Package................8  
7.8 Safety-Related Certifications For D Package............. 9  
7.9 Safety-Related Certifications For DWV Package........9  
7.10 Safety Limiting Values...............................................9  
7.11 Electrical Characteristics.........................................10  
7.12 Switching Characteristics........................................11  
7.13 Insulation Characteristics Curves........................... 12  
7.14 Typical Characteristics............................................12  
8 Parameter Measurement Information..........................16  
8.1 Propagation Delay, Inverting, and Noninverting  
Configuration...............................................................16  
4 Revision History  
注：以前版本的页码可能与当前版本的页码不同  
Changes from Revision C (June 2022) to Revision D (August 2022)  
Page  
• 将UCC5350SB-Q1 从“预告信息”更改为“量产数据”..................................................................................1  
Changes from Revision B (June 2020) to Revision C (June 2022)  
Page  
• 添加了UCC5350SBQDRQ1 器件的预告信息.................................................................................................... 1  
• 添加了节5 ......................................................................................................................................................... 3  
• Added the UCC5350SB device to 节6 ..............................................................................................................4  
• Added SB-Q1 D package power ratings.............................................................................................................6  
• Added SB-Q1 insulation specs...........................................................................................................................6  
• Added the UL certificate number for the D package...........................................................................................9  
• Added the UL certificate number for the DWV package.....................................................................................9  
• Added SB-Q1 D package safety limiting values................................................................................................. 9  
• Added SB-Q1 parameters................................................................................................................................ 10  
• Added minimum pulse width specs...................................................................................................................11  
• Added 表9-4 ....................................................................................................................................................23  
• Added SB-Q1 ESD figure ................................................................................................................................ 23  
• Added typical application circuit for SB-Q1.......................................................................................................25  
Copyright © 2022 Texas Instruments Incorporated  
2
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
5 说明（续）  
UCC5350-Q1 采用 4mm SOIC-8 (D) 或 8.5mm 宽体 SOIC-8 (DWV) 封装，可分别支持高达 3kVRMS 和 5kVRMS  
的隔离电压。输入侧通过SiO2 电容隔离技术与输出侧相隔离，隔离栅使用寿命超过40 年。UCC5350-Q1 非常适  
用于在高压牵引逆变器和车载充电器等应用中驱动IGBT 或MOSFET。  
与光耦隔离器相比，UCC5350-Q1 器件的器件间偏移更低，传播延迟更小，工作温度更高，并且CMTI 更高。  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
3
Product Folder Links: UCC5350-Q1  
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
6 Pin Configuration and Function  
VCC1  
IN+  
1
2
3
4
8
7
6
5
VEE2  
CLAMP  
OUT  
INœ  
GND1  
VCC2  
Not to scale  
图6-1. UCC5350MC-Q1 8-Pin SOIC Top View  
VCC1  
IN+  
1
2
3
4
8
7
6
5
VEE2  
OUTL  
OUTH  
VCC2  
INœ  
GND1  
Not to scale  
图6-2. UCC5350SB-Q1 8-Pin SOIC Top View  
表6-1. Pin Functions  
PIN  
NO.  
NO.  
TYPE(1)  
DESCRIPTION  
NAME  
UCC5350MC-Q1  
UCC5350SB-Q1  
Active Miller-clamp input used to prevent false turn-on of the power  
switches found on the 'M' version.  
CLAMP  
GND1  
7
I
—
Input ground. All signals on the input side are referenced to this  
ground.  
4
2
4
G
Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS  
input threshold. This pin is pulled low internally if left open. Use 表9-4  
to understand the input and output logic of these devices.  
IN+  
2
3
I
I
Inverting gate-drive voltage control input. The IN–pin has a CMOS  
input threshold. This pin is pulled high internally if left open. Use 表9-4  
to understand the input and output logic of these devices.  
3
IN–  
OUT  
6
O
O
O
Gate-drive output found on the 'M' version  
—
6
OUTH  
OUTL  
Gate-drive pullup output found on the 'S' version  
Gate-drive pulldown output found on the 'S' version  
—
—
7
Input supply voltage. Connect a locally decoupled capacitor to GND1.  
Use a low-ESR or ESL capacitor located as close to the device as  
possible.  
VCC1  
VCC2  
VEE2  
1
5
8
1
5
8
P
P
G
Positive output supply rail. Connect a locally decoupled capacitor to  
VEE2. Use a low-ESR or ESL capacitor located as close to the device  
as possible.  
Ground pin. Connect to MOSFET source or IGBT emitter. Connect a  
locally decoupled capacitor from VCC2 to VEE2. Use a low-ESR or ESL  
capacitor located as close to the device as possible.  
(1) P = Power, G = Ground, I = Input, O = Output  
Copyright © 2022 Texas Instruments Incorporated  
4
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
7 Specifications  
7.1 Absolute Maximum Ratings  
Over operating free air temperature range (unless otherwise noted)(1)  
MIN  
MAX  
UNIT  
GND1 –  
Input bias pin supply voltage  
18  
V
V
CC1 –GND1  
0.3  
Driver bias supply  
Output signal voltage  
Input signal voltage  
35  
VCC2 + 0.3  
VCC1 + 0.3  
150  
V
V
V
V
V
CC2 –VEE2  
–0.3  
OUTH –VEE2, VOUTL –VEE2, VOUT –VEE2, VCLAMP –VEE2  
IN+ –GND1, VIN– –GND1  
V
EE2 –0.3  
GND1 –5  
–40  
V
(2)  
Junction temperature, TJ  
°C  
°C  
Storage temperature, Tstg  
150  
–65  
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply  
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If  
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and  
this may affect device reliability, functionality, performance, and shorten the device lifetime.  
(2) To maintain the recommended operating conditions for TJ, see the Thermal Information table.  
7.2 ESD Ratings  
VALUE  
±4000  
±1500  
UNIT  
Human-body model (HBM), per AEC Q100-002(1)  
Charged-device model (CDM), per AEC Q100-011  
Electrostatic  
discharge  
V(ESD)  
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.  
7.3 Recommended Operating Conditions  
Over operating free-air temperature range (unless otherwise noted)  
MIN  
3
NOM  
MAX  
15  
UNIT  
VCC1  
VCC2  
VCC2  
TJ  
Supply voltage, input side  
V
V
13.2  
9.5  
-40  
33  
Positive supply voltage output side (VCC2 –VEE2), UCC5350MC  
Positive supply voltage output side (VCC2 –VEE2), UCC5350SB  
Junction Temperature  
33  
V
150  
°C  
7.4 Thermal Information  
UCC5350-Q1  
THERMAL METRIC(1)  
D
DWV  
8 PINS  
119.8  
64.1  
UNIT  
8 PINS  
109.5  
43.1  
RθJA  
RθJC(top)  
RθJB  
ΨJT  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Junction–to-ambient thermal resistance  
Junction–to-case (top) thermal resistance  
Junction–to-board thermal resistance  
51.2  
65.4  
18.3  
37.6  
Junction–to-top characterization parameter  
Junction–to-board characterization parameter  
50.7  
63.7  
ΨJB  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application  
Report.  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
5
Product Folder Links: UCC5350-Q1  
 
 
 
 
 
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
7.5 Power Ratings  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
D Package (UCC5350MC-Q1)  
Maximum power dissipation on input and  
output  
PD  
1.14  
W
VCC1 = 15 V, VCC2 = 15 V, f = 2.1-MHz,  
50% duty cycle, square wave, 2.2-nF load  
PD1  
PD2  
Maximum input power dissipation  
Maximum output power dissipation  
0.05  
1.09  
W
W
D Package (UCC5350SB-Q1)  
Maximum power dissipation on input and  
output  
PD  
0.99  
W
VCC1 = 15 V, VCC2 = 15 V, f = 1.8-MHz,  
50% duty cycle, square wave, 2.2-nF load  
PD1  
PD2  
Maximum input power dissipation  
Maximum output power dissipation  
0.05  
0.94  
W
W
DWV Package (UCC5350MC-Q1)  
Maximum power dissipation on input and  
output  
PD  
1.04  
W
VCC1 = 15 V, VCC2 = 15 V, f = 1.9-MHz,  
50% duty cycle, square wave, 2.2-nF load  
PD1  
PD2  
Maximum input power dissipation  
Maximum output power dissipation  
0.05  
0.99  
W
W
7.6 Insulation Specifications for D Package  
VALUE  
PARAMETER  
TEST CONDITIONS  
UNIT  
MCQD  
SBQD  
CLR  
CPG  
External Clearance(1)  
External Creepage(1)  
mm  
mm  
Shortest pin–to-pin distance through air  
≥4  
≥4  
> 21  
Shortest pin–to-pin distance across the package  
surface  
DTI  
CTI  
Distance through the insulation Minimum internal gap (internal clearance)  
µm  
V
Comparative tracking index  
Material Group  
> 600  
I
> 400  
II  
DIN EN 60112 (VDE 0303–11); IEC 60112  
According to IEC 60664–1  
I-IV  
I-III  
Rated mains voltage ≤150VRMS  
Rated mains voltage ≤300VRMS  
Overvoltage category per IEC 60664-1  
DIN V VDE 0884–11: 2017–01(2)  
Maximum repetitive peak  
isolation voltage  
VIORM  
AC voltage (bipolar)  
990  
VPK  
AC voltage (sine wave); time dependent dielectric  
breakdown (TDDB) test  
700  
990  
VRMS  
VDC  
VPK  
Maximum isolation working  
voltage  
VIOWM  
DC Voltage  
Maximum transient isolation  
voltage  
VTEST = VIOTM, t = 60 s (qualification);  
VTEST = 1.2 × VIOTM, t = 1 s (100% production)  
VIOTM  
4242  
Maximum surge isolation  
Test method per IEC 62368-1, 1.2/50-µs  
waveform, VTEST = 1.3 × VIOSM (qualification)  
VIOSM  
4242  
VPK  
pC  
pF  
voltage(3)  
Method a: After I/O safety test subgroup 2/3,  
Vini = VIOTM, tini = 60 s  
Vpd(m) = 1.2 × VIORM, tm = 10 s  
≤5  
Method a: After environmental tests subgroup 1,  
Vini = VIOTM, tini = 60 s;  
Vpd(m) = 1.2 × VIORM, tm = 10 s  
≤5  
qpd  
Apparent charge(4)  
Method b1: At routine test (100% production) and  
preconditioning (type test),  
Vini = 1.2 x VIOTM, tini = 1 s;  
≤5  
Vpd(m) = 1.5 × VIORM, tm = 1 s  
Barrier capacitance, input to  
output(5)  
CIO  
1.2  
VIO = 0.4 × sin (2πft), f = 1 MHz  
Copyright © 2022 Texas Instruments Incorporated  
6
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
7.6 Insulation Specifications for D Package (continued)  
VALUE  
UNIT  
PARAMETER  
TEST CONDITIONS  
MCQD  
SBQD  
VIO = 500 V, TA = 25°C  
> 1012  
> 1011  
> 109  
2
Isolation resistance, input to  
output(5)  
RIO  
VIO = 500 V, 100°C ≤TA ≤125°C  
Ω
VIO = 500 V at TS = 150°C  
Pollution degree  
Climatic category  
40/125/21  
UL 1577  
VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO, t = 1 s  
(100% production)  
VISO  
Withstand isolation voltage  
3000  
VRMS  
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.  
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the  
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in  
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these  
specifications.  
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings  
shall be ensured by means of suitable protective circuits.  
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.  
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).  
(5) All pins on each side of the barrier tied together creating a two-pin device.  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
7
Product Folder Links: UCC5350-Q1  
 
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
UNIT  
7.7 Insulation Specifications for DWV Package  
VALUE  
DWV  
PARAMETER  
TEST CONDITIONS  
CLR  
CPG  
External Clearance(1)  
External Creepage(1)  
mm  
mm  
Shortest pin–to-pin distance through air  
≥8.5  
Shortest pin–to-pin distance across the package  
surface  
≥8.5  
DTI  
CTI  
Distance through the insulation  
Comparative tracking index  
Material Group  
Minimum internal gap (internal clearance)  
DIN EN 60112 (VDE 0303–11); IEC 60112  
According to IEC 60664–1  
> 21  
> 600  
I
µm  
V
I-III  
I-II  
Rated mains voltage ≤600VRMS  
Rated mains voltage ≤1000VRMS  
Overvoltage category per IEC 60664-1  
DIN V VDE 0884–11: 2017–01(2)  
Maximum repetitive peak  
isolation voltage  
VIORM  
AC voltage (bipolar)  
2121  
VPK  
AC voltage (sine wave); time dependent dielectric  
breakdown (TDDB) test  
1500  
2121  
7000  
VRMS  
VDC  
VPK  
Maximum isolation working  
voltage  
VIOWM  
DC Voltage  
Maximum transient isolation  
voltage  
VTEST = VIOTM, t = 60 s (qualification) ;  
VTEST = 1.2 × VIOTM, t = 1 s (100% production)  
VIOTM  
Maximum surge isolation  
Test method per IEC 62368-1, 1.2/50-µs waveform,  
VTEST = 1.6 × VIOSM (qualification)  
VIOSM  
8000  
VPK  
voltage(3)  
Method a: After I/O safety test subgroup 2/3,  
Vini = VIOTM, tini = 60 s  
≤5  
Vpd(m) = 1.2 × VIORM, tm = 10 s  
Method a: After environmental tests subgroup 1,  
Vini = VIOTM, tini = 60 s;  
Vpd(m) = 1.6 × VIORM, tm = 10 s  
≤5  
qpd  
Apparent charge (4)  
pC  
Method b1: At routine test (100% production) and  
preconditioning (type test),  
Vini = 1.2 x VIOTM, tini = 1 s;  
≤5  
Vpd(m) = 1.875 × VIORM, tm = 1 s  
Barrier capacitance, input to  
output(5)  
CIO  
RIO  
1.2  
pF  
VIO = 0.4 × sin (2πft), f = 1 MHz  
VIO = 500 V, TA = 25°C  
> 1012  
> 1011  
> 109  
Isolation resistance, input to  
output(5)  
VIO = 500 V, 100°C ≤TA ≤125°C  
VIO = 500 V at TS = 150°C  
Ω
Pollution degree  
Climatic category  
2
40/125/21  
UL 1577  
VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 ×  
VISO, t = 1 s (100% production)  
VISO  
Withstand isolation voltage  
5000  
VRMS  
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.  
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the  
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in  
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these  
specifications.  
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured  
by means of suitable protective circuits.  
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.  
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).  
(5) All pins on each side of the barrier tied together creating a two-pin device.  
Copyright © 2022 Texas Instruments Incorporated  
8
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
7.8 Safety-Related Certifications For D Package  
UL  
Recognized under UL 1577 Component Recognition Program  
Single protection, 3000 VRMS  
File Number: E181974  
7.9 Safety-Related Certifications For DWV Package  
UL  
Recognized under UL 1577 Component Recognition Program  
Single protection, 5000 VRMS  
File Number: E181974  
7.10 Safety Limiting Values  
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
D PACKAGE (UCC5350MC-Q1)  
R
θJA = 109.5°C/W, VCC2 = 15 V, TJ =  
Output side  
Output side  
73  
36  
150°C, TA = 25°C, see 图7-2  
IS  
Safety output supply current  
Safety output supply power  
mA  
RθJA = 109.5°C/W, VCC2 = 30 V, TJ =  
150°C, TA = 25°C, see 图7-2  
Input side  
Output side  
Total  
0.05  
1.09  
1.14  
R
θJA = 109.5°C/W, TJ = 150°C, TA = 25°C,  
PS  
TS  
W
see 图7-4  
Maximum safety  
temperature(1)  
150  
°C  
D PACKAGE (UCC5350SB-Q1)  
R
θJA = 109.5°C/W, VCC2 = 15 V, TJ =  
Output side  
Output side  
63  
31  
150°C, TA = 25°C, see 图7-2  
IS  
Safety output supply current  
Safety output supply power  
mA  
RθJA = 109.5°C/W, VCC2 = 30 V, TJ =  
150°C, TA = 25°C, see 图7-2  
Input side  
Output side  
Total  
0.05  
0.94  
0.99  
R
θJA = 109.5°C/W, TJ = 150°C, TA = 25°C,  
PS  
TS  
W
see 图7-4  
Maximum safety  
temperature(1)  
150  
°C  
DWV PACKAGE (UCC5350MC-Q1)  
R
θJA = 119.8°C/W, VI = 15 V, TJ = 150°C,  
Output side  
Output side  
66  
33  
TA = 25°C, see 图7-1  
Safety input, output, or supply  
current  
IS  
mA  
RθJA = 119.8°C/W, VI = 30 V, TJ = 150°C,  
TA = 25°C, see 图7-1  
Input side  
Output side  
Total  
0.05  
0.99  
1.04  
R
θJA = 119.8°C/W, TJ = 150°C, TA = 25°C,  
Safety input, output, or total  
power  
PS  
W
see 图7-3  
Maximum safety  
TS  
150  
°C  
temperature(1)  
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS  
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be  
exceeded. These limits vary with the ambient temperature, TA.  
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for  
leaded surface-mount packages. Use these equations to calculate the value for each parameter:  
TJ = TA + RθJA × P, where P is the power dissipated in the device.  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
9
Product Folder Links: UCC5350-Q1  
 
 
 
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
TJ(max) = TS = TA + RθJA × PS , where TJ(max) is the maximum allowed junction temperature.  
PS = IS × VI , where VI is the maximum input voltage.  
7.11 Electrical Characteristics  
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL = 100-pF, TJ =  
–40°C to +125°C (UCC5350MC-Q1), TJ = –40°C to +150°C (UCC5350SB-Q1), (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP MAX UNIT  
SUPPLY CURRENTS  
IVCC1  
IVCC2  
Input supply quiescent current  
1.67  
1.1  
2.4  
1.8  
mA  
mA  
Output supply quiescent  
current  
SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS  
VCC1 Positive-going UVLO  
VIT+(UVLO1)  
2.6  
2.5  
0.1  
2.8  
V
V
V
threshold voltage  
VCC1 Negative-going UVLO  
VIT–(UVLO1)  
2.4  
10.3  
7.3  
threshold voltage  
VCC1 UVLO threshold  
Vhys(UVLO1)  
hysteresis  
OUTPUT SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (UCC5350MC-Q1)  
VCC2 Positive-going UVLO  
VIT+(UVLO2)  
12  
11  
1
13  
V
V
V
threshold voltage  
VCC2 Negative-going UVLO  
VIT–(UVLO2)  
threshold voltage  
VCC2 UVLO threshold voltage  
Vhys(UVLO2)  
hysteresis  
OUTPUT SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (UCC5350SB-Q1)  
VCC2 Positive-going UVLO  
VIT+(UVLO2)  
8.7  
8.0  
0.7  
9.4  
V
V
V
threshold voltage  
VCC2 Negative-going UVLO  
VIT–(UVLO2)  
threshold voltage  
VCC2 UVLO threshold voltage  
Vhys(UVLO2)  
hysteresis  
LOGIC I/O  
Positive-going input threshold  
voltage (IN+, IN–)  
0.7 ×  
VCC1  
VIT+(IN)  
0.55 × VCC1  
0.45 × VCC1  
0.1 × VCC1  
V
V
Negative-going input threshold  
voltage (IN+, IN–)  
VIT–(IN)  
0.3 × VCC1  
Input hysteresis voltage (IN+,  
IN–)  
Vhys(IN)  
V
IIH  
IIL  
High-level input leakage at IN+ IN+ = VCC1  
40  
–40  
–80  
240  
µA  
IN–= GND1  
–240  
–310  
µA  
Low-level input leakage at IN–  
IN–= GND1 –5 V  
GATE DRIVER STAGE  
High-level output voltage  
VOH  
(VCC2 - OUT) and (VCC2 -  
OUTH)  
100  
5
240  
7
mV  
mV  
IOUT = –20 mA  
Low level output voltage (OUT  
and OUTL)  
VOL  
IN+ = low, IN–= high; IOUT = 20 mA  
5
5
5
10  
8.5  
10  
A
A
A
UCC5350MC, IN+ = high, IN–= low  
UCC5350SB, IN+ = high, IN–= low  
IN+ = low, IN–= high  
IOH  
IOL  
Peak source current  
Peak sink current  
Active Miller Clamp (UCC5350MC-Q1 only)  
Copyright © 2022 Texas Instruments Incorporated  
10  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
7.11 Electrical Characteristics (continued)  
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL = 100-pF, TJ =  
–40°C to +125°C (UCC5350MC-Q1), TJ = –40°C to +150°C (UCC5350SB-Q1), (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP MAX UNIT  
VCLAMP  
ICLAMP  
Low-level clamp voltage  
Clamp low-level current  
ICLAMP = 20 mA  
7
10  
mV  
A
VCLAMP = VEE2 + 15 V  
VCLAMP = VEE2 + 2 V  
5
5
10  
Clamp low-level current for low  
output voltage  
ICLAMP(L)  
10  
A
V
VCLAMP-TH  
Clamp threshold voltage  
2.1  
2.3  
1.3  
SHORT CIRCUIT CLAMPING  
Clamping voltage  
VCLP-OUT  
IN+ = high, IN–= low, tCLAMP = 10 µs,  
IOUT= 500 mA  
1
1.5  
0.9  
V
V
(VOUT –VCC2  
)
IN+ = low, IN–= high, tCLAMP = 10 µs,  
IOUT = –500 mA  
Clamping voltage  
( VEE2 –VOUT  
VCLP-OUT  
)
IN+ = low, IN–= high,  
IOUT = –20 mA  
1
ACTIVE PULLDOWN  
Active pulldown voltage on  
OUT  
VOUTSD  
IOUT = 0.1 × IOUT(typ), VCC2 = open  
1.8  
2.5  
V
7.12 Switching Characteristics  
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, TJ = –40°C to  
+125°C, (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
26  
UNIT  
ns  
tr  
Output-signal rise time  
Output-signal fall time  
Propagation delay, high  
Propagation delay, low  
UVLO recovery delay of VCC1  
UVLO recovery delay of VCC2  
Pulse width distortion  
CLOAD = 1 nF  
CLOAD = 1 nF  
10  
10  
65  
65  
30  
50  
tf  
22  
100  
100  
ns  
tPLH  
CLOAD = 100 pF  
CLOAD = 100 pF  
See 图9-7.  
ns  
tPHL  
ns  
tUVLO1_rec  
tUVLO2_rec  
µs  
µs  
See 图9-7.  
tPWD  
CLOAD = 100 pF  
CLOAD = 100 pF  
CLOAD = 100 pF  
1
1
20  
25  
ns  
ns  
ns  
|tPHL –tPLH  
|
tsk(pp)  
tPWmin1  
Part-to-part skew(1)  
No response at OUT where OUT  
<10% × VCC2  
8
No response at OUT where OUT  
≥90% × VCC2  
tPWmin2  
CMTI  
CLOAD = 100 pF  
38  
ns  
Common-mode transient immunity PWM is tied to GND or VCC1, VCM = 1200 V  
100  
120  
kV/µs  
(1) tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same  
direction while operating at identical supply voltages, temperature, input signals and loads guaranteed by characterization.  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
11  
Product Folder Links: UCC5350-Q1  
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
7.13 Insulation Characteristics Curves  
80  
80  
60  
40  
20  
0
VCC2=15V  
VCC2=30V  
VCC2=15V  
VCC2=30V  
60  
40  
20  
0
0
50  
100  
Ambient Temperature (èC)  
150  
200  
0
50  
100  
Ambient Temperature (èC)  
150  
200  
DT0h0e1r  
图7-1. Thermal Derating Curve for Limiting Current  
图7-2. Thermal Derating Curve for Limiting Current  
per VDE for DWV Package  
per VDE for D Package  
1500  
1200  
900  
600  
300  
0
1500  
1200  
900  
600  
300  
0
0
50  
100  
Ambient Temperature (èC)  
150  
200  
0
50  
100  
Ambient Temperature (èC)  
150  
200  
DT0h0e1r  
图7-4. Thermal Derating Curve for Limiting Power  
图7-3. Thermal Derating Curve for Limiting Power  
per VDE for D Package  
per VDE for DWV Package  
7.14 Typical Characteristics  
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD  
= 1 nF, TJ = –40°C to +125°C, (unless otherwise noted)  
16  
15  
14  
13  
12  
11  
10  
9
16  
15  
14  
13  
12  
11  
10  
9
8
8
14  
16  
18  
20  
22  
24  
VCC2 (V)  
26  
28  
30  
32  
34  
14  
16  
18  
20  
22  
24  
VCC2 (V)  
26  
28  
30  
32  
34  
IOH_  
IOL_  
CLOAD = 150 nF  
CLOAD = 150 nF  
图7-5. Output-High Drive Current vs Output  
图7-6. Output-Low Drive Current vs Output  
Voltage  
Voltage  
Copyright © 2022 Texas Instruments Incorporated  
12  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
1.5  
1.45  
1.4  
2.5  
2.45  
2.4  
1.35  
1.3  
2.35  
2.3  
1.25  
1.2  
2.25  
2.2  
1.15  
1.1  
2.15  
2.1  
1.05  
1
2.05  
2
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
Temperature (èC)  
Temperature (èC)  
ICC1  
UCC5  
IN+ = L  
IN+ = H  
IN–= H  
IN–= L  
图7-7. ICC1 Supply Current vs Temperature  
图7-8. ICC1 Supply Current vs Temperature  
1.8  
1.78  
1.76  
1.74  
1.72  
1.7  
2.1  
1.95  
1.8  
1.65  
1.5  
1.35  
1.2  
1.68  
1.66  
1.64  
1.62  
1.6  
1.05  
0.9  
0.75  
0.6  
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
Frequency (MHz)  
1
1.1  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
Temperature (èC)  
ICC1  
ICC2  
Duty Cycle = 50%  
T = 25°C  
IN+ = L  
IN–= H  
图7-9. ICC1 Supply Current vs Input Frequency  
图7-10. ICC2 Supply Current vs Temperature  
2
1.9  
1.8  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1
1.7  
1.69  
1.68  
1.67  
1.66  
1.65  
1.64  
1.63  
1.62  
1.61  
1.6  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
Frequency (MHz)  
1
1.1  
Temperature (èC)  
UCC5  
ICC2  
IN+ = H  
Duty Cycle = 50%  
T = 25°C  
IN–= L  
图7-12. ICC2 Supply Current vs Input Frequency  
图7-11. ICC2 Supply Current vs Temperature  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
13  
Product Folder Links: UCC5350-Q1  
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
1.48  
1.44  
1.4  
10  
9.6  
9.2  
8.8  
8.4  
8
1.36  
1.32  
1.28  
1.24  
1.2  
7.6  
7.2  
6.8  
6.4  
6
1.16  
1.12  
1.08  
1
2
3
4
5
6
7
Load Capacitance (nF)  
8
9
10  
11  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
Temperature (èC)  
ICC2  
tr_v  
fSW = 1 kHz  
图7-14. Rise Time vs Temperature  
图7-13. ICC2 Supply Current vs Load Capacitance  
9.25  
55  
54.5  
54  
9
8.75  
8.5  
8.25  
8
53.5  
53  
52.5  
52  
7.75  
7.5  
7.25  
7
51.5  
51  
50.5  
50  
6.75  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
Temperature (èC)  
Temperature (èC)  
tf_v  
tPLH  
图7-16. Propagation Delay tPLH vs Temperature  
图7-15. Fall Time vs Temperature  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
30  
27  
24  
21  
18  
15  
12  
9
6
3
0
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
0
1
2
3
4
5
Load Capacitance (nF)  
6
7
8
9
10  
Temperature (èC)  
tPHL  
tr_v  
fSW = 1 kHz  
图7-17. Propagation Delay tPHL vs Temperature  
RGH = 0 Ω  
RGL = 0 Ω  
图7-18. Rise Time vs Load Capacitance  
Copyright © 2022 Texas Instruments Incorporated  
14  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
25  
22.5  
20  
40  
36  
32  
28  
24  
20  
16  
12  
8
0mA  
5mA  
10mA  
15mA  
20mA  
17.5  
15  
12.5  
10  
7.5  
5
2.5  
0
-2.5  
-5  
-7.5  
-10  
-75  
4
-45  
-15  
15  
45  
75  
105  
135  
165  
Temperature (èC)  
0
0
D022  
1
2
3
4
5
6
Load Capacitance (nF)  
7
8
9
10  
图7-20. VCLAMP vs Temperature  
tf_v  
fSW = 1 kHz  
RGH = 0 Ω  
RGL = 0 Ω  
图7-19. Fall Time vs Load Capacitance  
3
2.75  
2.5  
2.25  
2
1.75  
1.5  
1.25  
1
0.75  
0.5  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
Temperature (èC)  
VCLM  
图7-21. VCLAMP-TH vs Temperature  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
15  
Product Folder Links: UCC5350-Q1  
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
8 Parameter Measurement Information  
8.1 Propagation Delay, Inverting, and Noninverting Configuration  
图 8-1 shows the propagation delay for noninverting configurations. 图 8-2 shows the propagation delay with the  
inverting configuration. These figures also demonstrate the method used to measure the rise (tr) and fall (tf)  
times.  
0 V  
INœ  
50%  
tf  
tr  
IN+  
90%  
50%  
10%  
OUT  
tPLH  
tPHL  
图8-1. Propagation Delay, Noninverting Configuration  
INœ  
50%  
IN+  
tf  
tr  
90%  
50%  
OUT  
10%  
tPLH  
tPHL  
图8-2. Propagation Delay, Inverting Configuration  
Copyright © 2022 Texas Instruments Incorporated  
16  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
8.1.1 CMTI Testing  
图8-3 and 图8-4 are simplified diagrams of the CMTI testing configuration.  
15 V  
5 V  
VCC2  
VCC1  
C1  
C2  
C3  
C4  
GND1  
OUTH  
PWM  
IN+  
OUTL  
VEE2  
INœ  
+
œ
VCM  
Copyright © 2017, Texas Instruments Incorporated  
图8-3. CMTI Test Circuit for Split Output (UCC5350SB)  
15 V  
5 V  
VCC2  
VCC1  
C1  
C2  
C3  
C4  
GND1  
OUT  
PWM  
IN+  
CLAMP  
VEE2  
INœ  
+
œ
VCM  
Copyright © 2017, Texas Instruments Incorporated  
图8-4. CMTI Test Circuit for Miller Clamp (UCC5350MC)  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
17  
Product Folder Links: UCC5350-Q1  
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
9 Detailed Description  
9.1 Overview  
The UCC5350-Q1 family of isolated gate drivers has two variations: split output, and Miller clamp. The isolation  
inside the UCC5350-Q1 is implemented with high-voltage SiO2-based capacitors. The signal across the isolation  
has an on-off keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide based  
isolation barrier (see 图 9-2). The transmitter sends a high-frequency carrier across the barrier to represent one  
digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after  
advanced signal conditioning and produces the output through a buffer stage. The UCC5350-Q1 also  
incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated  
emissions from the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital  
capacitive isolator, 图 9-1, shows a functional block diagram of a typical channel. 图 9-2 shows a conceptual  
detail of how the OOK scheme works.  
图 9-1 shows how the input signal passes through the capacitive isolation barrier through modulation (OOK) and  
signal conditioning.  
9.2 Functional Block Diagram  
Transmitter  
Receiver  
OOK  
Modulation  
TX IN  
SiO based  
2
RX OUT  
TX Signal  
Conditioning  
RX Signal  
Conditioning  
Envelope  
Detection  
Capacitive  
Isolation  
Barrier  
Emissions  
Reduction  
Techniques  
Oscillator  
图9-1. Conceptual Block Diagram of a Capacitive Data Channel  
TX IN  
Carrier signal through  
isolation barrier  
RX OUT  
图9-2. On-Off Keying (OOK) Based Modulation Scheme  
Copyright © 2022 Texas Instruments Incorporated  
18  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
VCC2  
UVLO2  
VCC1  
UVLO1  
VCC2  
IN+  
Level  
Shifting  
and  
Control  
Logic  
OUTH  
OUTL  
INœ  
GND1  
VEE2  
图9-3. Functional Block Diagram —Split Output  
VCC2  
UVLO2  
VCC1  
UVLO1  
VCC2  
IN+  
Level  
Shifting  
and  
Control  
Logic  
OUT  
INœ  
CLAMP  
2 V  
GND1  
VEE2  
图9-4. Functional Block Diagram —Miller Clamp  
9.3 Feature Description  
9.3.1 Power Supply  
The VCC1 input power supply supports a wide voltage range from 3 V to 15 V and the VCC2 output supply  
supports a voltage range from 13.2 V to 33 V (UCC5350MC) or 9.5 V to 33 V (UCC5350SB).  
For operation with unipolar supply, the VCC2 supply is connected to 15 V with respect to VEE2 for IGBTs, and 20  
V for SiC MOSFETs. The VEE2 supply is connected to 0 V. In this use case, the Miller clamp helps to prevent a  
false turn-on of the power switch without a negative voltage rail. The Miller clamping function is implemented by  
adding a low impedance path between the gate of the power device and the VEE2 supply. Miller current sinks  
through the clamp pin, which clamps the gate voltage to be lower than the turn-on threshold value for the gate.  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
19  
Product Folder Links: UCC5350-Q1  
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
9.3.2 Input Stage  
The input pins (IN+ and IN–) of the UCC5350-Q1 are based on CMOS-compatible input-threshold logic that is  
completely isolated from the VCC2 supply voltage. The input pins are easy to drive with logic-level control signals  
(such as those from 3.3-V microcontrollers), because the UCC5350-Q1 has a typical high threshold (VIT+(IN)) of  
0.55 × VCC1 and a typical low threshold of 0.45 × VCC1. A wide hysteresis (Vhys(IN)) of 0.1 × VCC1 makes for good  
noise immunity and stable operation. If either of the inputs are left open, 128 kΩof internal pull-down resistance  
forces the IN+ pin low and 128 kΩ of internal resistance pulls IN– high. However, TI still recommends  
grounding an input or tying to VCC1 if it is not being used for improved noise immunity.  
Because the input side of the UCC5350-Q1 is isolated from the output driver, the input signal amplitude can be  
larger or smaller than VCC2 provided that it does not exceed the recommended limit. This feature allows greater  
flexibility when integrating the gate-driver with control signal sources and allows the user to choose the most  
efficient VCC2 for any gate. However, the amplitude of any signal applied to IN+ or IN– must never be at a  
voltage higher than VCC1  
.
9.3.3 Output Stage  
The output stage of the UCC5350-Q1 features a pull-up structure that delivers the highest peak-source current  
when it is most needed which is during the Miller plateau region of the power-switch turn-on transition (when the  
power-switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-  
channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel  
MOSFET is to provide a brief boost in the peak-sourcing current, which enables fast turn-on. Fast turn-on is  
accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing  
states from low to high. 表9-1 lists the typical internal resistance values of the pull-up and pull-down structure.  
表9-1. UCC5350-Q1 On-Resistance  
DEVICE OPTION  
UCC5350MC-Q1  
UCC5350SB-Q1  
RNMOS  
1.54  
ROH  
ROL  
0.26  
0.26  
RCLAMP  
0.26  
UNIT  
Ω
12  
1.54  
12  
Not applicable  
Ω
The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device  
only. This parameter is only for the P-channel device, because the pull-up N-channel device is held in the OFF  
state in DC condition and is turned on only for a brief instant when the output is changing states from low to high.  
Therefore, the effective resistance of the UCC5350-Q1 pull-up stage during this brief turn-on phase is much  
lower than what is represented by the ROH parameter, which yields a faster turn-on. The turn-on-phase output  
resistance is the parallel combination ROH || RNMOS  
.
The pull-down structure in the UCC5350-Q1 is simply composed of an N-channel MOSFET. The output of the  
UCC5350-Q1 is capable of delivering, or sinking, 5-A peak current pulses. The output voltage swing between  
VCC2 and VEE2 provides rail-to-rail operation because of the MOS-out stage which delivers very low dropout.  
Copyright © 2022 Texas Instruments Incorporated  
20  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
图9-5. Output Stage—S Version  
UVLO2  
VCC2  
ROH  
Level  
Shifting  
and  
RNMOS  
OUT  
Control  
Logic  
ROL  
CLAMP  
VEE2  
2 V  
图9-6. Output Stage—M Version  
9.3.4 Protection Features  
9.3.4.1 Undervoltage Lockout (UVLO)  
UVLO functions are implemented for both the VCC1 and VCC2 supplies between the VCC1 and GND1, and VCC2  
and VEE2 pins to prevent an underdriven condition on IGBTs and MOSFETs. When VCC is lower than VIT+ (UVLO)  
at device start-up or lower than VIT–(UVLO) after start-up, the voltage-supply UVLO feature holds the effected  
output low, regardless of the input pins (IN+ and IN–) as shown in 表 9-2. The VCC UVLO protection has a  
hysteresis feature (Vhys(UVLO)). This hysteresis prevents chatter when the power supply produces ground noise;  
this allows the device to permit small drops in bias voltage, which occurs when the device starts switching and  
operating current consumption increases suddenly. 图9-7 shows the UVLO functions.  
表9-2. UCC5350-Q1 VCC1 UVLO Logic  
INPUTS  
OUTPUT  
CONDITION  
IN+  
H
OUT  
IN–  
L
L
L
L
L
L
H
V
CC1 –GND1 < VIT+(UVLO1) during device start-up  
H
H
L
L
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
21  
Product Folder Links: UCC5350-Q1  
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
表9-2. UCC5350-Q1 VCC1 UVLO Logic (continued)  
INPUTS  
OUTPUT  
CONDITION  
IN+  
H
OUT  
IN–  
L
L
L
L
L
L
H
V
CC1 –GND1 < VIT–(UVLO1) after device start-up  
H
H
L
L
表9-3. UCC5350-Q1 VCC2 UVLO Logic  
INPUTS  
OUTPUT  
CONDITION  
IN+  
H
L
OUT  
IN–  
L
L
L
L
L
L
L
L
L
H
H
L
V
CC2 –VEE2 < VIT+(UVLO2) during device start-up  
H
L
H
L
L
H
H
L
V
CC2 –VEE2 < VIT–(UVLO2) after device start-up  
H
L
When VCC1 or VCC2 drops below the UVLO1 or UVLO2 threshold, a delay, tUVLO1_rec or tUVLO2_rec, occurs on the  
output when the supply voltage rises above VIT+(UVLO) or VIT+(UVLO2) again. 图9-7 shows this delay.  
IN+  
IN+  
VIT+ (UVLO1)  
VCC1  
VCC1  
VIT (UVLO1)  
œ
VCC2  
VCC2  
VIT+ (UVLO2)  
VITœ (UVLO2)  
tUVLO2_rec  
tUVLO1_rec  
VOUT  
VOUT  
图9-7. UVLO Functions  
9.3.4.2 Active Pulldown  
The active pull-down function is used to pull the IGBT or MOSFET gate to the low state when no power is  
connected to the VCC2 supply. This feature prevents false IGBT and MOSFET turn-on on the OUT and CLAMP  
pins by clamping the output to approximately 2 V.  
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an  
active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the upper PMOS is  
resistively held off by a pull-up resistor while the lower NMOS gate is tied to the driver output through a 500-kΩ  
resistor. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS  
device, which is approximately 1.5 V when no bias power is available.  
Copyright © 2022 Texas Instruments Incorporated  
22  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
9.3.4.3 Short-Circuit Clamping  
The short-circuit clamping function is used to clamp voltages at the driver output and pull the active Miller clamp  
pins slightly higher than the VCC2 voltage during short-circuit conditions. The short-circuit clamping function helps  
protect the IGBT or MOSFET gate from overvoltage breakdown or degradation. The short-circuit clamping  
function is implemented by adding a diode connection between the dedicated pins and the VCC2 pin inside the  
driver. The internal diodes can conduct up to 500-mA current for a duration of 10 µs and a continuous current of  
20 mA. Use external Schottky diodes to improve current conduction capability as needed.  
9.3.4.4 Active Miller Clamp  
The active Miller-clamp function helps to prevent a false turn-on of the power switches caused by Miller current  
in applications where a unipolar power supply is used. The active Miller-clamp function is implemented by adding  
a low impedance path between the power-switch gate terminal and ground (VEE2) to sink the Miller current. With  
the Miller-clamp function, the power-switch gate voltage is clamped to less than 2 V during the off state. 图 10-2  
shows a typical application circuit of this function.  
9.4 Device Functional Modes  
表9-5 lists the functional modes for the UCC5350-Q1 assuming VCC1 and VCC2 are in the recommended range.  
表9-4. Function Table for UCC5350SB-Q1  
IN+  
Low  
X
OUTH  
Hi-Z  
OUTL  
Low  
IN–  
X
High  
Low  
Hi-Z  
Low  
High  
High  
High-Z  
表9-5. Function Table for UCC5350MC-Q1  
IN+  
Low  
X
OUT  
IN–  
X
Low  
Low  
High  
High  
Low  
High  
9.4.1 ESD Structure  
图 9-9 shows the multiple diodes involved in the ESD protection components of the UCC5350-Q1 device. This  
provides pictorial representation of the absolute maximum rating for the device.  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
23  
Product Folder Links: UCC5350-Q1  
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
VCC1  
1
VCC2  
5
2
3
6
7
IN+  
OUTH  
OUTL  
18 V  
35 V  
INœ  
5.5 V  
4
8
GND1  
VEE2  
图9-8. ESD Structure 'S' version  
VCC1  
1
VCC2  
5
2
6
IN+  
OUT  
20 V  
40 V  
INœ  
3
7
CLAMP  
5.5 V  
4
8
GND1  
VEE2  
图9-9. ESD Structure ' M' Version  
Copyright © 2022 Texas Instruments Incorporated  
24  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
10 Application and Implementation  
备注  
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定  
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。  
10.1 Application Information  
The UCC5350-Q1 is a simple, isolated gate driver for power semiconductor devices, such as MOSFETs, IGBTs,  
or SiC MOSFETs. The family of devices is intended for use in applications such as motor control, solar inverters,  
switched-mode power supplies, and industrial inverters.  
The UCC5350-Q1 has two pinout configurations, featuring split outputs and Miller clamp. The split outputs,  
OUTH and OUTL, are used to separately decouple the power transistor turn on and turn off commutations.  
The M version features active Miller clamping, which can be used to prevent false turn-on of the power  
transistors induced by the Miller current. The device comes in an 8-pin D and 8-pin DWV package and has  
creepage, or clearance, of 4 mm and 8.5 mm, respectively, which is suitable for applications where basic or  
reinforced isolation is required. The UCC5350-Q1 offers a 5-A minimum drive current.  
10.2 Typical Application  
The circuits in 图10-1 and 图10-2 show a typical application for driving IGBTs.  
15 V  
VCC2  
5 V  
C3  
C4  
VCC1  
C1  
C2  
GND1  
RGON  
OUTH  
OUTL  
RGOFF  
Signal Emitter  
Rin  
PWM  
IN+  
Cin  
INœ  
VEE2  
Power Emitter  
Copyright © 2017, Texas Instruments Incorporated  
图10-1. Typical Application Circuit for UCC5350SB-Q1 to Drive IGBT  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
25  
Product Folder Links: UCC5350-Q1  
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
15 V  
VCC2  
5 V  
VCC1  
C3  
C4  
C1  
C2  
GND1  
RG  
OUT  
Rin  
Signal Emitter  
Power Emitter  
PWM  
CLAMP  
IN+  
Cin  
INœ  
VEE2  
Copyright © 2017, Texas Instruments Incorporated  
图10-2. Typical Application Circuit for UCC5350MC-Q1 to Drive IGBT  
10.2.1 Design Requirements  
表10-1. UCC5350-Q1 Design Requirements  
PARAMETER  
VALUE  
UNIT  
V
VCC1  
3.3  
18  
V
V
CC2 –VEE2  
IN+  
3.3  
V
GND1  
150  
-
IN–  
Switching frequency  
Gate Charge of Power Device  
kHz  
nC  
126  
10.2.2 Detailed Design Procedure  
10.2.2.1 Designing IN+ and IN–Input Filter  
TI recommends that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the  
signal at the output. However, a small input filter, RIN-CIN, can be used to filter out the ringing introduced by  
nonideal layout or long PCB traces.  
Such a filter should use an RIN resistor with a value from 0 Ωto 100 Ωand a CIN capacitor with a value from 10  
pF to 1000 pF. In the example, the selected value for RIN is 51 Ω and CIN is 33 pF, with a corner frequency of  
approximately 100 MHz.  
When selecting these components, pay attention to the trade-off between good noise immunity and propagation  
delay.  
10.2.2.2 Gate-Driver Output Resistor  
The external gate-driver resistors, RG(ON) and RG(OFF) are used to:  
1. Limit ringing caused by parasitic inductances and capacitances  
2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery  
3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss  
4. Reduce electromagnetic interference (EMI)  
The output stage has a pull-up structure consisting of a P-channel MOSFET and an N-channel MOSFET in  
parallel. The combined typical peak source current is 10 A for UCC5350-Q1. Use 方程式 1 to estimate the peak  
source current.  
Copyright © 2022 Texas Instruments Incorporated  
26  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
V
− V  
EE2  
CC2  
+ R + R  
GON GFET_Int  
I
=
(1)  
OH  
R
R
NMOS  
OH  
where  
• RGON is the external turn-on resistance, which is 2.2 Ωin this example.  
• RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will  
assume 1.8Ωfor our example.  
• IOH is the typical peak source current which is the minimum value between 10 A, the gate-driver peak source  
current, and the calculated value based on the gate-drive loop resistance.  
In this example, the peak source current is approximately 3.36 A as calculated in 方程式2.  
V
− V  
EE2  
CC2  
+ R + R  
GON GFET_Int  
18 V  
I
=
=
≈ 3.36A  
(2)  
(3)  
OH  
1.54Ω 12Ω + 2.2Ω + 1.8Ω  
R
R
NMOS  
OH  
Similarly, use 方程式3 to calculate the peak sink current.  
V
− V  
EE2  
CC2  
I
=
R
OL  
+ R  
+ R  
OL  
GOFF GFET_Int  
where  
• RGOFF is the external turn-off resistance, which is 2.2 Ωin this example.  
• IOL is the typical peak sink current which is the minimum value between 10 A, the gate-driver peak sink  
current, and the calculated value based on the gate-drive loop resistance.  
In this example, the peak sink current is the minimum value between 方程式4 and 10 A.  
V
− V  
EE2  
+ R  
CC2  
18 V  
I
=
=
≈ 4.23A  
(4)  
OL  
R
+ R  
0.26Ω + 2.2Ω + 1.8Ω  
OL  
GOFF GFET_Int  
备注  
The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic  
inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot  
and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized.  
Conversely, the peak source and sink current is dominated by loop parasitics when the load  
capacitance (CISS) of the power transistor is very small (typically less than 1 nF) because the rising  
and falling time is too small and close to the parasitic ringing period.  
10.2.2.3 Estimate Gate-Driver Power Loss  
The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC5350-Q1 device and  
the power losses in the peripheral circuitry, such as the external gate-drive resistor.  
The PGD value is the key power loss which determines the thermal safety-related limits of the UCC5350-Q1  
device, and it can be estimated by calculating losses from several components.  
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as  
driver self-power consumption when operating with a certain switching frequency. The PGDQ parameter is  
measured on the bench with no load connected to the OUT pins at a given VCC1, VCC2, switching frequency, and  
ambient temperature. In this example, VCC1 is 3.3V and VCC2 is 18 V. The current on each power supply, with  
PWM switching from 0 V to 3.3 V at 150 kHz, is measured to be ICC1 = 1.67 mA and ICC2 = 1.11 mA . Therefore,  
use 方程式5 to calculate PGDQ  
.
PGDQ =VCC1 ì IVCC1 + (VCC2 - VEE2)ì ICC2 ö23.31mW  
(5)  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
27  
Product Folder Links: UCC5350-Q1  
 
 
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
The second component is the switching operation loss, PGDO, with a given load capacitance which the driver  
charges and discharges the load during each switching cycle. Use 方程式 6 to calculate the total dynamic loss  
from load switching, PGSW  
.
PGSW = (VCC2 - VEE2)ìQG ì fSW  
(6)  
where  
• QG is the gate charge of the power transistor at VCC2  
.
So, for this example application the total dynamic loss from load switching is approximately 340 mW as  
calculated in 方程式7.  
PGSW = 18 V ì126 nCì150 kHz = 340 mW  
(7)  
QG represents the total gate charge of the power transistor and is subject to change with different testing  
conditions. The UCC5350-Q1 gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO is equal to PGSW  
if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the gate driver-loss  
will be dissipated inside the UCC5350-Q1. If an external turn-on and turn-off resistance exists, the total loss is  
distributed between the gate driver pull-up/down resistance, external gate resistance, and power-transistor  
internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink  
current is not saturated to 10 A, however, it will be non-linear if the source/sink current is saturated. The gate  
driver loss will be estimated in the case in which it is not saturated as given in 方程式8.  
P
R
R
R
GSW  
2
OH  
+ R  
NMOS  
+ R  
GFET_Int  
OL  
+ R  
P
=
+
(8)  
GDO  
R
+ R  
GOFF  
R
R
NMOS  
OL  
GFET_Int  
OH  
GON  
In this design example, all the predicted source and sink currents are less than 10 A, therefore, use 方程式 9 to  
estimate the gate-driver loss.  
≈
∆
«
’
÷
◊
340 mW  
2
12 W ||1.54 W  
12 W ||1.54 W + 2.2 W +1.8 W 0.26 W + 2.2 W +1.8 W  
0.26 W  
PGDO  
=
+
ö53.66 mW  
(9)  
where  
• VOUTH/L(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is  
saturated for some time, this value can be simplified as a constant-current source (10 A at turnon and turnoff)  
charging or discharging a load capacitor. Then, the VOUTH/L(t) waveform will be linear and the TR_Sys and  
TF_Sys can be easily predicted.  
Use 方程式10 to calculate the total gate-driver loss dissipated in the UCC5350-Q1 gate driver, PGD  
.
PGD = PGDQ + PGDO = 25.31mW + 53.66mW = 78.97mW  
(10)  
(11)  
10.2.2.4 Estimating Junction Temperature  
Use the equation below to estimate the junction temperature (TJ) of the UCC5350-Q1 family.  
TJ = TC + YJT ìPGD  
where  
• TC is the UCC5350-Q1 case-top temperature measured with a thermocouple or some other instrument.  
• ΨJT is the junction-to-top characterization parameter from the Thermal Information table.  
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance  
(RθJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal  
Copyright © 2022 Texas Instruments Incorporated  
28  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the  
total energy is released through the top of the case (where thermocouple measurements are usually conducted).  
The RθJC resistance can only be used effectively when most of the thermal energy is released through the case,  
such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of RθJC will  
inaccurately estimate the true junction temperature. The ΨJT parameter is experimentally derived by assuming  
that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the  
application environment. As long as the recommended layout guidelines are observed, junction temperature  
estimations can be made accurately to within a few degrees Celsius.  
10.2.3 Selecting VCC1 and VCC2 Capacitors  
Bypass capacitors for the VCC1 and VCC2 supplies are essential for achieving reliable performance. TI  
recommends choosing low-ESR and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with  
sufficient voltage ratings, temperature coefficients, and capacitance tolerances.  
备注  
DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V, 1-μF X7R  
capacitor is measured to be only 500 nF when a DC bias of 15-VDC is applied.  
10.2.3.1 Selecting a VCC1 Capacitor  
A bypass capacitor connected to the VCC1 pin supports the transient current required for the primary logic and  
the total current consumption, which is only a few milliamperes. Therefore, a 50-V MLCC with over 100 nF is  
recommended for this application. If the bias power-supply output is located a relatively long distance from the  
V
CC1 pin, a tantalum or electrolytic capacitor with a value greater than 1 μF should be placed in parallel with the  
MLCC.  
10.2.3.2 Selecting a VCC2 Capacitor  
A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the CVCC2 capacitor. If the bias power supply  
output is located a relatively long distance from the VCC2 pin, a tantalum or electrolytic capacitor with a value  
greater than 10 μF should be used in parallel with CVCC2  
.
10.2.3.3 Application Circuits with Output Stage Negative Bias  
When parasitic inductances are introduced by nonideal PCB layout and long package leads (such as TO-220  
and TO-247 type packages), ringing in the gate-source drive voltage of the power transistor could occur during  
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, unintended turn-on and shoot-through  
could occur. Applying a negative bias on the gate drive is a popular way to keep such ringing below the  
threshold. A few examples of implementing negative gate-drive bias follow.  
图 10-3 shows the first example with negative bias turn-off on the output using a Zener diode on the isolated  
power-supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power supply is  
equal to 20 V, the turn-off voltage is –5.1 V and the turn-on voltage is 20 V –5.1 V ≈15 V.  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
29  
Product Folder Links: UCC5350-Q1  
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
20 V  
VCC2  
C3  
VCC1  
CA1  
GND1  
RGON  
OUTH  
OUTL  
RGOFF  
Signal Emitter  
IN+  
INœ  
CA2  
VEE2  
Copyright © 2017, Texas Instruments Incorporated  
图10-3. Negative Bias With Zener Diode on Iso-Bias Power-Supply Output  
图 10-4 shows another example which uses two supplies (or single-input, double-output power supply). The  
power supply across VCC2 and the emitter determines the positive drive output voltage and the power supply  
across VEE2 and the emitter determines the negative turn-off voltage. This solution requires more power supplies  
than the first example, however, it provides more flexibility when setting the positive and negative rail voltages.  
VCC2  
CA3  
VCC1  
CA1  
+
œ
GND1  
OUT  
CLAMP  
IN+  
CA2  
+
œ
INœ  
VEE2  
图10-4. Negative Bias With Two Iso-Bias Power Supplies  
Copyright © 2022 Texas Instruments Incorporated  
30  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
10.2.4 Application Curve  
VCC2 = 20 V  
VEE2 = GND  
fSW = 10 kHz  
图10-5. PWM Input and Gate Voltage Waveform  
11 Power Supply Recommendations  
The recommended input supply voltage (VCC1) for the UCC5350-Q1 device is from 3 V to 15 V. The lower limit of  
the range of output bias-supply voltage (VCC2) is determined by the internal UVLO protection feature of the  
device. The VCC1 and VCC2 voltages should not fall below their respective UVLO thresholds for normal operation,  
or else the gate-driver outputs can become clamped low for more than 50 μs by the UVLO protection feature.  
For more information on UVLO, see the 节 9.3.4.1 section. The higher limit of the VCC2 range depends on the  
maximum gate voltage of the power device that is driven by the UCC5350-Q1 device, and should not exceed the  
recommended maximum VCC2 of 33 V. A local bypass capacitor should be placed between the VCC2 and VEE2  
pins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing an additional 100-nF capacitor  
in parallel with the device biasing capacitor for high frequency filtering. Both capacitors should be positioned as  
close to the device as possible. Low-ESR, ceramic surface-mount capacitors are recommended. Similarly, a  
bypass capacitor should also be placed between the VCC1 and GND1 pins. Given the small amount of current  
drawn by the logic circuitry within the input side of the UCC5350-Q1 device, this bypass capacitor has a  
minimum recommended value of 100 nF.  
12 Layout  
12.1 Layout Guidelines  
Designers must pay close attention to PCB layout to achieve optimum performance for the UCC5350-Q1. Some  
key guidelines are:  
• Component placement:  
– Low-ESR and low-ESL capacitors must be connected close to the device between the VCC1 and GND1  
pins and between the VCC2 and VEE2 pins to bypass noise and to support high peak currents when turning  
on the external power transistor.  
– To avoid large negative transients on the VEE2 pins connected to the switch node, the parasitic  
inductances between the source of the top transistor and the source of the bottom transistor must be  
minimized.  
• Grounding considerations:  
– Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area  
is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of  
the transistors. The gate driver must be placed as close as possible to the transistors.  
• High-voltage considerations:  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
31  
Product Folder Links: UCC5350-Q1  
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces  
or copper below the driver device. A PCB cutout or groove is recommended in order to prevent  
contamination that may compromise the isolation performance.  
• Thermal considerations:  
– A large amount of power may be dissipated by the UCC5350-Q1 if the driving voltage is high, the load is  
heavy, or the switching frequency is high (for more information, see the 节10.2.2.3 section). Proper PCB  
layout can help dissipate heat from the device to the PCB and minimize junction-to-board thermal  
impedance (θJB).  
– Increasing the PCB copper connecting to the VCC2 and VEE2 pins is recommended, with priority on  
maximizing the connection to VEE2. However, the previously mentioned high-voltage PCB considerations  
must be maintained.  
– If the system has multiple layers, TI also recommends connecting the VCC2 and VEE2 pins to internal  
ground or power planes through multiple vias of adequate size. These vias should be located close to the  
IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different  
high voltage planes are overlapping.  
12.2 Layout Example  
图 12-1 shows a PCB layout example with the signals and key components labeled. The UCC5390ECDWV  
evaluation module (EVM) is given as an example, available in the same DWV package as the UCC5350-Q1.  
The UCC5390EC has a split emitter versus Miller clamp so although the layout is not exactly the same, general  
guidelines and practices still apply. The evaluation board can be configured for the Miller clamp version, as well,  
as described in the UCC5390ECDWV Isolated Gate Driver Evaluation Module User's Guide.  
A. No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.  
图12-1. Layout Example  
图12-2 and 图12-3 show the top and bottom layer traces and copper.  
Copyright © 2022 Texas Instruments Incorporated  
32  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
图12-2. Top-Layer Traces and Copper  
图12-3. Bottom-Layer Traces and Copper (Flipped)  
图12-4 shows the 3D layout of the top view of the PCB.  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
33  
Product Folder Links: UCC5350-Q1  
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
图12-4. 3-D PCB View  
12.3 PCB Material  
Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of  
lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-  
extinguishing flammability-characteristics.  
图12-5 shows the recommended layer stack.  
High-speed traces  
10 mils  
Ground plane  
Keep this space  
FR-4  
free from planes,  
traces, pads, and  
vias  
40 mils  
0r ~ 4.5  
Power plane  
10 mils  
Low-speed traces  
图12-5. Recommended Layer Stack  
Copyright © 2022 Texas Instruments Incorporated  
34  
Submit Document Feedback  
Product Folder Links: UCC5350-Q1  
 
 
 
UCC5350-Q1  
ZHCSP86D –MAY 2020 –REVISED AUGUST 2022  
www.ti.com.cn  
13 Device and Documentation Support  
13.1 Device Support  
13.1.1 第三方产品免责声明  
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此  
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。  
13.2 Documentation Support  
13.2.1 Related Documentation  
For related documentation see the following:  
• Texas Instruments, Digital Isolator Design Guide  
• Texas Instruments, Isolation Glossary  
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet  
• Texas Instruments, SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet  
• Texas Instruments, UCC5390ECDWV Isolated Gate Driver Evaluation Module user's guide  
• Texas Instruments, UCC53x0xD Evaluation Module user's guide  
13.3 Certifications  
UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate  
Number: 20170718-E181974,  
13.4 接收文档更新通知  
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更  
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。  
13.5 支持资源  
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解  
答或提出自己的问题可获得所需的快速设计帮助。  
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅  
TI 的《使用条款》。  
13.6 Trademarks  
TI E2E™ is a trademark of Texas Instruments.  
所有商标均为其各自所有者的财产。  
13.7 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
13.8 术语表  
TI 术语表  
本术语表列出并解释了术语、首字母缩略词和定义。  
Copyright © 2022 Texas Instruments Incorporated  
Submit Document Feedback  
35  
Product Folder Links: UCC5350-Q1  
 
 
 
 
 
 
 
 
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
5-Apr-2023  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
PUCC5350MCQDWVQ1  
PUCC5350SBQDRQ1  
OBSOLETE  
ACTIVE  
SOIC  
SOIC  
DWV  
D
8
8
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
3000  
75  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
UCC5350MCQDQ1  
UCC5350MCQDRQ1  
UCC5350MCQDWVQ1  
UCC5350MCQDWVRQ1  
UCC5350SBQDRQ1  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
D
D
8
8
8
8
8
RoHS & Green  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
Level-3-260C-168 HR  
5350Q  
2500 RoHS & Green  
64 RoHS & Green  
5350Q  
DWV  
DWV  
D
5350MCQ  
5350MCQ  
5350Q  
1000 RoHS & Green  
2500 RoHS & Green  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
5-Apr-2023  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF UCC5350-Q1 :  
Catalog : UCC5350  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2023  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
UCC5350MCQDRQ1  
UCC5350MCQDRQ1  
UCC5350MCQDWVRQ1  
UCC5350SBQDRQ1  
SOIC  
SOIC  
SOIC  
SOIC  
D
D
8
8
8
8
2500  
2500  
1000  
2500  
330.0  
330.0  
330.0  
330.0  
12.4  
12.4  
16.4  
12.4  
6.4  
6.4  
5.2  
5.2  
2.1  
2.1  
3.3  
2.1  
8.0  
8.0  
12.0  
12.0  
16.0  
12.0  
Q1  
Q1  
Q1  
Q1  
DWV  
D
12.05 6.15  
6.4 5.2  
16.0  
8.0  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2023  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
UCC5350MCQDRQ1  
UCC5350MCQDRQ1  
UCC5350MCQDWVRQ1  
UCC5350SBQDRQ1  
SOIC  
SOIC  
SOIC  
SOIC  
D
D
8
8
8
8
2500  
2500  
1000  
2500  
350.0  
356.0  
350.0  
356.0  
350.0  
356.0  
350.0  
356.0  
43.0  
35.0  
43.0  
35.0  
DWV  
D
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2023  
TUBE  
T - Tube  
height  
L - Tube length  
W - Tube  
width  
B - Alignment groove width  
*All dimensions are nominal  
Device  
Package Name Package Type  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
UCC5350MCQDQ1  
UCC5350MCQDQ1  
UCC5350MCQDWVQ1  
D
D
SOIC  
SOIC  
SOIC  
8
8
8
75  
75  
64  
506.6  
505.46  
505.46  
8
3940  
3810  
4826  
4.32  
4
6.76  
13.94  
DWV  
6.6  
Pack Materials-Page 3  
PACKAGE OUTLINE  
DWV0008A  
SOIC - 2.8 mm max height  
S
C
A
L
E
2
.
0
0
0
SOIC  
C
SEATING PLANE  
11.5 0.25  
TYP  
PIN 1 ID  
AREA  
0.1 C  
6X 1.27  
8
1
2X  
5.95  
5.75  
NOTE 3  
3.81  
4
5
0.51  
0.31  
8X  
7.6  
7.4  
0.25  
C A  
B
A
B
2.8 MAX  
NOTE 4  
0.33  
0.13  
TYP  
SEE DETAIL A  
(2.286)  
0.25  
GAGE PLANE  
0.46  
0.36  
0 -8  
1.0  
0.5  
DETAIL A  
TYPICAL  
(2)  
4218796/A 09/2013  
NOTES:  
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm, per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DWV0008A  
SOIC - 2.8 mm max height  
SOIC  
8X (1.8)  
SEE DETAILS  
SYMM  
SYMM  
8X (0.6)  
6X (1.27)  
(10.9)  
LAND PATTERN EXAMPLE  
9.1 mm NOMINAL CLEARANCE/CREEPAGE  
SCALE:6X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
METAL  
0.07 MAX  
ALL AROUND  
0.07 MIN  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4218796/A 09/2013  
NOTES: (continued)  
5. Publication IPC-7351 may have alternate designs.  
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DWV0008A  
SOIC - 2.8 mm max height  
SOIC  
SYMM  
8X (1.8)  
8X (0.6)  
SYMM  
6X (1.27)  
(10.9)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:6X  
4218796/A 09/2013  
NOTES: (continued)  
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
8. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
PACKAGE OUTLINE  
D0008A  
SOIC - 1.75 mm max height  
SCALE 2.800  
SMALL OUTLINE INTEGRATED CIRCUIT  
C
SEATING PLANE  
.228-.244 TYP  
[5.80-6.19]  
.004 [0.1] C  
A
PIN 1 ID AREA  
6X .050  
[1.27]  
8
1
2X  
.189-.197  
[4.81-5.00]  
NOTE 3  
.150  
[3.81]  
4X (0 -15 )  
4
5
8X .012-.020  
[0.31-0.51]  
B
.150-.157  
[3.81-3.98]  
NOTE 4  
.069 MAX  
[1.75]  
.010 [0.25]  
C A B  
.005-.010 TYP  
[0.13-0.25]  
4X (0 -15 )  
SEE DETAIL A  
.010  
[0.25]  
.004-.010  
[0.11-0.25]  
0 - 8  
.016-.050  
[0.41-1.27]  
DETAIL A  
TYPICAL  
(.041)  
[1.04]  
4214825/C 02/2019  
NOTES:  
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.  
Dimensioning and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed .006 [0.15] per side.  
4. This dimension does not include interlead flash.  
5. Reference JEDEC registration MS-012, variation AA.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
SEE  
DETAILS  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:8X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED  
METAL  
EXPOSED  
METAL  
.0028 MAX  
[0.07]  
.0028 MIN  
[0.07]  
ALL AROUND  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4214825/C 02/2019  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
SOLDER PASTE EXAMPLE  
BASED ON .005 INCH [0.125 MM] THICK STENCIL  
SCALE:8X  
4214825/C 02/2019  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
重要声明和免责声明  
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，  
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担  
保。  
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验  
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。  
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。  
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成  
本、损失和债务，TI 对此概不负责。  
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改  
TI 针对 TI 产品发布的适用的担保或担保免责声明。  
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE  
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023，德州仪器 (TI) 公司  

相关型号：

UCC5350MCQDWVRQ1

 适用于 IGBT/SiC 且具有米勒钳位或分离输出的汽车类 ±5A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125
TI

UCC5350SBD

 具有米勒钳位或分离输出以及 8V 或 12V UVLO 的 3kVrms、5A/5A 单通道隔离式栅极驱动器 | D | 8 | -40 to 125
TI

UCC5350SBDR

 具有米勒钳位或分离输出以及 8V 或 12V UVLO 的 3kVrms、5A/5A 单通道隔离式栅极驱动器 | D | 8 | -40 to 125
TI

UCC5350SBQDRQ1

 适用于 IGBT/SiC 且具有米勒钳位或分离输出的汽车类 ±5A 单通道隔离式栅极驱动器 | D | 8 | -40 to 125
TI

UCC5390

 具有 UVLO（以 GND 为基准）或分离输出的 3kVrms/5kVrms、±10A 单通道隔离式栅极驱动器
TI

UCC5390-Q1

 适用于 IGBT/SiC MOSFET 且具有 UVLO（以 GND 为基准）的汽车类 5kVrms、17A 单通道隔离式栅极驱动器
TI

UCC5390ECD

 具有 UVLO（以 GND 为基准）或分离输出的 3kVrms/5kVrms、±10A 单通道隔离式栅极驱动器 | D | 8 | -40 to 125
TI

UCC5390ECDR

 具有 UVLO（以 GND 为基准）或分离输出的 3kVrms/5kVrms、±10A 单通道隔离式栅极驱动器 | D | 8 | -40 to 125
TI

UCC5390ECDWV

 具有 UVLO（以 GND 为基准）或分离输出的 3kVrms/5kVrms、±10A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125
TI

UCC5390ECDWVR

 具有 UVLO（以 GND 为基准）或分离输出的 3kVrms/5kVrms、±10A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125
TI

UCC5390ECQDWVQ1

 适用于 IGBT/SiC MOSFET 且具有 UVLO（以 GND 为基准）的汽车类 5kVrms、17A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125
TI

UCC5390ECQDWVRQ1

 适用于 IGBT/SiC MOSFET 且具有 UVLO（以 GND 为基准）的汽车类 5kVrms、17A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125
TI
©2020 ICPDF网 联系我们和版权申明