UCC28740QDRQ1 [TI]
具有集成高压启动和光耦合器反馈功能的汽车类超低待机功耗反激式控制器 | D | 7 | -40 to 125;
| 型号： | UCC28740QDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成高压启动和光耦合器反馈功能的汽车类超低待机功耗反激式控制器 | D | 7 | -40 to 125 控制器 高压 开关 光电二极管 |
| 文件： | 总41页 (文件大小：1588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC28740-Q1
ZHCSK45C –AUGUST 2019 –REVISED DECEMBER 2020
UCC28740-Q1 适用于汽车且具有集成式高压启动和光耦合器反馈功能的
超低待机功耗反激式控制器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
UCC28740-Q1 隔离式反激电源控制器可使用光耦合器
调节输出，以提供对大型负载阶跃的快速瞬态响应。
– 器件温度等级1：-40°C 至+125°C
– 器件HBM 分类等级2：±2kV
– 器件CDM 分类等级C4B：±750V
• 功能安全型
内部采用 700V 启动开关，可动态控制工作状态并定制
调制配置文件，支持超低待机功耗，并且不会影响启动
时间或输出瞬态响应。
UCC28740-Q1 中的控制算法可使操作效率达到或超过
适用标准。驱动输出接至一个 MOSFET 电源开关。带
有谷值开关的断续传导模式 (DCM) 减少了开关损耗。
开关频率的调制和初级电流峰值振幅（FM 和 AM）在
整个负载和线路范围内保持较高的转换效率。
– 可提供用于功能安全系统设计的文档
• 低于10mW 的空载功耗能力
• 可在线路和负载范围内实现±1% 的电压调节和
±5% 的电流调节
• 700V 启动开关
• 100kHz 的最高开关频率可实现高功率密度充电器
设计
此控制器有一个 100kHz 的最大开关频率并且一直保持
对变压器内峰值初级电流的控制。保护特性可抑制初级
和次级应力分量。170kHz 的最小开关频率可轻松实现
少于10mW 无负载功耗。
• 谐振环谷值开关运行模式可实现最高总体效率
• 频率抖动功能使其轻松符合EMI 标准
• MOSFET 钳位栅极驱动输出
• 过压、低压线路和过流保护功能
• 使用UCC28740-Q1 并借助WEBENCH® Power
Designer 创建定制设计方案
器件信息(1)
封装尺寸（标称值）
器件型号
封装
UCC28740-Q1
SOIC (7)
4.90mm × 3.91mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 具有集成式高压启动功能和光耦合器反馈功能的超
低待机功耗反激式控制器
• 牵引逆变器高压转低压备用电源
• HVAC 压缩机高压隔离式电源
• PTC 加热器高压隔离式电源
+ VF
œ
VOUT
VOCV
COUT
NP
NS
VIN
CIN
4 V
3 V
2 V
1 V
5%
UCC28740-Q1
SOIC-7
RTL
+ VFA
œ
VAUX
NA
VVDD
VDD
HV
ROPT
RFB1
CVDD
RS1
VE
VS
FB
DRV
CS
RLC
RFB3
CFB3
RS2
IOPT
ZFB
RCS
GND
IFB
RFB4
RFB2
Output Current (IO)
Copyright © 2019, Texas Instruments Incorporated
典型伏安图
简化版应用示意图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDT2
UCC28740-Q1
ZHCSK45C –AUGUST 2019 –REVISED DECEMBER 2020
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................13
8 Application and Implementation..................................18
8.1 Application Information............................................. 18
8.2 High Voltage Applications......................................... 18
8.3 Typical Application.................................................... 18
9 Power Supply Recommendations................................30
10 Layout...........................................................................31
10.1 Layout Guidelines................................................... 31
10.2 Layout Example...................................................... 32
11 Device and Documentation Support..........................33
11.1 Device Support........................................................33
11.2 Documentation Support.......................................... 35
11.3 Receiving Notification of Documentation Updates..35
11.4 Community Resources............................................35
11.5 Trademarks............................................................. 35
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................2
5.1 Pin Functions.............................................................. 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................6
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (May 2020) to Revision C (December 2020)
Page
• 添加了功能安全信息........................................................................................................................................... 1
Changes from Revision A (November 2019) to Revision B (May 2020)
Page
• Added to include start-up current IHV at 30V VHV. ........................................................................................... 5
Changes from Revision * (August 2019) to Revision A (November 2019)
Page
• 将销售状态从“预告信息”更改为“量产数据”。............................................................................................ 1
5 Pin Configuration and Functions
VDD
VS
1
2
3
4
8
HV
FB
6
5
DRV
CS
GND
图5-1. D Package 7-Pin SOIC Top View
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5.1 Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
The current-sense (CS) input connects to a ground-referenced current-sense resistor in series with the power
switch. The resulting voltage monitors and controls the peak primary current. A series resistor is added to this
pin to compensate for peak switch-current levels as the AC-mains input varies.
CS
5
I
DRV
6
O
Drive (DRV) is an output that drives the gate of an external high-voltage MOSFET switching transistor.
The feedback (FB) input receives a current signal from the optocoupler output transistor. An internal current
mirror divides the feedback current by 2.5 and applies it to an internal pullup resistor to generate a control
voltage, VCL. The voltage at this resistor directly drives the control law function, which determines the switching
frequency and the peak amplitude of the switching current .
FB
3
4
I
The ground (GND) pin is both the reference pin for the controller, and the low-side return for the drive output.
Special care must be taken to return all AC-decoupling capacitors as close as possible to this pin and avoid any
common trace length with analog signal-return paths.
GND
—
The high-voltage (HV) pin may connect directly, or through a series resistor, to the rectified bulk voltage and
provides a charge to the VDD capacitor for the startup of the power supply.
HV
8
1
I
I
VDD is the bias-supply input pin to the controller. A carefully placed bypass capacitor to GND is required on this
pin.
VDD
Voltage sense (VS) is an input used to provide demagnetization timing feedback to the controller to limit
frequency, to control constant-current operation, and to provide output-overvoltage detection. VS is also used
for AC-mains input-voltage detection for peak primary-current compensation. This pin connects to a voltage
divider between an auxiliary winding and GND. The value of the upper resistor of this divider programs the AC-
mains run and stop thresholds, and factors into line compensation at the CS pin.
VS
2
I
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6 Specifications
6.1 Absolute Maximum Ratings
See (1) and (2)
.
MIN
MAX
UNIT
V
VHV
VVDD
IDRV
IDRV
IFB
Start-up pin voltage, HV
Bias supply voltage, VDD
Continuous gate-current sink
Continuous gate-current source
Peak current, VS
700
38
V
50
mA
mA
mA
mA
V
Self-limiting
1
IVS
Peak current, FB
−1.2
VDRV
Gate-drive voltage at DRV
Voltage, CS
Self-limiting
–0.5
–0.5
–0.5
–0.75
–55
5
7
V
Voltage, FB
V
Voltage, VS
7
V
TJ
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. These ratings apply over the
operating ambient temperature ranges unless otherwise noted.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)(1)
±2000
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per Charged-device model (CDM), per AEC
Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
9
MAX
UNIT
V
VVDD
CVDD
IFB
Bias-supply operating voltage
VDD bypass capacitor
35
0.047
µF
Feedback current, continuous
VS pin current, out of pin
50
1
µA
mA
°C
IVS
TJ
Operating junction temperature
125
–40
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6.4 Thermal Information
UCC28740-Q1
THERMAL METRIC(1)
D (SOIC)
7 PINS
141.5
73.8
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
89
Junction-to-top characterization parameter
Junction-to-board characterization parameter
23.5
88.2
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, VVDD = 25 V, HV = open, VFB = 0 V, VVS = 4 V, TA = –40°C to +125°C, TJ = TA
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
HIGH-VOLTAGE START UP
VHV = 100 V, VVDD = 0 V, start state
100
130
250
500
410
IHV
Start-up current out of VDD
Leakage current at HV
µA
VHV = 30 V, VVDD = VVDD(on) –0.5 V, start
state
IHVLKG25
VHV = 400 V, run state, TJ = 25°C
0.01
0.5 µA
BIAS SUPPLY INPUT
IRUN
Supply current, run
IDRV = 0, run state
2
95
18
95
2.65 mA
125 µA
30 µA
IWAIT
ISTART
IFAULT
Supply current, wait
Supply current, start
Supply current, fault
IDRV = 0, wait state
IDRV = 0, VVDD = 18 V, start state, IHV = 0
IDRV = 0, fault state
130 µA
UNDERVOLTAGE LOCKOUT
VVDD(on)
VVDD(off)
VS INPUT
VVSNC
VDD turnon threshold
VDD turnoff threshold
VVDD low to high
VVDD high to low
19
21
23
V
V
7.35 7.75 8.15
Negative clamp level
Input bias current
190
250
0
325 mV
0.25 µA
IVSLS = –300 µA, volts below ground
IVSB
VVS = 4 V
–0.25
FB INPUT
IFBMAX
Full-range input current
Input voltage at full range
fSW = fSW(min)
16
23
30 µA
VFBMAX
IFB = 25 µA, TJ = 25°C
0.75 0.88
1
V
ΔIFB = 20 µA, centered at IFB = 15 µA, TJ =
25°C
RFB
FB-input resistance, linearized
10
14
18
kΩ
CS INPUT
VCST(max)
VCST(min)
KAM
Maximum CS threshold voltage
Minimum CS threshold voltage
AM-control ratio
IFB = 0 µA(1)
738
170
3.6
773
194
4
810 mV
215 mV
4.45 V/V
343 mV
IFB = 35 µA(1)
VCST(max) / VCST(min)
VCCR
Constant-current regulation factor
318
330
IVSLS = –300 µA, IVSLS / current out of CS
pin
KLC
Line-compensation current ratio
Leading-edge blanking time
24
25 28.6 A/A
tCSLEB
DRV output duration, VCS = 1 V
VDRV = 8 V, VVDD = 9 V
180
230
25
280
ns
DRIVERS
IDRS
DRV source current
20
mA
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over operating free-air temperature range, VVDD = 25 V, HV = open, VFB = 0 V, VVS = 4 V, TA = –40°C to +125°C, TJ = TA
(unless otherwise noted)
PARAMETER
DRV low-side drive resistance
DRV clamp voltage
TEST CONDITIONS
IDRV = 10 mA
MIN TYP MAX UNIT
RDRVLS
VDRCL
6
14
12
16
Ω
VVDD = 35 V
V
RDRVSS
DRV pulldown in start-state
150
190
230
kΩ
PROTECTION
VOVP
Overvoltage threshold
At VS input, TJ = 25°C(2)
At CS input
4.52
1.4
4.6 4.74
V
V
VOCP
Overcurrent threshold
1.5
225
80
1.6
IVSL(run)
IVSL(stop)
KVSL
VS line-sense run current
VS line-sense stop current
VS line sense ratio
Current out of VS pin increasing
Current out of VS pin decreasing
IVSL(run) / IVSL(stop)
190
70
275 µA
100 µA
2.45
2.8 3.05 A/A
165 °C
TJ(stop)
Thermal-shutdown temperature
Internal junction temperature
(1) This device automatically varies the control frequency and current sense thresholds to improve EMI performance. These threshold
voltages and frequency limits represent average levels.
(2) The overvoltage threshold level at VS decreases with increasing temperature by 0.8 mV/°C. This compensation is included to reduce
the power-supply output overvoltage detection variance over temperature.
6.6 Switching Characteristics
over operating free-air temperature range, VVDD = 25 V, HV = open, VFB = 0 V, VVS = 4 V, TA = –40°C to +125°C, TJ = TA
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
IFB = 0 µA(1)
IFB = 35 µA(1)
MIN
91
TYP
100
170
2.1
MAX
108
UNIT
kHz
Hz
fSW(max)
fSW(min)
tZTO
Maximum switching frequency
Minimum switching frequency
Zero-crossing timeout delay
140
1.8
210
2.55
µs
6.7 Typical Characteristics
VVDD = 25 V, TJ = 25°C, unless otherwise noted.
10
10
1
HV = Open
Run State
HV = Open
IRUN,
VDD = 25 V
1
IWAIT
,
VDD = 25 V
, VDD = 18 V
Wait State
0.1
0.1
ISTART
VDD Turn-Off
Start State
VDD Turn-On
0.01
0.001
0.01
0.001
0.0001
0.0001
0
5
10
15
20
25
30
35
-50
-25
0
25
50
75
100
125
TJ - Temperature (oC)
VDD - Bias-Supply Voltage (V)
C001
C002
HV = Open
HV = Open
图6-1. Bias-Supply Current vs. Bias-Supply
图6-2. Bias-Supply Current vs. Temperature
Voltage
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320
280
240
200
160
120
80
300
250
200
150
100
50
VHV = 100 V, VVDD = 0 V
IVSL(run)
IVSL(stop)
40
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Temperature (oC)
TJ - Temperature (oC)
C003
C004
VHV = 100 V, VVDD = 0 V
图6-4. VS Line-Sense Currents vs. Temperature
图6-3. HV Startup Current vs. Temperature
210
205
200
195
190
185
180
175
170
350
345
340
335
330
325
320
315
310
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Temperature (oC)
TJ - Temperature (oC)
C005
C006
图6-5. Minimum CS Threshold vs. Temperature
图6-6. Constant-Current Regulation Factor vs.
Temperature
200
190
180
170
160
150
140
34
VDRV = 8 V, VVDD = 9 V
32
30
28
26
24
22
20
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Temperature (oC)
TJ - Temperature (oC)
C007
C008
VDRV = 8 V, VVDD = 9 V
图6-7. Minimum Switching Frequency vs.
Temperature
图6-8. DRV Source Current vs. Temperature
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1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
4.68
4.66
4.64
4.62
4.60
4.58
4.56
4.54
4.52
0
5
10
15
20
25
30
35
-50
-25
0
25
50
75
100
125
TJ - Temperature (oC)
IFB - FB Input Current (µA)
C009
C010
图6-9. FB Input Voltage vs. FB Input Current
图6-10. VS Overvoltage Threshold vs. Temperature
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7 Detailed Description
7.1 Overview
The UCC28740-Q1 is a flyback power-supply controller which provides high-performance voltage regulation
using an optically coupled feedback signal from a secondary-side voltage regulator. The device provides
accurate constant-current regulation using primary-side feedback. The controller operates in discontinuous-
conduction mode (DCM) with valley-switching to minimize switching losses. The control law scheme combines
frequency with primary peak-current amplitude modulation to provide high conversion efficiency across the load
range. The control law provides a wide dynamic operating range of output power which allows the power-supply
designer to easily achieve less than 30-mW standby power dissipation using a standard shunt-regulator and
optocoupler. For a target of less than 10-mW standby power, careful loss-management design with a low-power
regulator and high-CTR optocoupler is required.
During low-power operating conditions, the power-management features of the controller reduce the device-
operating current at switching frequencies below 32 kHz. At and above this frequency, the UCC28740-Q1
includes features in the modulator to reduce the EMI peak energy of the fundamental switching frequency and
harmonics. A complete low-cost and low component-count charger-solution is realized using a straight-forward
design process.
7.2 Functional Block Diagram
IHV
GND
HV
OC Fault
OV Fault
VDD
FB
Power
and Fault
Management
UVLO
21 V / 7.75 V
Line Fault
5 V
IFB
5 V
14k
VDD
VCL
Control
Law
VCST
IFB / 2.5
25 mA
0.55 V
DRV
VS
14 V
+
Sampler
1 / fSW
190K
œ
OV Fault
VOVP
Valley
Switching
S
R
Q
Q
CS
+
Current
Regulation
Secondary
Timing Detect
œ
VCST
LEB
IVSLS
Line
Sense
IVSLS
IVSLS / KLC
œ
+
OC Fault
Line Fault
+
1.5 V
œ
2.25 V / 0.8 V
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7.3 Feature Description
7.3.1 Detailed Pin Description
VDD
The VDD pin connects to a bypass capacitor-to-ground. The turnon UVLO threshold is 21 V and
(Device
Bias
Voltage
Supply)
turnoff UVLO threshold is 7.75 V with an available operating range up to 35 V on VDD. The typical
USB-charging specification requires the output current to operate in constant-current mode from 5
V down to at least 2 V which is achieved easily with a nominal VVDD of approximately 25 V. The
additional VDD headroom up to 35 V allows for VVDD to rise due to the leakage energy delivered
to the VDD capacitor during high-load conditions.
GND
(Ground)
UCC28740 has a single ground reference external to the device for the gate-drive current and
analog signal reference. Place the VDD-bypass capacitor close to GND and VDD with short
traces to minimize noise on the VS, FB, and CS signal pins.
HV (High-
Voltage
Startup)
The HV pin connects directly to the bulk capacitor to provide a startup current to the VDD
capacitor. The typical startup current is approximately 250 µA which provides fast charging of the
VDD capacitor. The internal HV startup device is active until VVDD exceeds the turnon UVLO
threshold of 21 V at which time the HV startup device turns off. In the off state the HV leakage
current is very low to minimize standby losses of the controller. When VVDD falls below the 7.75 V
UVLO turnoff threshold the HV startup device turns on.
VS (Voltage The VS pin connects to a resistor-divider from the auxiliary winding to ground. The auxiliary
Sense)
voltage waveform is sampled at the end of the transformer secondary-current demagnetization
time to provide accurate control of the output current when in constant-current mode. The
waveform on the VS pin determines the timing information to achieve valley-switching, and the
timing to control the duty-cycle of the transformer secondary current. Avoid placing a filter
capacitor on this input which interferes with accurate sensing of this waveform.
During the MOSFET on-time, this pin also senses VS current generated through RS1 by the
reflected bulk-capacitor voltage to provide for AC-input run and stop thresholds, and to
compensate the current-sense threshold across the AC-input range. For the AC-input run/stop
function, the run threshold on VS is 225 µA and the stop threshold is 80 µA.
At the end of off-time demagnetization, the reflected output voltage is sampled at this pin to
provide output overvoltage protection. The values for the auxiliary voltage-divider upper-resistor,
RS1, and lower-resistor, RS2, are determined by 方程式1 and 方程式2.
V
´
2
IN(run)
RS1
=
NPA ´ IVSL(run)
(1)
where
• NPA is the transformer primary-to-auxiliary turns-ratio,
• VIN(run) is the AC RMS voltage to enable turnon of the controller (run),
(in case of DC input, leave out the √2 term in the equation),
• IVSL(run) is the run-threshold for the current pulled out of the VS pin during the switch on-time (see 节6.5).
RS1 ì VOVP
RS2
=
NAS
ì
V
- VF - V
OV OVP
(2)
where
• VOV is the maximum allowable peak voltage at the converter output,
• VF is the output-rectifier forward drop at near-zero current,
• NAS is the transformer auxiliary-to-secondary turns-ratio,
• RS1 is the VS divider high-side resistance,
• VOVP is the overvoltage detection threshold at the VS input (see 节6.5).
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FB
The FB pin connects to the emitter of an analog-optocoupler output transistor which usually has
(Feedback) the collector connected to VDD. The current supplied to FB by the optocoupler is reduced
internally by a factor of 2.5 and the resulting current is applied to an internal 480-kΩresistor to
generate the control law voltage (VCL). This VCL directly determines the converter switching
frequency and peak primary current required for regulation per the control-law for any given line
and load condition.
DRV (Gate
Drive)
The DRV pin connects to the MOSFET gate pin, usually through a series resistor. The gate
driver provides a gate-drive signal limited to 14 V. The turnon characteristic of the driver is a 25-
mA current source which limits the turnon dv/dt of the MOSFET drain and reduces the leading-
edge current spike while still providing a gate-drive current to overcome the Miller plateau. The
gate-drive turnoff current is determined by the RDSON of the low-side driver along with any
external gate-drive resistance. Adding external gate resistance reduces the MOSFET drain turn-
off dv/dt, if necessary.
CS (Current The current-sense pin connects through a series resistor (RLC) to the current-sense resistor
Sense)
(RCS). The maximum current-sense threshold (VCST(max)) is 0.773 V for IPP(max), and the
minimum current-sense threshold (VCST(min)) is 0.194 V for IPP(min). RLC provides the feed-
forward line compensation to eliminate changes in IPP with input voltage due to the propagation
delay of the internal comparator and MOSFET turnoff time. An internal leading-edge blanking
time of 235 ns eliminates sensitivity to the MOSFET turnon current spike. Placing a bypass
capacitor on the CS pin is unnecessary. The target output current in constant-current (CC)
regulation determines the value of RCS. The values of RCS and RLC are calculated using 方程式
3 and 方程式4. The term VCCR is the product of the demagnetization constant, 0.425, and
V
CST(max). VCCRis held to a tighter accuracy than either of its constituent terms. The term ηXFMR
accounts for the energy stored in the transformer but not delivered to the secondary. This term
includes transformer resistance and core loss, bias power, and primary-to-secondary leakage
ratio.
Example:
With a transformer core and winding loss of 5%, primary-to-secondary leakage inductance of 3.5%, and bias
power to output power ratio of 0.5%, the ηXFMR value at full power is approximately: 1 - 0.05 - 0.035 - 0.005 =
0.91.
V
´N
PS
CCR
R
=
´ h
XFMR
CS
2I
OCC
(3)
where
• VCCR is a constant-current regulation factor (see 节6.5),
• NPS is the transformer primary-to-secondary turns-ratio (a ratio of 13 to 15 is typical for 5-V output),
• IOCC is the target output current in constant-current regulation,
• ηXFMR is the transformer efficiency at full power.
K
´R ´R ´ t ´N
LC
S1
CS
D
PA
R
=
LC
L
P
(4)
where
• RS1 is the VS pin high-side resistor value,
• RCS is the current-sense resistor value,
• tD is the total current-sense delay consisting of MOSFET turnoff delay, plus approximately 50 ns internal
delay,
• NPA is the transformer primary-to-auxiliary turns-ratio,
• LP is the transformer primary inductance,
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• KLC is a current-scaling constant for line compensation (see 节6.5).
7.3.2 Valley-Switching and Valley-Skipping
The UCC28740-Q1 uses valley-switching to reduce switching losses in the MOSFET, to reduce induced-EMI,
and to minimize the turnon current spike at the current-sense resistor. The controller operates in valley-switching
in all load conditions unless the VDS ringing diminishes to the point where valleys are no longer detectable.
As shown in 图 7-1, the UCC28740-Q1 operates in a valley-skipping mode (also known as valley-hopping) in
most load conditions to maintain an accurate voltage or current regulation point and still switch on the lowest
available VDS voltage.
VDS
VDRV
图7-1. Valley-Skipping Mode
Valley-skipping modulates each switching cycle into discrete period durations. During FM operation, the
switching cycles are periods when energy is delivered to the output in fixed packets, where the power-per-cycle
varies discretely with the switching period. During operating conditions when the switching period is relatively
short, such as at high-load and low-line, the average power delivered per cycle varies significantly based on the
number of valleys skipped between cycles. As a consequence, valley-skipping adds additional ripple voltage to
the output with a frequency and amplitude dependent upon the loop-response of the shunt-regulator. For a load
with an average power level between that of cycles with fewer valleys skipped and cycles with more valleys
skipped, the voltage-control loop modulates the FB current according to the loop-bandwidth and toggles
between longer and shorter switching periods to match the required average output power.
7.3.3 Startup Operation
An internal high-voltage startup switch, connected to the bulk-capacitor voltage (VBULK) through the HV pin,
charges the VDD capacitor. This startup switch functions similarly to a current source providing typically 250 µA
to charge the VDD capacitor. When VVDD reaches the 21-V UVLO turnon threshold the controller is enabled, the
converter starts switching, and the startup switch turns off.
Often at initial turnon, the output capacitor is in a fully discharged state. The first three switching-cycle current
peaks are limited to IPP(min) to monitor for any initial input or output faults with limited power delivery. After these
three cycles, if the sampled voltage at VS is less than 1.33 V, the controller operates in a special startup mode.
In this mode, the primary current peak amplitude of each switching cycle is limited to approximately 0.63 ×
IPP(max) and DMAGCC increases from 0.425 to 0.735. These modifications to IPP(max) and DMAGCC during startup
allows high-frequency charge-up of the output capacitor to avoid audible noise while the demagnetization
voltage is low. Once the sampled VS voltage exceeds 1.38 V, DMAGCC is restored to 0.425 and the primary
current peak resumes as IPP(max). While the output capacitor charges, the converter operates in CC mode to
maintain a constant output current until the output voltage enters regulation. Thereafter, the controller responds
to the condition dictated by the control law. The time to reach output regulation consists of the time the VDD
capacitor charges to 21 V plus the time the output capacitor charges.
7.3.4 Fault Protection
The UCC28740-Q1 provides extensive fault protection. The protection functions include:
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• Output overvoltage
• Input undervoltage
• Internal overtemperature
• Primary overcurrent fault
• CS-pin fault
• VS-pin fault
A UVLO reset and restart sequence applies to all fault-protection events.
The output-overvoltage function is determined by the voltage feedback on the VS pin. If the voltage sample of
VS exceeds 4.6 V, the device stops switching and the internal current consumption becomes IFAULT which
discharges the VDD capacitor to the UVLO-turnoff threshold. After that, the device returns to the start state and
a startup sequence ensues.
The UCC28740-Q1 always operates with cycle-by-cycle primary peak current control. The normal operating
voltage range of the CS pin is 0.773 V to 0.194 V. An additional protection, not filtered by leading-edge blanking,
occurs if the CS pin voltage reaches 1.5 V, which results in a UVLO reset and restart sequence.
Current into the VS pin during the MOSFET on-time determines the line-input run and stop thresholds. While the
VS pin clamps close to GND during the MOSFET on-time, the current through RS1 is monitored to determine a
sample of VBULK. A wide separation of the run and stop thresholds allows for clean startup and shutdown of the
power supply with the line voltage. The run-current threshold is 225 µA and the stop-current threshold is 80 µA.
The internal overtemperature-protection threshold is 165°C. If the junction temperature reaches this threshold
the device initiates a UVLO-reset cycle. If the temperature is still high at the end of the UVLO cycle, the
protection cycle repeats.
Protection is included in the event of component failures on the VS pin. If complete loss of feedback information
on the VS pin occurs, the controller stops switching and restarts.
7.4 Device Functional Modes
7.4.1 Secondary-Side Optically Coupled Constant-Voltage (CV) Regulation
图 7-2 shows a simplified flyback convertor with the main output-regulation blocks of the device shown, along
with typical implementation of secondary-side-derived regulation. The power-train operation is the same as any
DCM-flyback circuit. A feedback current is optically coupled to the controller from a shunt-regulator sensing the
output voltage.
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+ VF
œ
VOUT
VBULK
COUT
Timing
Primary
Secondary
RLOAD
RS1
Auxiliary
VCL
Discriminator and
Sampler
VS
GD
DRV
CS
Control Law
RS2
VDD
RTL
Minimum Period
and Peak
Primary Current
RCS
Zero Crossings
ROPT
RFB1
Mirror Network
FB
IOPT
ZFB
IFB
RFB2
图7-2. Simplified Flyback Convertor (With the Main Voltage Regulation Blocks)
In this configuration, a secondary-side shunt-regulator, such as the TL431, generates a current through the input
photo-diode of an optocoupler. The photo-transistor delivers a proportional current that is dependent on the
current-transfer ratio (CTR) of the optocoupler to the FB input of the UCC28740-Q1 controller. This FB current
then converts into the VCL by the input-mirror network, detailed in the device block diagram (see 节 7.2). Output-
voltage variations convert to FB-current variations. The FB-current variations modify the VCL which dictates the
appropriate IPP and fSW necessary to maintain CV regulation. At the same time, the VS input senses the auxiliary
winding voltage during the transfer of transformer energy to the secondary output to monitor for an output
overvoltage condition. When fSW reaches the target maximum frequency, chosen between 32 kHz and 100 kHz,
CC operation is entered and further increases in VCL have no effect.
图 7-3 shows that as the secondary current decreases to zero, a clearly defined down slope reflects the
decreasing rectifier VF combined with stray resistance voltage-drop (ISRS). To achieve an accurate
representation of the secondary output voltage on the auxiliary winding, the discriminator reliably blocks the
leakage-inductance reset and ringing while continuously sampling the auxiliary voltage during the down slope
after the ringing diminishes. The discriminator then captures the voltage signal at the moment that the
secondary-winding current reaches zero. The internal overvoltage threshold on VS is 4.6 V. Temperature
compensation of –0.8 mV/°C on the overvoltage threshold offsets the change in the output-rectifier forward
voltage with temperature. The resistor divider is selected as outlined in the VS pin description (see 节7.3.1).
VS Sample
(VOUT+VF) NAS
0 V
œVBULK / NPA
图7-3. Auxiliary-Winding Voltage
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The UCC28740-Q1 VS-signal sampler includes signal-discrimination methods to ensure an accurate sample of
the output voltage from the auxiliary winding. Controlling some details of the auxiliary-winding signal to ensure
reliable operation is necessary; specifically, the reset time of the leakage inductance and the duration of any
subsequent leakage-inductance ringing. See 图 7-4 for a detailed illustration of waveform criteria to ensure a
reliable sample on the VS pin.
The first detail to examine is the duration of the leakage-inductance reset pedestal, tLK_RESET, in 图7-4. Because
tLK_RESET mimics the waveform of the secondary-current decay, followed by a sharp downslope, tLK_RESET is
internally blanked for a duration which scales with the peak primary current. Keeping the leakage-reset time to
less than 600 ns for IPP(min), and less than 2.2 µs for IPP(max) is important.
The second detail is the amplitude of ringing on the VAUX waveform following tLK_RESET. The peak-to-peak
voltage variation at the VS pin must be less than 100 mVp-p for at least 200 ns before the end of the
demagnetization time (tDM). A concern with excessive ringing usually occurs during light or no-load conditions,
when tDM is at the minimum. The tolerable ripple on VS is scaled up to the auxiliary-winding voltage by RS1 and
RS2, and is equal to 100 mV × (RS1 + RS2) / RS2
.
tLK_RESET
tSMPL
VS ring (p-p)
0 V
tDM
图7-4. Auxiliary-Winding Waveform Details
During voltage regulation, the controller operates in frequency-modulation mode and amplitude-modulation
mode, as shown in 图 7-5. The internal operating-frequency limits of the device are 100 kHz and fSW(min). The
maximum operating frequency of the converter at full-load is generally chosen to be slightly lower than 100 kHz
to allow for tolerances, or significantly lower due to switching-loss considerations. The maximum operating
frequency and primary peak current chosen determine the transformer primary inductance of the converter. The
shunt-regulator bias power, output preload resistor (if any), and low-power conversion efficiency determine the
minimum-operating frequency of the converter. Voltage-loop stability compensation is applied at the shunt-
regulator which drives the opto-coupled feedback signal. The tolerances chosen for the shunt-regulator
reference and the sense resistors determines the regulation accuracy.
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Control-Law Profile in Constant-Voltage (CV) Mode
IPP(max)
100 kHz
IPP
fSW
32 kHz
IPP(max) / 4
FM
AM
FM
fSW = 170 Hz
3 kHz
0 V
0.75 V
1.3 V
2.2 V
3.55 V
4.9 V
5 V
Control Law Voltage, Internal (VCL
)
26 µA
22.1 µA 19.3 µA
14.6 µA
7.55 µA
0.5 µA
Corresponding Feedback Current, FB Input (IFB
)
图7-5. Frequency and Amplitude Modulation Modes (During CV Regulation)
The level of feedback current (IFB) into the FB pin determines the internal VCL which determines the operating
point of the controller while in CV mode. When IFB rises above 22 µA, no further decrease in fSW occurs. When
the output-load current increases to the point where maximum fSW is reached, control transfers to CC mode. All
current, voltage, frequency, breakpoints, and curve-segment linearity depicted in 图 7-5 are nominal. 图 7-5
indicates the general operation of the controller while in CV mode, although minor variations may occur from part
to part. An internal frequency-dithering mechanism is enabled when IFB is less than 14.6 µA to help reduce
conducted EMI (including during CC-mode operation), and is disabled otherwise.
7.4.2 Primary-Side Constant-Current (CC) Regulation
When the load current of the converter increases to the predetermined constant-current limit, operation enters
CC mode. In CC mode, output voltage regulation is lost and the shunt-regulator drives the current and voltage at
FB to minimum. During CC mode, timing information at the VS pin and current information at the CS pin allow
accurate regulation of the average current of the secondary winding. The CV-regulation control law dictates that
as load increases approaches CC regulation the primary peak current will be at IPP(max). The primary peak
current, turns-ratio, demagnetization time tDM, and switching period tSW determine the secondary average output
current (see 图 7-6). Ignoring leakage-inductance effects, the average output current is given by 方程式 5. When
the demagnetization duty-cycle reaches the CC-regulation reference, DMAGCC, in the current-control block, the
controller operates in frequency modulation (FM) mode to control the output current for any output voltage at or
below the voltage-regulation target as long as the auxiliary winding keeps VVDD above the UVLO turnoff
threshold. As the output voltage falls, tDM increases. The controller acts to increase tSW to maintain the ratio of
tDM to switching period (tDM / tSW) at a maximum of 0.425 (DMAGCC), thereby maintaining a constant average
output current.
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I
S ´ NS
IPP
NP
tON
tDM
tSW
UDG-12203
图7-6. Transformer-Current Relationship
I
N
t
DM
PP
P
´
I
=
´
OUT
2
N
t
SW
S
(5)
Fast, accurate, opto-coupled CV control combined with line-compensated PSR CC control results in high-
performance voltage and current regulation which minimizes voltage deviations due to heavy load and unload
steps, as illustrated by the V-I curve in 图7-7.
VOCV
VO(min)
IOCC 5%
Minimum allowable
transient voltage level
for heavy load step
IOCC
Output Current (IO)
图7-7. Typical Target Output V-I Characteristic
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The UCC28740-Q1 is a flyback controller that provides constant-voltage (CV) mode control and constant current
(CC) mode control for precise output regulation. While in CV operating range, the controller uses an opto-coupler
for tight voltage regulation and improved transient response to large load steps. Accurate regulation while in CC
mode is provided by primary side control. The UCC28740-Q1 uses frequency modulation, peak primary current
modulation, valley switching and valley hopping in its control algorithm in order to maximize efficiency over the
entire operating range.
8.2 High Voltage Applications
The UCC28740-Q1 offers integrated 700-V start up through the HV pin. However for application where the input
(VBULK) is higher than 700-V the HV pin should be biased using a stacked capacitor bank (CIN1, CIN2) illustrated
in 图8-1.
VBULK
+VOUT
CIN1
COUT
-VOUT
HV Pin
CIN2
RCS
图8-1. Implementation to Support > 700 V Inputs
8.3 Typical Application
The UCC28740-Q1 is well suited for use in isolated off-line systems requiring high efficiency and fault protection
features such as USB compliant adapters and chargers for consumer electronics such a smart phones, tablet
computers, and cameras. A 10-W application for a USB charger is shown in 图8-2.
This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the
UCC28740-Q1 controller. See 图 8-2 for component names and network locations. The design procedure
equations use terms that are defined below.
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+ VF
œ
VOUT
COUT
NP
NS
VIN
CIN
UCC28740-Q1
SOIC-7
RTL
+ VFA
œ
VAUX
NA
VVDD
VDD
HV
ROPT
RFB1
CVDD
RS1
VE
VS
FB
DRV
CS
RLC
RFB3
CFB3
RS2
IOPT
ZFB
RCS
GND
IFB
RFB4
RFB2
Copyright © 2019, Texas Instruments Incorporated
图8-2. Design Procedure Application Example
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8.3.1 Design Requirements
表8-1. Design Parameters
PARAMETER
INPUT CHARACTERISTICS
Input Voltage, VIN
NOTES AND CONDITIONS
MIN
85
NOM
MAX
UNIT
115/230
0.265
265
VRMS
ARMS
Hz
Maximum Input Current
Line Frequency
VIN = VINmin, IOUT = IOUTmax
47
60/50
63
20
No Load Input Power
Consumption
mW
V
V
INmin ≤VIN ≤VINmax, IOUT = 0 A
OUTPUT CHARACTERISTICS
INmin ≤VIN ≤VINmax, 0 A ≤IOUT
≤
Output Voltage, VOUT
4.95
5
5.05
V
A
IOUTmax
Output Load Current, CV Mode,
IOUTmax
1.995
2.1
2.205
V
INmin ≤VIN ≤VINmax
Line Regulation: VINmin ≤VIN ≤VINmax
OUT ≤IOUTmax
,
0.1%
0.1%
I
Output Voltage Regulation
Load Regulation: 0 A ≤IOUT ≤IOUTmax
INmin ≤VIN ≤VINmax, 0 A ≤IOUT
V
≤
Output Voltage Ripple
150
2.5
2
mVpp
IOUTmax
Output Overcurrent, ICCC
A
V
V
V
INmin ≤VIN ≤VINmax
Minimum Output Voltage, CC
Mode
1.78
68
INmin ≤VIN ≤VINmax, IOUT = IOCC
Brown-out Protection
IOUT = IOUTmax
VRMS
V
Transient Response Undershoot IOUT = IOUTmax to 0-A load transient
4.3
1.2
Transient Response Time
SYSTEMS CHARACTERISTICS
Switching Frequency, fSW
IOUT = IOUTmax to 0-A load transient
20
71
ms
kHz
°C
25%, 50%, 75%, 100% load average at
nominal input voltages
Average Efficiency
81%
25
Operating Temperature
8.3.2 Detailed Design Procedure
8.3.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC28740-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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8.3.2.2 Standby Power Estimate and No-Load Switching Frequency
Assuming minimal no-load standby power is a critical design requirement, determine the estimated no-load
power loss based on an accounting of all no-load operating and leakage currents at their respective voltages.
Close attention to detail is necessary to account for all of the sources of leakage, however, in many cases,
prototype measurement is the only means to obtain a realistic estimation of total primary and secondary leakage
currents. At present, converter standby power is certified by compliance-agency authorities based on steady-
state room-temperature operation at the highest nominal input voltage rating (typically 230 Vrms).
方程式 6 estimates the standby power loss from the sum of all leakage currents of the primary-side components
of the converter. These leakage currents are measured in aggregate by disconnecting the HV input of the
controller from the bulk-voltage rail to prevent operating currents from interfering with the leakage measurement.
nP
PPRI_ SB = VBULK
ì
IPRI_LK
K
ƒ
k=1
(6)
方程式 7 estimates the standby power loss from the sum of all leakage and operating currents of the secondary-
side components on the output of the converter. Leakage currents result from reverse voltage applied across the
output rectifier and capacitors, while the operating current includes currents required by the shunt-regulator,
optocoupler, and associated components.
nS
PSEC _ SB = VOCV
ì
ISEC
K
ƒ
k=1
(7)
方程式 8 estimates the standby power loss from the sum of all leakage and operating currents of the auxiliary-
side components on the controller of the converter. Leakage currents of the auxiliary diode and capacitor are
usually negligible. The operating current includes the wait-state current, IWAIT, of the UCC28740-Q1 controller,
plus the optocoupler-output current for the FB network in the steady-state no-load condition. The VDD voltage in
the no-load condition VVDDNL are the lowest practicable value to minimize loss.
na
PAUX _ SB = VVDDNL
ì
IAUX
K
ƒ
k=1
(8)
Note that PPRI_SB is the only loss that is not dependent on transformer conversion efficiency. PSEC_SB and
PAUX_SB are processed through the transformer and incur additional losses as a consequence. Typically, the
transformer no-load conversion efficiency ηSWNL lies in the range of 0.50 to 0.70. Total standby input power (no-
load condition) is estimated by 方程式9.
1
PSB = P
+
P
+ PAUX _ SB
(
)
PRI_SB
SEC_ SB
hSWNL
(9)
Although the UCC28740-Q1 is capable of operating at the minimum switching frequency of 170 Hz, a typical
converter is likely to require a higher frequency to sustain operation at no-load. An accurate estimate of the no-
load switching frequency fSWNL entails a thorough accounting of all switching-related energy losses within the
converter including parasitic elements of the power-train components. In general, fSWNL is likely to lie within the
range of 400 Hz to 800 Hz. A more detailed treatment of standby power and no-load frequency is beyond the
scope of this data sheet.
8.3.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
Determine the minimum voltage on the input bulk capacitance, CB1 and CB2 total, in order to determine the
maximum Np-to-Ns turns-ratio of the transformer. The input power of the converter based on target full-load
efficiency, the minimum input RMS voltage, and the minimum AC input frequency determine the input
capacitance requirement.
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Maximum input power is determined based on IOCC, VOCV, VCBC (if used), and the full-load conversion-efficiency
target.
V
+ VCBC ì I
(
=
)
OCV
OCC
P
IN
h
(10)
方程式11 provides an accurate solution for the total input capacitance based on a target minimum bulk-capacitor
voltage. Alternatively, to target a given input capacitance value, iterate the minimum capacitor voltage to achieve
the target capacitance value.
æ
ö
÷
æ
ö
÷
÷
ø
VBULK(min)
1
ç
ç
ç
è
2P ´ 0.25 +
´ arcsin
IN
ç
è
2p
÷
2 ´ V
IN(min)
ø
CBULK
=
2
2
2V
(
- VBULK(min) ´ f
LINE
)
IN(min)
(11)
8.3.2.4
If using the stacked capacitor bank of CIN1 and CIN2 of figure 18 please size these capacitors with the following
equation
%
= %+02 = %$7.- × 2
+01
(12)
8.3.2.5 Transformer Turns-Ratio, Inductance, Primary Peak Current
The target maximum switching frequency at full-load, the minimum input-capacitor bulk voltage, and the
estimated DCM resonant time determine the maximum primary-to-secondary turns-ratio of the transformer.
Initially determine the maximum-available total duty-cycle of the on-time and secondary conduction time based
on the target switching frequency, fMAX, and DCM resonant time. For DCM resonant frequency, assume 500 kHz
if an estimate from previous designs is not available. At the transition-mode operation limit of DCM, the interval
required from the end of secondary current conduction to the first valley of the VDS voltage is ½ of the DCM
resonant period (tR), or 1 µs assuming 500 kHz resonant frequency. The maximum allowable MOSFET on-time
DMAX is determined using 方程式13.
t
≈
’
R
DMAX = 1-DMAGCC
-
ì fMAX
∆
«
÷
◊
2
(13)
When DMAX is known, the maximum primary-to-secondary turns-ratio is determined with 方程式 14. DMAGCC is
defined as the secondary-diode conduction duty-cycle during CC operation and is fixed internally by the
UCC28740-Q1 at 0.425. The total voltage on the secondary winding must be determined, which is the sum of
VOCV, VF, and VOCBC. For the 5-V USB-charger applications, a turns ratio range of 13 to 15 is typically used.
DMAX ´ VBULK(min)
NPS(max)
=
DMAGCC ´ V
(
+ VF + VOCBC
)
OCV
(14)
A higher turns-ratio generally improves efficiency, but may limit operation at low input voltage. Transformer
design iterations are generally necessary to evaluate system-level performance trade-offs. When the optimum
turns-ratio NPS is determined from a detailed transformer design, use this ratio for the following parameters.
The UCC28740-Q1 constant-current regulation is achieved by maintaining DMAGCC at the maximum primary
peak current setting. The product of DMAGCC and VCST(max) defines a CC-regulating voltage factor VCCR which is
used with NPS to determine the current-sense resistor value necessary to achieve the regulated CC target, IOCC
(see 方程式15).
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Because a small portion of the energy stored in the transformer does not transfer to the output, a transformer-
efficiency term is included in the RCS equation. This efficiency number includes the core and winding losses, the
leakage-inductance ratio, and a bias-power to maximum-output-power ratio. An overall-transformer efficiency of
0.91 is a good estimate based on 3.5% leakage inductance, 5% core & winding loss, and 0.5% bias power, for
example. Adjust these estimates as appropriate based on each specific application.
V
´N
PS
CCR
R
=
´ h
XFMR
CS
2I
OCC
(15)
The primary transformer inductance is calculated using the standard energy storage equation for flyback
transformers. Primary current, maximum switching frequency, output voltage and current targets, and
transformer power losses are included in 方程式17.
First, determine the transformer primary peak current using 方程式 16. Peak primary current is the maximum
current-sense threshold divided by the current-sense resistance.
VCST(max)
=
IPP(max)
RCS
(16)
(17)
2 V
(
+ VF + VOCBC ´ I
)
OCV
OCC
LP
=
2
hXFMR ´ IPP(max) ´ fMAX
NAS is determined by the lowest target operating output voltage while in constant-current regulation and by the
VDD UVLO turnoff threshold of the UCC28740-Q1. Additional energy is supplied to VDD from the transformer
leakage-inductance which allows a lower turns ratio to be used in many designs.
VVDD(off) + VFA
NAS
=
VOCC + VF
(18)
8.3.2.6 Transformer Parameter Verification
Because the selected transformer turns-ratio affects the MOSFET VDS and the secondary and auxiliary rectifier
reverse voltages, a review of these voltages is important. In addition, internal timing constraints of the
UCC28740-Q1 require a minimum on time of the MOSFET (tON) and a minimum demagnetization time (tDM) of
the transformer in the high-line minimum-load condition. The selection of fMAX, LP, and RCS affects the minimum
tON and tDM
.
方程式 19 and 方程式 20 determine the reverse voltage stresses on the secondary and auxiliary rectifiers. Stray
inductance can impress additional voltage spikes upon these stresses and snubbers may be necessary.
V
ì
2
IN(max)
VREVS
=
ì VOV
NPS
(19)
(20)
V
ì
2
IN(max)
VREVA
=
ì VVDD
NPA
For the MOSFET VDS peak voltage stress, an estimated leakage inductance voltage spike (VLK) is included.
VDSPK = V
ì
2 + V
+ VF + VOCBC ì N + VLK
)
OCV PS
(
IN(max)
(21)
方程式 22 determines if tON(min) exceeds the minimum tON target of 280 ns (maximum tCSLEB). 方程式 23 verifies
that tDM(min) exceeds the minimum tDM target of 1.2 µs.
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IPP(max)
LP
tON(min)
=
ì
KAM
V
ì 2
IN(max)
(22)
(23)
tON(min) ì V
ì 2
IN(max)
tDM(min)
=
NPS ì V
+ VF
OCV
8.3.2.7 VS Resistor Divider, Line Compensation
The VS divider resistors determine the output overvoltage detection point of the flyback converter. The high-side
divider resistor (RS1) determines the input-line voltage at which the controller enables continuous DRV operation.
RS1 is determined based on transformer primary-to-auxiliary turns-ratio and desired input voltage operating
threshold.
V
´
2
IN(run)
RS1
=
NPA ´ IVSL(run)
(24)
The low-side VS pin resistor is then selected based on the desired overvoltage limit, VOV
.
RS1 ì VOVP
RS2
=
NAS ì V - VF - V
OV
OVP
(25)
The UCC28740-Q1 maintains tight constant-current regulation over varying input line by using the line-
compensation feature. The line-compensation resistor (RLC) value is determined by current flowing in RS1 and
the total internal gate-drive and external MOSFET turnoff delay. Assume an internal delay of 50 ns in the
UCC28740-Q1.
K
´R ´R ´ t ´N
LC
S1
CS
D
PA
R
=
LC
L
P
(26)
8.3.2.8 Output Capacitance
The output capacitance value is often determined by the transient-response requirement from the no-load
condition. For example, in typical low-power USB-charger applications, there is a requirement to maintain a
minimum transient VO of 4.1 V with a load-step ITRAN from 0 mA to 500 mA. Yet new higher-performance
applications require smaller transient voltage droop VOΔ with ITRAN of much greater amplitude (such as from no-
load to full-load), which drives the need for high-speed opto-coupled voltage feedback.
ITRAN ì tRESP
COUT
í
VOD
(27)
where
• tRESP is the time delay from the moment ITRAN is applied to the moment when IFB falls below 1 µA
Additional considerations for the selection of appropriate output capacitors include ripple-current, ESR, and ESL
ratings necessary to meet reliability and ripple-voltage requirements. Detailed design criteria for these
considerations are beyond the scope of this datasheet.
8.3.2.9 VDD Capacitance, CVDD
The capacitance on VDD must supply the primary-side operating current used during startup and between low-
frequency switching pulses. The largest result of three independent calculations denoted in 方程式 28, 方程式
29, and 方程式30 determines the value of CVDD
.
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At startup, when VVDD(on) is reached, CVDD alone supplies the device operating current and MOSFET gate
current until the output of the converter reaches the target minimum-operating voltage in CC regulation, VOCC
.
Now the auxiliary winding sustains VDD for the UCC28740-Q1 above UVLO. The total output current available to
the load and to charge the output capacitors is the CC-regulation target, IOCC. 方程式 28 assumes that all of the
output current of the converter is available to charge the output capacitance until VOCC is achieved. For typical
applications, 方程式 28 includes an estimated qGfSW(max) of average gate-drive current and a 1-V margin added
to VVDD
.
COUT ì VOCC
IOCC
I
RUN + qGfSW(max)
ì
(
)
CVDD
í
VDD(on) - V
+1 V
VDD(off)
(28)
During a worst-case un-load transient event from full-load to no-load, COUT overcharges above the normal
regulation level for a duration of tOV, until the output shunt-regulator loading is able to drain VOUT back to
regulation. During tOV, the voltage feedback loop and optocoupler are saturated, driving maximum IFB and
temporarily switching at fSW(min). The auxiliary bias current expended during this situation exceeds that normally
required during the steady-state no-load condition. 方程式29 calculates the value of CVDD (with a safety factor of
2) required to ride through the tOV duration until steady-state no-load operation is achieved.
2 ì IAUXNL(max) ì tOV
CVDD
í
VVDDFL - V
+1 V
VDD(off)
(29)
Finally, in the steady-state no-load operating condition, total no-load auxiliary-bias current, IAUXNL is provided by
the converter switching at a no-load frequency, fSWNL, which is generally higher than fSW(min). CVDD is calculated
to maintain a target VDD ripple voltage lower than ΔVVDD, using 方程式30.
1
IAUXNL
ì
fSWNL
DVVDD
CVDD
í
(30)
8.3.2.10 Feedback Network Biasing
Achieving very low standby power while maintaining high-performance load-step transient response requires
careful design of the feedback network. Optically coupled secondary-side regulation is used to provide the rapid
response needed when a heavy load step occurs during the no-load condition. One of the most commonly used
devices to drive the optocoupler is the TL431 shunt-regulator, due to its simplicity, regulation performance, and
low cost. This device requires a minimum bias current of 1 mA to maintain regulation accuracy. Together with the
UCC28740-Q1 primary-side controller, careful biasing will ensure less than 30 mW of standby power loss at
room temperature. Where a more stringent standby loss limit of less than 10 mW is required, the TLV431 device
is recommended due to its minimum 80-µA bias capability.
Facilitating these low standby-power targets is the approximate 23-µA range of the FB input for full to no-load
voltage regulation. The control-law profile graph (see 图 7-5) shows that for FB-input current greater than 22 µA,
no further reduction in switching frequency is possible. Therefore, minimum power is converted at fSW(min)
.
However, the typical minimum steady-state operating frequency tends to be in the range of several-hundred
Hertz, and consequently the maximum steady-state FB current at no-load will be less than IFBMAX. Even so,
prudent design practice dictates that IFBMAX should be used for conservative steady-state biasing calculations. At
this current level, VFBMAX can be expected at the FB input.
Referring to the Design Procedure Application Example in 图 8-2, the main purpose of RFB4 is to speed up the
turnoff time of the optocoupler in the case of a heavy load-step transient condition. The value of RFB4 is
determined empirically due to the variable nature of the specific optocoupler chosen for the design, but tends to
fall within the range of 10 kΩ to 100 kΩ. A tradeoff must be made between a lower value for faster transient
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response and a higher value for lower standby power. RFB4 also serves to set a minimum bias current for the
optocoupler and to drain dark current.
It is important to understand the distinction between steady-state no-load bias currents and voltages which affect
standby power, and the varying extremes of these same currents and voltages which affect regulation during
transient conditions. Design targets for minimum standby loss and maximum transient response often result in
conflicting requirements for component values. Trade-offs, such as for RFB4 as discussed previously, must be
made.
During standby operation, the total auxiliary current (used in 方程式 8) is the sum of IWAIT into the IC and the no-
load optocoupler-output current ICENL. This optocoupler current is given by 方程式31.
VFBMAX
ICENL = IFBMAX
+
RFB4
(31)
For fast response, the optocoupler-output transistor is biased to minimize the variation of VCE between full-load
and no-load operation. Connecting the emitter directly to the FB input of the UCC28740-Q1 is possible, however,
an unload-step response may unavoidably drive the optocoupler into saturation which will overload the FB input
with full VDD applied. A series-resistor RFB3 is necessary to limit the current into FB and to avoid excess draining
of CVDD during this type of transient situation. The value of RFB3 is chosen to limit the excess IFB and RFB4
current to an acceptable level when the optocoupler is saturated. Like RFB4, the RFB3 value is also chosen
empirically during prototype evaluation to optimize performance based on the conditions present during that
situation. A starting value may be estimated using 方程式32.
VVDDNL -1 V
ICENL
RFB3
=
(32)
Note that RFB3 is estimated based on the expected no-load VDD voltage, but full-load VDD voltage will be higher
resulting in initially higher ICE current during the unload-step transient condition. Because RFB3 is interposed
between VE and the FB input, the optocoupler transistor VCE varies considerably more as ICE varies and
transient response time is reduced. Capacitor CFB3 across RFB3 helps to improve the transient response again.
The value of CFB3 is estimated initially by equating the RFB3CFB3 time constant to 1 ms, and later is adjusted
higher or lower for optimal performance during prototype evaluation.
The optocoupler transistor-output current ICE is proportional to the optocoupler diode input current by its current
transfer ratio, CTR. Although many optocouplers are rated with nominal CTR between 50% and 600%, or are
ranked into narrower ranges, the actual CTR obtained at the low currents used with the UCC28740-Q1 falls
around 5% to 15%. At full-load regulation, when IFB is near zero, VFB is still approximately 0.4 V and this sets a
minimum steady-state current for ICE through RFB4. After choosing an optocoupler, the designer must
characterize its CTR over the range of low output currents expected in this application, because optocoupler
data sheets rarely include such information. The actual CTR obtained is required to determine the diode input
current range at the secondary-side shunt-regulator.
Referring again to 图 8-2, the shunt-regulator (typically a TL431) current must be at least 1 mA even when
almost no optocoupler diode current flows. Since even a near-zero diode current establishes a forward voltage,
ROPT is selected to provide the minimum 1-mA regulator bias current. The optocoupler input diode must be
characterized by the designer to obtain the actual forward voltage versus forward current at the low currents
expected. At the full-load condition of the converter, IFB is around 0.5 µA, ICE may be around (0.4 V / RFB4), and
CTR at this level is about 10%, so the diode current typically falls in the range of 25 µA to 100 µA. Typical opto-
diode forward voltage at this level is about 0.97 V which is applied across ROPT. If ROPT is set equal to 1 kΩ, this
provides 970 µA plus the diode current for IOPT
.
As output load decreases, the voltage across the shunt-regulator also decreases to increase the current through
the optocoupler diode. This increases the diode forward voltage across ROPT. CTR at no-load (when ICE is
higher) is generally a few percent higher than CTR at full-load (when ICE is lower). At steady-state no-load
condition, the shunt-regulator current is maximized and can be estimated by 方程式 31 and 方程式 33. IOPTNL
,
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plus the sum of the leakage currents of all the components on the output of the converter, constitute the total
current required for use in 方程式7 to estimate secondary-side standby loss.
ICENL
VOPTNL
IOPTNL
=
+
CTRNL
ROPT
(33)
The shunt-regulator voltage can decrease to a minimum, saturated level of about 2 V. To prevent excessive
diode current, a series resistor, RTL, is added to limit IOPT to the maximum value necessary for regulation. 方程式
34 provides an estimated initial value for RTL, which may be adjusted for optimal limiting later during the
prototype evaluation process.
VOUTNL - VOPTNL - 2 V
IOPTNL
RTL
=
(34)
The output-voltage sense-network resistors RFB1 and RFB2 are calculated in the usual manner based on the
shunt-regulator reference voltage and input bias current. Having characterized the optocoupler at low currents
and determined the initial values of RFB1, RFB2, RFB3, RFB4, CFB3, ROPT and RTL using the above procedure, the
DC-bias states of the feedback network can be established for steady-state full-load and no-load conditions.
Adjustments of these initial values may be necessary to accommodate variations of the UCC28740-Q1,
optocoupler, and shunt-regulator parameters for optimal overall performance.
The shunt-regulator compensation network, ZFB, is determined using well-established design techniques for
control-loop stability. Typically, a type-II compensation network is used. The compensation design procedure is
beyond the scope of this datasheet.
8.3.3 Application Curves
The transient response shown in 图 8-3 was taken with a 115 VAC, 60 Hz input voltage and a load transition
from 0 A to full load. Channel 1 is the load current on a scale of 1 A per division, channel 4 is the otutput voltage
on a scale of 1 V per division. The cursor shows the minimum acceptable voltage limit, 4.30 V, under transient
conditions. Also note that the output waveform was taken with the probe on TP5 with the ground referenced to
TP4 but not using the tip and barrel technique accounting for the high frequency noise seen on the waveform.
The typical switching waveform can be seen in 图 8-4. Channel 1 shows the VS pin at 2 V per division and
channel 2 shows the MOSFET drain to source voltage at 100 V per division. The scan was taken at 1.8-A load,
115-VAC, 60-Hz input voltage. At this operating point, the switching frequency is dithering between 58.8 kHz and
52.6 kHz due to valley skipping.
The UCC28740-Q1 controller employs a unique control mechanism to help with EMI compliance. As shown in 图
8-5, the DRV pin, shown as channel 3, drives the gate of the MOSFET with a sequence of pulses in which there
will be two longer pulses, two medium pulses, and two shorter pulses at any operating point starting with the
amplitude modulation mode. The EMI dithering is not enabled at light load. Figure x shows the result of these
varying pulse widths on the CS signal, shown on channel 4. The longer pulses result in a peak current threshold
of 808 mV, the medium length pulses are shown measured at 780 mV, and the shorter pulses measure a
threshold voltage of 752 mV. This dithering adds to the frequency jitter caused by valley skipping and results in a
spread spectrum for better EMI compliance.
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115 VAC, 60 Hz
0 A to 2 A
CH 1 = VS
CH 2 = VDS
CH 1 = Load Current, 1 A/DIV
IOUT = 1.8 A
VIN = 115 VAC, 60 Hz
CH 4 = VOUT, cursor shows minimum limit
图8-4. Switching Waveform
图8-3. Transient Response
0.95
0.9
115 V, 60 Hz
230 V, 50 Hz
0.85
0.8
0.75
0.7
0
0.5
1 1.5
Load Current (A)
2
2.5
D005
图8-6. Efficiency
图8-5. EMI Dithering
0.82
0.815
0.81
20
18
16
14
12
10
8
0.805
0.8
0.795
0.79
0.785
0.78
0.775
0.77
6
0.765
0.76
4
0.755
0.75
2
0
85
80
110
140
170
Input Voltage (VAC
200
)
230
260
115
145
175
Input Voltage (VAC
205
)
235
265
D004
D003
图8-7. Average Efficiency
图8-8. No Load Power Consumption
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6
5.5
5
100
90
80
70
60
50
40
30
20
10
0
120 VDC
163 VDC
325 VDC
375 VDC
4.5
4
3.5
3
2.5
2
1.5
1
85 VAC, 60 Hz
115 VAC, 60 Hz
230 VAC, 50 Hz
265 VAC, 50 Hz
0.5
0
0
0.5
1 1.5
Load Current (A)
2
2.5
0
0.3
0.6
0.9 1.2
Load Current (A)
1.5
1.8
2.1
D002
D001
图8-9. VOUT vs. IOUT
图8-10. Control Law
60
200
Gain (dB)
Phase (degrees)
30
0
100
0
-30
-100
-60
10
-200
10000
100
1000
Frequency (Hz)
g6_b
VIN = 115 VAC
IOUT = 2 A
图8-11. Bode Plot
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9 Power Supply Recommendations
The UCC28740-Q1 is designed to be used with a Universal AC input, from 85 VAC to 265 VAC, at 47 Hz to 63
Hz. Other input line conditions can be used provided the HV pin can be set up to provide 500 µA to charge the
VDD capacitor for start-up through the internal startup switch. Once the VDD reaches the 21-V UVLO turnon
threshold, the VDD rail should be kept within the limits of the Bias Supply Input section of the 节 6.5 table. To
avoid the possibility that the device might stop switching, VDD must not be allowed to fall below the UVLO
VVDD(off) range.
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10 Layout
10.1 Layout Guidelines
In general, try to keep all high current loops as short as possible. Keep all high current/high frequency traces
away from other traces in the design. If necessary, high frequency/high current traces should be perpendicular to
signal traces, not parallel to them. Shielding signal traces with ground traces can help reduce noise pick up.
Always consider appropriate clearances between the high-voltage connections and any low-voltage nets.
10.1.1 VDD Pin
The VDD pin must be decoupled to GND with good quality, low ESR, low ESL ceramic bypass capacitors with
short traces to the VDD and GND pins. The value of the required capacitance on VDD is determined as shown in
the 节8 section.
10.1.2 VS Pin
The trace between the resistor divider and the VS pin should be as short as possible to reduce/eliminate
possible EMI coupling. The lower resistor of the resistor divider network connected to the VS pin should be
returned to GND with short traces. Avoid adding any external capacitance to the VS pin so that there is no delay
of signal; added capacitance would interfere with the accurate sensing of the timing information used to achieve
valley switching and also control the duty cycle of the transformer secondary current.
10.1.3 FB Pin
The PCB tracks from the opto-coupler to the FB pin should have minimal loop area. If possible, it is
recommended to provide screening for the FB trace with ground planes. A resistor to GND from the FB pin is
recommended to speed up the turnoff time of the opto-coupler during a heavy load step transient. This resistor
should be placed as close as possible to FB and GND with short traces, the value of this resistor, RFB4, is
detailed in the 节8 section.
10.1.4 GND Pin
The GND pin is the power and signal ground connection for the controller. As with all PWM controllers, the
effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. Place all
decoupling and filter capacitors as close as possible to the device pins with short traces. The IC ground and
power ground should meet at the bulk capacitor’s return. Try to ensure that high frequency/high current from
the power stage does not go through the signal ground.
10.1.5 CS Pin
A small filter capacitor may be placed on CS to GND, with short traces, to filter any ringing that may be present
at light load conditions when driving MOSFETs with large gate capacitance. This capacitor may not be required
in all designs; however, it is wise to put a place holder for it in your designs. The current sense resistor should be
returned to the ground terminal of the input bulk capacitor to minimize the loop area containing the input
capacitor, the transformer, the MOSFET, and the current sense resistor.
10.1.6 DRV Pin
The track connected to DRV carries high dv/dt signals. Minimize noise pickup by routing the trace to this pin as
far away as possible from tracks connected to the device signal inputs, FB and VS. There is no requirement for a
Gate to Source resistor with this device.
10.1.7 HV Pin
Sufficient PCB trace spacing must be given between the high-voltage connections and any low-voltage nets. The
HV pin may be connected directly, or through series resistance, to the rectified high voltage input rail.
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10.2 Layout Example
CVDD
VDD
VS
HV
1
8
RS1
2
3
4
FB
DRV
CS
6
5
RLC
GND
CCS
CIN
CIN
图10-1. Layout Example Schematic
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For design tools see the UCC28740 Design Calculator
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC28740 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.1.2 Device Nomenclature
11.1.2.1 Capacitance Terms in Farads
CBULK
CVDD
COUT
The total input capacitance of CB1 and CB2.
The minimum required capacitance on the VDD pin.
The minimum output capacitance required.
11.1.2.2 Duty Cycle Terms
DMAGCC The secondary diode conduction duty-cycle limit in CC mode, 0.425.
DMAX MOSFET on-time duty-cycle.
11.1.2.3 Frequency Terms in Hertz
fLINE
The minimum input-line frequency.
fMAX
The target full-load maximum switching frequency of the converter.
The steady-state minimum switching frequency of the converter.
The minimum possible switching frequency (see 节6.5).
fMIN
fSW(min)
11.1.2.4 Current Terms in Amperes
IOCC
The converter output constant-current target.
IPP(max)
ISTART
ITRAN
The maximum transformer primary peak current.
The startup bias-supply current (see 节6.5).
The required positive load-step current.
The VS-pin run current (see 节6.5).
IVSL(run)
11.1.2.5 Current and Voltage Scaling Terms
KAM
KLC
The maximum-to-minimum peak primary current ratio (see 节6.5).
The current-scaling constant for line compensation(see 节6.5).
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ZHCSK45C –AUGUST 2019 –REVISED DECEMBER 2020
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11.1.2.6 Transformer Terms
LP
The transformer primary inductance.
NAS
NPA
NPS
The transformer auxiliary-to-secondary turns-ratio.
The transformer primary-to-auxiliary turns-ratio.
The transformer primary-to-secondary turns-ratio.
11.1.2.7 Power Terms in Watts
PIN
The converter maximum input power.
POUT
PSB
The full-load output power of the converter.
The total standby power.
11.1.2.8 Resistance Terms in Ohms
RCS
RESR
RPL
RS1
RS2
The primary peak-current programming resistance.
The total ESR of the output capacitor(s).
The preload resistance on the output of the converter.
The high-side VS-pin sense resistance.
The low-side VS-pin sense resistance.
11.1.2.9 Timing Terms in Seconds
tD The total current-sense delay including MOSFET-turnoff delay; add 50 ns to MOSFET delay.
tDM(min) The minimum secondary rectifier conduction time.
tON(min) The minimum MOSFET on time.
tR
The resonant frequency during the DCM dead time.
tRESP The maximum response time of the voltage-regulation control-loop to the maximum required load-step.
11.1.2.10 Voltage Terms in Volts
VBLK
The highest bulk-capacitor voltage for standby power measurement.
VBULK(min) The minimum valley voltage on CB1 and CB2 at full power.
VCCR
The constant-current regulation factor (see 节6.5).
The CS-pin maximum current-sense threshold (see 节6.5).
The CS-pin minimum current-sense threshold (see 节6.5).
The UVLO turnoff voltage (see 节6.5).
VCST(max)
VCST(min)
VVDD(off)
VVDD(on)
VDSPK
VF
The UVLO turnon voltage (see 节6.5).
The MOSFET drain-to-source peak voltage at high line.
The secondary-rectifier forward-voltage drop at near-zero current.
The auxiliary-rectifier forward-voltage drop.
VFA
VLK
The estimated leakage-inductance energy reset voltage.
The output voltage drop allowed during the load-step transient in CV mode.
VOΔ
VOCBC
The target cable-compensation voltage added to VOCV (provided by an external adjustment circuit
applied to the shunt-regulator). Set equal to 0 V if not used.
VOCC
VOCV
VOV
The converter lowest output voltage target while in constant-current regulation.
The regulated output voltage of the converter.
The maximum allowable peak output voltage.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDT2
34
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VOVP
The overvoltage-detection level at the VS input (see 节6.5).
VREVA
VREVS
VRIPPLE
The peak reverse voltage on the auxiliary rectifier.
The peak reverse voltage on the secondary rectifier.
The output peak-to-peak ripple voltage at full-load.
11.1.2.11 AC Voltage Terms in VRMS
VIN(max)
VIN(min)
VIN(run)
The maximum input voltage to the converter.
The minimum input voltage to the converter.
The converter startup (run) input voltage.
11.1.2.12 Efficiency Terms
The converter overall efficiency at full-power output.
η
The estimated efficiency of the converter at no-load condition, excluding startup resistance or bias
losses. For a 5-V USB-charger application, 60% to 65% is a good initial estimate.
ηSB
The transformer primary-to-secondary power-transfer efficiency.
ηXFMR
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
• 12-W Ultra-Wide Input Range Power Supply
• 36-W, Universal Input, >90% Efficiency, Dual Output, Auxiliary Supply Reference Design for Server PSU
• 60-W, 24-V, High-Efficiency Industrial Power Supply With Precision Voltage, Current, and Power Limit
• Choosing Standard Recovery Diode or Ultra-Fast Diode in Snubber
• Control Challenges for Low Power AC/DC Converters
• Integrated 30-W Sensorless BLDC Motor Drive Retrofit Reference Design With 90- to 265-V AC Input
• Using the UCC28740EVM-525 10 W Constant- Voltage, Constant-Current Charger Adaptor Module
• 100-W, 24-V, High Efficiency, High PF, Industrial Power Supply With Precision Current and Power Limit
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
11.5 Trademarks
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SLUSDT2
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC28740QDRQ1
ACTIVE
SOIC
D
7
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
28740Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC28740-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2023
Catalog : UCC28740
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
D0007A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
8
1
.100
[2.54]
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X .050
[1.27]
4
5
7X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4220728/A 01/2018
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0007A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
7X (.024)
[0.6]
(.100 )
[2.54]
SYMM
5
4
4X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220728/A 01/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0007A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7X (.061 )
[1.55]
SYMM
1
8
7X (.024)
[0.6]
(.100 )
[2.54]
SYMM
5
4
4X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4220728/A 01/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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