UCC27614DSGR [TI]
具有 4V UVLO、30V VDD 和低传播延迟的 10A/10A 单通道栅极驱动器 | DSG | 8 | -40 to 150;
| 型号： | UCC27614DSGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 4V UVLO、30V VDD 和低传播延迟的 10A/10A 单通道栅极驱动器 | DSG | 8 | -40 to 150 栅极驱动 驱动器 |
| 文件： | 总39页 (文件大小：3010K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC27614
ZHCSKO8C –JUNE 2021 –REVISED JANUARY 2022
具有–10V 输入能力的UCC27614 单通道30V、10A 低侧栅极驱动器
1 特性
3 说明
• 典型10A 灌电流，10A 拉电流输出
• 输入和使能引脚可承受高达–10V 的电压
• 绝对最大VDD 电压：30V
• 宽VDD 工作电压范围：4.5V 至26V，具有UVLO
功能
• 采用2mm X 2mm SON8 封装
• 典型值为17.5ns 的传播延迟
• SOIC8 封装的EN（使能）引脚
• IN–引脚可用于启用/禁用功能
• VDD 独立输入阈值（兼容TTL）
• 可用作反相或同相驱动器
UCC27614 是一款单通道、高速、低侧栅极驱动器，
能够有效地驱动 MOSFET、IGBT、SiC 和 GaN 电源
开关。UCC27614 的典型峰值驱动强度为 10A，这有
助于缩短电源开关的上升和下降时间、降低开关损耗并
提高效率。UCC27614 器件的短传播延迟可改善系统
的死区优化、控制环路响应，提高脉宽利用率和瞬态性
能，从而提高功率级效率。
UCC27614 可以在输入端处理 –10V 的电压，通过平
缓的接地弹跳提高系统稳健性。输入与电源电压无关，
可以连接大多数控制器输出，从而更大程度地提高控制
灵活性。独立的使能信号支持在不依赖主控制逻辑的情
况下对功率级进行控制。如果在系统中检测到故障，栅
极驱动器可以快速关断功率级（需要关断动力总成）。
使能功能还可提高系统稳健性。许多高频开关电源在电
源器件的栅极都存在高频噪音，这种噪音会进入栅极驱
动器的输出引脚，造成驱动器故障。UCC27614 具有
瞬态反向电流和反向电压功能，因此在这种情况下具有
优异的性能。
• 工作结温范围：–40°C 至150°C
2 应用
• 电信开关模式电源
• 功率因数校正(PFC) 电路
• 太阳能电源
• 电机驱动器
• 高频线路驱动器
• 脉冲变压器驱动器
• 高功率缓冲器
如果VDD 电压低于指定的 UVLO 阈值，强大的内部下
拉 MOSFET 可使输出保持低电平。此有源下拉特性可
进一步改善系统稳健性。UCC27614 器件采用2-mm ×
2mm 封装并提供 10A 驱动电流，可提高系统功率密
度。这种小型封装还可优化栅极驱动器放置并改进布
局。
VBias
+
CVDD
UCC27614
œ
EN/IN-
VDD
VDD
To Switch
Node
From
Controller
器件信息
封装(1)
封装尺寸（标称值）
2.0mm x 2.0mm
IN/IN+
器件型号
UCC27614
UCC27614
OUT
OUT
Rg
GND
SON (8)
SOIC (8)
4.90mm × 3.91mm
GND
(1) 如需了解所有可用封装，请见产品说明书末尾的可订购产品附
录。
简化版应用示意图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSE26
UCC27614
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ZHCSKO8C –JUNE 2021 –REVISED JANUARY 2022
Table of Contents
7.4 Device Functional Modes..........................................16
8 Applications and Implementation................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................24
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 26
10.3 Thermal Consideration............................................26
11 Device and Documentation Support..........................27
11.1 第三方产品免责声明................................................27
11.2 接收文档更新通知................................................... 27
11.3 支持资源..................................................................27
11.4 Trademarks............................................................. 27
11.5 Electrostatic Discharge Caution..............................27
11.6 术语表..................................................................... 27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Timing Diagrams.........................................................6
6.8 Typical Characteristics................................................8
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................13
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (November 2021) to Revision C (January 2022)
Page
• 从整个数据表中删除了“预告信息”通知...........................................................................................................1
• Added additional DESCRIPTION information...................................................................................................11
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5 Pin Configuration and Functions
IN+
GND
GND
OUT
1
2
3
4
IN-
8
7
6
5
VDD
VDD
OUT
2mm
图5-1. 8-Pin SON DSG Package Top View
UCC27614
1
2
3
4
VDD
IN
8
7
6
5
VDD
OUT
OUT
GND
EN
GND
图5-2. 8-Pin SOIC D Package Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
EN
SON DSG NO. SOIC D NO.
3
4,5
2
I
G
I
Enable or disable control pin. If not used, connect to VDD.
Device ground or reference
—
GND
IN
2,3
Non-inverting PWM input
—
1
IN+
I
Non-inverting PWM input. If not used, connect to VDD.
Inverting PWM input. If not used, connect to GND.
Output of the driver
—
—
IN-
8
I
OUT
4,5
6,7
O
Driver bias supply. Connect the positive node of the voltage source to this
pin through an impedance for high common mode noise rejection. Bypass
this pin with two ceramic capacitors, generally >=1 µF and 0.1 µF, which
are referenced to GND pin of this device.
VDD
6,7
1,8
P
Connect to GND through large copper plane.
This pad is not a low-impedance path to GND.
Thermal Pad
—
—
(1) I/O = Digital input/output, IA = Analog input, AO= Analog output, P = Power connection
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
–0.3
–0.3
–2
MAX
UNIT
Supply voltage
VDD
30
V
Output Voltage (DC)
VOUT
VOUT
VDD +0.3
VDD +3
30
V
V
Output Voltage (200-ns Pulse)
Input Voltage IN, EN, IN+, IN–
Operating junction temperature, TJ
V
–10
–40
150
°C
Soldering, 10 s
Reflow
300
Lead temperature
°C
°C
260
Storage temperature, Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See 节
6.4 of the data sheet for thermal limitations and considerations of packages.
(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range. All voltages are with reference to GND (unless otherwise noted)
MIN
NOM
MAX
26
UNIT
V
Supply voltage, VDD
4.5
12
Input voltage, IN, IN+, IN-, EN
Output Voltage, OUT
26
V
–10
0
VDD
150
V
Operating junction temperature, TJ
°C
–40
6.4 Thermal Information
UCC27614
SON (DSG)
8 PINS
67.9
UCC27614
THERMAL METRIC(1)
SOIC (D)
8 PINS
126.4
67.0
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top) Junction-to-case (top) thermal resistance
81.1
RθJB
ψJT
Junction-to-board thermal resistance
33.4
69.9
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.4
19.2
ψJB
33.4
12.2
69.1
n/a
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics Application
Report (SPRA953).
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6.5 Electrical Characteristics
Unless otherwise noted, VDD = 12 V, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, No load on the output.
Typical condition specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
BIAS CURRENTS
IVDDq
IVDD
IVDD
VDD quiescent supply current VIN+/VIN = 3.3 V, VIN- = 0 V, EN=VDD, VDD = 3.4 V
305
500
μA
mA
mA
VDD static supply current
VDD static supply current
VIN+/VIN = 3.3 V, VIN- = 0 V, EN = VDD
VIN+/VIN = 0 V, VIN- = 0 V, EN = VDD
0.64 0.92
0.71
0.75
1.0
4.0
1.0
VDD dynamic operating
current
fSW = 1000 kHz, EN = VDD, VIN+/VIN = 0 V to 3.3 V PWM, VIN-
= 0 V
IVDDO
IDIS
mA
mA
VDD disable current
VIN+/VIN = 0 V, VIN- = 3.3 V, EN = 0 V
UNDERVOLTAGE LOCKOUT (UVLO)
VVDD_ON VDD UVLO rising threshold
VVDD_OFF VDD UVLO falling threshold
3.8
3.5
4.1
3.8
4.4
4.1
V
V
VVDD_HY
VDD UVLO hysteresis
0.3
V
S
INPUT (IN, IN+)
Input signal high threshold,
output high
VIN_H
Output high, IN- = LOW, EN=HIGH
Output low, IN- = LOW, EN=HIGH
1.8
0.8
2
1
2.3
1.2
V
V
Input signal low threshold,
output low
VIN_L
VIN_HYS Input signal hysteresis
1
V
RIN
INPUT (IN-)
Input signal high threshold,
INx pin Pulldown resistance
IN+/IN = 3.3 V
120
kΩ
VIN-_H
Output low, IN+ = HIGH, EN = high
Output high, IN+ = HIGH, EN = high
1.8
0.8
2
1
2.3
1.2
V
V
output low
Input signal low threshold,
output high
VIN-_L
VIN-_HYS Input signal hysteresis
RIN- IN- pin pullup resistance
ENABLE (EN)
VEN_H Enable signal high threshold
VEN_L Enable signal low threshold
VEN_HYS Enable signal hysteresis
REN EN pin pullup resistance
1
V
IN- = 0 V
200
kΩ
Output high, IN+/IN = high, IN- =0 V
Output low, IN+/IN = high, IN- = 0 V
1.8
0.8
2
1
2.3
1.2
V
V
1
V
EN = 0 V
200
kΩ
OUTPUT (OUT)
(1)
ISRC
Peak output source current
VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz
VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz
10
A
A
(1)
(2)
ISNK
Peak output sink current
OUTH, pullup resistance
OUTL, pulldown resistance
–10
IOUT = –50 mA
See: 节7.3.4
ROH
ROL
2.5
4.5
Ω
Ω
IOUT = 50 mA
0.34 0.55
(1) Parameter not tested in production.
(2) Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure.
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6.6 Switching Characteristics
Unless otherwise noted, VDD = VEN = 12 V, IN- = GND, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, No
load on the output. Typical condition specifications are at 25°C (1)
PARAMETER
TEST CONDITIONS
CLOAD = 1.8 nF, 20% to 80%, VIN = 0 V to 3.3 V
CLOAD = 1.8 nF, 90% to 10%, VIN = 0 V to 3.3 V
MIN TYP MAX UNIT
tR
tF
Rise time
4.5
4
6
ns
ns
Fall time
5.5
CLOAD = 1.8 nF, VIN_H of the input rise to 10% of output rise,
VIN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, TJ = 125°C
tD1
Turnon propagation delay
Turn-off propagation delay
Enable propagation delay
Disable propagation delay
VDD UVLO ON delay
17.5
17.5
17.5
17.5
3.2
27
27
27
27
6
ns
ns
ns
ns
µs
us
ns
CLOAD = 1.8 nF, VIN_L of the input fall to 90% of output fall, VIN
= 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, TJ = 125°C
tD2
CLOAD = 1.8 nF, VEN_H of the enable rise to 10% of output rise,
VIN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, TJ = 125°C
tPD_EN
tPD_DIS
tVDD+_OUT
tVDD-_OUT
tPWmin
CLOAD = 1.8 nF, VEN_L of the enable fall to 90% of output fall,
VIN = 0 V to 3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C
VDD = 0 V to 4.5 V in 100 ns. Measured delay from VDD = 4.5
V to 10% of OUT
VDD = 4.5 V to 3.4 V in 100 ns. Measured delay from VDD =
3.4 V to 90% of OUT
VDD UVLO OFF delay
7.5
15
Minimum input pulse width
that passes to the output
CLOAD = 1.8 nF, VIN = 0 V to 3.3 V, Fsw = 500 kHz, Vo > 1.5 V
9
(1) Switching parameters are not tested in production.
6.7 Timing Diagrams
VIN_H
Input
VIN_L
High
Enable
Low
90%
Output
10%
tD1
tR
tD2 tF
图6-1. Single Input Version, IN = PWM
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VIN_H
Input
(IN- pin)
VIN_L
High
Enable pin
Low
90%
Output
10%
tD1 tR
tD2
tF
图6-2. Dual Input Version, IN+ = PWM, IN- = GND
High
Input
(IN- pin)
Low
High
Enable pin
Low
90%
Output
10%
tD1 tR
tD2
tF
图6-3. Dual Input Version, IN- = PWM, IN+ = High (or VDD)
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6.8 Typical Characteristics
Unless otherwise specified, VDD = 12 V, IN+ = 3.3 V, IN- = GND, TJ = 25 °C, No load
18
16
14
12
10
8
15
14
13
12
11
10
9
8
6
7
4
6
2
5
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
Isou
Isin
图6-4. Peak Source Current vs VDD
图6-5. Peak Sink Current vs VDD
20
18
16
14
12
10
8
10
9
8
7
6
5
4
6
3
4
2
2
1
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
Tris
Tfal
CLOAD = 1.8 nF
CLOAD = 1.8 nF
图6-6. Output Rise Time vs VDD
图6-7. Output Fall Time vs VDD
22
21.5
21
20.5
20
19.5
19
18.5
18
17.5
17
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
Tpd_
CLOAD = 1.8 nF
CLOAD = 1.8 nF
图6-9. Rising (Turnon) Propagation Delay vs VDD
图6-8. Output Rise and Fall Time vs Temperature
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22
21.5
21
20.5
20
19.5
19
18.5
18
17.5
17
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
Tpd_
CLOAD = 1.8 nF
CLOAD = 1.8 nF
图6-10. Falling (Turnoff) Propagation Delay vs VDD
图6-11. Propagation Delay vs Temperature
2.6
10kHz
2.4
100kHz
500kHz
Float
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
IDD
图6-12. Operating Supply Current vs VDD
图6-13. Operating Static Supply Current vs
Temperature
2.2
Rise
Fall
2
1.8
1.6
1.4
1.2
1
0.8
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
Vin_
图6-14. Input Threshold vs VDD
图6-15. Input Threshold vs Temperature
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2.46
2.44
2.42
2.4
2.38
2.36
2.34
2.32
2.3
2.28
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5
VDD (V)
ROH
图6-17. Output Pullup Resistance vs VDD
图6-16. Input Threshold Hysteresis vs
Temperature
图6-19. Output Pulldown Resistance vs VDD
图6-18. Output Pullup Resistance vs Temperature
图6-20. Output Pulldown Resistance vs
图6-21. UVLO Threshold vs Temperature
Temperature
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图6-22. UVLO Hysteresis vs Temperature
7 Detailed Description
7.1 Overview
The UCC27614 device is a single-channel, high-speed, gate drivers capable of effectively driving MOSFET, SiC
MOSFET, and IGBT power switches with 10-A source and 10-A sink (symmetrical drive) peak current. A strong
source and sink capability boost immunity against a parasitic Miller turnon effect. The UCC27614 device can be
directly connected to the gate driver transformer or line driver transformer as the inputs of UCC27614 can handle
–10V. The driver has a good transient handling capability on its output due to reverse currents, as well as rail-
to-rail drive capability and small propagation delay, typically 17.5 ns.
The input threshold of UCC27614 is compatible to TTL low-voltage logic, which is fixed and independent of VDD
supply voltage. The driver can also work with CMOS based controllers as long as the threshold requirement is
met. The 1-V typical hysteresis offers excellent noise immunity.
The driver has an EN pin with fixed TTL compatible threshold. EN is internally pulled up; pulling EN low disables
the driver, while leaving EN open provides normal operation. The EN pin can be used as an additional input with
the same performance as the IN, IN+, and IN- pins.
表7-1. UCC27614 Features and Benefits
FEATURE
BENEFIT
Enhanced signal reliability and device robustness in noisy environments that experience
ground bounce on the gate driver.
–10 V IN and EN capability
High source and sink current capability, 10 A High current capability helps drive large gate charge loads to minimize switching losses.
Low 17.5 ns (typ) propagation delay.
Wide VDD operating range of 4.5 V to 26 V
VDD UVLO protection
Extremely low pulse transmission distortion
Flexibility in system design
Outputs are held Low in UVLO condition, which ensures predictable, glitch-free operation at
power up and power down.
UVLO of 4 V (typical) allows use in high switching frequency applications at low bias
voltage to reduce switching losses.
Outputs held low when input pin (INx) in
floating condition
Safety feature, especially useful in passing abnormal condition tests during safety
certification
EN can float
Safe operation when the output of the controller, ties to the EN pin in tristate
High immunity to high dV/dt Miller turnon events
Strong sink current (10 A) and low pulldown
impedance (0.34 Ω)
TTL compatible input threshold logic with wide Enhanced noise immunity, while retaining compatibility with microcontroller logic level input
hysteresis
signals (3.3 V, 5 V) optimized for digital power
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7.2 Functional Block Diagram
VDD
UVLO
IN-
VDD
ON/OFF
LOGIC
OUT
OUT
DRIVER
STAGE
IN+
GND
GND
UCC27614DSG
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VDD
EN
UVLO
VDD
ON/OFF
LOGIC
OUT
DRIVER
STAGE
IN
OUT
GND
GND
UCC27614D
Typical
EN/IN- pullup resistance is 200 kΩand IN/IN+ pulldown resistance is 120 kΩ.
7.3 Feature Description
7.3.1 VDD Undervoltage Lockout
The UCC27614 device offers an undervoltage lockout threshold of 4 V. The device's hysteresis range helps to
avoid any chattering due to the presence of noise on the bias supply. 0.3 V of typical UVLO hysteresis is
expected for 4-V UVLO devices. There is no significant driver output turnon delay due to the UVLO feature, and
5 μs of UVLO delay is expected. The UVLO turn-off delay is also minimized as much as possible. The UVLO
delay is designed to minimize chattering that may occur due to very fast transients that may appear on VDD.
When the bias supply is below UVLO thresholds, the outputs are held actively low irrespective of the state of
input pins and enable pin. The device accepts a wide range of slew rates on its VDD pin, and VDD noise within
the hysteresis range does not affect the output state of the driver (neither ON nor OFF).
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VDD Threshold
VDD
IN
OUT
图7-1. Power Up
7.3.2 Input Stage
The inputs of the UCC27614 device are compatible with TTL based threshold logic and the inputs are
independent of the VDD supply voltage. With typical high threshold of 2 V and typical low threshold of 1 V, the
logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V logic. Wider
hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL logic implementations,
where the hysteresis is typically less than 0.5 V. This device also features tight control of the input pin threshold
voltage levels which eases system design considerations and ensures stable operation across temperature. The
very low input capacitance, typically less than 8 pF, on these pins reduces loading and increases switching
speed.
The device features an important protection function wherein, whenever the input pin is in a floating condition,
the output is held in the low state. This is achieved with internal pullup or pulldown resistors on the input pins as
shown in the simplified functional block diagrams. In some applications, due to difference in bias supply
sequencing, different ICs power-up at different times. This may cause output of the controller to be in tri-state.
This output of the controller gets connected to the input of the driver IC. If the driver IC does not have a pulldown
resistor then the output of the driver may go high erroneously and damage the switching power device.
The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly varying input signals, especially in situations where the device
is located in a separate daughter board or PCB layout has long input connection traces:
• High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce.
Because the device features just one GND pin which may be referenced to the power ground, this may
interfere with the differential voltage between Input pins and GND and trigger an unintended change of output
state. Because of fast 17.5-ns propagation delay, this can ultimately result in high-frequency oscillations,
which increases power dissipation and poses risk of damage.
• 1-V Input threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
An external resistance is highly recommended between the output of the driver and the power device instead of
adding delays on the input signal. This also limits the rise or fall times to the power device which reduces the
EMI. The external resistor has the additional benefit of reducing part of the gate charge related power dissipation
in the gate driver device package and transferring it into the external resistor itself.
Finally, because of the unique input structure that allows negative voltage capability on the Input and Enable
pins, caution must be used in the following applications:
• Input or Enable pins are switched to amplitude > 15 V.
• Input or Enable pins are switched at dV/dt > 2 V/ns.
If both of these conditions occur, add a series 150-Ω resistor for the pin(s) being switched to limit the current
through the input structure.
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7.3.3 Enable Function
The Enable (EN) pin of the UCC27614 device also has TTL compatible input thresholds with wide hysteresis.
The typical turnon threshold is 2 V and the typical turn-off threshold is 1 V with typical hysteresis of 1 V. The
Enable (EN) pin of the UCC27614 has an internal pullup resistor to an internal reference voltage. Thus, leaving
the Enable pin floating turns on the driver and allows it to send output signals properly. If desired, the Enable can
also be driven by low-voltage logic to enable and disable the driver. There is minimum delay from the enable
block to the output for fast system response time. Similar to the input pins, the enable pin can also handle
significant negative voltage and therefore provides system robustness. The enable pin can withstand wide range
of slew rate such as 1 V/ns to 1 V/ms. The enable signal is independent of VDD voltage and stable across the
full operating temperature range.
7.3.4 Output Stage
The output stage of the UCC27614 device is illustrated in 图 7-2. The UCC27614 device features a unique
architecture on the output stage which delivers the highest peak source current when it is most needed during
the Miller plateau region of the power switch turnon transition (when the power switch drain/collector voltage
experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel arrangement of N-
Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant when
the output changes state from low to high, the gate driver device is able to deliver a brief boost in the peak
sourcing current enabling fast turnon. The on-resistance of this N-channel MOSFET (RNMOS) is approximately
0.52 Ωwhen activated.
VDD
ROH
RNMOS ,Pull Up
OUT
Anti Shoot-
Input Signal
Through
Circuitry
Narrow Pulse at
each Turn On
ROL
图7-2. UCC27614 Gate Driver Output Stage
The ROH parameter (see Electrical Table) is a DC measurement and it is representative of the on-resistance of
the P-Channel device only, because the N-Channel device is turned on only during output change of state from
low to high. Thus, the effective resistance of the hybrid pullup stage is much lower than what is represented by
ROH parameter. The pulldown structure is composed of a N-channel MOSFET only. The ROL is also a DC
measurement, and it is representative of true impedance of the pulldown stage in the device.
The UCC27614 can deliver 10-A source, and up to 10-A sink at VDD = 12 V. Strong sink capability results in a
very low pulldown impedance in the driver output stage which boosts immunity against the parasitic Miller turnon
(high slew rate dV/dt turnon) effect that is seen in both IGBT and FET power switches.
An example of a situation where Miller turnon is a concern is synchronous rectification (SR). In SR application,
the dV/dt occurs on MOSFET drain when the MOSFET is already held in OFF state by the gate driver. The
current charging the CGD Miller capacitance during this high dV/dt is shunted by the pulldown stage of the driver.
If the pulldown impedance is not low enough then a voltage spike can result in the VGS of the MOSFET, which
can result in spurious turnon. This phenomenon is illustrated in 图7-3.
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VDS
VIN
Miller Turn -On Spike in V GS
CGD
Gate Driver
VTH
VIN
VGS of
MOSFET
RG
COSS
ISNK
ON OFF
CGS
ROL
VDS of
MOSFET
图7-3. Low Pull-Down Impedance in UCC27614 (Output Stage Mitigates Miller Turnon Effect)
The driver output voltage swings between VDD and GND providing rail-to-rail operation because of the low
dropout of the output stage. In most applications, the external Schottky diode clamps may be eliminated
because the presence of the MOSFET body diodes offers low impedance to switching overshoots and
undershoots. The output stage of the UCC27614 devices can handle significant transient reverse current. The
two OUT pins of the device should be shorted on the application board. The application may use resistor and
parallel diode-resistor combination at the gate of the MOSFET or IGBT to program different rise (pullup current)
time and fall (pulldown) time.
7.4 Device Functional Modes
The UCC27614 devices operate in normal mode and UVLO mode (see 节7.3.1 section for information on UVLO
operation). In normal mode, the output state is dependent on the states of the device, and the input pins.
The UCC27614D features a single, non-inverting input, but also contains enable and disable functionality
through the EN pin. Setting the EN pin to logic HIGH will enable the non-inverting input to output on the IN pin.
The two OUT pins are internally shorted and shall be shorted on the application board as well.
The UCC27614DSG features dual input; for example, IN+ and IN-. One inverting (IN-), and one non-inverting
(IN+). This device does not contain a dedicated enable (EN) pin as in UCC27614D.
表7-2. UCC27614DSG Truth Table
IN+
H
IN-
OUT
L
H
L
L
L
L
L
H
H
L
H
L
L
Float
Any
Any
Float
表7-3. UCC27614D Truth Table
IN
H
H
L
EN
OUT
L
H
H
L
L
H
L
L
L
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表7-3. UCC27614D Truth Table (continued)
IN
EN
OUT
L
Float
Any
Any
Float
IN
8 Applications and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
High-current gate driver devices are required in switching power applications for a variety of reasons. To enable
fast switching of power devices and reduce associated switching power losses, a powerful gate driver can be
employed between the PWM output of controllers or signal isolation devices and the gates of the power
semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the
PWM controller directly drive the gates of the switching devices. The situation will be often encountered because
the PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not
capable of effectively turning on a power switch. A level-shifting circuitry is needed to boost the logic-level signal
to the gate-drive voltage in order to fully turn on the power device and minimize conduction losses. Traditional
buffer drive circuits based on NPN/PNP bipolar, (or P- N-channel MOSFET), transistors in totem-pole
arrangement, being emitter follower configurations, prove inadequate for this because they lack level-shifting
capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting, buffer drive
and UVLO functions. Gate drivers also find other needs such as minimizing the effect of switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses into itself.
The UCC27614 is very flexible in this role with a strong drive current capability and wide recommended supply
voltage range of 4.5V to 26 V. This allows the driver to be used in 5-V bias logic level very high frequency
MOSFET applications, 12-V MOSFET applications, 20-V and -5-V (relative to Source) SiC FET applications, 15-
V and -8-V (relative to Emitter) IGBT applications and many others. As a single-channel driver, the UCC27614
can be used as a low-side or high-side driver. To use as a low-side driver, the switch ground is usually the
system ground so it can be connected directly to the gate driver. To use as a high-side driver with a floating
return node however, signal isolation is needed from the controller as well as a bias supply that is referenced to
the UCC27614 ground pin. Alternatively, in a high-side drive configuration the UCC27614 can be tied directly to
the controller signal and biased with a nonisolated supply. However, in this configuration the output of the
UCC27614 must drive a pulse transformer which then drives the power-switch to work properly with the floating
source and emitter of the power switch.
These requirements, coupled with the need for low propagation delays and availability in compact, and low-
inductance packages with good thermal capability, make gate driver devices such as the UCC27614 extremely
important components in switching power combining benefits of high-performance, low cost, low component
count, board space reduction and simplified system design.
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8.2 Typical Application
8.2.1 Driving MOSFET/IGBT/SiC MOSFET
L
D
To Load
VBias
+
–
Vin
VDD
VDD
UCC27614DSG
6
7
IN+
RG_2
DG
COUT
OUT
OUT
Q
From
Controller
5
4
1
IN-
8
RG_1
RGS
GND
CVDD
3
GND
2
图8-1. Driving a MOSFET/IGBT/SiC MOSFET in a Boost Converter
8.2.1.1 Design Requirements
When selecting the gate driver device for an end application, some design considerations must be evaluated in
order to make the most appropriate selection. Following are some of the design parameters that should be used
when selecting the gate driver device for an end application: input-to-output configuration, the input threshold
type, bias supply voltage levels, peak source and sink currents, availability of independent enable and disable
functions, propagation delay, power dissipation, and package type. See the example design parameters and
requirements in 表8-1.
表8-1. Design Parameters
DESIGN PARAMETER
Input to output logic
Input threshold type
Bias supply voltage levels
Negative output low voltage
dVDS/dt(1)
EXAMPLE VALUE
Non-inverting
TTL
+18 V
N/A
100 V/ns
Yes
Enable function
Disable function
N/A
Propagation delay
Power dissipation
<30 ns
<1 W
Package type
SON8 or SOIC8
(1) dVDS/dt is a typical requirement for a given design. This value
can be used to find the peak source/sink currents needed as
shown in 节8.2.1.2.4.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Input-to-Output Configuration
The design should specify which type of input-to-output configuration should be used. If turning on the power
MOSFET or IGBT when the input signal is in high state is preferred, then a device capable of the non-inverting
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configuration must be selected. If turning off the power MOSFET or IGBT when the input signal is in high state is
preferred, then a device capable of the inverting configuration must be chosen. UCC27614DSG offers non-
inverting output when IN+ pin is used as PWM input while IN- is grounded. When IN- pin is used as PWM input
and IN+ is pulled high, the UCC27614DSG works as inverting output gate driver.
If ground-bouncing is a potential issue, a gate driver with negative voltage handling capability should be chosen.
UCC27614 devices can handle -10-V at its input and -2-V on its output. The input of the UCC27614 devices can
handle wide range of slew rate at its input and the inputs have wide hysteresis.
8.2.1.2.2 Input Threshold Type
The type of Input voltage threshold determines the type of controller that can be used with the gate driver device.
The UCC27614 devices feature a TTL compatible input threshold logic, with wide hysteresis. The threshold
voltage levels are low voltage and independent of the VDD supply voltage, which allows compatibility with both
logic-level input signals from microcontrollers as well as higher-voltage input signals from analog controllers. See
the Electrical Characteristics table for the actual input threshold voltage levels and hysteresis specifications for
the UCC27614 devices.
8.2.1.2.3 VDD Bias Supply Voltage
The bias supply voltage to be applied to the VDD pin of the device should not exceed the values listed in the
Recommended Conditions table. However, different power switches demand different voltage levels to be
applied at the gate terminals for effective turnon and turn-off. With certain power switches, a positive gate
voltage may be required for turnon and a negative gate voltage may be required for turn-off, in which case the
VDD bias supply equals the voltage differential. With an operating range from 4.5 V to 26 V, the UCC27614
devices can be used to drive a power switches such as logic level MOSFETs, power MOSFETS, SiC MOSFETs,
and IGBTs.
8.2.1.2.4 Peak Source and Sink Currents
Generally, the switching speed of the power switch during turnon and turn-off should be as fast as possible to
minimize switching power losses. The gate driver device must be able to provide the required peak current for
achieving the targeted switching speeds for the targeted power switching devices such as logic level MOSFETs,
power MOSFETs, SiC MOSFETs, and IGBTs.
Using the example of a power MOSFET, the system requirement for the switching speed is typically described in
terms of the slew rate of the drain-to-source voltage of the power MOSFET (such as dVDS/dt). For example, the
system requirement might state that a 600V power MOSFET must be turned on with a dVDS/dt of 100 V/ns or
higher under a DC bus voltage of 400 V in a continuous-conduction-mode (CCM) boost PFC-converter
application. This type of application is an inductive hard-switching application and reducing switching power
losses is critical. This requirement means that the entire drain-to-source voltage swing during power MOSFET
turnon event (from 400 V in the OFF state to VDS(on) in on state) must be completed in approximately 4 ns or
less. When the drain-to-source voltage swing occurs, the Miller charge of the power MOSFET (QGD parameter of
the 600V power MOSFET, let us say, is 32 nC) is supplied by the peak current of gate driver. According to power
MOSFET inductive switching mechanism, the gate-to-source voltage of the power MOSFET at this time is the
Miller plateau voltage, which is typically a few volts higher than the threshold voltage of the power MOSFET,
VGS(th)
.
To achieve the targeted dVDS/dt, the gate driver must be capable of providing the QGD charge in 4 ns or less. In
other words a peak current of 8 A (= 32 nC / 4 ns) or higher must be provided by the gate driver. The UCC27614
series of gate drivers can provide 10-A peak sourcing current, and 10A peak sinking current which clearly
exceeds the design requirement and has the capability to meet the switching speed needed. The significantly
high drive capability provides an extra margin against part-to-part variations in the QGD parameter of the power
MOSFET along with additional flexibility to insert external gate resistors and fine tune the switching speed for
efficiency versus EMI optimizations. However, in practical designs the parasitic trace inductance in the gate drive
circuit of the PCB will have a definitive role to play on the power MOSFET switching speed. The effect of this
trace inductance is to limit the dI/dt of the output current pulse of the gate driver. To illustrate this, consider output
current pulse waveform from the gate driver to be approximated to a triangular profile, where the area under the
triangle (½ ×IPeak × time) would equal the total gate charge of the 600V power MOSFET (QG parameter in the
power MOSFET datasheet). If the parasitic trace inductance limits the dI/dt then a situation may occur in which
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the full peak current capability of the gate driver is not fully achieved in the time required to deliver the QG of the
switching power MOSFET. In other words, the time parameter in the above equation would dominate and the
IPeak value of the current pulse would be much less than the true peak current capability of the driver, while the
required QG is still delivered. Because of this, the desired switching speed may not be realized, even when
theoretical calculations indicate the gate driver can achieve the targeted switching speed. Thus, placing the gate
driver device very close to the power MOSFET and designing a very small gate drive-loop with minimal PCB
trace inductance is important to realize fast switching.
8.2.1.2.5 Enable and Disable Function
Certain applications demand independent control of the output state of the driver without involving the input
PWM signal. A pin which offers an enable and disable function achieves this requirement. For these
applications, the UCC27614D is suitable as it features an input pin (IN) and an Enable pin (EN). Both of these
pins are independent of each other and are also independent of VDD.
Other applications require multiple inputs. For such applications UCC27614DSG is suitable. The
UCC27614DSG features an IN+ and IN–pin, both of which control the state of the output as listed in the Device
Functional Modes truth table. Based on whether an inverting or non-inverting input signal is provided to the
driver, the appropriate input pin can be selected as the primary input for controlling the gate driver. The other
unused input pin can be conveniently used for the enable and disable functionality if needed. If the design does
not require an enable function, the unused input pin can be tied to either the VDD pin (IN+ is the unused pin), or
GND (in case IN–is unused pin) in order to ensure it does not affect the output status.
8.2.1.2.6 Propagation Delay and Minimum Input Pulse Width
The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is
used and the acceptable level of pulse distortion to the system. The UCC27614 devices feature 17.5-ns (typical)
propagation delays which ensures very little pulse distortion and allows operation at very high frequencies. Very
high switching frequency applications also need the gate driver to satisfactorily produce the output pulse when
the input pulse width is very small. The UCC27614 devices can typically handle less than 10ns at its input and
produce satisfactory output depending on the load. See Switching Characteristics table for the propagation and
other timing specifications of the UCC27614 devices.
8.2.1.2.7 Power Dissipation
Power dissipation of the gate driver has two portions as shown in equation below:
P
= P + P
DC SW
DISS
(1)
The DC portion of the power dissipation is PDC = IQ × VDD where IQ is the quiescent current for the driver. The
quiescent current is the current consumed by the device to bias all internal circuits such as input stage,
reference voltage, logic circuits, protections, and so on, and any current associated with switching of internal
devices when the driver output changes state (such as charging and discharging of internal parasitic
capacitances, parasitic shoot-through). The UCC27614 features low quiescent currents (less than 1 mA) and
contains internal logic to minimize any shoot-through (PMOS to NMOS and vice versa) in the output driver stage.
Thus, the effect of the PDC on the total power dissipation within the gate driver can be assumed to be negligible.
In practice this is the power consumed by driver when its output is disconnected from the gate of power switch.
As explained in earlier sections, the output stage of the gate driver is based on PMOS and NMOS. These NMOS
and PMOS are designed in such a way that they offer very low resistance during switching. And therefore they
have very low drop-out. The power dissipated in the gate driver package during switching (PSW) depends on the
following factors:
• Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD due to low VOx drop-out)
• Switching frequency
• Power MOSFET internal and external gate resistor
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When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power
that is required from the bias supply. The energy that must be transferred from the bias supply to charge the
capacitor is given by:
1
2
EG
=
CLOADVDD
2
(2)
where
• CLOAD is load capacitor and VDD is bias voltage feeding the driver.
There is an equal amount of energy dissipated when the capacitor is discharged. During turnoff the energy
stored in capacitor is fully dissipated in drive circuit. This leads to a total power loss during switching cycle given
by the following:
2
LOAD DD sw
P
= C
V
f
G
(3)
where
• ƒSW is the switching frequency
The switching load presented by a power FET and IGBT can be converted to an equivalent capacitance by
examining the gate charge required to switch the device. This gate charge includes the effects of the input
capacitance plus the added charge needed to swing the drain voltage of the power device as it switches
between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate
charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the
power that must be dissipated when charging a capacitor. This is done by using the equivalence, Qg
CLOADVDD, to provide the following equation for power:
=
2
LOAD DD sw
P
= C
V
f
= Q V f
g DD sw
G
(4)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET and IGBT is being turned
on or off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other
half is dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is
employed between the driver IC and MOSFET/IGBT, this power is completely dissipated inside the driver IC.
With the use of external gate drive resistors, the power dissipation is shared between the internal resistance of
driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the
higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is
calculated as shown in following equation. This primarily applies to those applications where total external gate
resistor is significantly large to limit the peak current of the gate driver.
æ
ö
÷
÷
ø
ROFF
+ RGATE
RON
PSW = 0.5´Qg ´ VDD ´ f
+
ç
sw ç
è
R
(
R
ON + RGATE
) (
)
OFF
(5)
where
• ROFF = ROL and RON (effective resistance of pullup structure)
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8.2.1.3 Application Curves
Many telecom and datacom isolated power modules employ synchronous rectification on the secondary side
with center tap topology (as shown in UCC27614DSG Used to Drive Secondary Side Synchronous Rectifiers).
The low-side driver UCC27614 can drive these synchronous rectifier MOSFETs as they are referenced to the
output ground. These power modules are very power dense and the printed circuit board real estate is at a
premium. These power modules may also have very high output current requirements and therefore either need
very small Rds(on) MOSFETs or parallel multiple MOSFETs to achieve lower total Rds(on). In either case, the
total get charge increases and therefore such applications need a gate driver with high drive current capability.
UCC27614DSG fulfills all these requirements. The UCC27614DSG device is used in one such application of a
400-V to 12-V isolated DC-DC converter. Waveforms shown here are captured in this actual application power
supply.
Primary Side
Power Stage
VBias
VBias
Vo
VDD
VDD
VDD
VDD
UCC27614DSG
UCC27614DSG
IN-
OUT
OUT
IN-
OUT
OUT
IN+
IN+
From
From
Controller
Controller
GND
CVDD
GND
CVDD
GND
GND
图8-2. UCC27614DSG Used to Drive Secondary Side Synchronous Rectifiers
Driver OUT
Driver IN+
Driver IN+
Driver OUT
T
PD = 17.5ns
T
PD = 17.5ns
图8-3. UCC27614 Rising (Turn-On) Propagation
图8-4. UCC27614 Falling (Turn-Off) Propagation
Delay
Delay
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MOSFET VDS
MOSFET VDS
Driver
OUT
Driver OUT
图8-5. Synchronous Rectifier MOSFET VDS Rising 图8-6. Synchronous Rectifier MOSFET VDS Falling
Edge Using UCC27614DSG
Edge Using UCC27614DSG
MOSFET VDS
MOSFET VDS
Converter Output 12V
Converter Outut 10A
Converter Output 12V
Converter
Input 380V
Driver
OUT
Driver
OUT
图8-7. Input and Output Voltage of Converter
图8-8. Output Voltage and Current of a Converter
Using UCC27614DSG
Using UCC27634DSG
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9 Power Supply Recommendations
The bias supply voltage range for which the UCC27614 devices are recommended to operate is from 4.5 V to 26
V. The lower end of this range is governed by the internal UVLO protection feature on the VDD pin supply circuit
blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start
threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is
driven by the 26-V recommended maximum voltage rating of the VDD pin of the device. The absolute maximum
voltage for the VDD pin is 30 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification. Therefore,
ensuring that, while operating at or near the 4.5 V range, the voltage ripple on the auxiliary power supply output
is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown.
During system shutdown, the device operation continues until the VDD pin voltage has dropped below the VDD
UVLO falling threshold which must be accounted for while evaluating system shutdown timing design
requirements. Likewise, at system start-up, the device does not begin operation until the VDD pin voltage has
exceeded above the VDD UVLO rising threshold. The quiescent current consumed by the internal circuit blocks
of the device is supplied through the VDD pin. Although this fact is well known, recognizing that the charge for
source current pulses delivered by the OUT pin is also supplied through the same VDD pin is important. As a
result, every time a current is sourced out of the output pin (OUT), a corresponding current pulse is delivered into
the device through the VDD pin. Thus ensuring that local bypass capacitors are provided between the VDD and
GND pins and located as close to the device as possible for the purpose of decoupling is important. A low-ESR,
ceramic surface-mount capacitor is needed. TI recommends having two capacitors; a 100-nF ceramic surface-
mount capacitor placed less than 1mm from the VDD pin of the device and another ceramic surface-mount
capacitor of few microfarads added in parallel.
UCC27614 is a high current gate driver. If the gate driver is placed far from the switching power device such as
MOSFET then that may create large inductive loop. Large inductive loop may cause excessive ringing on any
and all pins of the gate driver. This may result in stress exceeding device recommended rating. Therefore, it is
recommended to place the gate driver as close to the switching power device as possible. It is also advisable to
use an external gate resistor to damp any ringing due to the high switching currents and board parasitic
elements.
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10 Layout
10.1 Layout Guidelines
Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device
operation and design robustness. The UCC27614 gate driver incorporates short propagation delays and
powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of
power switch to facilitate voltage transitions very quickly. Very high di/dt can cause unacceptable ringing if the
trace lengths and impedances are not well controlled. The following circuit layout guidelines are recommended
when designing with these high-speed drivers.
• Place the driver device as close as possible to power device to minimize the length of high-current traces
between the driver output pins and the gate of the power switch device.
• Place the bypass capacitors between VDD pin and the GND pin as close to the driver pins as possible to
minimize trace length for improved noise filtering. TI recommends having two capacitors; a 100-nF ceramic
surface-mount capacitor placed less than 1mm from the VDD pin of the device and another ceramic surface-
mount capacitor of few microfarads added in parallel. These capacitors support high peak current being
drawn from VDD during turnon of power switch. The use of low inductance surface-mount components such
as chip capacitors is highly recommended.
• The turnon and turn-off current loop paths (driver device, power switch and VDD bypass capacitor) should be
minimized as much as possible in order to keep the stray inductance to a minimum. High di/dt is established
in these loops at two instances –during turnon and turn-off transients, which induces significant voltage
transients on the output pins of the driver device and gate of the power switch.
• Wherever possible, parallel the source and return traces of a current loop, taking advantage of flux
cancellation
• Separate power traces and signal traces, such as output and input signals.
• To minimize switch node transients and ringing, adding some gate resistance and/or snubbers on the power
devices may be necessary. These measures may also reduce EMI.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM
controller, and so forth, at a single point. The connected paths should be as short as possible to reduce
inductance and be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT pin may corrupt the input
signals during transitions. The ground plane must not be a conduction path for any current loop. Instead the
ground plane should be connected to the star-point with one trace to establish the ground potential. In
addition to noise shielding, the ground plane can help in power dissipation as well.
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10.2 Layout Example
VDD Capacitor
External
Gate
Resistor
UCC27614D
Power MOSFET
图10-1. Layout Example: UCC27614D
10.3 Thermal Consideration
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the package. In order for a gate driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The thermal metrics for the driver package is summarized in the Thermal Characteristics section of
the data sheet. For detailed information regarding the thermal information table, refer to IC Package Thermal
Metrics Application Note (SPRA953).
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11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC27614DR
ACTIVE
ACTIVE
SOIC
D
8
8
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 150
-40 to 150
U27614
U614
UCC27614DSGR
WSON
DSG
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Feb-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27614DR
SOIC
D
8
8
2500
3000
330.0
180.0
12.4
8.4
6.4
2.3
5.2
2.3
2.1
8.0
4.0
12.0
8.0
Q1
Q2
UCC27614DSGR
WSON
DSG
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC27614DR
SOIC
D
8
8
2500
3000
356.0
210.0
356.0
185.0
35.0
35.0
UCC27614DSGR
WSON
DSG
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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TI
UCC27712
支持互锁功能的 1.8A/2.8A、620V 半桥驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC27712-Q1
具有互锁功能的汽车类 1.8A/2.8A、620V 半桥栅极驱动器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
UCC27712D
支持互锁功能的 1.8A/2.8A、620V 半桥驱动器 | D | 8 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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