UCC27531-Q1 [TI]
具有 8V UVLO、35V VDD 和分离输出的汽车类 2.5A/5A 单通道栅极驱动器;
| 型号： | UCC27531-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 8V UVLO、35V VDD 和分离输出的汽车类 2.5A/5A 单通道栅极驱动器 栅极驱动 驱动器 |
| 文件： | 总26页 (文件大小：1370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
2.5A 和 5A，35VMAX VDD 场效应晶体管 (FET) 和绝缘栅双极晶体管
(IGBT) 单栅极驱动器
1
特性
应用范围
•
•
符合汽车应用要求
•
•
•
•
•
•
•
•
车载
具有符合 AEC-Q100 的下列结果：
开关模式电源
–
–
器件温度 1 级
直流到直流转换器
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
太阳能逆变器、电机控制、不间断电源 (UPS)
混合动力车 (HEV) 和电动车辆 (EV) 充电器
家用电器
H2
–
器件充电器件模型 (CDM) ESD 分类等级 C4B
•
•
•
低成本栅极驱动器（为驱动 FET 和 IGBT 提供最佳
解决方案）
可再生能源功率转换
SiC FET 转换器
离散晶体管对驱动的出色替代产品（提供与控制器
的简便对接）
说明
TTL 和 CMOS 兼容输入逻辑阀值，（与电源电压
无关）
UCC27531-Q1 是一款单通道、高速、栅极驱动器，此
驱动器可借助于高达 2.5A 源电流和 5A 灌电流（非对
称驱动）峰值电流来有效驱动金属氧化物半导体场效应
晶体管 (MOSFET) 和 IGBT 电源开关。 强劲的非对称
驱动中的吸收能力提升了抗寄生米勒 (Miller) 接通效应
的能力。 UCC27531-Q1 器件还特有一个分离输出配
置，在此配置中栅极驱动电流从 OUTH 引脚拉出并从
OUTL 引脚被灌入。 这个独特的引脚安排使得用户能
够分别在 OUTH 和 OUTL 引脚上采用独立的接通和关
闭电阻器并且能很轻易地控制开关的转换率。
•
•
•
•
分离输出选项实现打开和关闭电流调节
反向和非反向输入配置
由固定 TTL 兼容阀值启用
18V VDD 时的高 2.5A 源电流和 2.5A 或 5A 灌峰
值驱动电流
•
•
从 10V 到高达 35V 的宽 VDD 范围
能够耐受比接地最多低 5V 的直流电压的输入和使
能引脚
•
当输入悬空或 VDD 欠压闭锁 (UVLO) 期间，输出
保持低电平
此驱动器具有轨到轨驱动能力和典型值为 17ns 的极小
传播延迟。
•
•
快速传播延迟（典型值 17ns）
快速上升和下降时间
（1800pF 负载时的典型值分别为 15ns 和 7ns）
UCC27531-Q1 的输入阀值基于与 TTL 和 COMS 兼容
的低压逻辑电路，此逻辑电路是固定的且与 VDD 电源
电压无关。 1V 滞后典型值提供出色的抗扰度。
•
•
欠压闭锁 (UVLO)
被用作高侧或低侧驱动器（如果采用适当的偏置和
信号隔离设计）
UCC27531-Q1
•
•
低成本、节省空间的 6 引脚 DBV（小外形尺寸晶
体管 (SOT)-23）封装 选项
(顶视图)
UCC27531-Q1
-40°C 至 140°C 的运行温度范围
EN
IN
1
2
3
6
5
OUTH
OUTL
VDD
4
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
版权 © 2013, Texas Instruments Incorporated
English Data Sheet: SLVSC82
UCC27531-Q1
ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
www.ti.com.cn
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
说明（继续）
此驱动器具有支持固定 TTL 兼容阀值的 EN 引脚。 EN 被内部上拉；将 EN 下拉为低电平禁用驱动器，而将其保持
打开可提供正常运行。 EN 引脚可被用作一个额外输入，其性能与 IN 引脚一样。
将驱动器的输入引脚保持开状态将把输出保持为低电平。 驱动器的逻辑运行方式被显示在应用图、时序图和输入与
输出逻辑真值表中。
VDD 引脚上的内部电路提供一个欠压闭锁功能，此功能在 VDD 电源电压处于运行范围内之前将输出保持为低电
平。
UCC27531-Q1 驱动器采用 6 引脚标准 SOT-23 (DBV) 封装。 此器件在 -40°C 至 140°C 的宽运行温度范围运行。
ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
MAX
UNIT
Supply voltage range,
Continuous
VDD
35
OUTH, OUTL, OUT
OUTH, OUTL, OUT (200 ns)
–0.3 VDD + 0.3
–2 VDD + 0.3
V
Pulse
Continuous IN, EN, IN+, IN-, IN1,
IN2
–5
27
27
Pulse IN, EN, IN+, IN-, IN1, IN2 (1.5
µs)
–6.5
V
Human body model, HBM classification level H2
Charged device model, CDM classification level C4B
±2000
750
Electrostatic discharge (ESD) ratings
Operating virtual junction temperature range, TJ
Storage temperature range, Tstg
–40
–65
150
150
°C
Soldering, 10 sec.
Reflow
300
Lead temperature
260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
THERMAL INFORMATION
UCC27531-Q1
THERMAL METRIC(1)
UNIT
DBV (6 PINS)
178.3
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
109.7
28.3
°C/W
ψJT
ψJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
14.7
27.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
Copyright © 2013, Texas Instruments Incorporated
UCC27531-Q1
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ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
V
Supply voltage range, VDD
Ambient temperature range
Input voltage, IN, IN+, IN-, IN1, IN2
Enable, EN
10
–40
–5
18
32
140
25
°C
V
–5
25
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VDD = 18 V, TA = –40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are
positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531-Q1. Typical condition
specifications are at 25°C.
PARAMETER
Bias Currents
TEST CONDITION
MIN
TYP
MAX
UNITS
VDD = 7, IN, EN = VDD
100
200
300
IDDoff
Startup current
μA
IN, EN = GND
100
217
300
Under Voltage Lockout (UVLO)
VON
Supply start threshold
8
8.9
8.2
0.7
9.8
9.1
Minimum operating voltage
after supply start
VOFF
7.3
V
VDD_H
Supply voltage hysteresis
Input (IN)
Input signal high threshold,
output high
VIN_H
Output High, EN = HIGH
Output Low, EN = HIGH
1.8
0.8
2
2.2
1.2
Input signal low threshold,
output low
V
V
VIN_L
1
1
VIN_HYS
Input signal hysteresis
Enable (EN)
VEN_H
VEN_L
Enable signal high threshold
Enable signal low threshold
Output High
Output Low
1.7
0.8
1.9
1
2.1
1.2
VEN_HYS Enable signal hysteresis
0.9
Outputs (OUTH/OUTL)
Source peak current (OUTH)/
ISRC/SNK
CLOAD = 0.22 µF, f = 1 kHz
IOUTH = –10 mA
–2.5 / +5
A
V
sink peak current (OUTL)
VDD -
0.2
VDD -
0.12
VDD -
0.07
VOH
VOL
OUTH, high voltage
OUTL, low voltage
IOUTL = 100 mA
0.065
12
0.125
12.5
20
TA = 25°C, IOUT = –10 mA
TA = –40°C to 140°C, IOUT = –10 mA
TA = 25°C, IOUT = 100 mA
TA = –40°C to 140°C, IOUT = 100 mA
11
7
ROH
OUTH, pullup resistance
12
Ω
0.45
0.3
0.65
0.65
0.85
1.25
ROL
OUTL, pulldown resistance
Switching Time
tR
Rise time
CLOAD = 1.8 nF
15
7
tF
Fall time
CLOAD = 1.8 nF
ns
tD1
tD2
Turn-on propagation delay
Turn-off propagation delay
CLOAD = 1.8 nF, IN = 0 V to 5 V
CLOAD = 1.8 nF, IN = 5 V to 0 V
17
17
26
26
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3
UCC27531-Q1
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TIMING DIAGRAM
Figure 1. (OUTPUT = OUTH tied to OUTL) INPUT = IN,
(EN = VDD), or INPUT = EN, (IN = VDD)
BLOCK DIAGRAM
VDD
IN
2
3
6
5
VDD
VREF
EN
1
4
OUTH
OUTL
VDD
GND
UVLO
Figure 2. UCC27531-Q1
(EN Pullup Resistance to VREF = 500 kΩ,
VREF = 5.8 V, in Pulldown Resistance to GND = 230 kΩ)
4
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UCC27531-Q1
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ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
TYPICAL APPLICATION DIAGRAMS
UCC27531-Q1
EN
IN
OUTH
OUTL
GND
1
2
3
6
5
4
+
VDD
GND
Bouncing Up
to -6.5 V
18 V
+
–
ISENSE
VCE(sense)
Controller
VCC
+
–
Figure 3. Driving IGBT Without Negative Bias
UCC27531-Q1
EN
IN
OUTH
OUTL
GND
1
2
3
6
5
4
+
VDD
+
–
18 V
13 V
+
–
Figure 4. Driving IGBT With 13-V Negative Turn-Off Bias
Copyright © 2013, Texas Instruments Incorporated
5
UCC27531-Q1
ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
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E/2
+
–
Isol.
UCC27531-Q1
Isol.
UCC27531-Q1
Controller
Isol.
UCC27531-Q1
Isol.
UCC27531-Q1
E/2
+
–
Figure 5. Using UCC27531-Q1 Drivers in an Inverter
6
Copyright © 2013, Texas Instruments Incorporated
UCC27531-Q1
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ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
UCC27531-Q1 PRODUCT MATRIX
UCC27531-Q1 Product Matrix
UCC27531-Q1
ION PEAK
IOFF PEAK
PACKAGE
IN
2.5 A
5 A
SOT-23-6
Single
TTL/CMOS
Yes
IN LOGIC
EN
OUTPUT
INVERTING
MAX VDD
Split
No
35 V
UCC27531-Q1
EN
IN
1
2
3
6
5
OUTH
OUTL
PIN OUT
VDD
4
GND
PIN FUNCTIONS
PIN
I/O
FUNCTION
NAME
NO.
Enable (Pull EN to GND in order to disable output, pull it high or leave open to enable
output)
EN
1
I
GND
IN
4
2
6
5
3
-
I
Ground (all signals are referenced to this node)
Driver non-inverting input
OUTH
OUTL
VDD
O
O
I
2.5-A Source Current Output of driver
5-A sink current output of driver
Bias supply input
spacer
INPUT/OUTPUT LOGIC TRUTH TABLE
(For Single Output Driver)
UCC27531QDBVRQ1
IN PIN
OUT
EN PIN
OUTH PIN
OUTL PIN
(OUTH and OUTL pins
tied together)
L
L
High-impedance
High-impedance
High-impedance
H
L
L
L
L
H
L
H
H
L
H
L
L
High-impedance
High-impedance
L
H
H
L
H
FLOAT
H
H
FLOAT
High-impedance
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TYPICAL CHARACTERISTICS
If not specified, INPUT refers to non-inverting input
RISE TIME
FALL TIME
vs
SUPPLY VOLTAGE
vs
SUPPLY VOLTAGE
12
10
8
25
20
15
10
5
6
4
Cload = 1.8nF
30
Cload = 1.8nF
2
0
10
20
30
40
0
10
20
40
C002
Supply Voltage (V)
Figure 7.
C001
Supply Voltage (V)
Figure 6.
PROPAGATION DELAY
vs
SUPPLY VOLTAGE
IN - PROPAGATION DELAY
vs
SUPPLY
27
21
19
17
15
OUT RISING, IN- 5V to
0V
OUT FALLING, IN- 0V
to 5V
Turn-
On
25
23
21
19
17
15
Turn-
Off
0
10
20
30
40
C003
Supply Voltage (V)
0
10
20
30
40
Supply Voltage (V)
C001
Figure 8.
Figure 9.
8
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UCC27531-Q1
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ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
OPERATING SUPPLY CURRENT
START-UP CURRENT
vs
vs
FREQUENCY
TEMPERATURE
300
250
200
150
100
30
VDD = 10V
EN=IN=Vdd
EN=IN=GND
VDD = 18V
VDD = 32V
25
20
15
10
5
Cload = 1.8nF
Vdd = 7V
0
0
100
200
300
400
500
Frequency (kHz)
C001
-50
0
50
100
150
7HPSHUDWXUHꢀꢁÛ&ꢂ
C005
Figure 10.
Figure 11.
OPERATING SUPPLY CURRENT
vs
TEMPERATURE (OUTPUT SWITCHING)
UVLO THRESHOLD VOLTAGE
vs
TEMPERATURE
4.5
4.3
4.1
3.9
3.7
3.5
9.6
9.2
8.8
8.4
8
UVLO Rising
UVLO Falling
Vdd = 18V
Cload = 1.8nF
fsw = 100kHz
-50
0
50
100
150
-50
0
50
100
150
7HPSHUDWXUHꢀꢁÛ&ꢂ
7HPSHUDWXUHꢀꢁÛ&ꢂ
C006
C007
Figure 12.
Figure 13.
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UCC27531-Q1
ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
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TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
INPUT THRESHOLD
ENABLE THRESHOLD
vs
vs
TEMPERATURE
TEMPERATURE
2.4
2.4
2.2
2
Enable
Disable
Turn-On
Turn-Off
2.2
2
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1
0.8
0.8
-50
0
50
100
150
-50
0
50
100
150
7HPSHUDWXUHꢀꢁÛ&ꢂ
7HPSHUDWXUHꢀꢁÛ&ꢂ
C008
C009
Figure 14.
Figure 15.
OUTPUT PULLUP RESISTANCE
OUTPUT PULLDOWN RESISTANCE
vs
vs
TEMPERATURE
TEMPERATURE
25
20
15
10
5
1.2
1
ROH
ROL
0.8
0.6
0.4
0.2
Vdd = 18V
Vdd = 18V
-50
0
50
100
150
-50
0
50
100
150
7HPSHUDWXUHꢀꢁÛ&ꢂ
7HPSHUDWXUHꢀꢁÛ&ꢂ
C010
C011
Figure 16.
Figure 17.
10
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ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
OPERATING SUPPLY CURRENT
INPUT-TO-OUTPUT PROPAGATION DELAY
vs
vs
TEMPERATURE (OUTPUT IN DC ON/OFF CONDITION)
TEMPERATURe
0.6
30
25
20
15
10
IN=HIGH
Turn-On
Turn-Off
IN=LOW
0.5
0.4
0.3
Vdd = 18V
Vdd = 18V
0.2
-50
0
50
100
150
-50
0
50
100
150
7HPSHUDWXUHꢀꢁÛ&ꢂ
7HPSHUDWXUHꢀꢁÛ&ꢂ
C012
C013
Figure 18.
Figure 19.
IN- INPUT-TO-OUTPUT PROPAGATION DELAY
RISE TIME
vs
TEMPERATURE
vs
TEMPERATURE
30
26
22
18
14
10
16
15
14
13
12
11
OUT RISING, IN- 5V to 0V
OUT FALLING, IN- 0V to 5V
Vdd = 18V
Cload = 1.8nF
Vdd = 18V
-50
0
50
100
150
Temperature (Ü&ꢀ
C003
-50
0
50
100
150
7HPSHUDWXUHꢀꢁÛ&ꢂ
C014
Figure 20.
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
FALL TIME
OPERATING SUPPLY CURRENT
vs
SUPPLY VOLTAGE (OUTPUT SWITCHING)
vs
TEMPERATURE
9
10
8
8
7
6
6
4
Vdd = 18V
Cload = 1.8nF
Cload = 10nF
fsw = 20kHz
5
4
2
0
-50
0
50
100
150
0
10
20
30
40
7HPSHUDWXUHꢀꢁÛ&ꢂ
Supply Voltage (V)
C015
C016
Figure 22.
Figure 23.
RISE TIME
vs
SUPPLY VOLTAGE
FALL TIME
vs
SUPPLY VOLTAGE
140
120
100
80
70
60
50
40
30
20
10
60
Cload = 10nF
30
Cload = 10nF
30
40
0
10
20
40
0
10
20
40
Supply Voltage (V)
Supply Voltage (V)
C017
C018
Figure 24.
Figure 25.
12
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ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
APPLICATION INFORMATION
High-current gate driver devices are required in switching power applications for a variety of reasons. In order to
enable fast switching of power devices and reduce associated switching power losses, a powerful gate driver can
be employed between the PWM output of controllers or signal isolation devices and the gates of the power
semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the
PWM controller directly drive the gates of the switching devices. The situation is encountered often because the
PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not
capable of effectively turning on a power switch. A level shifting circuitry is needed to boost the logic-level signal
to the gate-drive voltage in order to fully turn on the power device and minimize conduction losses. Traditional
buffer drive circuits based on NPN/PNP bipolar, (or p- n-channel MOSFET), transistors in totem-pole
arrangement, being emitter follower configurations, prove inadequate for this because they lack level-shifting
capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting, buffer drive
and UVLO functions. Gate drivers also find other needs such as minimizing the effect of switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses into itself.
The UCC27531-Q1 is very flexible in this role with a strong current drive capability and wide supply voltage
range up to 32 V. This allows the driver to be used in 12-V Si MOSFET applications, 20-V and –5-V (relative to
Source) SiC FET applications, 15-V and –15-V(relative to Emitter) IGBT applications and many others. As a
single-channel driver, the UCC27531-Q1 can be used as a low-side or high-side driver. To use as a low-side
driver, the switch ground is usually the system ground so it can be connected directly to the gate driver. To use
as a high-side driver with a floating return node however, signal isolation is needed from the controller as well as
an isolated bias to the UCC27531-Q1. Alternatively, in a high-side drive configuration the UCC27531-Q1 can be
tied directly to the controller signal and biased with a non-isolated supply. However, in this configuration the
outputs of the UCC27531-Q1 need to drive a pulse transformer which then drives the power-switch to work
properly with the floating source and emitter of the power switch. Further, having the ability to control turn-on and
turn-off speeds independently with both the OUTH and OUTL pins ensures optimum efficiency while maintaining
system reliability. These requirements coupled with the need for low propagation delays and availability in
compact, low-inductance packages with good thermal capability makes gate driver devices such as the
UCC27531-Q1 extremely important components in switching power combining benefits of high-performance, low
cost, component count and board space reduction and simplified system design.
Table 1. UCC27531-Q1 Features and Benefits
FEATURE
BENEFIT
High source and sink current capability, 2.5 A and
5 A (asymmetrical).
High current capability offers flexibility in employing UCC27531-Q1 device to drive a
variety of power switching devices at varying speeds.
Low 17 ns (typ) propagation delay.
Extremely low pulse transmission distortion.
Flexibility in system design.
Wide VDD operating range of 10 V to 32 V.
Can be used in split-rail systems such as driving IGBTs with both positive and
negative (relative to Emitter) supplies.
Optimal for many SiC FETs.
VDD UVLO protection.
Outputs are held Low in UVLO condition, which ensures predictable, glitch-free
operation at power-up and power-down.
High UVLO of 8.9-V typical ensures that power switch is not on in high-impedance
state which could result in high power dissipation or even failures.
Outputs held low when input pin (INx) in floating
condition.
Safety feature, especially useful in passing abnormal condition tests during safety
certification
Split output structure option (OUTH, OUTL).
Allows independent optimization of turn-on and turn-off speeds using series gate
resistors.
Strong sink current (5 A) and low pulldown
High immunity to high dV/dt Miller turn-on events.
impedance (0.65 Ω).
CMOS and TTL compatible input threshold logic
with wide hysteresis.
Enhanced noise immunity, while retaining compatibility with microcontroller logic level
input signals (3.3 V, 5 V) optimized for digital power.
Input capable of withstanding –6.5 V.
Enhanced signal reliability in noisy environments that experience ground bounce on
the gate driver.
Copyright © 2013, Texas Instruments Incorporated
13
UCC27531-Q1
ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
www.ti.com.cn
VDD Under Voltage Lockout
The UCC27531-Q1 device has internal under voltage lockout (UVLO) protection feature on the VDD pin supply
circuit blocks. To ensure acceptable power dissipation in the power switch, this UVLO prevents the operation of
the gate driver at low supply voltages. Whenever the driver is in UVLO condition (when VDD voltage less than
VON during power-up and when VDD voltage is less than VOFF during power down), this circuit holds all outputs
LOW, regardless of the status of the inputs. The UVLO is typically 8.9 V with 700-mV typical hysteresis. This
hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also
when there are droops in the VDD bias voltage when the system commences switching and there is a sudden
increase in IDD. The capability to operate at voltage levels such as 10 V to 32 V provides flexibility to drive Si
MOSFETs, IGBTs, and emerging SiC FETs.
VDD Threshold
VDD
IN
OUT
Figure 26. Power Up
Input Stage
The input pins of UCC27531-Q1 device are based on a TTL and CMOS compatible input threshold logic that is
independent of the VDD supply voltage. With typical high threshold = 2 V and typical low threshold = 1 V, the
logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V logic. Wider
hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL logic implementations,
where the hysteresis is typically less than 0.5 V. This device also features tight control of the input pin threshold
voltage levels which eases system design considerations and guarantees stable operation across temperature.
The very low input capacitance , typically 20 pF, on these pins reduces loading and increases switching speed.
The device features an important safety function wherein, whenever the input pin is in a floating condition, the
output is held in the low state. This is achieved using pullup or pulldown resistors on the input pins as shown in
the block diagrams.
The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly varying input signals, especially in situations where the device
is located in a separate daughter board or PCB layout has long input connection traces:
•
High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. Since
the device features just one GND pin which may be referenced to the power ground, this may interfere with
the differential voltage between Input pins and GND and trigger an unintended change of output state.
Because of fast 17 ns propagation delay, this can ultimately result in high-frequency oscillations, which
increases power dissipation and poses risk of damage
•
1-V Input threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
If limiting the rise or fall times to the power device to reduce EMI is necessary, then an external resistance is
highly recommended between the output of the driver and the power device instead of adding delays on the input
signal. This external resistor has the additional benefit of reducing part of the gate charge related power
dissipation in the gate driver device package and transferring it into the external resistor itself.
14
Copyright © 2013, Texas Instruments Incorporated
UCC27531-Q1
www.ti.com.cn
ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
Finally, because of the unique input structure that allows negative voltage capability on the Input and Enable
pins, caution must be used in the following applications:
•
•
Input or Enable pins are switching to amplitude > 15 V
Input or Enable pins are switched at dV/dt > 2 V/ns
If both of these conditions occur, it is advised to add a series 150-Ω resistor for the pin(s) being switched to limit
the current through the input structure.
Enable Function
The Enable (EN) pin of the UCC27531-Q1 has an internal pullup resistor to an internal reference voltage so
leaving Enable floating turns on the driver and allows it to send output signals properly. If desired, the Enable can
also be driven by low-voltage logic to enable and disable the driver.
Output Stage
The output stage of the UCC27531-Q1 device is illustrated in Figure 27. The UCC27531-Q1 device features a
unique architecture on the output stage which delivers the highest peak source current when it is most needed
during the Miller plateau region of the power switch turn-on transition (when the power switch drain/collector
voltage experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel
arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a
narrow instant when the output changes state from low to high, the gate driver device is able to deliver a brief
boost in the peak sourcing current enabling fast turn on.
VDD
ROH
RNMOS, Pull Up
OUTH
Anti Shoot-
Through
Circuitry
Input Signal
OUTL
Narrow Pulse at
each Turn On
ROL
Figure 27. UCC27531-Q1 Gate Driver Output Stage
Split output depicted in Figure 27. For devices with single OUT pin, OUTH and OUTL are connected internally
and then connected to OUT.
The ROH parameter (see ELECTRICAL CHARACTERISTICS) is a DC measurement and it is representative of
the on-resistance of the P-Channel device only, because the N-Channel device is turned-on only during output
change of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what
is represented by ROH parameter. The pulldown structure is composed of a N-Channel MOSFET only. The ROL
parameter (see ELECTRICAL CHARACTERISTICS), which is also a DC measurement, is representative of true
impedance of the pulldown stage in the device. In UCC27531-Q1, the effective resistance of the hybrid pullup
structure is approximately 3 x ROL
.
The UCC27531-Q1 is capable of delivering 2.5-A source, and up to 5-A sink at VDD = 18 V. Strong sink
capability results in a very low pulldown impedance in the driver output stage which boosts immunity against the
parasitic Miller turn-on (high slew rate dV/dt turn on) effect that is seen in both IGBT and FET power switches .
Copyright © 2013, Texas Instruments Incorporated
15
UCC27531-Q1
ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
www.ti.com.cn
An example of a situation where Miller turn on is a concern is synchronous rectification (SR). In SR application,
the dV/dt occurs on MOSFET drain when the MOSFET is already held in Off state by the gate driver. The current
charging the CGD Miller capacitance during this high dV/dt is shunted by the pulldown stage of the driver. If the
pulldown impedance is not low enough then a voltage spike can result in the VGS of the MOSFET, which can
result in spurious turn on. This phenomenon is illustrated in Figure 28.
VDS
VIN
Miller Turn -On Spike in V GS
CGD
Gate Driver
VTH
VGS of
MOSFET
RG
COSS
ISNK
ON OFF
VIN
CGS
ROL
VDS of
MOSFET
Figure 28. Low Pulldown Impedance in UCC27531-Q1
(Output Stage Mitigates Miller Turn-on Effect)
The driver output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS
output stage which delivers very low dropout. The presence of the MOSFET body diodes also offers low
impedance to switching overshoots and undershoots. This means that in many cases, external Schottky diode
clamps may be eliminated.
Power Dissipation
Power dissipation of the gate driver has two portions as shown in Equation 1.
P
= P + P
DC SW
DISS
(1)
The DC portion of the power dissipation is PDC = IQ x VDD where IQ is the quiescent current for the driver. The
quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference
voltage, logic circuits, protections etc and also any current associated with switching of internal devices when the
driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-
through). The UCC27531-Q1 features very low quiescent currents (less than 1 mA) and contains internal logic to
eliminate any shoot-through in the output driver stage. Thus the effect of the PDC on the total power dissipation
within the gate driver can be safely assumed to be negligible. In practice this is the power consumed by driver
when its output is disconnected from the gate of power switch.
The power dissipated in the gate driver package during switching (PSW) depends on the following factors:
•
Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD due to low VOH drop-out)
•
•
Switching frequency
Use of external gate resistors
When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power
that is required from the bias supply. The energy that must be transferred from the bias supply to charge the
capacitor is given in Equation 2.
1
2
EG
=
CLOADVDD
2
where
•
CLOAD is load capacitor and VDD is bias voltage feeding the driver.
(2)
16
Copyright © 2013, Texas Instruments Incorporated
UCC27531-Q1
www.ti.com.cn
ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
There is an equal amount of energy dissipated when the capacitor is discharged. During turn off the energy
stored in capacitor is fully dissipated in drive circuit. This leads to a total power loss during switching cycle given
by Equation 3.
2
LOAD DD sw
P
= C
V
f
G
where
•
ƒSW is the switching frequency
(3)
The switching load presented by a power FET and IGBT can be converted to an equivalent capacitance by
examining the gate charge required to switch the device. This gate charge includes the effects of the input
capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between
the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC,
to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that
must be dissipated when charging a capacitor. This is done by using the equivalence, Qg = CLOADVDD, to provide
Equation 4 for power
2
LOAD DD sw
P
= C
V
f
= Q V f
g DD sw
G
(4)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET and IGBT is being turned
on or off. Half of the total power is dissipated when the load capacitor is charged during turn-on, and the other
half is dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is
employed between the driver and MOSFET and IGBT, this power is completely dissipated inside the driver
package. With the use of external gate drive resistors, the power dissipation is shared between the internal
resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power
dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation
during switching is calculated in Equation 5.
æ
ö
÷
÷
ø
ROFF
+ RGATE
RON
PSW = 0.5´Qg ´ VDD ´ f
+
ç
sw ç
è
R
(
R
ON + RGATE
) (
)
OFF
where
•
ROFF = ROL and RON (effective resistance of pullup structure) = 3 x ROL
(5)
Thermal Information
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the package. In order for a gate driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The thermal metrics for the driver package are summarized in the THERMAL INFORMATION
section of the datasheet. For detailed information regarding the thermal information table, please refer to the TI
Application Note, IC Package Thermal Metrics (SPRA953A).
Copyright © 2013, Texas Instruments Incorporated
17
UCC27531-Q1
ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
www.ti.com.cn
PCB Layout
Proper PCB layout is extremely important in a high current, fast switching circuit to provide appropriate device
operation and design robustness. The UCC27531-Q1 gate driver incorporates short propagation delays and
powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of
power switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current capability is
even higher (2.5-A and 5-A peak current is at VDD = 18 V). Very high di/dt can cause unacceptable ringing if the
trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly
recommended when designing with these high-speed drivers.
•
Locate the driver device as close as possible to power device in order to minimize the length of high-current
traces between the driver Output pins and the gate of the power switch device.
•
Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal
trace length to improve the noise filtering. These capacitors support high peak current being drawn from VDD
during turn-on of power switch. The use of low inductance SMD components such as chip resistors and chip
capacitors is highly recommended.
•
•
The turn-on and turn-off current loop paths (driver device, power switch and VDD bypass capacitor) should be
minimized as much as possible in order to keep the stray inductance to a minimum. High di/dt is established
in these loops at two instances – during turn-on and turn-off transients, which induces significant voltage
transients on the output pins of the driver device and gate of the power switch.
Wherever possible, parallel the source and return traces of a current loop, taking advantage of flux
cancellation
•
•
Separate power traces and signal traces, such as output and input signals.
Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM
controller etc at one, single point. The connected paths should be as short as possible to reduce inductance
and be as wide as possible to reduce resistance.
•
Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well.
18
Copyright © 2013, Texas Instruments Incorporated
UCC27531-Q1
www.ti.com.cn
ZHCSBV0A –AUGUST 2013–REVISED DECEMBER 2013
REVISION HISTORY
Changes from Original (August 2013) to Revision A
Page
•
Changed 文档状态，从 产品预览 改为 生成数据 .................................................................................................................. 1
Copyright © 2013, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC27531QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
EAHQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27531QDBVRQ1
SOT-23
DBV
6
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
UCC27531QDBVRQ1
6
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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