UCC27282 [TI]

具有 5V UVLO、互锁和使能功能的 3A、120V 半桥栅极驱动器;


型号：	UCC27282
厂家：	TEXAS INSTRUMENTS
描述：	具有 5V UVLO、互锁和使能功能的 3A、120V 半桥栅极驱动器栅极驱动驱动器
文件：	总40页 (文件大小：2444K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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UCC27282

SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020

UCC27282 120-V Half-Bridge Driver

with Cross Conduction Protection and Low Switching Losses

1 Features

3 Description

The UCC27282 is a robust N-channel MOSFET

•

Drives two N-channel MOSFETs in high-side low-

side configuration

driver with a maximum switch node (HS) voltage

rating of 100 V. It allows for two N-channel MOSFETs

to be controlled in half-bridge or synchronous buck

configuration based topologies. Its 3.5-A peak sink

current and 2.5-A peak source current along with low

pull-up and pull-down resistance allows the

UCC27282 to drive large power MOSFETs with

minimum switching losses during the transition of the

MOSFET Miller plateau. Since the inputs are

independent of the supply voltage, UCC27282 can be

used in conjunction with both analog and digital

controllers.

•

5-V typical under voltage lockout

Input interlock

Enable/disable functionality in DRC package

16-ns typical propagation delay

12-ns rise, 10-ns fall time with 1.8-nF load

1-ns typical delay matching

Absolute Maximum Negative Voltage Handling on

Inputs (–5 V)

•

Absolute Maximum Negative Voltage Handling on

HS (–14 V)

The input pins as well as the HS pin are able to

tolerate significant negative voltage, which improves

system robustness. Input interlock further improves

robustness and system reliability in high noise

applications. The enable and disable functionality

provides additional system flexibility by reducing

power consumption by the driver and responds to

fault events within the system. 5-V UVLO allows

systems to operate at lower bias voltages, which is

necessary in many high frequency applications and

improves system efficiency in certain operating

modes. Small propagation delay and delay matching

specifications minimize the dead-time requirement

which further improves efficiency.

•

3.5-A sink, 2.5-A Source output currents

Absolute maximum boot voltage 120 V

Low current (7-µA) consumption when disabled

Integrated bootstrap diode

Specified from –40°C to 140°C junction

temperature

2 Applications

•

Telecom and merchant power supplies

Motor drives and power tools

Auxiliary inverters

Under voltage lockout (UVLO) is provided for both the

high-side and low-side driver stages forcing the

outputs low if the VDD voltage is below the specified

threshold. An integrated bootstrap diode eliminates

the need for an external discrete diode in many

applications, which saves board space and reduces

system cost. UCC27282 is offered in a small package

enabling high density designs.

Half-bridge and full-bridge converters

Active-clamp forward converters

High voltage synchronous-buck converters

Class-D audio amplifiers

Simplified Application Diagram

Device Information⁽¹⁾

75V

PART NUMBER

PACKAGE (SIZE)

SON10 (3 mm x 3 mm)

SOIC8 (6 mm x 5mm))

UCC27282

VDD

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

To Load

0 …F

VSS

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC27282

SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020

www.ti.com

Table of Contents

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Application ................................................. 18

Power Supply Recommendations...................... 26

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 6

6.7 Timing Diagrams....................................................... 7

6.8 Typical Characteristics.............................................. 7

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 13

10 Layout................................................................... 27

10.1 Layout Guidelines ................................................. 27

10.2 Layout Example .................................................... 27

11 Device and Documentation Support ................. 28

11.1 Receiving Notification of Documentation Updates 28

11.2 Community Resources.......................................... 28

11.3 Trademarks........................................................... 28

11.4 Electrostatic Discharge Caution............................ 28

11.5 Glossary................................................................ 28

12 Mechanical, Packaging, and Orderable

Information ........................................................... 28

4 Revision History

Changes from Original (November 2018) to Revision A

Page

•

Added SOIC 8-Pin D package to the Device Information table. ........................................................................................... 1

Added SOIC 8-Pin D package image and updated the Pin Functions table.......................................................................... 3

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SNVSAQ5A –NOVEMBER 2018–REVISED JANUARY 2020

5 Pin Configuration and Functions

DRC Package

10-Pin VSON With Exposed Thermal Pad

Top View

VDD

VSS

Thermal

Pad

Not to scale

D Package

8-Pin SOIC

Top View

VDD

VSS

Not to scale

Pin Functions

I/O⁽¹⁾

DESCRIPTION

Name

DRC

Enable input. When this pin is pulled high, it will enable the driver. If left floating or pulled low, it will

disable the driver. 1 nF filter capacitor is recommended for high-noise systems.

n/a

High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is

required. Connect positive side of the bootstrap capacitor to this pin. Typical recommended value of

HB bypass capacitor is 0.1 μF, This value primarily depends on the gate charge of the high-side

MOSFET. When using external boot diode, connect cathode of the diode to this pin.

High-side input.

High-side output. Connect to the gate of the high-side power MOSFET or one end of external gate

resistor, when used.

High-side source connection. Connect to source of high-side power MOSFET. Connect negative

side of bootstrap capacitor to this pin.

Low-side input

Low-side output. Connect to the gate of the low-side power MOSFET or one end of external gate

resistor, when used.

—

VDD

VSS

n/a

Not connected internally.

Positive supply to the low-side gate driver. Decouple this pin to VSS. Typical decoupling capacitor

value is 1 μF. When using an external boot diode, connect the anode to this pin.

—

Negative supply terminal for the device which is generally the system ground.

Thermal

pad

Connect to a large thermal mass trace (generally IC ground plane) to improve thermal performance.

This can only be electrically connected to VSS.

n/a

(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output

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6 Specifications

6.1 Absolute Maximum Ratings

(1)(2)

All voltages are with respect to V_ss

MIN

–0.3

MAX

UNIT

V_DD

Supply voltage

V_EN, V_HI, V_LI

Input voltages on EN, HI and LI

–5

–0.3

V_DD+ 0.3

V_HB+ 0.3

100

V_LO

V_HO

V_HS

Output voltage on LO

Output voltage on HO

Voltage on HS

Pulses < 100 ns⁽³⁾

–2

V_HS– 0.3

V_HS– 2

–10

Pulses < 100 ns⁽³⁾

–14

100

V_HB

Voltage on HB

–0.3

120

V_HB-HS

T_J

Voltage on HB with respect to HS

Operating junction temperature

Lead temperature (soldering, 10 sec.)

Storage temperature

–0.3

–40

150

°C

300

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to V_ss. Currents are positive into, negative out of the specified terminal.

(3) Values are verified by characterization only.

6.2 ESD Ratings

VALUE

±2000

±1500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽²⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽³⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) Pins HS, HB and HO are rated at 500V HBM

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_DD

Supply voltage

5.5

V_EN, V_HI, V_LIInput Voltage

V_DD+0.3

V_HB+0.3

100

V_LO

V_HO

Low side output voltage

High side output voltage

Voltage on HS⁽¹⁾

V_HS

–8

V_HS

Voltage on HS (Pulses < 100 ns)⁽¹⁾

–12

100

V_HB

V_sr

T_J

Voltage on HB

V_HS+ 5.5

V_HS+16

Voltage slew rate on HS

Operating junction temperature

V/ns

°C

–40

140

(1) V_HB-HS< 16V (Voltage on HB with respect to HS must be less than 16V)

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6.4 Thermal Information

UCC27282

THERMAL METRIC⁽¹⁾

DRC

UNIT

8 PINS 10 PINS

R_θJA

Junction-to-ambient thermal resistance

118.3

53.6

63.1

10.7

62.1

n/a

47.3

50.3

21.3

1.0

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

R_θJB

ψ_JT

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

21.2

4.4

R_θJC(bot)Junction-to-case (bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

V_DD= V_HB= V_EN=12 V, V_HS= V_SS= 0 V, No load on LO or HO, T_J= –40°C to +140°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SUPPLY CURRENTS

I_DD

VDD quiescent current

VDD operating current

V_LI= V_HI= 0

0.3

2.2

0.2

2.5

2.0

0.1

7.0

0.4

4.5

0.4

μA

I_DDO

f = 500 kHz, C_LOAD= 0

V_LI= V_HI= 0 V

I_HB

HB quiescent current

I_HBO

HB operating current

f = 500 kHz, C_LOAD= 0

V_HS= V_HB= 110 V

f = 500 kHz, C_LOAD= 0

V_EN= 0

I_HBS

HB to VSS quiescent current

HB to VSS operating current⁽¹⁾

I_DDwhen driver is disabled

I_HBSO

I_{DD_DIS}

INPUT

V_HIT

μA

Input rising threshold

Input falling threshold

Input voltage Hysteresis

Input pulldown resistance

1.9

0.9

2.1

1.1

1.0

250

2.4

1.3

V_LIT

V_IHYS

R_IN

100

0.7

350

2.0

kΩ

ENABLE

V_EN

Voltage threshold on EN pin to enable the driver

Voltage threshold on EN pin to disable the driver

Enable pin Hysteresis

1.54

1.21

0.3

V_DIS

V_ENHYS

R_EN

EN pin internal pull-down resistor

250

kΩ

Time to enable the driver once the EN pin is

pulled high

T_EN

V_EN= 2V

V_EN= 0V

μs

Time to disable the driver once the EN pin is

pulled low

T_DIS

1.5

UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)

V_DDR

VDD rising threshold

4.7

4.2

5.0

4.5

0.5

3.7

3.3

0.3

5.4

4.9

V_DDF

VDD falling threshold

V_DDHYS

V_HBR

VDD threshold hysteresis

HB rising threshold with respect to HS pin

HB falling threshold with respect to HS pin

HB threshold hysteresis

3.3

3.0

4.4

4.1

V_HBF

V_HBHYS

BOOTSTRAP DIODE

V_F

Low-current forward voltage

I_VDD-HB= 100 μA

0.55

0.88

1.5

0.85

1.0

Ω

V_FI

R_D

High-current forward voltage

I_VDD-HB= 80 mA

Dynamic resistance, ΔV_F/ΔI

I_VDD-HB= 100 mA and 80 mA

2.5

(1) Parameter not tested in production

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Electrical Characteristics (continued)

V_DD= V_HB= V_EN=12 V, V_HS= V_SS= 0 V, No load on LO or HO, T_J= –40°C to +140°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

LO GATE DRIVER

V_LOL

V_LOH

Low level output voltage

I_LO= 100 mA

0.085

0.13

2.5

0.4

High level output voltage

I_LO= -100 mA, V_LOH= V_DD– V_LO

V_LO= 0 V

0.42

(1)

Peak pullup current

(1)

Peak pulldown current

V_LO= 12 V

3.5

HO GATE DRIVER

V_HOL

V_HOH

Low level output voltage

I_HO= 100 mA

0.1

0.13

2.5

0.4

High level output voltage

I_HO= –100 mA, V_HOH= V_HB- V_HO

V_HO= 0 V

0.42

(1)

Peak pullup current

(1)

Peak pulldown current

V_HO= 12 V

3.5

6.6 Switching Characteristics

V_DD= V_HB= 12 V, V_HS= V_SS= 0 V, No load on LO or HO, T_J= –40°C to +140°C, (unless otherwise noted)

PARAMETER

PROPAGATION DELAYS

TEST CONDITIONS

MIN

TYP

MAX UNIT

t_DLFF

t_DHFF

t_DLRR

t_DHRR

V_LIfalling to V_LOfalling

V_HIfalling to V_HOfalling

V_LIrising to V_LOrising

V_HIrising to V_HOrising

See Timing Diagrams

DELAY MATCHING

t_MON

From LO being ON to HO being OFF

From LO being OFF to HO being ON

See Timing Diagrams

t_MOFF

OUTPUT RISE AND FALL TIME

t_R

t_F

t_R

t_F

LO, HO rise time

C_LOAD= 1800 pF, 10% to 90%

C_LOAD= 1800 pF, 90% to 10%

C_LOAD= 0.1 μF, 30% to 70%

C_LOAD= 0.1 μF, 70% to 30%

μs

LO, HO fall time

LO, HO (3 V to 9 V) rise time

LO, HO (3 V to 9 V) fall time

0.33

0.23

0.6

MISCELLANEOUS

T_PW,minMinimum input pulse width that changes the output

Bootstrap diode turnoff time⁽¹⁾

I_F= 20 mA, I_REV= 0.5 A

(1) Parameter not tested in production

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6.7 Timing Diagrams

Input

(HI, LI)

T_DLRR, T_DHRR

Output

(HO, LO)

T_DLFF

T_DHFF

Time (s)

T_MOFF

T_MON

6.8 Typical Characteristics

Unless otherwise specified V_VDD=V_HB= 12 V, V_HS=V_VSS= 0 V, No load on outputs

0.3

0.28

0.26

0.24

0.22

0.2

0.22

0.18

0.14

0.1

0.18

0.16

0.14

0.12

0.1

0.06

5.5V

12V

16V

5.5V

12V

16V

0.02

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

IDDQ

IHBQ

V_HI= V_LI= 0 V

Figure 1. VDD Quiescent Current

V_HI= V_LI= 0 V

Figure 2. HB Quiescent Current

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Typical Characteristics (continued)

Unless otherwise specified V_VDD=V_HB= 12 V, V_HS=V_VSS= 0 V, No load on outputs

4.5

-40°C

25°°C

140°°C

-40°C

25°C

140°C

3.5

2.5

1.5

0.5

3 4 5 67 10

20 30 50 70100 200

Frequency (kHz)

500 1000

3 4 567 10

20 30 50 70100 200

Frequency (kHz)

500 1000

IDDO

IHBO

C_L= 0 F

V_DD=V_HB= 12V

C_L= 0 F

V_DD=V_HB= 12V

Figure 3. VDD Operating Current

Figure 4. HB Operating Current

5.5V

12V

16V

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

IDD_

IHBS

C_L= 0 F

V_EN= 0 V

V_HB=V_HS=100V

Figure 6. HB to VSS Quiescent Current

Figure 5. VDD Current When Disabled

2.22

2.215

2.21

1.145

1.14

1.135

1.13

2.205

2.2

2.195

2.19

1.125

1.12

2.185

2.18

1.115

1.11

2.175

2.17

5.5V

12V

16V

5.5V

12V

16V

2.165

1.105

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

IN_R

IN_F

Figure 7. Input Rising Threshold

Figure 8. Input Falling Threshold

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Typical Characteristics (continued)

Unless otherwise specified V_VDD=V_HB= 12 V, V_HS=V_VSS= 0 V, No load on outputs

280

270

260

250

240

230

1.75

5.5V

12V

16V

1.7

1.65

1.6

1.55

1.5

1.45

1.4

1.35

1.3

1.25

1.2

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

R_IN

EN_T

Figure 9. Input Pull-down Resistor

Figure 10. Enable Threshold

1.35

1.3

5.5V

12V

16V

5.5V

12V

16V

1.25

1.2

1.15

1.1

1.05

0.95

0.9

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

Dis_

T_EN

Figure 11. Disable Threshold

Figure 12. Enable Delay

2.2

2.15

2.1

5.2

5.5V

12V

16V

2.05

4.8

4.6

4.4

4.2

1.95

1.9

1.85

1.8

1.75

1.7

Rise

Fall

1.65

1.6

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

T_Di

VDDU

Figure 13. Disable Delay

Figure 14. VDD UVLO Threshold

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Typical Characteristics (continued)

Unless otherwise specified V_VDD=V_HB= 12 V, V_HS=V_VSS= 0 V, No load on outputs

3.8

3.6

3.4

3.2

0.95

0.9

100uA

80mA

0.85

0.8

0.75

0.7

0.65

0.6

0.55

0.5

0.45

0.4

0.35

0.3

Rise

Fall

0.25

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

HBUV

Figure 15. HB UVLO Threshold

Figure 16. Boot Diode Forward Voltage Drop

0.135

0.13

1.8

1.75

1.7

0.125

0.12

1.65

1.6

0.115

0.11

1.55

1.5

0.105

0.1

0.095

0.09

1.45

1.4

0.085

0.08

1.35

1.3

5.5V

12V

16V

0.075

0.07

1.25

0.065

1.2

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

V_LO

R_Dy

I_O=100mA

Figure 18. LO Low Output Voltage (V_LOL

)

Figure 17. Boot Diode Dynamic Resistance

0.155

0.15

0.21

0.2

0.145

0.14

0.19

0.18

0.17

0.16

0.15

0.14

0.13

0.12

0.11

0.1

0.135

0.13

0.125

0.12

0.115

0.11

0.105

0.1

5.5V

12V

16V

5.5V

12V

16V

0.095

0.09

0.085

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

V_LO

UV_CHCO2

I_O=-100mA

Figure 19. LO High Output Voltage (V_LOH

I_O=100mA

Figure 20. HO Low Output Voltage (V_HOL

)

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Typical Characteristics (continued)

Unless otherwise specified V_VDD=V_HB= 12 V, V_HS=V_VSS= 0 V, No load on outputs

0.19

0.18

0.17

0.16

0.15

0.14

0.13

0.12

0.11

0.1

14.5

5.5V

12V

16V

13.5

12.5

11.5

10.5

5.5V

12V

16V

0.09

9.5

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

V_HO

LO_R

I_O=-100mA

C_L=1800pF

Figure 21. HO High Output Voltage (V_HOH

)

Figure 22. LO Rise Time

10.2

5.5V

12V

16V

5.5V

12V

16V

9.8

9.6

9.4

9.2

8.8

8.6

8.4

8.2

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

LO_F

HO_R

C_L=1800pF

Figure 23. LO Fall Time

Figure 24. HO Rise Time

8.8

8.6

8.4

8.2

0.4

0.38

0.36

0.34

0.32

0.3

5.5V

12V

16V

0.28

0.26

0.24

0.22

0.2

7.8

7.6

7.4

7.2

Rise

Fall

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

HO_F

LO_R

C_L=1800pF

C_L=100nF

Figure 25. HO Fall Time

Figure 26. LO Rise & Fall Time

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Typical Characteristics (continued)

Unless otherwise specified V_VDD=V_HB= 12 V, V_HS=V_VSS= 0 V, No load on outputs

0.45

0.425

0.4

19.5

0.375

0.35

0.325

0.3

18.5

17.5

0.275

0.25

0.225

0.2

16.5

15.5

5.5V

12V

16V

Rise

Fall

0.175

14.5

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

HO_R

TDHR

C_L=100nF

Figure 27. HO Rise & Fall Time

C_L=No Load

Figure 28. HO Rising Propagation Delay (TDHRR)

20.5

19.5

18.5

17.5

16.5

15.5

5.5V

12V

16V

5.5V

12V

16V

15.5

14.5

-40

-20

40 60

Temperature (°C)

100 120 140

-40

-20

40 60

Temperature (°C)

100 120 140

TDHF

TDLR

C_L= No Load

Figure 29. HO Falling Propagation Delay (TDHFF)

Figure 30. LO Rising Propagation Delay (TDLRR)

18.5

17.5

16.5

15.5

5.5V

12V

16V

14.5

-40

-20

40 60

Temperature (°C)

100 120 140

TDLF

C_L= No Load

Figure 31. LO Falling Propagation Delay (TDLFF)

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7 Detailed Description

7.1 Overview

The UCC27282 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel

FETs in a synchronous buck or a half-bridge configurations. The two outputs are independently controlled with

two TTL-compatible input signals. The device can also work with CMOS type control signals at its inputs as long

as signals meet turn-on and turn-off threshold specifications of the UCC27282. The floating high-side driver is

capable of working with HS voltage up to 100 V with respect to VSS. A 100 V bootstrap diode is integrated in the

UCC27282 device to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high

speed while consuming low power and provides clean level transitions from the control logic to the high-side gate

driver. Undervoltage lockout (UVLO) is provided on both the low-side and the high-side power rails. EN pin is

provided (in DRC packaged parts) to enable or disable the driver. The driver also has input interlock functionality,

which shuts off both the outputs when the two inputs overlap.

7.2 Functional Block Diagram

UVLO

DRIVER

STAGE

LEVEL

SHIFT

VDD

UVLO

DRIVER

STAGE

Interlock Logic

VSS

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7.3 Feature Description

7.3.1 Enable

The device in DRC package has an enable (EN) pin. The outputs will be active only if the EN pin voltage is

above the threshold voltage. Outputs will be held low if EN pin is left floating or pulled-down to ground. An

internal 250 kΩ resistor connects EN pin to VSS pin. Thus, leaving the EN pin floating disables the device.

Externally pulling EN pin to ground shall also disable the device. If the EN pin is not used, then it is

recommended to connect it to VDD pin. If a pull-up resistor needs to be used then a strong pull-up resistor is

recommended. For 12V supply voltage, a 10kΩ pull-up is suggested. In noise prone application, a small filter

capacitor, 1nF, should be connected from the EN pin to VSS pin as close to the device as possible. An analog or

a digital controller output pin could be connected to EN pin to enable or disable the device. Built-in hysteresis

helps prevent any nuisance tripping or chattering of the outputs.

7.3.2 Start-up and UVLO

Both the high-side and the low-side driver stages include UVLO protection circuitry which monitors the supply

voltage (V_DD) and the bootstrap capacitor voltage (V_HB–HS). The UVLO circuit inhibits each output until sufficient

supply voltage is available to turn on the external MOSFETs. The built-in UVLO hysteresis prevents chattering

during supply voltage variations. When the supply voltage is applied to the VDD pin of the device, both the

outputs are held low until VDD exceeds the UVLO threshold, typically 5 V. Any UVLO condition on the bootstrap

capacitor (V_HB–HS) disables only the high- side output (HO).

Table 1. VDD UVLO Logic Operation

Condition (V_HB-HS> V_HBRand V_EN> Enable Threshold)

V_DD-V_SS< V_DDRduring device start-up

V_DD-V_SS< V_DDR– V_DDHafter device start-up

Table 2. HB UVLO Logic Operation

Condition (V_DD> V_DDRand V_EN> Enable Threshold)

V_HB-HS< V_HBRduring device start-up

V_HB-HS< V_HBR– V_HBHafter device start-up

7.3.3 Input Stages and Interlock

The two inputs operate independently, with an exception that both outputs will be pulled low when both inputs

are high or overlap. The independence allows for full control of two outputs compared to the gate drivers that

have a single input. The device has input interlock or cross-conduction protection. Whenever both the inputs are

high, the internal logic turns both the outputs off. Once the device is in shoot-through mode, when one of the

inputs goes low, the outputs follow the input logic. There is no other fixed time de-glitch filter implemented in the

device and therefore propagation delay and delay matching are not sacrificed. In other words, there is no built-in

dead-time due to the interlock feature. Any noise on the input that could cause the output to shoot-through will be

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filtered by this feature and the system stays protected. Because the inputs are independent of supply voltage,

they can be connected to outputs of either digital controller or analog controller. Inputs can accept wide slew rate

signals and input can withstand negative voltage to increase the robustness. Small filter at the inputs of the driver

further improves system robustness in noise prone applications. The inputs have internal pull down resistors with

typical value of 250 kΩ. Thus, when the inputs are floating, the outputs are held low.

Interlock

Time

Figure 32. Interlock or Input Shoot-through Protection

7.3.4 Level Shifter

The level shift circuit is the interface from the high-side input, which is a VSS referenced signal, to the high-side

driver stage which is referenced to the switch node (HS pin). The level shift allows control of the HO output which

is referenced to the HS pin. The delay introduced by the level shifter is kept as low as possible and therefore the

device provides excellent propagation delay characteristic and delay matching with the low-side driver output.

Low delay matching allows power stages to operate with less dead time. The reduction in dead-time is very

important in applications where high efficiency is required.

7.3.5 Output Stage

The output stages are the interface from level shifter output to the power MOSFETs in the power train. High slew

rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power

MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS. The device

output stages are robust to handle harsh environment, such as –2 V transient for 100 ns. The device can also

sustain positive transients on the outputs. The device output stages feature a pull-up structure which delivers the

highest peak source current when it is most needed, during the Miller plateau region of the power switch turn on

transition. The output pull-up and pull-down structure of the device is totem pole NMOS-PMOS structure.

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7.3.6 Negative Voltage Transients

In most applications, the body diode of the external low-side power MOSFET clamps the HS node to ground. In

some situations, board capacitances and inductances can cause the HS node to transiently swing several volts

below ground, before the body diode of the external low-side MOSFET clamps this swing. When used in

conjunction with the UCC27282, the HS node can swing below ground as long as specifications are not violated

and conditions mentioned in this section are followed.

HS must always be at a lower potential than HO. Pulling HO more negative than specified conditions can

activate parasitic transistors which may result in excessive current flow from the HB supply. This may result in

damage to the device. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be

placed externally between HO and HS or LO and VSS to protect the device from this type of transient. The diode

must be placed as close to the device pins as possible in order to be effective.

Ensure that the HB to HS operating voltage is 16 V or less. Hence, if the HS pin transient voltage is –5 V, then

VDD (and thus HB) is ideally limited to 11 V to keep the HB to HS voltage below 16 V. Generally when HS

swings negative, HB follows HS instantaneously and therefore the HB to HS voltage does not significantly

overshoot.

Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation of the gate

driver device. The capacitor should be located at the leads of the device to minimize series inductance. The peak

currents from LO and HO can be quite large. Any series inductances with the bypass capacitor causes voltage

ringing at the leads of the device which must be avoided for reliable operation.

Based on application board design and other operating parameters, along with HS pin, other pins such as inputs,

HI and LI, might also transiently swing below ground. To accommodate such operating conditions UCC27282

input pins are capable of handling absolute maximum of -5V. As explained earlier, based on the layout and other

design constraints, some times the outputs, HO and LO, might also see transient voltages for short durations.

Therefore, UCC27282 gate drivers can also handle -2 V 100 ns transients on output pins, HO and LO.

7.4 Device Functional Modes

When the device is enabled, the device operates in normal mode and UVLO mode. See Start-up and UVLO for

more information on UVLO operation mode. In normal mode when the V_DDand V_HB–HSare above UVLO

threshold, the output stage is dependent on the states of the EN, HI and LI pins. The output HO and LO will be

low if input state is floating.

Table 3. Input/Output Logic in Normal Mode of Operation

(1)

(2)

Floating

(1) HO is measured with respect to HS

(2) LO is measured with respect to VSS

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Most electronic devices and applications are becoming more and more power hungry. These applications are

also reducing in overall size. One way to achieve both high power and low size is to improve the efficiency and

distribute the power loss optimally. Most of these applications employ power MOSFETs and they are being

switched at higher and higher frequencies. To operate power MOSFETs at high switching frequencies and to

reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller

and the gates of the power semiconductor devices, such as power MOSFETs, IGBTs, SiC FETs, and GaN FETs.

Many of these applications require proper UVLO protection so that power semiconductor devices are turned ON

and OFF optimally. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly

drive the gates of the switching devices. With the advent of digital power, this situation is often encountered

because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a

power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V or 5

V) in order to fully turn-on the power device, minimize conduction losses, and minimize the switching losses.

Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove

inadequate with digital power because they lack level-shifting capability and under voltage lockout protection.

Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also solve other

problems such as minimizing the effect of high-frequency switching noise (by placing the high-current driver

device physically close to the power switch), driving gate-drive transformers and controlling floating power device

gates. This helps reduce power dissipation and thermal stress in controllers by moving gate charge power losses

from the controller IC to the gate driver.

UCC27282 gate drivers offer high voltage (100 V), small delays (16 ns), and good driving capability (2.5 A/3.5 A)

in a single device. The floating high-side driver is capable of operating with switch node voltages up to 100 V.

This allows for N-channel MOSFETs control in half-bridge, full-bridge, synchronous buck, synchronous boost,

and active clamp topologies. UCC27282 gate driver IC also has built-in bootstrap diode to help power supply

designers optimize PWB area and to help reduce bill of material cost in most applications. The driver has an

enable/disable functionality to be used in applications where driver needs to be enabled or disabled based on

fault condition in other parts of the circuit. Interlock functionality of the device is very useful in applications where

overall reliability of the system is of utmost criteria and redundant protection is desired. Each channel is

controlled by its respective input pins (HI and LI), allowing flexibility to control ON and OFF state of the output.

Both the outputs are forced OFF when the two inputs overlap.

Switching power devices such as MOSFETs have two main loss components; switching losses and conduction

losses. Conduction loss is dominated by current through the device and ON resistance of the device. Switching

losses are dominated by gate charge of the switching device, gate voltage of the switching device, and switching

frequency. Applications where operating switching frequency is very high, the switching losses start to

significantly impact overall system efficiency. In such applications, to reduce the switching losses it becomes

essential to reduce the gate voltage. The gate voltage is determined by the supply voltage the gate driver ICs,

therefore, the gate driver IC needs to operate at lower supply voltage in such applications. UCC27282 gate driver

has typical UVLO level of 5V and therefore, they are perfectly suitable for such applications. There is enough

UVLO hysteresis provided to avoid any chattering or nuisance tripping which improves system robustness.

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8.2 Typical Application

7 V

75 V

VDD

SECONDARY

SIDE

CIRCUIT

DRIVE

PWM

CONTROLLER

DRIVE

UCC27282

ISOLATION

AND

FEEDBACK

Figure 33. Typical Application

8.2.1 Design Requirements

Table below lists the system parameters. UCC27282 needs to operate satisfactorily in conjunction with them.

Table 4. Design Requirements

Parameter

MOSFET

Value

CSD19535KTT

75V

Maximum Bus/Input Voltage, V_in

Operating Bias Votage, V_DD

Switching Frequency, Fsw

Total Gate Charge of FET at given VDD, Q_G

300kHz

52nC

MOSFET Internal Gate Resistance,

R_{GFET_Int}

1.4

Maximum Duty Cycle, D_Max

Gate Driver

0.5

UCC27282

8.2.2 Detailed Design Procedure

8.2.2.1 Select Bootstrap and VDD Capacitor

The bootstrap capacitor must maintain the V_HB-HSvoltage above the UVLO threshold for normal operation.

Calculate the maximum allowable drop across the bootstrap capacitor, ΔV_HB, with Equation 1.

¿V_HB= V_DDF V_DHF V_HBL

;

= 7 V ꢀ 1 V ꢀ (4.4 V ꢀ 0.37 V) = 1.97 V

where

•

V_DDis the supply voltage of gate driver device

V_DHis the bootstrap diode forward voltage drop

V_HBLis the HB falling threshold ( V_HBR(max)– V_HBH

)

(1)

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In this example the allowed voltage drop across bootstrap capacitor is 1.97 V.

It is generally recommended that ripple voltage on both the bootstrap capacitor and VDD capacitor should be

minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value of

0.5 V.

Use Equation 2 to estimate the total charge needed per switching cycle from bootstrap capacitor.

D_MAX

I_HB

Q_TOTAL= Q_G+ I_HBS× l

p + l

f_SW

= 52 nC + 0.083 nC + 1.33 nC = 53.41 nC

where

•

Q_Gis the total MOSFET gate charge

I_HBSis the HB to VSS leakage current from datasheet

D_Maxis the converter maximum duty cycle

I_HBis the HB quiescent current from the datasheet

(2)

(3)

The caculated total charge is 53.41 nC.

Next, use Equation 3 to estimate the minimum bootstrap capacitor value.

Q_TOTAL

53.41 nC

1.97 V

C_{BOOT min}

;

= 27.11 nF

¿V_HB

The calculated value of minimum bootstrap capacitor is 27.11 nF. It should be noted that, this value of

capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than

calculated value to allow for situations where the power stage may skip pulse due to various transient conditions.

It is recommended to use a 100-nF bootstrap capacitor in this example. It is also recommenced to include

enough margin and place the bootstrap capacitor as close to the HB and HS pins as possible. Also place a small

size, 0402, low value, 1000 pF, capacitor to filter high frequency noise, in parallel with main bypass capacitor.

For this application, choose a C_BOOTcapacitor that has the following specifications: 0.1 µF, 25 V, X7R

As a general rule the local VDD bypass capacitor must be greater than the value of bootstrap capacitor value

(generally 10 times the bootstrap capacitor value). For this application choose a C_VDDcapacitor with the following

specifications: 1 µF , 25 V, X7R

C_VDDcapacitor is placed across VDD and VSS pin of the gate driver. Similar to bootstrap capacitors, place a

small size and low value capacitor in parallel with the main bypass capacitor. For this application, choose 0402,

1000 pF, capacitance in parallel with main bypass capacitor to filter high frequency noise.

The bootstrap and bias capacitors must be ceramic types with X7R dielectric or better. Choose a capacitor with a

voltage rating at least twice the maximum voltage that it will be exposed to. Choose this value because most

ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of

the system.

8.2.2.2 Estimate Driver Power Losses

The total power loss in gate driver device such as the UCC27282 is the summation of the power loss in different

functional blocks of the gate driver device. These power loss components are explained in this section.

1. Equation 4 describes how quiescent currents (I_DDand I_HB) affect the static power losses, P_QC

;

P_QC= V_DD× I_DD+ V_DDF V_DH× I_HB

= 7 V × 0.4 mA + 6 V × 0.4 mA = 5.2 mW

(4)

it is not shown here, but for better approximation, add no load operating current, I_DDOand I_HBOin above

equation.

2. Equation 5 shows how high-side to low-side leakage current (I_HBS) affects level-shifter losses (P_IHBS).

IHBS

= V_HB× I_HBS× D = 82 V × 50 µA × 0.5 = 2.05 mW

where

•

D is the high-side MOSFET duty cycle

V_HBis the sum of input voltage and voltage across bootstrap capacitor.

(5)

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3. Equation 6 shows how MOSFETs gate charge (Q_G) affects the dynamic losses, P_QG

R_{GD _R}

P_QG= 2 × V_DD× Q_G× f_SW

R_{GD _R}+ R_GATE+ R_{GFET int}

;

= 2

× 7

V × 52

nC × 300

kHz × 0.74

= 0.16

where

•

Q_Gis the total MOSFET gate charge

f_SWis the switching frequency

R_{GD_R}is the average value of pullup and pulldown resistor

R_GATEis the external gate drive resistor

R_GFET(int)is the power MOSFETs internal gate resistor

(6)

Assume there is no external gate resistor in this example. The average value of maximum pull-up and pull

down resistance of the driver output section is approximately 4 Ω. Substitute the application values to

calculate the dynamic loss due to gate charge, which is 160 mW here.

4. Equation 7 shows how parasitic level-shifter charge (Q_P) on each switching cycle affects dynamic losses,

(P_LS) during high-side switching.

P = V_HB× Q_P× f_SW

(7)

For this example and simplicity, it is assumed that value of parasitic charge Q_Pis 1 nC. Substituting values

results in 24.6 mW as level shifter dynamic loss. This estimate is very high for level shifter dynamic losses.

The sum of all the losses is 191.85 mW as a total gate driver loss. As shown in this example, in most

applications the dynamic loss due to gate charge dominates the total power loss in gate driver device. For gate

drivers that include bootstrap diode, one should also estimate losses in bootstrap diode. Diode forward

conduction loss is computed as product of average forward voltage drop and average forward current.

Equation 8 estimates the maximum allowable power loss of the device for a given ambient temperature.

kT F T_Ao

P_MAX

R_EJA

where

•

P_MAXis the maximum allowed power dissipation in the gate driver device

T_Jis the recommended maximum operating junction temperature

T_Ais hte ambient temperature of the gate driver device

R_θJAis the junction-to-ambient thermal resistance

(8)

To better estimate the junction temperature of the gate driver device in the application, it is recommended to first

accurately measure the case temperature and then determine the power dissipation in a given application. Then

use ψ_JTto calculate junction temperature. After estimating junction temperature and measuring ambient

temperature in the application, calculate θ_{JA(effective)}. Then, if design parameters (such as the value of an external

gate resistor or power MOSFET) change during the development of the project, use θ_{JA(effective)}to estimate how

these changes affect junction temperature of the gate driver device.

For detailed information regarding the thermal information table, please refer to the Semiconductor and Device

Package Thermal Metrics application report.

8.2.2.3 Selecting External Gate Resistor

In high-frequency switching power supply applications where high-current gate drivers such as the UCC27282

are used, parasitic inductances, parasitic capacitances and high-current loops can cause noise and ringing on

the gate of power MOSFETs. Often external gate resistors are used to damp this ringing and noise. In some

applications the gate charge, which is load on gate driver device, is significantly larger than gate driver peak

output current capability. In such applications external gate resistors can limit the peak output current of the gate

driver. it is recommended that there should be provision of external gate resistor whenever the layout or

application permits.

Use Equation 9 to calculate the driver high-side pull-up current.

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V_DDF V_DH

R_HOH+ R_GATE+ R_{GFET int}

I_OHH

;

where

•

I_OHHis the high-side, peak pull-up current

V_DHis the bootstrap diode forward voltage drop

R_HOHis the gate driver internal high-side pull-up resistor. Value either directly provided in datasheet or can be

calculated from test conditions (R_HOH= V_HOH/I_HO

)

•

R_GATEis the external gate resistance connected between driver output and power MOSFET gate

R_GFET(int)is the MOSFET internal gate resistance provided by MOSFET datasheet

(9)

(10)

(11)

(12)

Use Equation 10 to calculate the driver high-side sink current.

V_DDF V_DH

I_OLH

R_HOL+ R_GATE+ R_{GFET int}

;

where

•

R_HOLis the gate driver internal high-side pull-down resistance

Use Equation 11 to calculate the driver low-side source current.

V_DD

I_OHL

R_LOH+ R_GATE+ R_{GFET int}

;

where

•

R_LOHis the gate driver internal low-side pull-up resistance

Use Equation 12 to calculate the driver low-side sink current.

V_DD

I_OLL

R_LOL+ R_GATE+ R_{GFET int}

;

where

•

R_LOLis the gate driver internal low-side pull-down resistance

Typical peak pull up and pull down current of the device is 2.5 A and 3.5 A respectively. These equations help

reduce the peak current if needed. To establish different rise time value compared to fall time value, external

gate resistor can be anti-paralleled with diode-resistor combination as shown in Figure 33. Generally selecting an

optimal value or configuration of external gate resistor is an iterative process. For additional information on

selecting external gate resistor please refer to External Gate Resistor Design Guide for Gate Drivers

8.2.2.4 Delays and Pulse Width

The total delay encountered in the PWM, driver and power stage need to be considered for a number of reasons,

primarily delay in current limit response. Also to be considered are differences in delays between the drivers

which can lead to various concerns depending on the topology. The synchronous buck topology switching

requires careful selection of dead-time between the high-side and low-side switches to avoid cross conduction as

well as excessive body diode conduction.

Bridge topologies can be affected by a volt-second imbalance on the transformer if there is imbalance in the

high-side and low-side pulse widths in any operating condition. The UCC27282 device has maximum

propagation delay, across process, and temperature variation, of 30 ns and delay matching of 7 ns, which is one

of the best in the industry.

Narrow input pulse width performance is an important consideration in gate driver devices, because output may

not follow input signals satisfactorily when input pulse widths are very narrow. Although there may be relatively

wide steady state PWM output signals from controller, very narrow pulses may be encountered under following

operating conditions.

•

soft-start period

large load transients

short circuit conditions

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These narrow pulses appear as an input signal to the gate driver device and the gate driver device need to

respond properly to these narrow signals.

Figure 34 shows that the UCC27282 device produces reliable output pulse even when the input pulses are very

narrow and bias voltages are very low. The propagation delay and delay matching do not get affected when the

input pulse width is very narrow.

HI (2V/div)

BW=1GHz

LI (2V/div)

BW=1GHz

LO (5V/div)

BW=1GHz

HO (5V/div)

BW=1GHz

Figure 34. Input and Output Pulse Width

8.2.2.5 External Bootstrap Diode

The UCC27282 incorporates the bootstrap diode necessary to generate the high-side bias for HO to work

satisfactorily. The characteristics of this diode are important to achieve efficient, reliable operation. The

characteristics to consider are forward voltage drop and dynamic resistance. Generally, low forward voltage drop

diodes are preferred for low power loss during charging of the bootstrap capacitor. The device has a boot diode

forward voltage drop rated at 0.85 V and dynamic resistance of 1.5 Ω for reliable charge transfer to the bootstrap

capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery

times that are specified without operating conditions, can be misleading. Diode recovery times at no forward

current (I_F) can be noticeably less than with forward current applied. The UCC27282 boot diode recovery is

specified as 50 ns at I_F= 20 mA, I_REV= 0.5 A. Dynamic impedance of UCC27282 bootstrap diode naturally limits

the peak forward current and prevents any damage if repetitive peak forward current pulses exist in the system

for most applications.

In applications where switching frequencies are very high, for example in excess of 1 MHz, and the low-side

minimum pulse widths are very small, the diode peak forward current could be very high and peak reverse

current could also be very high, specifically if high bootstrap capacitor value has been chosen. In such

applications it might be advisable to use external Schottkey diode as bootstrap diode. It is safe to at least make a

provision for such diode on the board if possible.

8.2.2.6 VDD and Input Filter

Some switching power supply applications are extremely noisy. Noise may come from ground bouncing and

ringing at the inputs, (which are the HI and LI pins of the gate driver device). To mitigate such situations, the

UCC27282 offers both negative input voltage handling capability and wide input threshold hysteresis. If these

features are not enough, then the application might need an input filter. Small filter such as 10-Ω resistor and 47-

pF capacitor might be sufficient to filter noise at the inputs of the gate driver device. This RC filter would

introduce delay and therefore need to be considered carefully. High frequency noise on bias supply can cause

problems in performance of the gate driver device. To filter this noise it is recommended to use 1-Ω resistor in

series with VDD pin as shown in Figure 33. This resistor also acts as a current limiting element. In the event of

short circuit on the bias rail, this resistor opens up and prevents further damage. This resistor can also be helpful

in debugging the design during development phase.

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8.2.2.7 Transient Protection

As mentioned in previous sections, high power high switching frequency power supplies are inherently noisy.

High dV/dt and dI/dt in the circuit can cause negative voltage on different pins such as HO, LO, and HS. The

device tolerates negative voltage on all of these pins as mentioned in specification tables. If parasitic elements of

the circuit cause very large negative swings, circuit might require additional protection. In such cases fast acting

and low leakage type Schottky diode should be used. This diode must be placed as close to the gate driver

device pin as possible for it to be effective in clamping excessive negative voltage on the gate driver device pin.

Sometimes a small resistor, (for example 2 Ω, in series with HS pin) is also effective in improving performance

reliability. To avoid the possibility of driver device damage due to over-voltage on its output pins or supply pins,

low leakage Zener diode can be used. A 15-V Zener diode is often sufficient to clamp the voltage below the

maximum recommended value of 16 V.

8.2.3 Application Curves

To minimize the switching losses in power supplies, turn-ON and turn-OFF of the power MOSFETs need to be

as fast as possible. Higher the drive current capability of the driver, faster the switching. Therefore, the

UCC27282 is designed with high drive current capability and low resistance of the output stages. One of the

common way to test the drive capability of the gate driver device , is to test it under heavy load. Rise time and

fall time of the outputs would provide idea of drive capability of the gate driver device. There must not be any

resistance in this test circuit. Figure 35 and Figure 36 shows rise time and fall time of HO respectively of

UCC27282. Figure 37 and Figure 38 shows rise time and fall time of LO respectively of UCC27282. For accuracy

purpose, the VDD and HB pin of the gate driver device were connected together. HS and VSS pins are also

connected together for this test.

Peak current capability can be estimated using the fastest dV/dt along the rise and fall curve of the plot. This

method is also useful in comparing performance of two or more gate driver devices.

As explained in Delays and Pulse Width, propagation delay plays an important role in reliable operation of many

applications. Figure 39 and Figure 40

Figure 40 shows propagation delay and delay matching of UCC27282. In many switching power supply

applications input signals to the gate driver have large amplitude high frequency noise. If there is no filter

employed at the input, then there is a possibility of false signal passing through the gate driver and causing

shoot-through on the output. UCC27282 prevents such shoot-through. If two inputs are high at the same time,

UCC27282 shuts both the outputs off. Figure 41 shows interlock feature of UCC27282 and Figure 42 shows

input negative voltage handling capability of UCC27282.

V_DD= V_HB=6 V, HS =

VSS

C_LOAD= 10

Ch4 = HO

V_DD= V_HB= 6 V, HS =

VSS

C_LOAD= 10

Ch4 = HO

Figure 36. HO Fall Time

Figure 35. HO Rise Time

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V_DD= V_HB= 6 V, HS =

VSS

C_LOAD= 10 nF Ch4 = LO

V_DD= V_HB= 6 V, HS = VSS

C_LOAD= 10 nF

Ch4 =

Figure 38. LO Fall Time

Figure 37. LO Rise Time

V_DD= 6 V

C_LOAD= 2

Ch1 = HI Ch2 = LI Ch3 = HO Ch4

= LO

V_DD= 6

C_LOAD= 2 nF

Ch1 = HI Ch2 = LI Ch3 = HO Ch4

= LO

Figure 39. Propagation Delay and Delay Matching

Figure 40. Propagation Delay and Delay Matching

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HI (2V/div)

LI (2V/div)

HO (5V/div)

LO (5V/div)

V_DD= 10 V V_in

100 V

C_L= 1

Ch1 = HI Ch2 = LI Ch3 = HO

Ch4 = LO

V_DD= V_HB= 12 V, HS = VSS

C_LOAD= 0 nF

Figure 41. Input Shoot-through Protection or Interlock

Figure 42. Input Negative Voltage

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9 Power Supply Recommendations

The recommended bias supply voltage range for UCC27282 is from 5.5 V to 16 V. The lower end of this range is

governed by the internal under voltage-lockout (UVLO) protection feature, 5 V typical, of the V_DDsupply circuit

block. The upper end of this range is driven by the 16-V recomended maximum voltage rating of the V_DD. It is

recommended that voltage on VDD pin should be lower than maximum recommended voltage. In some transient

condition it is not possible to keep this voltage below recommended maximum level and therefore absolute

maximum voltage rating of the UCC27282 is 20 V.

The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in

normal mode, if the V_DDvoltage drops, the device continues to operate in normal mode as far as the voltage

drop do not exceeds the hysteresis specification, V_DDHYS. If the voltage drop is more than hysteresis

specification, the device shuts down. Therefore, while operating at or near the 5.5-V range, the voltage ripple on

the auxiliary power supply output should be smaller than the hysteresis specification of UCC27282 to avoid

triggering device shutdown.

A local bypass capacitor should be placed between the VDD and GND pins. This capacitor should be located as

close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is

recommended to use two capacitors across VDD and GND: a low capacitance ceramic surface-mount capacitor

for high frequency filtering placed very close to VDD and GND pin, and another high capacitance value surface-

mount capacitor for device bias requirements. In a similar manner, the current pulses delivered by the HO pin are

sourced from the HB pin. Therefore, two capacitors across the HB to HS are recommended. One low value small

size capacitor for high frequency filtering and another one high capacitance value capacitor to deliver HO pulses.

UCC27282 has enable/disable functionality through EN pin. Therefore, signal at the EN pin should be as clean

as possible. If EN pin is not used, then it is recommended to connect the pin to VDD pin. If EN pin is pulled up

through a resistor, then the pull-up resistor needs to be strong. In noise prone applications, it is recommended to

filter the EN pin with small capacitor, such as X7R 0402 1nF.

In power supplies where noise is very dominant and there is space on the PWB (Printed Wiring Board), it is

recommended to place a small RC filter at the inputs. This allows for improving the overall performance of the

design. In such applications. it is also recommended to have a place holder for power MOSFET external gate

resistor. This resistor allows the control of not only the drive capability but also the slew rate on HS, which

impacts the performance of the high-side circuit. If diode is used across the external gate resistor, it is

recommended to use a resistor in series with the diode, which provides further control of fall time.

In power supply applications such as motor drives, there exist lot of transients through-out the system. This

sometime causes over voltage and under voltage spikes on almost all pins of the gate driver device. To increase

the robustness of the design, it is recommended that the clamp diode should be used on HO and LO pins. If user

does not wish to use power MOSFET parasitic diode, external clamp diode on HS pin is recommended, which

needs to be high voltage high current type (same rating as MOSFET) and very fast acting. The leakage of these

diodes across the temperature needs to be minimal.

In power supply applications where it is almost certain that there is excessive negative HS voltage, it is

recommended to place a small resistor between the HS pin and the switch node. This resistance helps limit

current into the driver device up to some extent. This resistor will impact the high side drive capability and

therefore needs to be considered carefully.

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10 Layout

10.1 Layout Guidelines

To achieve optimum performance of high-side and low-side gate drivers, one must consider following printed

wiring board (PWB) layout guidelines.

•

Low ESR/ESL capacitors must be connected close to the device between VDD and VSS pins and between

HB and HS pins to support high peak currents drawn from VDD and HB pins during the turn-on of the

external MOSFETs.

•

To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a

good quality ceramic capacitor must be connected between the high side MOSFET drain and ground (VSS).

In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between the

source of the high-side MOSFET and the source of the low-side MOSFET (synchronous rectifier) must be

minimized.

•

Overlapping of HS plane and ground (VSS) plane should be minimized as much as possible so that coupling

of switching noise into the ground plane is minimized.

Thermal pad should be connected to large heavy copper plane to improve the thermal performance of the

device. Generally it is connected to the ground plane which is the same as VSS of the device. It is

recommended to connect this pad to the VSS pin only.

•

Grounding considerations:

–

The first priority in designing grounding connections is to confine the high peak currents that charge and

discharge the MOSFET gates to a minimal physical area. This confinement decreases the loop inductance

and minimize noise issues on the gate terminals of the MOSFETs. Place the gate driver as close to the

MOSFETs as possible.

–

The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap

diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The

bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground

referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak

current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.

10.2 Layout Example

VSS Plane

(Top and Bottom Layer)

Input Filters

(Top Layer)

Input PWMs

VDD Capacitors

(Top Layer)

To Low Side

MOSFET

Figure 43. Layout Example

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11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.2 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

E2E is a trademark of Texas Instruments.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

12-Sep-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PUCC27282DR

UCC27282D

ACTIVE

SOIC

2500

TBD

Call TI

-40 to 125

Green (RoHS

& no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

U282

UCC27282DR

UCC27282DRCR

UCC27282DRCT

ACTIVE

SOIC

VSON

2500

3000

250

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

-40 to 125

DRC

Green (RoHS

& no Sb/Br)

U27282

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

12-Sep-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC27282 :

Automotive: UCC27282-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Sep-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC27282DR

UCC27282DRCR

UCC27282DRCT

SOIC

VSON

2500

3000

250

330.0

180.0

12.5

12.4

6.4

3.3

5.2

3.3

2.1

1.1

8.0

12.0

DRC

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Sep-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC27282DR

UCC27282DRCR

UCC27282DRCT

SOIC

VSON

2500

3000

250

340.5

367.0

210.0

338.1

367.0

185.0

20.6

35.0

DRC

Pack Materials-Page 2

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

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EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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GENERIC PACKAGE VIEW

DRC 10

3 x 3, 0.5 mm pitch

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226193/A

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PACKAGE OUTLINE

DRC0010J

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

1.65 0.1

2X (0.5)

(0.2) TYP

EXPOSED

THERMAL PAD

4X (0.25)

SYMM

2.4 0.1

8X 0.5

0.30

0.18

10X

SYMM

PIN 1 ID

0.1

C A B

(OPTIONAL)

0.05

0.5

0.3

10X

4218878/B 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DRC0010J

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

10X (0.24)

(2.4)

(3.4)

SYMM

(0.95)

8X (0.5)

(R0.05) TYP

(

0.2) VIA

TYP

(0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218878/B 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DRC0010J

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

EXPOSED METAL

TYP

10X (0.6)

(1.53)

10X (0.24)

(1.06)

SYMM

(0.63)

8X (0.5)

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4218878/B 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

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warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

UCC27282 [TI]

相关型号：

UCC27282-Q1

UCC27282-Q1-V02

UCC27282-Q1_V03

UCC27282D

UCC27282DR

UCC27282DRCR

UCC27282DRCT

UCC27282DRMR

UCC27282QDDAQ1

UCC27282QDDARQ1

UCC27282QDQ1

UCC27282QDRCRQ1