UCC27211A-Q1 [TI]
具有 8V UVLO 和负电压处理能力的汽车类 4A、120V 半桥栅极驱动器;
| 型号： | UCC27211A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 8V UVLO 和负电压处理能力的汽车类 4A、120V 半桥栅极驱动器 栅极驱动 驱动器 |
| 文件： | 总29页 (文件大小：2173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC27211A-Q1
ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
UCC27211A-Q1 120V 升压 4A 峰值电流的高频高侧和低侧驱动器
1 特性
2 应用
1
•
适用于汽车电子 应用
•
•
•
•
•
•
•
针对电信，数据通信和商用的电源
•
具有符合 AEC-Q100 标准的下列结果：
半桥和全桥转换器
推挽转换器
–
器件温度等级：–40°C 至 +140°C 的工作环境
温度范围
高电压同步降压型转换器
两开关正激式转换器
有源箝位正激式转换器
D 类音频放大器
–
–
器件人体放电模式 (HBM) 分类等级 2
器件组件充电模式 (CDM) 分类等级 C6
•
可通过独立输入驱动两个采用高侧/低侧配置的 N
沟道金属氧化物半导体场效应晶体管 (MOSFET)
3 说明
•
•
•
•
最大引导电压 120V 直流
4A 吸收，4A 源输出电流
0.9Ω 上拉和下拉电阻
UCC27211A-Q1 器件驱动器基于广受欢迎的
UCC27201 MOSFET 驱动器；但该器件相比之下具有
显著的性能提升。
输入引脚能够耐受 –10V 至 +20V 的电压，并且与
电源电压范围无关
峰值输出上拉和下拉电流已经被提高至 4A 拉电流和
4A 灌电流，并且上拉和下拉电阻已经被减小至 0.9Ω，
因此可以在 MOSFET 的米勒效应平台转换期间用尽可
能小的开关损耗来驱动大功率 MOSFET。输入结构能
够直接处理 -10 VDC，这提高了稳健耐用性，并且无
需使用整流二极管即可实现与栅极驱动变压器的直接对
接。此输入与电源电压无关，并且具有 20V 的最大额
定值。
•
•
•
TTL 兼容输入
8V 至 17V VDD 运行范围（绝对最大值 20V）
7.2ns 上升时间和 5.5ns 下降时间（采用 1000pF
负载时）
•
•
•
•
•
快速传播延迟时间（典型值 20ns）
4ns 延迟匹配
用于高侧和低侧驱动器的对称欠压锁定功能
采用行业标准 SO-PowerPAD SOIC-8 封装
－40℃ 至 +140°C 的额定温度范围
器件信息(1)
器件型号
封装
封装尺寸（标称值）
小外形尺寸 (SO)
PowerPAD™(8)
UCC27211A-Q1
4.89mm × 3.90mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
典型应用图
传播延迟与电源电压间的关系
(T = 25°C)
12 V
100 V
32
28
24
20
16
12
SECONDARY
SIDE
CIRCUIT
VDD
HB
HI
LI
DRIVE
HI
HO
HS
PWM CONTROLLER
LO
DRIVE
LO
UCC27211A-Q1
VSS
TDLRR
TDLFF
8
TDHRR
TDHFF
4
0
ISOLATION AND
FEEDBACK
8
12
16
20
Supply Voltage (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCG0
UCC27211A-Q1
ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
目录
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Switching Characteristics.......................................... 6
7.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 11
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
11.3 Thermal Considerations........................................ 19
12 器件和文档支持 ..................................................... 20
12.1 文档支持................................................................ 20
12.2 社区资源................................................................ 20
12.3 商标....................................................................... 20
12.4 静电放电警告......................................................... 20
12.5 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 20
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2016 年 1 月
*
最初发布。
5 说明 （续）
UCC27211A-Q1 的开关节点（HS 引脚）最高可处理 –18V 电压，从而保护高侧通道不受寄生电感和杂散电容所固
有的负电压影响。UCC27211A-Q1 已经增加了滞后特性，从而使得用于模拟或数字脉宽调制 (PWM) 控制器的接口
具有增强的抗扰度。
低端和高端栅极驱动器是独立控制的，并在彼此的接通和关断之间实现了至 2ns 的匹配。
由于在芯片上集成了一个额定电压为 120V 的自举二极管，因此无需采用外部分立式二极管。高侧和低侧驱动器均
配有欠压锁定功能，可提供对称的导通和关断行为，并且能够在驱动电压低于指定阈值时将输出强制为低电平。
UCC27211A-Q1 器件采用 8 引脚 SO-PowerPAD 封装。
2
Copyright © 2015–2016, Texas Instruments Incorporated
UCC27211A-Q1
www.ti.com.cn
ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
6 Pin Configuration and Functions
DDA Package
8-Pin SO-PowerPAD
Top View
VDD
HB
1
2
3
4
8
7
6
5
LO
VSS
LI
Thermal
Pad
HO
HS
HI
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is
required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass
capacitor is 0.022 µF to 0.1 µF. The capacitor value is dependant on the gate charge of the high-
side MOSFET and must also be selected based on speed and ripple criteria.
HB
2
P
HI
5
3
I
High-side input.(1)
HO
O
High-side output. Connect to the gate of the high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect the
negative side of bootstrap capacitor to this pin.
HS
4
P
LI
6
8
I
Low-side input.(1)
LO
O
Low-side output. Connect to the gate of the low-side power MOSFET.
Positive supply to the lower-gate driver. De-couple this pin to VSS (GND). Typical decoupling
capacitor range is 0.22 µF to 4.7 µF (See (2)).
VDD
1
7
P
VSS
—
—
Negative supply terminal for the device that is generally grounded.
Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to
dramatically improve thermal performance.
Thermal pad(3)
(1) HI or LI input is assumed to connect to a low impedance source signal. The source output impedance is assumed less than 100 Ω. If the
source impedance is greater than 100 Ω, add a bypassing capacitor, each, between HI and VSS and between LI and VSS. The added
capacitor value depends on the noise levels presented on the pins, typically from 1 nF to 10 nF should be effective to eliminate the
possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic
outputs.
(2) For cold temperature applications TI recommends the upper capacitance range. Follow the Layout Guidelines for PCB layout.
(3) The thermal pad is not directly connected to any leads of the package; however, it is electrically and thermally connected to the
substrate which is the ground of the device.
Copyright © 2015–2016, Texas Instruments Incorporated
3
UCC27211A-Q1
ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
(2)
VDD
,
Supply voltage range
–0.3
20
VHB – VHS
VLI, VHI
Input voltages on LI and HI
–10
–0.3
20
VDD + 0.3
VDD + 0.3
VHB + 0.3
VHB + 0.3
115
V
DC
VLO
VHO
VHS
Output voltage on LO
Output voltage on HO
Voltage on HS
V
V
V
Repetitive pulse < 100 ns(3)
–2
DC
VHS – 0.3
VHS – 2
–1
Repetitive pulse < 100 ns(3)
DC
Repetitive pulse < 100 ns(3)
–(24 V – VDD)
–0.3
115
VHB
TJ
Voltage on HB
120
V
Operating virtual junction temperature range
Storage temperature
–40
150
°C
°C
TSTG
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to VSS unless otherwise noted. Currents are positive into and negative out of the specified terminal.
(3) Verified at bench characterization. VDD is the value used in an application design.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC
±2000
V(ESD)
Electrostatic discharge
V
All pins
±1500
Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
all voltages are with respect to VSS; currents are positive into and negative out of the specified terminal. –40°C < TJ = TA <
140°C (unless otherwise noted)
MIN
NOM
MAX UNIT
VDD, VHB
VHS
–
Supply voltage range
8
12
17
V
VHS
VHS
Voltage on HS
–1
105
110
V
V
Voltage on HS (repetitive pulse < 100 ns)
–(24 V – VDD)
VHS + 8,
VDD – 1
VHS + 17,
115
VHB
Voltage on HB
V
Voltage slew rate on HS
50
V/ns
°C
Operating junction temperature
–40
140
4
Copyright © 2015–2016, Texas Instruments Incorporated
UCC27211A-Q1
www.ti.com.cn
ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
7.4 Thermal Information
UCC27211A-Q1
THERMAL METRIC(1)
DDA (SO-PowerPAD)
UNIT
8 PINS
37.7
47.2
9.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.8
ψJB
9.4
RθJC(bot)
3.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
VDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = –40°C to 140°C, (unless otherwise noted)
PARAMETER
SUPPLY CURRENTS
TEST CONDITION
MIN
TYP
MAX UNIT
IDD
VDD quiescent current
V(LI) = V(HI) = 0 V
0.05
2.1
0.085
2.5
0.17
6.5
0.1
5.1
1
mA
mA
mA
mA
µA
IDDO
IHB
VDD operating current
f = 500 kHz, CLOAD = 0
V(LI) = V(HI) = 0 V
Boot voltage quiescent current
Boot voltage operating current
HB to VSS quiescent current
HB to VSS operating current
0.015
1.5
0.065
2.5
IHBO
IHBS
IHBSO
INPUT
VHIT
VLIT
f = 500 kHz, CLOAD = 0
V(HS) = V(HB) = 115 V
f = 500 kHz, CLOAD = 0
0.0005
0.07
1.2
mA
Input voltage threshold
Input voltage threshold
Input voltage hysteresis
Input pulldown resistance
1.7
1.2
2.3
1.6
700
68
2.55
1.9
V
V
VIHYS
RIN
mV
kΩ
UNDER-VOLTAGE LOCKOUT (UVLO)
VDDR VDD turnon threshold
VDDHYS Hysteresis
6.2
5.6
7
0.5
6.7
1.1
7.8
7.9
V
V
V
V
VHBR
VHB turnon threshold
VHBHYS Hysteresis
BOOTSTRAP DIODE
VF
Low-current forward voltage
IVDD-HB = 100 µA
0.65
0.85
0.5
0.8
0.95
0.85
V
V
Ω
VFI
RD
High-current forward voltage
IVDD-HB = 100 mA
Dynamic resistance, ΔVF/ΔI
IVDD-HB = 100 mA and 80 mA
0.3
LO GATE DRIVER
VLOL
VLOH
Low-level output voltage
ILO = 100 mA
0.05
0.1
0.1
0.16
3.7
0.19
0.29
V
V
A
A
High level output voltage
Peak pullup current(1)
Peak pulldown current(1)
ILO = –100 mA, VLOH = VDD – VLO
VLO = 0 V
VLO = 12 V
4.5
HO GATE DRIVER
VHOL
VHOH
Low-level output voltage
IHO = 100 mA
0.05
0.1
0.1
0.16
3.7
0.19
0.29
V
V
A
A
High-level output voltage
Peak pullup current(1)
Peak pulldown current(1)
IHO = –100 mA, VHOH = VHB – VHO
VHO = 0 V
VHO = 12 V
4.5
(1) Ensured by design.
Copyright © 2015–2016, Texas Instruments Incorporated
5
UCC27211A-Q1
ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PROPAGATION DELAYS
TDLFF
TDHFF
TDLRR
TDHRR
VLI falling to VLO falling
CLOAD = 0
CLOAD = 0
CLOAD = 0
CLOAD = 0
10
10
10
10
16
16
20
20
30
30
42
42
ns
ns
ns
ns
VHI falling to VHO falling
VLI rising to VLO rising
VHI rising to VHO rising
DELAY MATCHING
TJ = 25°C
4
4
4
4
9.5
17
ns
ns
ns
ns
TMON
From HO OFF to LO ON
TJ = –40°C to 140°C
TJ = 25°C
9.5
17
TMOFF
From LO OFF to HO ON
TJ = –40°C to 140°C
OUTPUT RISE AND FALL TIME
tR
tR
tF
tF
tR
tF
LO rise time
HO rise time
LO fall time
HO fall time
LO, HO
CLOAD = 1000 pF, from 10% to 90%
CLOAD = 1000 pF, from 10% to 90%
CLOAD = 1000 pF, from 90% to 10%
CLOAD = 1000 pF, from 90% to 10%
CLOAD = 0.1 µF, (3 V to 9 V)
7.2
7.2
ns
ns
ns
ns
µs
µs
5.5
5.5
0.36
0.15
0.6
0.4
LO, HO
CLOAD = 0.1 µF, (9 V to 3 V)
MISCELLANEOUS
Minimum input pulse width that changes the
output
Bootstrap diode turnoff time(1)(2)
50
ns
ns
IF = 20 mA, IREV = 0.5 A(3)
20
(1) Ensured by design.
(2) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
(3) Typical values for TA = 25°C.
LI
Input
(HI, LI)
HI
T
DLRR, TDHRR
LO
Output
(HO, LO)
T
DLFF, TDHFF
HO
T
MON
T
MOFF
Figure 1. Timing Diagram
6
Copyright © 2015–2016, Texas Instruments Incorporated
UCC27211A-Q1
www.ti.com.cn
ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
7.7 Typical Characteristics
100
80
60
40
20
0
100
10
1
CL = 0 pF, T = −40°C
CL = 0 pF, T = 25°C
0.1
0.01
CL = 0 pF, T = 140°C
CL = 1000 pF, T = 25°C
CL = 1000 pF, T = 140°C
CL = 4700 pF, T = 140°C
IDD
IHB
0
2
4
6
8
10
12
14
16
18
20
10
100
Frequency (kHz)
1000
Supply Voltage (V)
G002
T = 25°C
VDD = 12 V
Figure 2. Quiescent Current vs Supply Voltage
Figure 3. IDD Operating Current vs Frequency
100
10
100
10
1
1
CL = 0 pF, T = −40°C
CL = 0 pF, T = 25°C
CL = 0 pF, T = −40°C
CL = 0 pF, T = 25°C
0.1
0.01
CL = 0 pF, T = 140°C
CL = 1000 pF, T = 25°C
CL = 1000 pF, T = 140°C
CL = 4700 pF, T = 140°C
0.1
0.01
CL = 0 pF, T = 140°C
CL = 1000 pF, T = 25°C
CL = 1000 pF, T = 140°C
CL = 4700 pF, T = 140°C
10
100
Frequency (kHz)
1000
10
100
Frequency (kHz)
1000
VDD = 12 V
VHB – VHS = 12 V
Figure 4. IDD Operating Current vs Frequency
Figure 5. Boot Voltage Operating Current vs
Frequency (HB To HS)
6
5
6
5
4
4
3
3
2
2
1
1
0
0
Rising
Falling
Rising
Falling
−1
−1
−40 −20
0
20
40
60
Temperature (°C)
80
100 120 140
8
12
16
20
Supply Voltage (V)
VDD = 12 V
Figure 7. Input Thresholds vs Temperature
T = 25°C
Figure 6. Input Threshold vs Supply Voltage
Copyright © 2015–2016, Texas Instruments Incorporated
7
UCC27211A-Q1
ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
www.ti.com.cn
Typical Characteristics (continued)
0.32
0.28
0.24
0.2
0.2
0.16
0.12
0.08
0.04
0
0.16
0.12
VDD = VHB = 8 V
VDD = VHB = 8 V
0.08
0.04
0
VDD = VHB = 12 V
VDD = VHB = 16 V
VDD = VHB = 20 V
VDD = VHB = 12 V
VDD = VHB = 16 V
VDD = VHB = 20 V
−40 −20
0
20
40
Temperature (°C)
60
80
100 120 140
−40 −20
0
20
40
Temperature (°C)
60
80
100 120 140
IHO = ILO = 100 mA
IHO = ILO = 100 mA
Figure 8. LO and HO High-Level Output Voltage
vs Temperature
Figure 9. LO and HO Low-Level Output Voltage
vs Temperature
8
7.6
7.2
6.8
6.4
6
1.5
1.2
0.9
0.6
0.3
0
5.6
5.2
VDD Rising Threshold
HB Rising Threshold
VDD UVLO Hysteresis
HB UVLO Hysteresis
−40 −20
0
20
40
60
80
100 120 140
−40 −20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
G009
G010
Figure 10. Undervoltage Lockout Threshold
vs Temperature
Figure 11. Undervoltage Lockout Threshold Hysteresis
vs Temperature
40
36
32
28
24
20
16
12
8
32
24
16
TDLRR
TDLFF
TDHRR
TDHFF
TDLRR
TDLFF
8
TDHRR
TDHFF
4
0
0
−40 −20
0
20
40
Temperature (°C)
60
80
100 120 140
−40 −20
0
20
40
Temperature (°C)
60
80
100 120 140
VDD = VHB = 12 V
Figure 12. Propagation Delays vs Temperature
VDD = VHB = 12 V
Figure 13. Propagation Delays vs Temperature
8
Copyright © 2015–2016, Texas Instruments Incorporated
UCC27211A-Q1
www.ti.com.cn
ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
Typical Characteristics (continued)
10
8
32
28
24
20
16
12
8
6
4
2
TDLRR
TDLFF
TDHRR
TDHFF
0
TMON
4
TMOFF
−2
0
−40 −20
0
20
40
60
Temperature (°C)
80
100 120 140
8
12
16
20
Supply Voltage (V)
VDD = VHB = 12 V
Figure 15. Delay Matching vs Temperature
T = 25°C
Figure 14. Propagation Delays vs Supply Voltage
(VDD = VHB
)
100
10
5
4
3
2
1
0
Pulldown Current
Pullup Current
1
0.1
0.01
0.001
500
550
600
650
700
750
800
850
0
2
4
6
8
10
12
Diode Voltage (mV)
Output Voltage (V)
G017
G016
VDD = VHB = 12 V
Figure 17. Diode Current vs Diode Voltage
Figure 16. Output Current vs Output Voltage
Copyright © 2015–2016, Texas Instruments Incorporated
9
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8 Detailed Description
8.1 Overview
The UCC2721A-Q1 device represents Texas Instruments’ latest generation of high-voltage gate drivers, which
are designed to drive both the high-side and low-side of N-Channel MOSFETs in a half- and full-bridge or
synchronous-buck configuration. The floating high-side driver can operate with supply voltages of up to 120 V,
which allows for N-Channel MOSFET control in half-bridge, full-bridge, push-pull, two-switch forward, and active
clamp forward converters.
The UCC27211A-Q1 device features 4-A source and sink capability, industry best-in-class switching
characteristics and a host of other features listed in Table 1. These features combine to ensure efficient, robust
and reliable operation in high-frequency switching power circuits.
Table 1. UCC27211A-Q1 Highlights
FEATURE
BENEFIT
High peak current ideal for driving large power MOSFETs with
minimal power loss (fast-drive capability at Miller plateau)
4-A source and sink current with 0.9-Ω output resistance
Increased robustness and ability to handle undershoot and
overshoot can interface directly to gate-drive transformers without
having to use rectification diodes.
Input pins (HI and LI) can directly handle –10 VDC up to 20 VDC
120-V internal boot diode
Provides voltage margin to meet telecom 100-V surge requirements
Allows the high-side channel to have extra protection from inherent
negative voltages caused by parasitic inductance and stray
capacitance
Switch node (HS pin) able to handle –18 V maximum for 100 ns
Robust ESD circuitry to handle voltage spikes
Excellent immunity to large dV/dT conditions
Best-in-class switching characteristics and extremely low-pulse
transmission distortion
18-ns propagation delay with 7.2-ns rise time and 5.5-ns fall time
2-ns (typical) delay matching between channels
Symmetrical UVLO circuit
Avoids transformer volt-second offset in bridge
Ensures high-side and low-side shut down at the same time
Complementary to analog or digital PWM controllers; increased
hysteresis offers added noise immunity
TTL optimized thresholds with increased hysteresis
In the UCC27211A-Q1 device, the high side and low side each have independent inputs that allow maximum
flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal
to the UCC27211A. The UCC27211A is a TTL or logic compatible device. The high-side driver is referenced to
the switch node (HS), which is typically the source pin of the high-side MOSFET and drain pin of the low-side
MOSFET. The low-side driver is referenced to VSS, which is typically ground. The UCC27211A-Q1 functions are
divided into the input stages, UVLO protection, level shift, boot diode, and output driver stages.
10
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8.2 Functional Block Diagram
2
I.
UVLO
3
4
Ih
I{
LEVEL
SHIFT
5
IL
1
ëꢀꢀ
UVLO
[h
8
7
ë{{
6
[L
8.3 Feature Description
8.3.1 Input Stages
The input stages of the UCC27211A-Q1 device have impedance of 70-kΩ nominal and input capacitance is
approximately 2 pF. Pulldown resistance to VSS (ground) is 70 kΩ. The logic level compatible input provides a
rising threshold of 2.3 V and a falling threshold of 1.6 V.
8.3.2 Undervoltage Lockout (UVLO)
The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS
differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified
threshold. The rising VDD threshold is 7 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side
driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is
6.7 V with 1.1-V hysteresis.
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Feature Description (continued)
8.3.3 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.
8.3.4 Boot Diode
The boot diode necessary to generate the high-side bias is included in the UCC27211A-Q1 family of drivers. The
diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the
HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot
diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and
reliable operation.
8.3.5 Output Stages
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and
high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-
side output stage is referenced from VDD to VSS and the high side is referenced from VHB to VHS
.
8.4 Device Functional Modes
The device operates in normal mode and UVLO mode. See the Undervoltage Lockout (UVLO) section for
information on UVLO operation mode. In the normal mode the output state is dependent on states of the HI and
LI pins. Table 2 lists the output states for different input pin combinations.
Table 2. Device Logic Table
HI PIN
LI PIN
HO(1)
LO(2)
L
L
L
H
L
L
L
L
H
L
H
H
H
H
H
H
(1) HO is measured with respect to HS.
(2) LO is measured with respect to VSS.
12
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers, and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
Finally, emerging wide band-gap power device technologies such as GaN based switches, which are capable of
supporting very high switching frequency operation, are driving very special requirements in terms of gate drive
capability. These requirements include operation at low VDD voltages (5 V or lower), low propagation delays and
availability in compact, low-inductance packages with good thermal capability. Gate-driver devices are extremely
important components in switching power, and they combine the benefits of high-performance, low-cost
component count and board-space reduction as well as simplified system design.
9.2 Typical Application
12 V
100 V
SECONDARY
SIDE
VDD
CIRCUIT
HB
HI
LI
DRIVE
HI
HO
HS
PWM CONTROLLER
LO
DRIVE
LO
UCC27211A-Q1
VSS
ISOLATION AND
FEEDBACK
Figure 18. UCC27211A-Q1 Typical Application Diagram
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Typical Application (continued)
12 V
SECONDARY
SIDE
VDD
100 V
CIRCUIT
HB
HI
DRIVE
HI
HO
HS
PWM CONTROLLER
LI
LO
DRIVE
LO
UCC27211A-Q1
VSS
12 V
VDD
100 V
HB
HI
LI
DRIVE
HI
HO
HS
LO
DRIVE
LO
UCC27211A-Q1
Figure 19. UCC27211-Q1 Typical Application Diagram
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Specifications
DESIGN PARAMETER
Supply voltage, VDD
Voltage on HS, VHS
Voltage on HB, VHB
Output current rating, IO
Operating frequency
EXAMPLE VALUE
12 V
0 V to 100 V
12 V to 112 V
–4 A to 4 A
500 kHz
14
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9.2.2 Detailed Design Procedure
9.2.2.1 Input Threshold Type
The UCC27211A-Q1 device has an input maximum voltage range from –10 V to 20 V. This increased robustness
means that both parts can be directly interfaced to gate drive transformers. The UCC27211A-Q1 device features
TTL compatible input threshold logic with wide hysteresis. The threshold voltage levels are low voltage and
independent of the VDD supply voltage, which allows compatibility with both logic-level input signals from
microcontrollers as well as higher-voltage input signals from analog controllers. See the Electrical Characteristics
table for the actual input threshold voltage levels and hysteresis specifications for the UCC27211A-Q1 device.
9.2.2.2 VDD Bias Supply Voltage
The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the
Absolute Maximum Ratings table. However, different power switches demand different voltage levels to be
applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate voltage
may be required for turnon and a negative gate voltage may be required for turnoff, in which case the VDD bias
supply equals the voltage differential. With a wide operating range from 8 V to 17 V, the UCC27211A-Q1 device
can be used to drive a variety of power switches, such as Si MOSFETs, IGBTs, and wide-bandgap power
semiconductors (such as GaN, certain types of which allow no higher than 6 V to be applied to the gate
terminals).
9.2.2.3 Peak Source and Sink Currents
Generally, the switching speed of the power switch during turnon and turnoff should be as fast as possible in
order to minimize switching power losses. The gate driver device must be able to provide the required peak
current for achieving the targeted switching speeds with the targeted power MOSFET. The system requirement
for the switching speed is typically described in terms of the slew rate of the drain-to-source voltage of the power
MOSFET (such as dVDS/dt). For example, the system requirement might state that a SPP20N60C3 power
MOSFET must be turned-on with a dVDS/dt of 20 V/ns or higher with a DC bus voltage of 400 V in a continuous-
conduction-mode (CCM) boost PFC-converter application. This type of application is an inductive hard-switching
application and reducing switching power losses is critical. This requirement means that the entire drain-to-
source voltage swing during power MOSFET turnon event (from 400 V in the OFF state to VDS(on) in on state)
must be completed in approximately 20 ns or less. When the drain-to-source voltage swing occurs, the Miller
charge of the power MOSFET (QGD parameter in the SPP20N60C3 data sheet is 33 nC typical) is supplied by
the peak current of gate driver. According to power MOSFET inductive switching mechanism, the gate-to-source
voltage of the power MOSFET at this time is the Miller plateau voltage, which is typically a few volts higher than
the threshold voltage of the power MOSFET, VGS(TH)
.
To achieve the targeted dVDS/dt, the gate driver must be capable of providing the QGD charge in 20 ns or less. In
other words a peak current of 1.65 A (= 33 nC / 20 ns) or higher must be provided by the gate driver. The
UCC27211A gate driver is capable of providing 4-A peak sourcing current which clearly exceeds the design
requirement and has the capability to meet the switching speed needed. The 2.4× overdrive capability provides
an extra margin against part-to-part variations in the QGD parameter of the power MOSFET along with additional
flexibility to insert external gate resistors and fine tune the switching speed for efficiency versus EMI
optimizations. However, in practical designs the parasitic trace inductance in the gate drive circuit of the PCB will
have a definitive role to play on the power MOSFET switching speed. The effect of this trace inductance is to
limit the dI/dt of the output current pulse of the gate driver. In order to illustrate this, consider output current pulse
waveform from the gate driver to be approximated to a triangular profile, where the area under the triangle
(½ × IPEAK × time) would equal the total gate charge of the power MOSFET (QG parameter in SPP20N60C3
power MOSFET datasheet = 87 nC typical). If the parasitic trace inductance limits the dI/dt then a situation may
occur in which the full peak current capability of the gate driver is not fully achieved in the time required to deliver
the QG required for the power MOSFET switching. In other words the time parameter in the equation would
dominate and the IPEAK value of the current pulse would be much less than the true peak current capability of the
device, while the required QG is still delivered. Because of this, the desired switching speed may not be realized,
even when theoretical calculations indicate the gate driver is capable of achieving the targeted switching speed.
Thus, placing the gate driver device very close to the power MOSFET and designing a tight gate drive-loop with
minimal PCB trace inductance is important to realize the full peak-current capability of the gate driver.
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9.2.2.4 Propagation Delay
The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is
used and the acceptable level of pulse distortion to the system. The UCC27211A-Q1 device features 16-ns
(typical) propagation delays, which ensures very little pulse distortion and allows operation at very high-
frequencies. See the Electrical Characteristics table for the propagation and switching characteristics of the
UCC27211A-Q1 device.
9.2.2.5 Power Dissipation
Power dissipation of the gate driver has two portions as shown in Equation 1.
PDISS = PDC + PSW
(1)
Use Equation 2 to calculate the DC portion of the power dissipation (PDC).
PDC = IQ × VDD
where
•
IQ is the quiescent current for the driver.
(2)
The quiescent current is the current consumed by the device to bias all internal circuits such as input stage,
reference voltage, logic circuits, protections, and also any current associated with switching of internal devices
when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic
shoot-through, and so forth). The UCC27211A-Q1 features very low quiescent currents (less than 0.17 mA, refer
to the Electrical Characteristics table and contain internal logic to eliminate any shoot-through in the output driver
stage. Thus the effect of the PDC on the total power dissipation within the gate driver can be safely assumed to
be negligible. The power dissipated in the gate-driver package during switching (PSW) depends on the following
factors:
•
Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD)
•
•
Switching frequency
Use of external gate resistors. When a driver device is tested with a discrete, capacitive load calculating the
power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias
supply to charge the capacitor is given by Equation 3.
2
EG = ½CLOAD × VDD
where
•
•
CLOAD is load capacitor
VDD is bias voltage feeding the driver
(3)
There is an equal amount of energy dissipated when the capacitor is charged and when it is discharged. This
leads to a total power loss given by Equation 4.
PG = CLOAD × VDD2 × fSW
where
•
fSW is the switching frequency
(4)
The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the
device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when
switching a capacitor which is calculated using the equation QG = CLOAD × VDD to provide Equation 5 for power.
PG = CLOAD × VDD2 × fSW = QG × VDD × fSW
(5)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on
and off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half
is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed
between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the
use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and
external gate resistor.
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9.2.3 Application Curves
Figure 20. Negative 10-V Input
Figure 21. Step Input
Figure 22. Symmetrical UVLO
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10 Power Supply Recommendations
The bias supply voltage range for which the UCC27211A-Q1 device is recommended to operate is from 8 V to
17 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on
the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below
the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The
upper end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device
(which is a stress rating). Keeping a 3-V margin to allow for transient voltage spikes, the maximum
recommended voltage for the VDD pin is 17 V. The UVLO protection feature also involves a hysteresis function,
which means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to
operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage
drop exceeds the hysteresis specification VDD(hys). Therefore, ensuring that, while operating at or near the 8-V
range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the
device is important to avoid triggering device shutdown. During system shutdown, the device operation continues
until the VDD pin voltage has dropped below the V(OFF) threshold, which must be accounted for while evaluating
system shutdown timing design requirements. Likewise, at system start-up the device does not begin operation
until the VDD pin voltage has exceeded the V(ON) threshold.
The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin.
Although this fact is well known, it is important to recognize that the charge for source current pulses delivered by
the HO pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the HO
pin, a corresponding current pulse is delivered into the device through the VDD pin. Thus, ensure that a local
bypass capacitor is provided between the VDD and GND pins and located as close to the device as possible for
the purpose of decoupling is important. A lo-ESR, ceramic surface-mount capacitor is required. TI recommends
using a capacitor in the range 0.22 µF to 4.7 µF between VDD and GND. In a similar manner, the current pulses
delivered by the LO pin are sourced from the HB pin. Therefore a 0.022-µF to 0.1-µF local decoupling capacitor
is recommended between the HB and HS pins.
11 Layout
11.1 Layout Guidelines
To improve the switching characteristics and efficiency of a design, the following layout rules must be followed.
•
•
•
Locate the driver as close as possible to the MOSFETs.
Locate the VDD – VSS and VHB-VHS (bootstrap) capacitors as close as possible to the device (see Figure 23).
Pay close attention to the GND trace. Use the thermal pad of the DRM package as GND by connecting it to
the VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFET, but must not
be in the high current path of the MOSFET drain or source current.
•
•
Use similar rules for the HS node as for GND for the high-side driver.
For systems using multiple and UCC27211A-Q1 device, TI recommends that dedicated decoupling capacitors
be located at VDD-VSS for each device.
•
•
Care must be taken to avoid placing VDD traces close to LO, HS, and HO signals.
Use wide traces for LO and HO closely following the associated GND or HS traces. A width of 60 to 100 mils
is preferable where possible.
•
•
Use as least two or more vias if the driver outputs or SW node must be routed from one layer to another. For
GND, the number of vias must be a consideration of the thermal pad requirements as well as parasitic
inductance.
Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce
significant noise into the relatively high impedance leads.
A poor layout can cause a significant drop in efficiency or system malfunction, and it can even lead to decreased
reliability of the whole system.
18
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ZHCSEM1A –DECEMBER 2015–REVISED JANUARY 2016
11.2 Layout Example
HB Bypassing Cap
(Bottom Layer)
Ground plane
(Bottom Layer)
VDD Bypassing Cap
Ext. Gate
Resistance
(LO)
Ext. Gate
Resistance
(HO)
To LO
Load
To HO
Load
Figure 23. UCC27211A-Q1 PCB Layout Example
11.3 Thermal Considerations
The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal
characteristics of the package. For a gate driver to be useful over a particular temperature range, the package
must allow for efficient removal of the heat produced while keeping the junction temperature within rated limits.
The thermal metrics for the driver package are listed in . For detailed information regarding the table, refer to the
Application Note from Texas Instruments entitled Semiconductor and IC Package Thermal Metrics (SPRA953).
The UCC27211A-Q1 device is offered in an 8-pin SO-PowerPAD package.
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
应用报告《PowerPAD™ 耐热增强型封装》（文献编号：SLMA002）
应用报告《PowerPAD™ 速成》（文献编号：SLMA004）
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC27211AQDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 140
27211Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27211AQDDARQ1
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
UCC27211AQDDARQ1
8
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DDA 8
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4202561/G
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