UCC23313QDWYQ1 [TI]
UCC23313-Q1 4-A Source, 5-A Sink, 3.75-kVRMS Basic, Opto-Compatible, Single-Channel Isolated Gate Driver;型号: | UCC23313QDWYQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | UCC23313-Q1 4-A Source, 5-A Sink, 3.75-kVRMS Basic, Opto-Compatible, Single-Channel Isolated Gate Driver 栅 |
文件: | 总41页 (文件大小:9361K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UCC23313-Q1
SLUSDV7B – OCTOBER 2019 – REVISED MARCH 2021
UCC23313-Q1 4-A Source, 5-A Sink, 3.75-kVRMS Basic, Opto-Compatible,
Single-Channel Isolated Gate Driver
performance and reliability upgrades over standard
1 Features
opto-coupler based gate drivers while maintaining
pin-to-pin compatibility in both schematic and layout
design. Performance highlights include high common
mode transient immunity (CMTI), low propagation
delay, and small pulse width distortion. Tight process
control results in small part-to-part skew. The input
stage is an emulated diode (e-diode) which means
long term reliability and excellent aging characteristics
compared to traditional LEDs found in optocoupler
gate drivers. It is offered in a stretched SO6 package
with > 8.5-mm creepage and clearance, and a
mold compound from material group I, which has a
comparative tracking index (CTI) > 600 V. UCC23313-
Q1's high performance and reliability makes it ideal
for use in automotive motor drives such as the traction
inverter, on-board chargers, DC charging stations,
and automotive HVAC and heating systems. The
higher operating temperature opens up opportunities
for applications not previously able to be supported by
traditional optocouplers.
•
•
AEC-Q100 qualified for automotive applications
3.75-kVRMS single channel isolated gate driver with
opto-compatible input
Pin-to-pin, drop in upgrade for opto isolated gate
drivers
4.5-A source, 5.3-A sink, peak output current
Maximum 33-V output driver supply voltage
8-V (B) or 12-V VCC UVLO options
Rail-to-rail output
105-ns (maximum) propagation delay
25-ns (maximum) part-to-part delay matching
35-ns (maximum) pulse width distortion
150-kV/μs (minimum) common-mode transient
immunity (CMTI)
•
•
•
•
•
•
•
•
•
•
•
Isolation barrier life > 50 Years
13-V reverse polarity voltage handling capability
on input stage supporting interlock
Stretched SO-6 package with > 8.5-mm creepage
and clearance
Operating junction temperature, TJ: –40°C to
+150°C
Functional Safety-Capable
– Documentation available to aid functional safety
system design
•
•
•
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC23313-Q1
Stretched SO-6 7.5 mm x 4.68 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
Safety-related certifications:
VCC
1
2
3
6
5
4
– 6000-VPK basic isolation per DIN V VDE
V0884-11: 2017-01 (In Progress)
– 3.75-kVRMS isolation for 1 minute per UL 1577
ANODE
UVLO
2 Applications
e
NC
VOUT
•
•
•
•
•
Traction inverter for EVs
On-board charger and DC charging station
HVAC
Heaters
Industrial motor-control drives
VEE
CATHODE
3 Description
Functional Block Diagram
The UCC23313-Q1 is an Opto-compatible, single-
channel, isolated gate driver for IGBTs, MOSFETs
and SiC MOSFETs, with 4.5-A source and 5.3-A
sink peak output current and 3.75-kVRMS basic
isolation rating. The high supply voltage range of 33
V allows the use of bipolar supplies to effectively
drive IGBTs and SiC power FETs. UCC23313-Q1
can drive both low side and high side power FETs.
Key features and characteristics bring significant
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC23313-Q1
SLUSDV7B – OCTOBER 2019 – REVISED MARCH 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Function.....................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 6
6.7 Safety-Related Certifications...................................... 7
6.8 Safety Limiting Values.................................................7
6.9 Electrical Characteristics.............................................8
6.10 Switching Characteristics..........................................9
6.11 Insulation Characteristics Curves............................10
6.12 Typical Characteristics............................................ 11
7 Parameter Measurement Information..........................14
7.1 Propagation Delay, rise time and fall time.................14
7.2 IOH and IOL testing.....................................................14
7.3 CMTI Testing.............................................................14
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................29
11 Layout...........................................................................30
11.1 Layout Guidelines................................................... 30
11.2 Layout Example...................................................... 31
11.3 PCB Material...........................................................34
12 Mechanical, Packaging, and Orderable
Information.................................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2020) to Revision B (March 2021)
Page
•
Marketing status changed from Advance Information to Production Data .........................................................1
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5 Pin Configuration and Function
1
6
ANODE
VCC
5
2
NC
VOUT
3
4
CATHODE
VEE
Figure 5-1. UCC23313-Q1 Package SO-6 Top View
Pin Functions
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
UCC23313-Q1
ANODE
CATHODE
NC
1
3
2
6
4
5
I
I
Anode
Cathode
-
No Connection
VCC
P
P
O
Positive output supply rail
Negative output supply rail
Gate-drive output
VEE
VOUT
(1) P = Power, G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free air temperature range (unless otherwise noted)(1)
MIN
MAX
25
UNIT
mA
A
Average Input Current
Peak Transient Input Current
Reverse Input Voltage
Output supply voltage
Output signal voltage
Output signal voltage
Junction temperature
Storage temperature
IF(AVG)
-
IF(TRAN) <1us pulse, 300pps
VR(MAX)
1
14
V
VCC – VEE
-0.3
35
V
VOUT – VCC
VOUT – VEE
0.3
V
-0.3
-40
-65
V
(2)
TJ
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) To maintain the recommended operating conditions for TJ, see the Thermal Information Section.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
UCC23313-Q1
(12-V UVLO Version)
14
33
V
V
VCC
Output Supply Voltage(VCC – VEE)
UCC23313B-Q1
(8-V UVLO Version)
10
33
IF (ON)
Input Diode Forward Current (Diode "ON")
7
-13
16
0.9
mA
V
VF (OFF) Anode voltage - Cathode voltage (Diode "OFF")
TJ
Junction temperature
Ambient temperature
–40
–40
150
125
°C
°C
TA
6.4 Thermal Information
UCC23313-Q1
SO6
THERMAL METRIC(1)
UNIT
6 Pins
126
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
66.1
62.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
29.6
ΨJB
60.8
(1) For more information about traditional and new thermal metrics, see the http://www.ti.com/lit/SPRA953 application report.
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6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Maximum power dissipation on input and
output(1)
PD
750
mW
VCC = 20 V, IF= 10mA 10-kHz, 50% duty
cycle, square wave,180-nF load, TA=25oC
PD1
PD2
Maximum input power dissipation(2)
10
mW
mW
Maximum output power dissipation
740
(1) Derate at 6 mW/°C beyond 25°C ambient temperature
(2) Recommended maximum PD1 = 40mW. Absolute maximum PD1 = 55mW
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6.6 Insulation Specifications
SPECIFIC
ATION
PARAMETER
TEST CONDITIONS
UNIT
mm
CLR
CPG
External clearance(1)
External Creepage(1)
Shortest terminal-to-terminal distance through air >8.5
Shortest terminal-to-terminal distance across the
package surface
>8.5
mm
DTI
CTI
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
>17
>600
I
µm
V
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
Overvoltage category per IEC 60664-1
DIN V VDE 0884-11 (VDE V 0884-11)(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
990
700
990
5300
VPK
VRMS
VDC
AC voltage (sine wave); time-dependent dielectric
breakdown (TDDB) test; see Figure 1
VIOWM
Maximum isolation working voltage
DC voltage
VTEST = VIOTM, t = 60 sec (qualification)
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
VPK
Test method per IEC 62368, 1.2/50 ms waveform,
VTEST = 1.6 x VIOSM = 9600 VPK (qualification)
6000
≤5
VPK
Method a: After I/O safety test subgroup 2/3,Vini
VIOTM
=
,
tini = 60 s; Vpd(m) = 1.2 x VIORM = 1188 VPK, tm
10 s
=
Method a: After environmental tests subgroup 1,
qpd
Apparent charge(4)
pC
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 x VIORM
1584 VPK, tm = 10 s
=
≤5
Method b1: At routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s; ≤5
Vpd(m) = 1.875 x VIORM = 1856VPK, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance, input to output(5)
VIO = 0.4 x sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
0.5
pF
Ω
>1012
>1011
>109
2
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
40/125/21
UL 1577
VTEST = VISO = 3750 VRMS, t = 60 s (qualification),
VTEST = 1.2 x VISO = 4500 VRMS, t = 1 s (100%
production)
VISO
Withstand isolation voltage
3750
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Plan to certify according to UL 1577 Component Recognition
Program
Plan to certify according to DIN V VDE V 0884-11: 2017-01
Basic insulation Maximum transient isolation voltage, 5300 VPK
;
Maximum repetitive peak isolation voltage, 990 VPK
Maximum surge isolation voltage, 6000 VPK
;
Single protection, 3750 VRMS
File number: E181974
Certificate in progress
6.8 Safety Limiting Values
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RqJA = 126°C/W, VI = 15 V, TJ = 150°C,
TA = 25°C
50
IS
Safety input, output, or supply current
mA
RqJA = 126°C/W, VI = 30 V, TJ = 150°C,
TA = 25°C
25
PS
TS
Safety input, output, or total power
Maximum safety temperature(1)
RqJA = 126°C/W, TJ = 150°C, TA = 25°C
750
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ , specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RqJA, in the Thermal Information
table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value
for each parameter: TJ = TA + RqJA ´ P, where P is the power dissipated in the device. TJ(max) = TS = TA + RqJA ´ PS, where TJ(max) is
the maximum allowed junction temperature. PS = IS ´ VI , where VI is the maximum supply voltage.
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6.9 Electrical Characteristics
Unless otherwise noted, all typical values are at TA = 25°C, VCC–VEE= 15V, VEE= GND. All min and max specifications are at
recommended operating conditions (TJ = -40C to 150°C, IF(on)= 7 mA to 16 mA, VEE= GND, VCC= 15 V to 30 V, VF(off)= –5V
to 0.8V)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
IFLH
Input forward threshold current low to High
Input Forward Voltage
VOUT > 5 V, Cg = 1 nF
IF =10 mA
1.5
1.8
0.9
2.8
2.1
4
mA
V
VF
2.4
VF_HL
ΔVF/ΔT
VR
Threshold input voltage High to low
Temp coefficient of Input forward voltage
Input Reverse Breakdown voltage
Input Capacitance
V < 5 V, Cg = 1 nF
IF =10 mA
V
1
1.35 mV/°C
IR= 10 uA
15
V
CIN
F = 0.5 MHz
15
pF
OUTPUT
IF = 10 mA, VCC
=15V, CLOAD=0.18uF,
CVDD=10uF, pulse
width <10us
IOH
High Level Peak Output Current
3
4.5
5.3
A
A
VF= 0 V, VCC
=15V, CLOAD=0.18uF,
CVDD=10uF, pulse
width <10us
IOL
Low Level Peak Output Current
High Level Output Voltage
3.5
IF = 10 mA, IO= -20mA
(with respect to VCC)
0.07
0.18
VCC
0.36
V
VOH
IF = 10 mA, IO= 0 mA
VF = 0 V, IO= 20 mA
IF = 10 mA, IO= 0 mA
VF = 0 V, IO= 0 mA
V
VOL
Low Level Output Voltage
25
2.2
2
mV
mA
mA
ICC_H
ICC_L
Output Supply Current (Diode On)
Output Supply Current (Diode Off)
UNDER VOLTAGE LOCKOUT, UCC23313-Q1 (12-V UVLO Version)
UVLOR
UVLOF
Under Voltage Lockout VCC rising
Under Voltage Lockout VCC falling
VCC_Rising, IF=10 mA
VCC_Falling, IF=10 mA
11
10
12.5
11.5
1.0
13.5
12.5
V
V
V
UVLOHYS UVLO Hysteresis
UNDER VOLTAGE LOCKOUT, UCC23313B-Q1 (8-V UVLO Version)
UVLOR
UVLOF
Under Voltage Lockout VCC rising
Under Voltage Lockout VCC falling
VCC_Rising, IF=10 mA
VCC_Falling, IF=10 mA
7.8
8.5
7.75
0.75
9.2
V
V
V
7.05
8.45
UVLOHYS UVLO Hysteresis
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6.10 Switching Characteristics
Unless otherwise noted, all typical values are at TA = 25°C, VCC-VEE= 30 V, VEE= GND. All min and max specifications are at
recommended operating conditions (TJ = -40 to 150°C, IF(ON)= 7 mA to 16 mA, VEE= GND, VCC= 15 V to 30 V, VF(OFF)= –5V
to 0.8V)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr
Output-signal Rise Time
Output-signal Fall Time
Propagation Delay, Low to High
Propagation Delay, High to Low
28
ns
tf
25
ns
Cg = 1nF
FSW = 20 kHz, (50% Duty Cycle)
VCC=15V
tPLH
tPHL
70
70
105
105
ns
ns
Pulse Width Distortion |tPHL
tPLH
–
tPWD
35
ns
ns
|
Cg = 1nF
FSW = 20 kHz, (50% Duty Cycle)
VCC=15V, IF=10mA
Part-to-Part Skew in Propagation
Delay Between any Two Parts(1)
tsk(pp)
25
30
tUVLO_rec
CMTIH
UVLO Recovery Delay
VCC Rising from 0V to 15V
20
µs
Common-mode Transient
Immunity (Output High)
IF = 10 mA, VCM = 1500 V, VCC= 30 V,
TA= 25°C
150
150
kV/µs
Common-mode Transient
Immunity (Output Low)
VF = 0 V, VCM = 1500 V, VCC= 30 V, TA=
25°C
CMTIL
kV/µs
(1) tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads ensured by characterization.
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6.11 Insulation Characteristics Curves
60
800
600
400
200
0
VCC=15V
VCC=30V
50
40
30
20
10
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
75
TA (°C)
100
125
150
D014
D015
Figure 6-2. Thermal Derating Curve for Limiting
Power per VDE
Figure 6-1. Thermal Derating Curve for Limiting
Current per VDE
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6.12 Typical Characteristics
VCC= 15 V, 1-µF capacitor from VCC to VEE, CLOAD = 1 nF for timing tests and 180nF for IOH and IOL tests, TJ =
–40°C to +150°C, (unless otherwise noted)
1.5
1.45
1.4
6.6
6.3
6
ICC H
ICC L
IOH
IOL
1.35
1.3
5.7
5.4
5.1
4.8
4.5
4.2
3.9
3.6
3.3
1.25
1.2
1.15
1.1
1.05
1
0.95
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temp (èC)
D002
Temp (èC)
D001
Figure 6-4. Supply currents versus Temperature
CLOAD = 180-nF
Figure 6-3. Output Drive currents versus
Temperature
1.4
3.5
3.4
3.3
3.2
3.1
3
ICC H
ICC L
1.3
1.2
1.1
1
2.9
2.8
2.7
2.6
-40 -20
0
20
40
60
80 100 120 140 160
13
15.5
18
20.5
23 25.5
VCC (V)
28
30.5
33 35
Temp (èC)
D004
D003
Figure 6-6. Forward threshold current versus
Temperature
Figure 6-5. Supply current versus Supply Voltage
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66
64
62
60
58
56
84
tPDLH
tPDHL
82
80
78
76
74
72
70
68
66
64
tPDLH
tPDHL
7
9
11
13
15
17
19
21
23
25
-40 -20
0
20
40
60
80 100 120 140 160
IF (mA)
Temp (èC)
D006
D005
CLOAD = 1-nF
CLOAD = 1-nF
Figure 6-8. Propagation delay versus Forward
current
Figure 6-7. Propagation delay versus Temperature
0.9
0.85
0.8
300
280
260
240
220
200
180
160
140
120
0.75
0.7
0.65
0.6
0.55
0.5
0.45
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temp (èC)
Temp (èC)
D007
D008
IOUT = 0mA
IOUT = 20mA
(sourcing)
Figure 6-9. VOH (No Load) versus Temperature
Figure 6-10. VOH (20mA Load) versus Temperature
20
19
18
17
16
15
14
13
12
11
10
71
70
69
tPLH
tPHL
68
67
-40 -20
0
20
40
60
80 100 120 140 160
10
15
20
25
30
35
Temp (èC)
VCC (V)
D009
D010
Figure 6-12. Propagation delay versus Supply
voltage
IOUT = 20mA
(sinking)
Figure 6-11. VOL versus Temperature
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3
2.8
2.6
2.4
2.2
2
2.2
2.1
2
1.9
1.8
1.7
1.6
1.8
1.6
1.4
1.2
1
0
4
6
8
10 12 14 16 18 20 22 24 25
IF (mA)
20
40
60
80 100 120 140 160 180 200
Freq (KHz)
D012
D011
Figure 6-13. Supply current versus Frequency
TA = 25°C
Figure 6-14. Forward current versus Forward
voltage drop
2.3
2.28
2.26
2.24
2.22
2.2
2.18
2.16
2.14
2.12
2.1
2.08
-40 -20
0
20
40
60
80 100 120 140 160
Temp (èC)
D013
IF = 10mA
Figure 6-15. Forward voltage drop versus Temperature
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7 Parameter Measurement Information
7.1 Propagation Delay, rise time and fall time
Figure 7-1 shows the propagation delay from the input forward current IF, to VOUT. This figures also shows the
circuit used to measure the rise (tr) and fall (tf) times and the propagation delays tPDLH and tPDHL
.
ANODE
VCC
270Q
1
6
IF
IF
+
VOUT
NC
5
tPD_LH
tPD_HL
e
15V
0
2
5
-
1nF
80%
50%
20%
VEE
CATHODE
VOUT
3
4
tr
tf
Figure 7-1. IF to VOUT Propagation Delay, Rise Time and Fall Time
7.2 IOH and IOL testing
Figure 7-2 shows the circuit used to measure the output drive currents IOH and IOL. A load capacitance of 180nF
is used at the output. The peak dv/dt of the capacitor voltage is measured in order to determine the peak source
and sink currents of the gate driver.
ANODE
VCC
270Q
1
6
IF
+
VOUT
NC
5
IOH
e
15V
0
2
5
IOL
-
180nF
VEE
CATHODE
3
4
Figure 7-2. IOH and IOL
7.3 CMTI Testing
Figure 7-3 is the simplified diagram of the CMTI testing. Common mode voltage is set to 1500V. The test is
performed with IF = 6mA (VOUT= High) and IF = 0mA (VOUT = LOW). The diagram also shows the fail criteria
for both cases. During the application on the CMTI pulse with IF = 6mA, if VOUT drops from VCC to ½VCC it is
considered as a failure. With IF= 0mA, if VOUT rises above 1V, it is considered as a failure.
e-diode off
VCM
e-diode on
VCM
ANODE
VCC
150Q
150Q
1500V
0V
1500V
0V
IF
+
VOUT
+
-
e
30V
5V
-
VOUT
1nF
30V
15V
0V
VEE
CATHODE
Fail Threshold
Fail Threshold
1V
0V
VOUT
t
t
VCM =1500V
Figure 7-3. CMTI Test Circuit for UCC23313-Q1
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8 Detailed Description
8.1 Overview
UCC23313-Q1 is a single channel isolated gate driver, with an opto-compatible input stage, that can drive
IGBTs, MOSFETs and SiC FETs. It has 4A peak output current capability with max output driver supply voltage
of 33V. The inputs and the outputs are galvanically isolated. UCC23313-Q1 is offered in an industry standard
6 pin (SO6) package with >8.5mm creepage and clearance. It has a working voltage of 700-VRMS, isolation
rating of 3.75 kVRMS for 60s and a surge rating of 6 kVPK. It is pin-to-pin compatible with standard opto isolated
gate drivers. While standard opto isolated gate drivers use an LED as the input stage, UCC23313-Q1 uses an
emulated diode (or "e-diode") as the input stage which does not use light emission to transmit signals across
the isolation barrier. The input stage is isolated from the driver stage by dual, series HV SiO2 capacitors in full
differential configuration that not only provides isolation but also offers best-in-class common mode transient
immunity of >150kV/us. The e-diode input stage along with capacitive isolation technology gives UCC23313-Q1
several performance advantages over standard opto isolated gate drivers. They are as follows:
1. Since the e-diode does not use light emission for its operation, the reliability and aging characteristics of
UCC23313-Q1 are naturally superior to those of standard opto isolated gate drivers.
2. Higher ambient operating temperature range of 125°C, compared to only 105°C for most opto isolated gate
drivers
3. The e-diode forward voltage drop has less part-to-part variation and smaller variation across temperature.
Hence, the operating point of the input stage is more stable and predictable across different parts and
operating temperature.
4. Higher common mode transient immunity than opto isolated gate drivers
5. Smaller propagation delay than opto isolated gate drivers
6. Due to superior process controls achievable in capacitive isolation compared to opto isolation, there is less
part-to-part skew in the prop delay, making the system design simpler and more robust
7. Smaller pulse width distortion than opto isolated gate drivers
The signal across the isolation has an on-off keying (OOK) modulation scheme to transmit the digital data across
a silicon dioxide based isolation barrier (see Figure 8-1). The transmitter sends a high-frequency carrier across
the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver
demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. The
UCC23313-Q1 also incorporates advanced circuit techniques to maximize the CMTI performance and minimize
the radiated emissions from the high frequency carrier and IO buffer switching. Figure 8-2 shows conceptual
detail of how the OOK scheme works.
8.2 Functional Block Diagram
Receiver
Transmitter
VCC
IF
UVLO
Anode
NC
VBIAS
RNMOS
ROH
VEE
Level
Shift /
Pre
VOUT
Amplifier
Oscillator
Demodulator
Vclamp
driver
ROL
Cathode
VEE
Figure 8-1. Conceptual Block Diagram of a Isolated Gate Driver with an Opto Emulated Input Stage (SO6
pkg)
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IF IN
Carrier signal
through isolation
barrier
RX OUT
Figure 8-2. On-Off Keying (OOK) Based Modulation Scheme
8.3 Feature Description
8.3.1 Power Supply
Since the input stage is an emulated diode, no power supply is needed at the input.
The output supply, VCC, supports a voltage range from 10 V to 33 V. For operation with bipolar supplies, the
power device is turned off with a negative voltage on the gate with respect to the emitter or source. This
configuration prevents the power device from unintentionally turning on because of current induced from the
Miller effect. The typical values of the VCC and VEE output supplies for bipolar operation are 15V and -8V with
respect to GND for IGBTs, and 20V and -5V for SiC MOSFETs.
For operation with unipolar supply, the VCC supply is connected to 15V with respect to GND for IGBTs, and 20V
for SiC MOSFETs. The VEE supply is connected to 0V.
8.3.2 Input Stage
The input stage of UCC23313-Q1 is simply the e-diode and therefore has an Anode (Pin 1) and a Cathode
(Pin 3). Pin 2 has no internal connection and can be left open or connected to ground. The input stage does
not have a power and ground pin. When the e-diode is forward biased by applying a positive voltage to the
Anode with respect to the Cathode, a forward current IF flows into the e-diode. The forward voltage drop across
the e-diode is 2.1V (typ). An external resistor should be used to limit the forward current. The recommended
range for the forward current is 7mA to 16mA. When IF exceeds the threshold current IFLH(2.8mA typ.) a high
frequency signal is transmitted across the isolation barrier through the high voltage SiO2 capacitors. The HF
signal is detected by the receiver and VOUT is driven high. See Section 9.2.2.1 for information on selecting the
input resistor. The dynamic impedance of the e-diode is very small(<1.0Ω) and the temperature coefficient of the
e-diode forward voltage drop is <1.35mV/°C. This leads to excellent stability of the forward current IF across all
operating conditions. If the Anode voltage drops below VF_HL (0.9V), or reverse biased, the gate driver output
is driven low. The reverse breakdown voltage of the e-diode is >15V. So for normal operation, a reverse bias
of up to 13V is allowed. The large reverse breakdown voltage of the e-diode enables UCC23313-Q1 to be
operated in interlock architecture (see example in Figure 8-3) where VSUP can be as high as 12V. The system
designer has the flexibility to choose a 3.3V, 5.0V or up to 12V PWM signal source to drive the input stage of
UCC23313-Q1 using an appropriate input resistor. The example shows two gate drivers driving a set of IGBTs.
The inputs of the gate drivers are connected as shown and driven by two buffers that are controlled by the MCU.
Interlock architecture prevents both the e-diodes from being "ON" at the same time, preventing shoot through in
the IGBTs. It also ensures that if both PWM signals are erroneously stuck high (or low) simultaneously, both gate
driver outputs will be driven low.
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VSUP
ANODE
1
R1
VCC
HSON from MCU
6
GND
UVLO
To High Side
NC
2
VOUT
Gate
e
5
VSUP
VEE
CATHODE
3
R2
LSON from MCU
4
GND
ANODE
1
VCC
6
UVLO
To Low Side
Gate
NC
2
VOUT
e
5
CATHODE
3
VEE
4
Figure 8-3. Interlock
8.3.3 Output Stage
The output stages of the UCC23313-Q1 family feature a pullup structure that delivers the highest peak-source
current when it is most needed which is during the Miller plateau region of the power-switch turnon transition
(when the power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure
features a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The function of the
N-channel MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turnon. Fast turnon is
accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing
states from low to high. The on-resistance of this N-channel MOSFET (RNMOS) is approximately 5.1 Ω when
activated.
Table 8-1. UCC23313-Q1 On-Resistance
RNMOS
ROH
ROL
UNIT
5.1
9.5
0.40
Ω
The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device
only. This parameter is only for the P-channel device because the pullup N-channel device is held in the OFF
state in DC condition and is turned on only for a brief instant when the output is changing states from low
to high. Therefore, the effective resistance of the UCC23313-Q1 pullup stage during this brief turnon phase is
much lower than what is represented by the ROH parameter, yielding a faster turn on. The turnon-phase output
resistance is the parallel combination ROH || RNMOS
.
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The pulldown structure in the UCC23313-Q1 is simply composed of an N-channel MOSFET. The output voltage
swing between VCC and VEE provides rail-to-rail operation because of the MOS-out stage which delivers very low
dropout.
VCC
UVLO
RNMOS
ROH
VEE
Level
Shift /
Pre
VOUT
Demodulator
driver
ROL
VEE
Figure 8-4. Output Stage
8.3.4 Protection Features
8.3.4.1 Undervoltage Lockout (UVLO)
UVLO function is implemented for VCC and VEE pins to prevent an under-driven condition on IGBTs and
MOSFETs. When VCC is lower than UVLOR at device start-up or lower than UVLOF after start-up, the voltage-
supply UVLO feature holds the effected output low, regardless of the input forward current as shown in Table
8-2. The VCC UVLO protection has a hysteresis feature (UVLOhys). This hysteresis prevents chatter when the
power supply produces ground noise which allows the device to permit small drops in bias voltage, which occurs
when the device starts switching and operating current consumption increases suddenly.
When VCC drops below UVLOF, a delay, tUVLO_rec occurs on the output when the supply voltage rises above
UVLOR again.
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10mA
IF
VCC
UVLOR
UVLOF
VCC
tUVLO_rec
VOUT
t
Figure 8-5. UVLO functionality
8.3.4.2 Active Pulldown
The active pull-down function is used to pull the IGBT or MOSFET gate to the low state when no power is
connected to the VCC supply. This feature prevents false IGBT and MOSFET turn-on by clamping VOUT pin to
approximately 2V.
When the output stage of the driver is in an unbiased condition (VCC floating), the driver outputs (see Figure
8-4) are held low by an active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the
upper PMOS & NMOS are held off while the lower NMOS gate is tied to the driver output through an internal
500-kΩ resistor. In this configuration, the lower NMOS device effectively clamps the output (VOUT) to less than
2V.
8.3.4.3 Short-Circuit Clamping
The short-circuit clamping function is used to clamp voltages at the driver output and pull the output pin VOUT
slightly higher than the VCC voltage during short-circuit conditions. The short-circuit clamping function helps
protect the IGBT or MOSFET gate from overvoltage breakdown or degradation. The short-circuit clamping
function is implemented by adding a diode connection between the dedicated pins and the VCC pin inside the
driver. The internal diodes can conduct up to 500-mA current for a duration of 10 µs and a continuous current of
20 mA. Use external Schottky diodes to improve current conduction capability as needed.
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8.4 Device Functional Modes
Table 8-2 lists the functional modes for UCC23313-Q1
Table 8-2. Function Table for UCC23313-Q1 with VCC Rising
e-diode
VCC
VOUT
Low
Low
High
OFF (IF< IFLH
)
0V - 33V
ON (IF> IFLH
)
0V - UVLOR
UVLOR - 33V
ON ( (IF> IFLH
)
Table 8-3. Function Table for UCC23313-Q1 with VCC Falling
e-diode
VCC
VOUT
Low
Low
High
OFF (IF< IFLH
)
0V - 33V
UVLOF- 0V
33V - UVLOF
ON (IF> IFLH
)
ON ( (IF> IFLH
)
8.4.1 ESD Structure
Figure 8-6 shows the multiple diodes involved in the ESD protection components of the UCC23313-Q1 device .
This provides pictorial representation of the absolute maximum rating for the device.
VCC
Anode
40V
20V
VOUT
40V
2.5V
36V
Cathode
VEE
Figure 8-6. ESD Structure
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
UCC23313-Q1 is a single channel, isolated gate driver with opto-compatible input for power semiconductor
devices, such as MOSFETs, IGBTs, or SiC MOSFETs. It is intended for use in applications such as motor
control, industrial inverters, and switched-mode power supplies. It differs from standard opto isolated gate drivers
as it does not have an LED input stage. Instead of an LED, it has an emulated diode (e-diode). To turn the
e-diode "ON", a forward current in the range of 7mA to 16mA should be driven into the Anode. This will drive the
gate driver output High and turn on the power FET. Typically, MCU's are not capable of providing the required
forward current. Hence a buffer has to be used between the MCU and the input stage of UCC23313-Q1. Typical
buffer power supplies are either 5V or 3.3V. A resistor is needed between the buffer and the input stage of
UCC23313-Q1 to limit the current. It is simple, but important to choose the right value of resistance. The resistor
tolerance, buffer supply voltage tolerance and output impedance of the buffer, have to be considered in the
resistor selection. This will ensure that the e-diode forward current stays within the recommended range of 7mA
to 16mA. Detailed design recommendations are given in the Section 9.1. The current driven input stage offers
excellent noise immunity that is need in high power motor drive systems, especially in cases where the MCU
cannot be located close to the isolated gate driver. UCC23313-Q1 offers best in class CMTI performance of
>150kV/us at 1500V common mode voltages.
The e-diode is capable of 25mA continuous in the forward direction. The forward voltage drop of the e-diode
has a very tight part to part variation (1.8V min to 2.4V max). The temperature coefficient of the forward drop
is <1.35mV/°C. The dynamic impedance of the e-diode in the forward biased region is ~1Ω. All of these factors
contribute in excellent stability of the e-diode forward current. To turn the e-diode "OFF", the Anode - Cathode
voltage should be <0.8V, or IF should be <IFLH. The e-diode can also be reverse biased up to 5V (7V abs max) in
order to turn it off and bring the gate driver output low.
The output power supply for UCC23313-Q1 can be as high as 33V (35V abs max). The output power supply
can be configured externally as a single isolated supply up to 33V or isolated bipolar supply such that VCC-VEE
does not exceed 33V, or it can be bootstrapped (with external diode & capacitor) if the system uses a single
power supply with respect to the power ground. Typical quiescent power supply current from VCC is 1.2mA (max
2.2mA).
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9.2 Typical Application
The circuit in Figure 9-1, shows a typical application for driving IGBTs.
VSUP
REXT/2
ANODE
1
IF
VCC
6
+
+
-
15V
VOUT
5
NC
RGON
RG_int
-
e
VF
2
RGOFF
VEE
4
CATHODE
3
REXT/2
PWM
M1
GND
Figure 9-1. Typical Application Circuit for UCC23313-Q1 to Drive IGBT
9.2.1 Design Requirements
Table 9-1 lists the recommended conditions to observe the input and output of the UCC23313-Q1 gate driver.
Table 9-1. UCC23313-Q1 Design Requirements
PARAMETER
VALUE
UNIT
V
VCC
15
10
8
IF
mA
kHz
Switching frequency
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9.2.2 Detailed Design Procedure
9.2.2.1 Selecting the Input Resistor
The input resistor limits the current that flows into the e-diode when it is forward biased. The threshold current
IFLH is 2.8 mA typ. The recommended operating range for the forward current is 7 mA to 16 mA (e-diode ON).
All the electrical specifications are guaranteed in this range. The resistor should be selected such that for typical
operating conditions, IF is 10 mA. Following are the list of factors that will affect the exact value of this current:
1. Supply Voltage VSUP variation
2. Manufacturer's tolerance for the resistor and variation due to temperature
3. e-diode forward voltage drop variation (at IF=10 mA, VF= typ 2.1 V, min 1.8 V, max 2.4 V, with a temperature
coefficient < 1.35 mV/°C and dynamic impedance < 1 Ω)
See Figure 9-2 for the schematic using a single NMOS and split resistor combination to drive the input stage of
UCC23313-Q1. The input resistor can be selected using the equation shown.
VSUP
REXT/2
ANODE
1
IF
VCC
6
+
-
VOUT
5
NC
e
VF
2
VEE
4
CATHODE
3
REXT/2
PWM
M1
GND
VSUP F VF
REXT
=
F RM1
IF
Figure 9-2. Configuration 1: Driving the input stage of UCC23313-Q1 with a single NMOS and split
resistors
Driving the input stage of UCC23313-Q1 using a single buffer is shown in Figure 9-3 and using 2 buffers is
shown in Figure 9-4
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VSUP
IF
ANODE
VCC
REXT/2
PWM (From MCU)
1
6
GND
+
NC
e
VF
2
5
-
VEE
REXT/2
CATHODE
3
4
GND
VSUP F VF
REXT
=
F ROH_buf
IF
Figure 9-3. Configuration 2: Driving the input stage of UCC23313-Q1 with one Buffer and split resistors
VSUP
IF
ANODE
VCC
REXT/2
PWM (From MCU)
1
6
GND
+
NC
e
VF
2
5
VSUP
-
VEE
REXT/2
CATHODE
PWM (From MCU)
3
4
VSUP F VF
REXT
=
F (ROH_buf + ROL_buf)
IF
Figure 9-4. Configuration 3: Driving the input stage of UCC23313-Q1 with 2 buffers and split resistors
Table 9-2 shows the range of values for REXT for the 3 different configurations shown in Figure 9-2, Figure 9-3
and Figure 9-4.The assumptions used in deriving the range for REXT are as follows:
1. Target forward current IF is 7mA min, 10mA typ and 16mA max
2. e-diode forward voltage drop is 1.8V to 2.4V
3. VSUP (Buffer supply voltage) is 5V with ±5% tolerance
4. Manufacturer's tolerance for REXT is 1%
5. NMOS resistance is 0.25Ω to 1.0Ω (for configuration 1)
6. ROH(buffer output impedance in output "High" state) is 13Ω min, 18Ω typ and 22Ω max
7. ROL(buffer output impedance in "Low" state) is 10Ω min, 14Ω typ and 17Ω max
Table 9-2. REXT Values to Drive The Input Stage
REXT
Ω
Configuration
Min
218
Typ
Max
331
Single NMOS and
REXT
290
Single Buffer and
REXT
204
194
272
259
311
294
Two Buffers and REXT
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9.2.2.2 Gate Driver Output Resistor
The external gate-driver resistors, RG(ON) and RG(OFF) are used to:
1. Limit ringing caused by parasitic inductances and capacitances
2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
4. Reduce electromagnetic interference (EMI)
The output stage has a pull up structure consisting of a P-channel MOSFET and an N-channel MOSFET in
parallel. The combined peak source current is 4.5 A Use Equation 1 to estimate the peak source current as an
example.
VCC F VGDF
IOH = minH4.5A,
I
(RNMOS||ROH + RGON + RGFET
)
INT
(1)
where
•
•
RGON is the external turnon resistance.
RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will
assume 0Ω for our example
•
•
IOH is the peak source current which is the minimum value between 4.5A, the gate-driver peak source
current, and the calculated value based on the gate-drive loop resistance.
VGDF is the forward voltage drop for each of the diodes in series with RGON and RGOFF. The diode drop for
this example is 0.7 V.
In this example, the peak source current is approximately 1.7A as calculated in Equation 2.
15 F 0.7
IOH = minH4.5A,
I = 1.72A
(5.sÀ||9.wÀ + wÀ + rÀ)
(2)
(3)
Similarly, use Equation 3 to calculate the peak sink current.
VCC F VGDF
IOL = minH5.3A,
I
(ROL+ RGOFF + RGFET
)
INT
where
•
•
RGOFF is the external turnoff resistance.
IOL is the peak sink current which is the minimum value between 5.3A, the gate-driver peak sink current, and
the calculated value based on the gate-drive loop resistance.
In this example, the peak sink current is the minimum of 5.3A and Equation 4.
15 F 0.7
IOL = minH5.3A,
I = 1.38A
(0.vÀ + srÀ + rÀ)
(4)
The diodes shown in series with each, RGON and RGOFF, in Figure 9-1 ensure the gate drive current flows
through the intended path, respectively, during turn-on and turn-off. Note that the diode forward drop will reduce
the voltage level at the gate of the power switch. To achieve rail-to-rail gate voltage levels, add a resistor from
the VOUT pin to the power switch gate, with a resistance value approximately 20 times higher than RGON and
RGOFF. For the examples described in this section, a good choice is 100 Ω to 200 Ω.
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Note
The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot
and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized.
Conversely, the peak source and sink current is dominated by loop parasitics when the load
capacitance (CISS) of the power transistor is very small (typically less than 1 nF) because the rising
and falling time is too small and close to the parasitic ringing period.
9.2.2.3 Estimate Gate-Driver Power Loss
The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC23313-Q1 device
and the power losses in the peripheral circuitry, such as the external gate-drive resistor.
The PGD value is the key power loss which determines the thermal safety-related limits of the UCC23313-Q1
device, and it can be estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes power dissipated in the input stage (PGDQ_IN
)
as well as the quiescent power dissipated in the output stage (PGDQ_OUT) when operating with a certain
switching frequency under no load. PGDQ_IN is determined by IF and VF and is given by Equation 5. The
PGDQ_OUT parameter is measured on the bench with no load connected to VOUT pin at a given VCC, switching
frequency, and ambient temperature. In this example, VCC is 15 V. The current on the power supply, with PWM
switching at 10 kHz, is measured to be ICC = 1.33 mA . Therefore, use Equation 6 to calculate PGDQ_OUT
.
1
PGDQ _IN = Û VF * IF
2
(5)
(6)
PGDQ _OUT = VCC* ICC
The total quiescent power (without any load capacitance) dissipated in the gate driver is given by the sum of
Equation 5 and Equation 6 as shown in Equation 7
PGDQ = PGDQ _IN + PGDQ _OUT = 10 mW + 20mW = 30mW
(7)
The second component is the switching operation loss, PGDSW, with a given load capacitance which the driver
charges and discharges the load during each switching cycle. Use Equation 8 to calculate the total dynamic loss
from load switching, PGSW
.
PGSW = VCC2 ìQG ì fSW
(8)
where
QG is the gate charge of the power transistor at VCC
•
.
So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated
in Equation 9.
PGSW = 15 V ì120 nC ì10 kHz = 18 mW
(9)
QG represents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change
with different testing conditions. The UCC23313-Q1 gate-driver loss on the output stage, PGDO, is part of PGSW
.
PGDO is equal to PGSW if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and
all the gate driver-loss will be dissipated inside the UCC23313-Q1. If an external turn-on and turn-off resistance
exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and
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power-transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if
the source/sink current is not saturated to 4.5A/5.3A, however, it will be non-linear if the source/sink current is
saturated. Therefore, PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
P
ROH||RNMOS
ROL
GSW
P
GDO
=
H
+
I
2
ROH||RNMOS + RGON + RGFET_int ROL + RGOFF + RGFET_int
(10)
In this design example, all the predicted source and sink currents are less than 4.5 A and 5.3 A, therefore, use
Equation 10 to estimate the UCC23313-Q1 gate-driver loss.
18 mW
2
9.5À||5.1À
0.4À
P
GDO
=
H
+
I = 3.9 mW
9.5À||5.1À + 5.1À + 0À 0.4À + 10À + 0À
(11)
Case 2 - Nonlinear Pull-Up/Down Resistor:
T
T
F_Sys
R_Sys
P
GDO
= fsw x f4.5A x
±
(VCC F VOUT (t))dt + 5.3A x
±
VOUT (t) dtj
0
0
(12)
where
•
VOUT(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is
saturated for some time, this value can be simplified as a constant-current source (4.5 A at turnon and 5.3 A
at turnoff) charging or discharging a load capacitor. Then, the VOUT(t) waveform will be linear and the TR_Sys
and TF_Sys can be easily predicted.
For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO
is a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown
based on this discussion.
Use Equation 13 to calculate the total gate-driver loss dissipated in the UCC23313-Q1 gate driver, PGD
.
PGD = PGDQ + PGDO = 30mW + 3.9mW = 33.9mW
(13)
(14)
9.2.2.4 Estimating Junction Temperature
Use Equation 14 to estimate the junction temperature (TJ) of UCC23313-Q1.
TJ = TC + YJT ìPGD
where
•
•
TC is the UCC23313-Q1 case-top temperature measured with a thermocouple or some other instrument.
ΨJT is the junction-to-top characterization parameter from the table.
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RθJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
The RθJC resistance can only be used effectively when most of the thermal energy is released through the case,
such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of RθJC will
inaccurately estimate the true junction temperature. The ΨJT parameter is experimentally derived by assuming
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that the dominant energy leaving through the top of the IC will be similar in both the testing environment and
the application environment. As long as the recommended layout guidelines are observed, junction temperature
estimations can be made accurately to within a few degrees Celsius.
9.2.2.5 Selecting VCC Capacitor
Bypass capacitors for VCC is essential for achieving reliable performance. TI recommends choosing low-ESR
and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with sufficient voltage ratings, temperature
coefficients, and capacitance tolerances. A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the
CVCC capacitor. If the bias power supply output is located a relatively long distance from the VCC pin, a tantalum
or electrolytic capacitor with a value greater than 10 μF should be used in parallel with CVCC
.
Note
DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V, 1-μF X7R
capacitor is measured to be only 500 nF when a DC bias of 15-VDC is applied.
9.2.3 Application Performance Plots
Figure 9-5. 1-A Load Performace Data
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10 Power Supply Recommendations
The recommended input supply voltage (VCC) for the UCC23313-Q1 device is from to 33 V. The lower limit of the
range of output bias-supply voltage (VCC) is determined by the internal UVLO protection feature of the device.
VCC voltage should not fall below the UVLO threshold for normal operation, or else the gate-driver outputs
can become clamped low for more than 20 μs by the UVLO protection feature. The higher limit of the VCC
range depends on the maximum gate voltage of the power device that is driven by the UCC23313-Q1 device,
and should not exceed the recommended maximum VCC of 33 V. A local bypass capacitor should be placed
between the VCC and VEE pins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing
an additional 100-nF capacitor in parallel with the device biasing capacitor for high frequency filtering. Both
capacitors should be positioned as close to the device as possible. Low-ESR, ceramic surface-mount capacitors
are recommended.
If only a single, primary-side power supply is available in an application, isolated power can be generated for the
secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501
Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for
Isolated Power Supplies data sheet.
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11 Layout
11.1 Layout Guidelines
Designers must pay close attention to PCB layout to achieve optimum performance for the UCC23313-Q1.
Some key guidelines are:
•
Component placement:
– Low-ESR and low-ESL capacitors must be connected close to the device between the VCC and VEE pins
to bypass noise and to support high peak currents when turning on the external power transistor.
– To avoid large negative transients on the VEE pins connected to the switch node, the parasitic inductances
between the source of the top transistor and the source of the bottom transistor must be minimized.
•
•
•
Grounding considerations:
– Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area
is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of
the transistors. The gate driver must be placed as close as possible to the transistors.
High-voltage considerations:
– To ensure isolation performance between the primary and secondary side, avoid placing any PCB
traces or copper below the driver device. A PCB cutout or groove is recommended in order to prevent
contamination that may compromise the isolation performance.
Thermal considerations:
– A large amount of power may be dissipated by the UCC23313-Q1 if the driving voltage is high, the load
is heavy, or the switching frequency is high. Proper PCB layout can help dissipate heat from the device to
the PCB and minimize junction-to-board thermal impedance (θJB).
– Increasing the PCB copper connecting to the VCC and VEE pins is recommended, with priority on
maximizing the connection to VEE. However, the previously mentioned high-voltage PCB considerations
must be maintained.
– If the system has multiple layers, TI also recommends connecting the VCC and VEE pins to internal ground
or power planes through multiple vias of adequate size. These vias should be located close to the IC pins
to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high
voltage planes are overlapping.
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11.2 Layout Example
Figure 11-1 shows a PCB layout example with the signals and key components labeled.
A. No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.
Figure 11-1. Layout Example
Figure 11-2 and Figure 11-3 show the top and bottom layer traces and copper.
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Figure 11-2. Top-Layer Traces and Copper
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Figure 11-3. Bottom-Layer Traces and Copper (Flipped)
Figure 11-4 shows the 3D layout of the top view of the PCB.
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A. The location of the PCB cutout between primary side and secondary sides ensures isolation performance.
Figure 11-4. 3-D PCB View
11.3 PCB Material
Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because
of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the
self-extinguishing flammability-characteristics.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
850
850
(1)
(2)
(3)
(4/5)
(6)
PUCC23313BQDWYRQ1
PUCC23313QDWYRQ1
ACTIVE
SOIC
SOIC
DWY
6
6
Non-RoHS &
Non-Green
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
ACTIVE
DWY
Non-RoHS &
Non-Green
Call TI
UCC23313BQDWYQ1
UCC23313BQDWYRQ1
UCC23313QDWYQ1
UCC23313QDWYRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DWY
DWY
DWY
DWY
6
6
6
6
100
850
100
850
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
C23313BQ
C23313BQ
UC23313Q
UC23313Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Mar-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC23313-Q1 :
Catalog : UCC23313
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
SOIC -3.55 mm max height
SOIC
DWY0006A
C
11.75
11.25
SEATING PLANE
PIN 1 ID
AREA
0.1 C
A
6X 1.27
SYMM
6
1
3
2X
2.54
4.78
4.58
4
0.51
0.28
6X
SYMM
0.25
C A
B
3.55 MAX
7.60
7.40
B
0.304
0.204
A
SEE DETAIL
(3.18)
GAGE PLANE 0.25
ꢀꢁꢂ
0.30
0.10
1.00
0.50
DETAIL A
TYPICAL
4223977/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.70 per side.
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EXAMPLE BOARD LAYOUT
SOIC - 3.55 mm max height
SOIC
DWY0006A
SYMM
6X(1.905)
SEE DETAILS
SYMM
6X(0.76)
6X(1.27)
(10.75)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAAILS
4223977/A 01/2018
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
SOIC - 3.55 mm max height
SOIC
DWY0006A
SYMM
6X(1.905)
SEE DETAILS
SYMM
6X(0.76)
6X(1.27)
(10.75)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 6X
4223977/A 01/2018
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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