UCC21737-Q1 [TI]

适用于 SiC/IGBT、具有主动短路保护功能的汽车类 10A 隔离式单通道栅极驱动器;
UCC21737-Q1
型号: UCC21737-Q1
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

适用于 SiC/IGBT、具有主动短路保护功能的汽车类 10A 隔离式单通道栅极驱动器

栅极驱动 双极性晶体管 驱动器
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中文:  中文翻译
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UCC21737-Q1  
ZHCSOE5B MARCH 2022 REVISED JANUARY 2023  
UCC21737-Q1 适用SiC/IGBT 并具有主动保护和CMTI 10A 拉电流和灌电  
流增强型隔离式汽车单通道栅极驱动器  
输入侧通过 SiO2 电容隔离技术与输出侧相隔离支持  
高达 1.5kVRMS 的工作电压、12.8kVPK 的浪涌抗扰  
1 特性  
5.7kV RMS 单通道隔离式栅极驱动器  
• 具有符AEC-Q100 标准的下列特性:  
隔离层寿命超过 40 并提供较低的器件间偏  
共模噪声抗扰(CMTI) 150V/ns。  
– 器件温度等0-40°C +150°C 环境工作温  
度范围  
– 器HBM ESD 分类等3A  
– 器CDM ESD 分类等C6  
功能安全质量管理型  
UCC21737-Q1 包括先进的保护特性如快速过流和短  
路检测、分流电流检测支持、故障报告、有源米勒钳  
位、输入和输出侧电源 UVLO用于优化 SiC IGBT  
开关行为和稳健性。可以利用 ASC 功能在系统故障  
事件期间强制打开电源开关从而进一步提高驱动器的  
多功能性并消减系统设计工作量、尺寸和成本。  
可提供用于功能安全系统设计的文档  
• 高2121Vpk SiC MOSFET IGBT  
33V 最大输出驱动电(VDD-VEE)  
±10A 驱动强度和分离输出  
器件信息  
器件型号(1)  
封装尺寸标称值)  
封装  
UCC21737-Q1  
DW SOIC-16  
10.3mm × 7.5mm  
150V/ns CMTI  
• 具270 ns 快速响应时间的过流保护  
• 外部有源米勒钳位  
(1) 如需了解所有可用封装请参阅数据表末尾的可订购产品附  
录。  
• 发生故障时900mA 软关断  
• 隔离侧ASC 输入用于在系统故障期间打开电源  
开关  
器件引脚配置  
• 过流警FLT 和通RST/EN 重置  
• 针RST/EN 的快速启用/禁用响应  
• 抑制输入引脚上<40ns 噪声瞬态和脉冲  
RDY 12V VDD UVLO -3V VEE UVLO具  
有电源正常指示功能)  
• 具有高5V 过冲/欠冲瞬态电压抗扰度的输入/输出  
130 ns最大传播延迟30 ns最大脉冲/器  
件间偏移  
SOIC-16 DW 封装爬电距离和间> 8mm  
• 工作结温范围-40°C +150°C  
2 应用  
• 适用EV 的牵引逆变器  
• 车载充电器和充电桩  
• 用HEV/EV 的直流/直流转换器  
3 说明  
UCC21737-Q1 是一款电隔离单通道栅极驱动器设计  
用于直流工作电压高达 2121V SiC MOSFET 和  
IGBT具有先进的保护功能、出色的动态性能和稳健  
性。该器件具有高±10A 的峰值拉电流和灌电流。  
本文档旨在为方便起见提供有TI 产品中文版本的信息以确认产品的概要。有关适用的官方英文版本的最新信息请访问  
www.ti.com其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前请务必参考最新版本的英文版本。  
English Data Sheet: SLUSEM3  
 
 
 
 
 
UCC21737-Q1  
ZHCSOE5B MARCH 2022 REVISED JANUARY 2023  
www.ti.com.cn  
Table of Contents  
7.6 ASC Support.............................................................20  
8 Detailed Description......................................................23  
8.1 Overview...................................................................23  
8.2 Functional Block Diagram.........................................24  
8.3 Feature Description...................................................24  
8.4 Device Functional Modes..........................................30  
9 Applications and Implementation................................31  
9.1 Application Information............................................. 31  
9.2 Typical Application.................................................... 31  
10 Power Supply Recommendations..............................43  
11 Layout...........................................................................44  
11.1 Layout Guidelines................................................... 44  
11.2 Layout Example...................................................... 45  
12 Device and Documentation Support..........................46  
12.1 Device Support....................................................... 46  
12.2 Documentation Support.......................................... 46  
12.3 支持资源..................................................................46  
12.4 Trademarks.............................................................46  
12.5 静电放电警告.......................................................... 46  
12.6 术语表..................................................................... 46  
13 Mechanical, Packaging, and Orderable  
1 特性................................................................................... 1  
2 应用................................................................................... 1  
3 说明................................................................................... 1  
4 Revision History.............................................................. 2  
5 Pin Configuration and Functions...................................3  
6 Specifications.................................................................. 4  
6.1 Absolute Maximum Ratings........................................ 4  
6.2 ESD Ratings............................................................... 4  
6.3 Recommended Operating Conditions.........................4  
6.4 Thermal Information....................................................5  
6.5 Power Ratings.............................................................5  
6.6 Insulation Specifications............................................. 5  
6.7 Safety Limiting Values.................................................6  
6.8 Electrical Characteristics.............................................7  
6.9 Switching Characteristics............................................9  
6.10 Insulation Characteristics Curves........................... 10  
6.11 Typical Characteristics.............................................11  
7 Parameter Measurement Information..........................15  
7.1 Propagation Delay.................................................... 15  
7.2 Input Deglitch Filter...................................................16  
7.3 Active Miller Clamp................................................... 17  
7.4 Undervoltage Lockout (UVLO)..................................17  
7.5 Overcurrent (OC) Protection.....................................20  
Information.................................................................... 46  
4 Revision History  
以前版本的页码可能与当前版本的页码不同  
Changes from Revision A (July 2022) to Revision B (January 2023)  
Page  
• 向“特性”添加了“功能安全质量管理型”要点................................................................................................ 1  
Changes from Revision * (March 2022) to Revision A (July 2022)  
Page  
• 将“预告信息”更改为“量产数据”.................................................................................................................. 1  
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UCC21737-Q1  
ZHCSOE5B MARCH 2022 REVISED JANUARY 2023  
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5 Pin Configuration and Functions  
APWM  
VCC  
RST/EN  
FLT  
ASC  
1
16  
15  
OC  
2
14  
13  
12  
11  
10  
9
COM  
3
OUTH  
4
RDY  
INÅ  
VDD  
5
OUTL  
6
CLMPE  
IN+  
7
GND  
VEE  
8
Not to scale  
5-1. UCC21737-Q1 DW SOIC (16) Top View  
5-1. Pin Functions  
PIN  
I/O(1)  
DESCRIPTION  
NAME  
NO.  
Active high to enable active short circuit function to force output high during system failure events. Tie to  
COM if unused.  
ASC  
1
I
OC  
2
3
4
I
Overcurrent detection pin for SenseFET, DESAT, and shunt resistor sensing. Tie to COM if unused.  
Common ground reference. Connect to emitter pin for IGBT and source pin for SiC-MOSFET  
Gate driver output pull up  
COM  
OUTH  
P
O
Positive supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate  
driver source peak current capability. Place decoupling capacitor close to the pin.  
VDD  
5
6
7
P
O
O
OUTL  
CLMPE  
Gate driver output pull down  
External active Miller clamp control. Connect this pin to the gate of the external Miller clamp MOSFET.  
Leave floating if unused.  
Negative supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified  
gate driver sink peak current capability. Place decoupling capacitor close to the pin.  
VEE  
8
P
GND  
IN+  
9
P
I
Input power supply and logic ground reference  
10  
11  
Noninverting gate driver control input. Tie to VCC if unused.  
Inverting gate driver control input. Tie to GND if unused.  
I
IN–  
Power good for VCC-GND, VDD-COM, and VEE-COM. RDY is open drain configuration and can be  
paralleled with other RDY signals.  
RDY  
FLT  
12  
13  
O
O
Active low fault alarm output upon overcurrent or short circuit. FLT is in open drain configuration and can be  
paralleled with other faults.  
The RST/EN serves two purposes:  
1) Enable or shutdown the output side. The FET is turned off by a regular turn-off if EN is set to low;  
2) Resets the OC condition signaled on FLT pin if RST/EN is set to low for more than 1000 ns. A reset of  
signal FLT is asserted at the rising edge of RST/EN.  
RST/EN  
14  
I
For automatic reset function, this pin only serves to enable or shutdown the output side. The FET is turned  
off by a regular turn-off, if terminal EN is set to low. Tie to IN+ for automatic reset.  
Input power supply from 3 V to 5.5 V. Bypass with a >1-μF capacitor to GND. Place decoupling capacitor  
close to the pin.  
VCC  
15  
16  
P
APWM  
O
Isolated PWM output monitoring ASC pin status. Leave floating if unused.  
(1) P = Power, G = Ground, I = Input, O = Output  
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UCC21737-Q1  
ZHCSOE5B MARCH 2022 REVISED JANUARY 2023  
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6 Specifications  
6.1 Absolute Maximum Ratings  
Over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
0.3  
MAX  
UNIT  
V
VCC  
VDD  
VEE  
VMAX  
VCC - GND  
6
36  
VDD - COM  
V
0.3  
VEE - COM  
0.3  
V
17.5  
VDD - VEE  
36  
V
0.3  
DC  
VCC  
VCC+5.0  
6
V
GND0.3  
GND5.0  
0.3  
IN+, IN-, RST/EN  
Transient, less than 100 ns (2)  
Reference to COM  
Reference to COM  
DC  
V
ASC  
OC  
V
6
V
0.3  
VDD  
VDD+5.0  
5
V
VEE0.3  
VEE5.0  
0.3  
OUTH, OUTL  
Transient, less than 100 ns (2)  
Reference to VEE  
V
CLMPE  
V
RDY, FLT, APWM  
VCC  
20  
V
GND0.3  
IFLT, IRDY  
IAPWM  
TJ  
FLT and RDY pin input current  
APWM pin output current  
Junction Temperature  
mA  
mA  
°C  
°C  
20  
150  
40  
65  
Tstg  
Storage Temperature  
150  
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply  
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If  
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and  
this may affect device reliability, functionality, performance, and shorten the device lifetime  
(2) Values are verified by characterization on bench.  
6.2 ESD Ratings  
VALUE  
UNIT  
Human body model (HBM), per AEC Q100-002(1)  
HBM ESD classification level 3A  
±4000  
V(ESD)  
Electrostatic discharge  
V
Charged-device model (CDM), per AEC Q100-011  
CDM ESD classification level C6  
±1500  
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.  
6.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
3
MAX  
UNIT  
V
VCC  
VDD  
VEE  
VMAX  
VCC-GND  
5.5  
33  
VDD-COM  
13  
V
VEE-COM  
-16  
-3.5  
V
VDD-VEE  
33  
V
Reference to GND, High level input voltage  
Reference to GND, Low level input voltage  
Reference to COM  
0.7xVCC  
VCC  
0.3xVCC  
5
V
IN+, IN-,  
RST/EN  
0
0
V
ASC  
tRST/EN  
TA  
V
Minimum pulse width that reset the fault  
Ambient temperature  
1000  
40  
ns  
°C  
125  
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6.3 Recommended Operating Conditions (continued)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
MAX  
UNIT  
TJ  
Junction temperature  
150  
°C  
40  
6.4 Thermal Information  
UCC21737-Q1  
DW (SOIC)  
16 PINS  
68.3  
THERMAL METRIC(1)  
UNIT  
RθJA  
RθJC(top)  
RθJB  
ΨJT  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
27.5  
32.9  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
14.1  
32.3  
ΨJB  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
6.5 Power Ratings  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
985  
20  
UNIT  
mW  
mW  
mW  
PD  
Maximum power dissipation (both sides)  
Maximum power dissipation (side-1)  
Maximum power dissipation (side-2)  
VCC = 5V, VDD-COM = 20V, COM-VEE =  
5V, IN+/= 5V, 150kHz, 50% Duty Cycle  
for 10nF load, Ta = 25℃  
PD1  
PD2  
965  
6.6 Insulation Specifications  
PARAMETER  
GENERAL  
TEST CONDITIONS  
VALUE  
UNIT  
CLR  
CPG  
External clearance(1)  
Shortest terminal-to-terminal distance through air  
> 8  
> 8  
mm  
mm  
Shortest terminal-to-terminal distance across the  
package surface  
External creepage(1)  
DTI  
CTI  
Distance through the insulation  
Comparative tracking index  
Material Group  
Minimum internal gap (internal clearance)  
DIN EN 60112 (VDE 0303-11); IEC 60112  
According to IEC 606641  
> 17  
> 600  
I
µm  
V
I-IV  
I-IV  
I-III  
Rated mains voltage 300 VRMS  
Rated mains voltage 600 VRMS  
Rated mains voltage 1000 VRMS  
Overvoltage Category per IEC 606641  
DIN V VDE 0884-11 (VDE V 0884-11): 2017-01(2)  
VIORM  
Maximum repetitive peak isolation voltage  
AC voltage (bipolar)  
2121  
1500  
VPK  
AC voltage (sine wave); time-dependent dielectric  
breakdown (TDDB) test  
VRMS  
VIOWM  
Maximum isolation working voltage  
DC voltage  
2121  
8000  
VDC  
VPK  
VTEST = VIOTM, t = 60 s (qualification test)  
VIOTM  
Maximum transient isolation voltage  
Maximum surge isolation voltage(3)  
VTEST= 1.2 × VIOTM, t = 1 s (100% production  
test)  
8000  
8000  
VPK  
Test method per IEC 62368-1, 1.2/50 µs  
waveform, VTEST = 1.6 × VIOSM = 12800 VPK  
(qualification)  
VIOSM  
VPK  
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UNIT  
6.6 Insulation Specifications (continued)  
PARAMETER  
TEST CONDITIONS  
VALUE  
Method a: After I/O safety test subgroup 2/3, Vini  
=VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545  
VPK, tm = 10 s  
5  
Method a: After environmental tests subgroup  
1,Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM  
3394 VPK, tm = 10 s  
qpd  
Apparent charge(4)  
=
pC  
5  
Method b1: At routine test (100% production) and  
preconditioning (type test), Vini = VIOTM, tini = 1 s;  
Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s  
5  
CIO  
RIO  
Barrier capacitance, input to output(5)  
Insulation resistance, input to output(5)  
~ 1  
pF  
VIO = 0.5 × sin (2πft), f = 1 MHz  
VIO = 500 V, TA = 25°C  
1012  
1011  
109  
2
VIO = 500 V, 100°C TA 125°C  
VIO = 500 V at TS = 150°C  
Ω
Pollution degree  
Climatic category  
40/125/21  
UL 1577  
VTEST = VISO = 5700 VRMS, t = 60 s (qualification),  
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%  
production)  
VISO  
Withstand isolation voltage  
5700  
VRMS  
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be  
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the  
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques  
such as inserting grooves and ribs on the PCB are used to help increase these specifications.  
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured  
by means of suitable protective circuits.  
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.  
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).  
(5) All pins on each side of the barrier tied together creating a two-pin device.  
6.7 Safety Limiting Values  
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure  
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to  
overheatthe die and damage the isolation barrier, potentially leading to secondary system failures.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
R
θJA = 68.3°C/W, VDD = 15 V, VEE = -5V,  
61  
TJ = 150°C, TA = 25°C  
θJA = 68.3°C/W, VDD = 20 V, VEE = -5V,  
TJ = 150°C, TA = 25°C  
θJA = 68.3°C/W, VDD = 20 V, VEE = -5V,  
TJ = 150°C, TA = 25°C  
IS  
Safety input, output, or supply current  
mA  
R
49  
R
PS  
TS  
Safety input, output, or total power  
Maximum safety temperature  
1220  
150  
mW  
°C  
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ , specified for the device. The IS  
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be  
exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RqJA, in the Thermal Information  
table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value  
for each parameter: TJ = TA + RqJA ´ P, where P is the power dissipated in the device. TJ(max) = TS = TA + RqJA ´ PS, where TJ(max) is the  
maximum allowed junction temperature. PS = IS ´ VI , where VI is the maximum supply voltage.  
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6.8 Electrical Characteristics  
VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDDCOM = 20 V, 18 V or 15 V, COMVEE = 5 V, 8 V or 15 V,  
CL = 100pF, 40°C<TJ<150°C (unless otherwise noted)(1)(2)  
.
Parameter  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
VCC UVLO THRESHOLD AND DELAY  
VVCC_ON  
2.55  
2.35  
2.7  
2.5  
0.2  
10  
2.85  
2.65  
V
V
VVCC_OFF  
VVCC_HYS  
tVCCFIL  
VCC - GND  
V
VCC UVLO deglitch time  
µs  
µs  
µs  
µs  
µs  
tVCC+ to OUT  
tVCC- to OUT  
tVCC+ to RDY  
tVCC- to RDY  
VCC UVLO on delay to output high  
VCC UVLO off delay to output low  
VCC UVLO on delay to RDY high  
VCC UVLO off delay to RDY low  
28  
5
37.8  
10  
55  
15  
55  
15  
IN+ = VCC, IN= GND  
30  
5
37.8  
10  
RST/EN = VCC  
VDD UVLO THRESHOLD AND DELAY  
VVDD_ON  
10.5  
9.9  
11.4  
10.6  
0.8  
5
12.8  
11.8  
V
V
VVDD_OFF  
VVDD_HYS  
tVDDFIL  
VDD - COM  
V
VDD UVLO deglitch time  
µs  
µs  
µs  
µs  
µs  
tVDD+ to OUT  
tVDD- to OUT  
tVDD+ to RDY  
tVDD- to RDY  
VDD UVLO on delay to output high  
VDD UVLO off delay to output low  
VDD UVLO on delay to RDY high  
VDD UVLO off delay to RDY low  
2
5
15  
15  
15  
15  
IN+ = VCC, IN= GND  
5
10  
10  
RST/EN = VCC  
VEE UVLO THRESHOLD AND DELAY  
VVEE_ON  
-3.5  
-3.0  
-3.1  
-2.6  
-0.5  
5
-2.7  
-2.2  
V
V
VVEE_OFF  
VVEE_HYS  
tVEEFIL  
VEE - COM  
V
VEE UVLO deglitch time  
µs  
µs  
µs  
µs  
µs  
tVEE+ to OUT  
tVEE- to OUT  
tVEE+ to RDY  
tVEE- to RDY  
VEE UVLO on delay to output high  
VEE UVLO off delay to output low  
VEE UVLO on delay to RDY high  
VEE UVLO off delay to RDY low  
8
15  
15  
25  
25  
IN+ = VCC, IN= GND  
5
10  
12  
RST/EN = VCC  
VCC, VDD QUIESCENT CURRENT  
OUT(H) = High, fS = 0Hz  
2.5  
1.45  
2.4  
3
2
4
2.75  
5.3  
mA  
mA  
mA  
mA  
µA  
IVCCQ  
IVDDQ  
IVEEQ  
VCC quiescent current  
OUT(L) = Low, fS = 0Hz  
OUT(H) = High, fS = 0Hz  
3.1  
VDD quiescent current  
VEE quiescent current  
OUT(L) = Low, fS = 0Hz  
2.2  
2.9  
4.7  
OUT(H) = High, fS = 0Hz, VEE = -3.5V  
OUT(L) = Low, fS = 0Hz, VEE = -3.5V  
-830  
-830  
-630  
-630  
-430  
-430  
µA  
LOGIC INPUTS - IN+, IN- and RST/EN  
VINH  
VINL  
VINHYS  
IIH  
Input high threshold  
Input low threshold  
1.85  
1.52  
0.33  
90  
2.31  
V
V
VCC=3.3V  
0.99  
Input threshold hysteresis  
V
Input high level input leakage current VIN = VCC  
uA  
uA  
kΩ  
kΩ  
IIL  
Input low level input leakage current  
Input pins pull down resistance  
Input pins pull up resistance  
VIN = GND  
-90  
55  
RIND  
RINU  
55  
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6.8 Electrical Characteristics (continued)  
VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDDCOM = 20 V, 18 V or 15 V, COMVEE = 5 V, 8 V or 15 V,  
CL = 100pF, 40°C<TJ<150°C (unless otherwise noted)(1)(2)  
.
Parameter  
TEST CONDITIONS  
MIN  
28  
TYP  
40  
MAX UNIT  
IN+, INand RST/EN deglitch (ON  
and OFF) filter time  
TINFIL  
fS = 50kHz  
60  
ns  
ns  
TRSTFIL  
Deglitch filter time to reset FLT  
500  
650  
800  
GATE DRIVER STAGE  
IOUTH Peak source current  
IOUTL  
10  
10  
A
A
CL = 0.18µF, fS = 1kHz  
Peak sink current  
(3)  
ROUTH  
ROUTL  
VOUTH  
VOUTL  
Output pull-up resistance  
Output pull-down resistance  
High level output voltage  
Low level output voltage  
IOUTH = -0.1A  
2.5  
0.3  
17.5  
60  
Ω
Ω
IOUTL = 0.1A  
IOUTH = -0.2A, VDD = 18V  
IOUTL= 0.2A  
V
mV  
ACTIVE PULLDOWN  
IOUTL(typ) = 0.1×IOUTL(typ)  
VDD=OPEN, VEE=COM  
,
VOUTPD  
Output active pull down on OUTL  
1.5  
2.0  
2.5  
V
EXTERNAL ACTIVE MILLER CLAMP  
VCLMPTH  
VCLMPE  
ICLMPEH  
ICLMPEL  
tCLMPER  
tDCLMPE  
Miller clamp threshold voltage  
1.5  
4.8  
2.0  
5
2.5  
5.3  
V
V
Reference to VEE  
CCLMPE = 10nF  
CCLMPE = 330pF  
Output high voltage  
Peak source current  
Peak sink current  
Rising time  
0.12  
0.12  
0.25  
0.25  
20  
A
0.37  
40  
A
ns  
ns  
Miller clamp ON delay time  
40  
70  
SHORT CIRCUIT CLAMPING  
OUT = High, IOUT(H) = 500mA,  
tCLP=10µs  
VCLP-OUT(H)  
VCLP-OUT(L)  
0.9  
1.8  
V
V
V
V
OUTHVDD  
OUTLVDD  
OUT = High, IOUT(L) = 500mA,  
tCLP=10µs  
OC PROTECTION  
IDCHG  
OC pull down current  
VOC = 1V  
40  
0.7  
mA  
V
VOCTH  
Detection threshold  
0.63  
0.77  
VOCL  
Voltage when OUTL = Low  
OC fault deglitch filter  
Reference to COM, IOC = 5mA  
0.13  
120  
270  
530  
V
tOCFIL  
95  
150  
300  
180  
400  
750  
ns  
ns  
ns  
tOCOFF  
OC propagation delay to OUTL 90%  
OC to FLT low delay  
tOCFLT  
INTERNAL SOFT TURN OFF  
ISTO Soft turn-off current on fault condition VDD-VEE = 20 V, OUTL = 8 V  
ACTIVE SHORT CIRCUIT (ASC)  
500  
900  
1200  
mA  
VASCL  
ASC input low threshold  
1.35  
2.7  
1.5  
2.9  
1.71  
3.17  
1120  
477  
V
V
VASCH  
ASC input high threshold  
tASC_r  
ASC to output rising edge delay  
ASC to output falling edge delay  
390  
152  
660  
300  
ns  
ns  
tASC_f  
APWM Monitor  
fAPWM  
APWM output frequency  
APWM duty cycle  
VASC=2.5V  
VASC=0.6V  
VASC=2.5V  
VASC=4.5V  
360  
9
400  
11.5  
50  
440  
13.5  
51.5  
92.5  
kHz  
%
DAPWM  
48.5  
87.5  
%
90  
%
FLT AND RDY REPORTING  
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6.8 Electrical Characteristics (continued)  
VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDDCOM = 20 V, 18 V or 15 V, COMVEE = 5 V, 8 V or 15 V,  
CL = 100pF, 40°C<TJ<150°C (unless otherwise noted)(1)(2)  
.
Parameter  
TEST CONDITIONS  
MIN  
0.55  
0.55  
TYP  
MAX UNIT  
VDD UVLO RDY low minimum holding  
time  
tRDYHLD  
1
1
ms  
ms  
tFLTMUTE  
RODON  
VODL  
Output mute time on fault  
Reset fault through RST/EN  
IODON = 5mA  
Open drain output on resistance  
Open drain low output voltage  
30  
0.3  
V
COMMON MODE TRANSIENT IMMUNITY  
CMTI Common-mode transient immunity  
150  
V/ns  
(1) Currents are positive into and negative out of the specified terminal.  
(2) All voltages are referenced to COM unless otherwise notified.  
(3) For internal PMOS only. Refer to Driver Stage for effective pull-up resistance.  
6.9 Switching Characteristics  
VCC = 5.0 V, 1-µF capacitor from VCC to GND, VDD - COM = 20V, 18V or 15V, COM - VEE = 3 V, 5 V or 8 V, CL = 100pF,  
-40<TJ<150(unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
60  
TYP  
90  
MAX  
130  
130  
30  
UNIT  
ns  
tPDLH  
tPDHL  
PWD  
tsk-pp  
tr  
Propagation delay time low-to-high  
Propagation delay time low-to-high  
60  
90  
ns  
Pulse width distortion (tPDHL-tPDLH  
)
ns  
Part to part skew  
Rising or falling propagation delay  
CL = 10nF  
30  
ns  
Driver output rise time  
33  
27  
ns  
tf  
Driver output fall time  
CL = 10nF  
ns  
fMAX  
Maximum switching frequency  
1
MHz  
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6.10 Insulation Characteristics Curves  
80  
1400  
1200  
1000  
800  
600  
400  
200  
0
VDD=15V; VEE=-5V  
VDD=20V; VEE=-5V  
60  
40  
20  
0
0
25  
50  
75  
100  
125  
150  
0
20  
40  
60  
80  
100  
120  
140  
160  
Ambient Temperature (oC)  
Ambient Temperature (oC)  
Safe  
Safe  
6-1. Thermal Derating Curve for Limiting Current per VDE  
6-2. Thermal Derating Curve for Limiting Power per VDE  
1.E+12  
1.E+11  
1.E+10  
54 Yrs  
1.E+09  
1.E+08  
1.E+07  
TDDB Line (< 1 ppm Fail Rate)  
1.E+06  
1.E+05  
1.E+04  
1.E+03  
1.E+02  
1.E+01  
VDE Safety Margin Zone  
1800VRMS  
2200  
200  
1200  
3200  
4200  
5200  
6200  
Applied Voltage (VRMS  
)
6-3. Reinforced Isolation Capacitor Lifetime Projection  
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6.11 Typical Characteristics  
22  
20  
18  
16  
14  
12  
10  
8
22  
20  
18  
16  
14  
12  
10  
8
6
6
4
4
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (C)  
Temperature (C)  
VDD = 20 V, VEE = 5 V  
VDD = 20 V, VEE = 5 V  
6-4. Output High Drive Current vs Temperature  
6-5. Output Low Driver Current vs Temperature  
6
4
VCC = 3.3V  
VCC = 5V  
VCC = 3.3V  
VCC = 5V  
5.5  
3.5  
5
4.5  
4
3
2.5  
2
3.5  
1.5  
3
1
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
D015  
D014  
IN+ = High  
IN- = Low  
IN+ = Low  
IN- = Low  
6-6. IVCCQ Supply Current vs Temperature  
6-7. IVCCQ Supply Current vs Temperature  
5
4.5  
4
6
5.5  
5
VCC = 3.3V  
VCC = 5V  
4.5  
4
3.5  
3
3.5  
3
2.5  
2
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (C)  
30  
70  
110  
150  
190  
230  
270  
310  
Frequency (kHz)  
IN+ = High, IN- = Low  
VDD = 20 V, VEE = 5 V  
6-8. IVCCQ Supply Current vs Input Frequency  
6-9. IVDDQ Supply Current vs Temperature  
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6.11 Typical Characteristics  
6
10  
9
5.5  
5
8
7
4.5  
4
6
5
4
3.5  
3
3
2
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
30  
70  
110  
150  
190  
230  
270  
310  
Temperature (C)  
Frequency (kHz)  
IN+ = Low, IN- = Low  
VDD = 20 V, VEE = 5 V  
VDD/VEE = 20 V/5 V  
6-11. IVDDQ Supply Current vs Input Frequency  
6-10. IVDDQ Supply Current vs Temperature  
4
3.5  
3
14  
13.5  
13  
12.5  
12  
2.5  
2
11.5  
11  
10.5  
10  
1.5  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
D002  
D001  
6-13. VDD UVLO vs Temperature  
6-12. VCC UVLO vs Temperature  
100  
90  
80  
70  
60  
50  
100  
90  
80  
70  
60  
50  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
D022  
D021  
VCC = 3.3 V  
VDD = 18 V  
CL = 100 pF  
VCC = 3.3 V  
VDD = 18 V  
CL = 100 pF  
RON = 0 Ω  
ROFF = 0 Ω  
RON = 0 Ω  
ROFF = 0 Ω  
6-15. Propagation Delay tPDHL vs Temperature  
6-14. Propagation Delay tPDLH vs Temperature  
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6.11 Typical Characteristics  
60  
60  
50  
40  
30  
20  
10  
50  
40  
30  
20  
10  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
D023  
D024  
VCC = 3.3 V  
VDD = 18 V  
CL = 10 nF  
VCC = 3.3 V  
VDD = 18 V  
CL = 10 nF  
RON = 0 Ω  
ROFF = 0 Ω  
RON = 0 Ω  
ROFF = 0 Ω  
6-16. tr Rise Time vs Temperature  
6-17. tf Fall Time vs Temperature  
3
2.75  
2.5  
2.5  
2.25  
2
1.75  
1.5  
1.25  
1
2.25  
2
1.75  
1.5  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
D025  
D008  
6-19. VCLP-OUT(H) Short Circuit Clamping Voltage vs  
6-18. VOUTPD Output Active Pulldown Voltage vs Temperature  
Temperature  
2
1.75  
1.5  
3
2.75  
2.5  
1.25  
1
2.25  
2
0.75  
0.5  
1.75  
0.25  
1.5  
50  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
70  
90  
110  
130  
150 160  
D026  
Temperature (èC)  
D009  
6-20. VCLP-OUT(L) Short Circuit Clamping Voltage vs  
6-21. VCLMPTH Miller Clamp Threshold Voltage vs  
Temperature  
Temperature  
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6.11 Typical Characteristics  
400  
70  
60  
50  
40  
30  
350  
300  
250  
200  
150  
100  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
D010  
D011  
6-22. ICLMPEL Miller Clamp Sink Current vs Temperature  
6-23. tDCLMPE Miller Clamp ON Delay Time vs Temperature  
1
0.8  
0.6  
0.4  
0.2  
-60 -40 -20  
0
20 40 60 80 100 120 140 160  
Temperature (èC)  
D003  
6-24. VOCTH OC Detection Threshold vs Temperature  
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7 Parameter Measurement Information  
7.1 Propagation Delay  
7.1.1 Regular Turn-OFF  
7-1 shows the propagation delay measurement for noninverting configurations. 7-2 shows the propagation  
delay measurement with the inverting configurations.  
50%  
50%  
IN+  
INÅ  
tPDLH  
tPDHL  
90%  
10%  
OUT  
7-1. Noninverting Logic Propagation Delay Measurement  
IN+  
INÅ  
50%  
50%  
tPDLH  
tPDHL  
90%  
OUT  
10%  
7-2. Inverting Logic Propagation Delay Measurement  
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7.2 Input Deglitch Filter  
In order to increase the robustness of gate driver over noise transient and accidental small pulses on the input  
pins; that is, IN+, IN, RST/EN, a 40-ns deglitch filter is designed to filter out the transients and make sure there  
is no faulty output responses or accidental driver malfunctions. When the IN+ or INPWM pulse is smaller than  
the input deglitch filter width, TINFIL, there will be no responses on OUT drive signal. 7-3 and 7-4 show the  
IN+ pin ON and OFF pulse deglitch filter effect. 7-5 and 7-6 show the INpin ON and OFF pulse deglitch  
filter effect.  
IN+  
tPWM < TINFIL  
tPWM < TINFIL  
IN+  
INÅ  
INÅ  
OUT  
OUT  
7-3. IN+ ON Deglitch Filter  
7-4. IN+ OFF Deglitch Filter  
IN+  
IN+  
INÅ  
tPWM < TINFIL  
tPWM < TINFIL  
INÅ  
OUT  
OUT  
7-5. INON Deglitch Filter  
7-6. INOFF Deglitch Filter  
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7.3 Active Miller Clamp  
7.3.1 External Active Miller Clamp  
An active Miller clamp can help add an additional low impedance path to bypass the Miller current and prevent  
the high dV/dt introduced unintentional turn-on through the Miller capacitance. Different from the internal active  
Miller clamp, an external active Miller clamp function is used for applications where the gate driver may not be  
close to the power device or power module due to system layout considerations. An external active Miller clamp  
function provides a 5-V gate drive signal to turn on the external Miller clamp FET when the gate driver voltage is  
less than the Miller clamp threshold, VCLMPTH. 7-7 shows the timing diagram for the external active Miller  
clamp function.  
(IN+Å INÅ)  
IN  
VDD  
tDCLMPE  
OUT  
VCLMPTH  
COM  
VEE  
HIGH  
90%  
tCLMPER  
LOW  
10%  
CLMPE  
7-7. Timing Diagram for External Active Miller Clamp Function  
7.4 Undervoltage Lockout (UVLO)  
Undervoltage lockout (UVLO) is one of the key protection features designed to protect the system in case of bias  
supply failures on VCC, the primary side power supply, and VDD or VEE, the secondary side power supplies.  
7.4.1 VCC UVLO  
The VCC UVLO protection details are discussed in this section. 7-8 shows the timing diagram illustrating the  
definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AINAPWM.  
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IN  
(IN+Å INÅ)  
tVCCFIL  
tVCCÅ to OUT  
VVCC_ON  
VCC  
VDD  
VVCC_OFF  
COM  
VEE  
tVCC+ to OUT  
90%  
VCLMPTH  
OUT  
10%  
tVCC+ to RDY  
tRDYHLD  
tVCCÅ to RDY  
Hi-Z  
RDY  
7-8. VCC UVLO Protection Timing Diagram  
7.4.2 VDD UVLO  
The VDD UVLO protection details are discussed in this section. 7-9 shows the timing diagram illustrating the  
definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AINAPWM.  
IN  
(IN+Å INÅ)  
tVDDFIL  
VDD  
tVDDÅ to OUT  
VVDD_ON  
VVDD_OFF  
COM  
VEE  
VCC  
tVDD+ to OUT  
VCLMPTH  
OUT  
90%  
tRDYHLD  
10%  
tVDD+ to RDY  
tVDDÅ to RDY  
RDY  
Hi-Z  
7-9. VDD UVLO Protection Timing Diagram  
7.4.3 VEE UVLO  
The VEE UVLO protection details are discussed in this section. 7-10 shows the timing diagram illustrating the  
definition of UVLO ON/OFF threshold, deglitch filter, response time, and RDY.  
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IN  
(IN+Å INÅ)  
tVEEÅ to OUT  
VDD  
tVEEFIL  
COM  
VEE  
VVEE_OFF  
VVEE_ON  
VCC  
90%  
tVEE+ to OUT  
OUT  
RDY  
VCLMPTH  
10%  
tVEEÅ to RDY  
tVEE+ to RDY  
tRDYHLD  
Hi-Z  
7-10. VEE UVLO Protection Timing Diagram  
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7.5 Overcurrent (OC) Protection  
7.5.1 OC Protection with Soft Turn-OFF  
OC protection is used to sense the current of the SiC-MOSFETs and IGBTs under overcurrent or shoot-through  
condition. 7-11 shows the timing diagram of OC operation with soft turn-off.  
IN  
(”IN+Å ”INÅ)  
tOCFIL  
VOCTH  
OC  
tOCOFF  
90%  
GATE  
VCLMPTH  
tOCFLT  
tFLTMUTE  
Hi-Z  
FLT  
tRSTFIL  
tRSTFIL  
RST/EN  
HIGH  
Hi-Z  
OUTH  
OUTL  
LOW  
Hi-Z  
LOW  
7-11. OC Protection with Soft Turn-OFF  
7.6 ASC Support  
When the ASC pin receives a logic high signal, the output is forced high regardless of the input side pin  
conditions. The ASC function has higher priority than the input signal and VCC UVLO. The priority of VDD and  
VEE UVLO, and the overcurrent fault event are higher than the ASC function.  
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(IN+Å INÅ)  
IN  
VVCC_ON  
VCC  
VDD  
VVCC_OFF  
COM  
VEE  
tVCC- to RDY  
tVCC+ to RDY  
RDY  
ASC  
tASC_r  
tASC_f  
OUT  
7-12. ASC Support with VCC UVLO  
(IN+Å INÅ)  
IN  
VCC  
VDD  
VVDD_ON  
VVDD_OFF  
COM  
VEE  
tVDD- to RDY  
tVDD+ to RDY  
RDY  
ASC  
tVDD- to OUT  
tASC_r  
tVDD+ to OUT  
tASC_f  
OUT  
7-13. ASC Support with VDD UVLO  
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(IN+Å INÅ)  
IN  
tOCFIL  
VOCTH  
OC  
tOCFLT  
FLT  
RST/EN  
ASC  
tOCOFF  
90%  
GATE  
7-14. ASC Support with OC Fault  
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8 Detailed Description  
8.1 Overview  
The UCC21737-Q1 device is an advanced isolated gate driver with state-of-art protection and sensing features  
for SiC MOSFETs and IGBTs. The device can support up to 2121-V DC operating voltage based on SiC  
MOSFETs and IGBTs, and can be used to above 10-kW applications such as HEV/EV traction inverter, motor  
drive, on-board and off-board battery charger, solar inverter, and so forth. The galvanic isolation is implemented  
by the capacitive isolation technology, which can realize a reliable reinforced isolation between the low voltage  
DSP/MCU and high voltage side.  
The ±10-A peak sink and source current of the UCC21737-Q1 can drive the SiC MOSFET modules and IGBT  
modules directly without an extra buffer. The driver can also be used to drive higher power modules or parallel  
modules with external buffer stage. The input side is isolated with the output side with a reinforced isolation  
barrier based on capacitive isolation technology. The device can support up to 1.5-kVRMS working voltage, 12.8-  
kVPK surge immunity with longer than 40 years isolation barrier life. The strong drive strength helps to switch the  
device fast and reduce the switching loss, while the 150V/ns minimum CMTI ensures the reliability of the system  
with fast switching speed. The small propagation delay and part-to-part skew can minimize the deadtime setting,  
so the conduction loss can be reduced.  
The device includes extensive protection and monitor features to increase the reliability and robustness of the  
SiC MOSFET and IGBT based systems. The 12-V output side power supply UVLO is suitable for switches with  
gate voltage 15 V. The active Miller clamp feature prevents the false turn on caused by Miller capacitance  
during fast switching. An external Miller clamp FET can be used, providing more versatility to the system design.  
The device has a state-of-art overcurrent and short circuit detection time, and fault reporting function to the low  
voltage side DSP/MCU. The soft turn off is triggered when the overcurrent or short circuit fault is detected,  
minimizing the short circuit energy while reducing the overshoot voltage on the switches.  
The active short circuit feature can create a phase-to-phase short circuit for a three-phase inverter, which is  
useful for motor drive applications to protect the battery if the microcontroller loses control.  
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8.2 Functional Block Diagram  
CLAMPE  
OUTH  
7
4
6
10  
11  
15  
9
IN+  
INt  
PWM Inputs  
MOD  
DEMOD  
Output Stage  
t
ON/OFF Control  
STO  
VCC  
OUTL  
VDD  
VCC  
UVLO  
VCC Supply  
5
GND  
RDY  
UVLO  
LDO[s for VEE,  
COM and channel  
3
8
COM  
VEE  
OC  
12  
13  
14  
16  
Fault Decode  
FLT  
OCP  
2
Fault Encode  
RST/EN  
ASC Circuit  
PWM Driver  
ASC  
1
APWM  
DEMOD  
MOD  
8.3 Feature Description  
8.3.1 Power Supply  
The input side power supply VCC can support a wide voltage range from 3 V to 5.5 V. The device supports a  
bipolar power supply on the output side with a wide range from 13 V to 33 V from VDD to VEE. The negative  
power supply with respect to switch source or emitter is usually adopted to avoid false turn on when the other  
switch in the phase leg is turned on. The negative voltage is especially important for SiC MOSFET due to its fast  
switching speed.  
8.3.2 Driver Stage  
The UCC21737-Q1 has ±10-A peak drive strength and is suitable for high power applications. The high drive  
strength can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without an extra  
buffer stage. The UCC21737-Q1 can also be used to drive higher power modules or parallel modules with an  
extra buffer stage. Regardless of the values of VDD, the peak sink and source current can be kept at 10 A. The  
driver features an important safety function wherein, when the input pins are floating, the OUTH/OUTL is held  
low. The split output of the driver stage is depicted in 8-1. The driver has rail-to-rail output by implementing a  
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hybrid pullup structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and an N-Channel  
MOSFET to pulldown. The pullup NMOS is the same as the pulldown NMOS, so the on resistance RNMOS is the  
same as ROL. The hybrid pullup structure delivers the highest peak-source current when it is most needed,  
during the Miller plateau region of the power semiconductor turn-on transient. The ROH in 8-1 represents the  
on-resistance of the pullup P-Channel MOSFET. However, the effective pullup resistance is much smaller than  
ROH. Since the pullup N-Channel MOSFET has much smaller on-resistance than the P-Channel MOSFET, the  
pullup N-Channel MOSFET dominates most of the turn-on transient, until the voltage on OUTH pin is about 3V  
below VDD voltage. The effective resistance of the hybrid pullup structure during this period is about 2 x ROL  
.
Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pullup impedance results in  
strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of  
the power semiconductor and reduces the turn-on switching loss.  
The pulldown structure of the driver stage is implemented solely by a pulldown N-Channel MOSFET. This  
MOSFET can ensure the OUTL voltage be pulled down to VEE rail. The low pulldown impedance not only  
results in high sink current to reduce the turn-off time, but also helps to increase the noise immunity considering  
the Miller effect.  
VDD  
ROH  
RNMOS  
OUTH  
Input  
Signal  
Anti Shoot-  
through  
Circuitry  
OUTL  
ROL  
8-1. Gate Driver Output Stage  
8.3.3 VCC, VDD, and VEE Undervoltage Lockout (UVLO)  
The UCC21737-Q1 implements the internal UVLO protection feature for both input and output power supplies  
VCC and VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW.  
The output only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature  
not only reduces the power consumption of the driver itself during low power supply voltage condition, but also  
increases the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the  
gate-source voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD  
value, the conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the  
power stage. The UCC21737-Q1 implements a 12-V threshold voltage of VDD UVLO, with 800-mV hysteresis; a  
-3-V threshold voltage of VEE UVLO, with 400-mV hysteresis. This threshold voltage is suitable for both SiC  
MOSFET and IGBT.  
The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity  
of the power supply. During the turn-on and turn-off switching transient, the driver sources and sinks a peak  
transient current from the power supply, which can result in a sudden voltage drop of the power supply. With  
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hysteresis and UVLO deglitch filter, the internal UVLO protection block ignores small noises during the normal  
switching transients.  
The timing diagrams of the UVLO feature of VCC, VDD, and VEE are shown in 7-8, 7-9, and 7-10. The  
RDY pin on the input side is used to indicate the power-good condition. The RDY pin is open drain. During  
UVLO condition, the RDY pin is held in low status and connected to GND. Normally the pin is pulled up  
externally to VCC to indicate the power good.  
8.3.4 Active Pulldown  
The UCC21737-Q1 implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE  
when the VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active  
pulldown feature can prevent the output being falsely turned on before the device is back to control.  
VDD  
OUTL  
Ra  
Control  
Circuit  
VEE  
COM  
8-2. Active Pulldown  
8.3.5 Short Circuit Clamping  
During a short circuit condition, the Miller capacitance can cause a current sinking to the OUTH/OUTL pin due to  
the high dV/dt and boost the OUTH/OUTL voltage. The short circuit clamping feature of the UCC21737-Q1 can  
clamp the OUTH/OUTL pin voltage to be slightly higher than VDD, which can protect the power semiconductors  
from a gate-source and gate-emitter overvoltage breakdown. This feature is realized by an internal diode from  
the OUTH/OUTL to VDD.  
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VDD  
D1 D2  
OUTH  
OUTL  
Control  
Circuitry  
8-3. Short Circuit Clamping  
8.3.6 External Active Miller Clamp  
The active Miller clamp feature is important to prevent the false turn-on while the driver is in the OFF state. In  
applications in which the device can be in synchronous rectifier mode, the body diode conducts the current  
during the dead time while the device is in the OFF state, the drain-source or collector-emitter voltage remains  
the same and the dV/dt happens when the other power semiconductor of the phase leg turns on. The low  
internal pulldown impedance of the UCC21737-Q1 can provide a strong pull down to hold OUTL to VEE.  
However, external gate resistance is usually adopted to limit the dV/dt. The Miller effect during the turn-on  
transient of the other power semiconductor can cause a voltage drop on the external gate resistor, which boosts  
the gate-source or gate-emitter voltage. If the voltage on VGS or VGE is higher than the threshold voltage of the  
power semiconductor, a shoot-through can happen and cause catastrophic damage. The active Miller clamp  
feature of the UCC21737-Q1 drives an external MOSFET, which connects to the device gate. The external  
MOSFET is triggered when the gate voltage is lower than VCLMPTH, which is 2 V above VEE, and creates a low  
impedance path to avoid the false turn-on issue.  
VCLMPTH  
VCC  
OUTH  
+
3V to 5.5V  
IN+  
œ
CLMPE  
OUTL  
Control  
Circuitry  
µC  
MOD  
DEMOD  
IN-  
VEE  
COM  
VCC  
8-4. Active Miller Clamp  
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8.3.7 Overcurrent and Short Circuit Protection  
The UCC21737-Q1 implements a fast overcurrent and short circuit protection feature to protect the SiC  
MOSFET or IGBT from catastrophic breakdown during fault. The OC pin of the device has a typical 0.7-V  
threshold with respect to COM, source or emitter of the power semiconductor. When the input is in floating  
condition, or the output is held in low state, the OC pin is pulled down by an internal MOSFET and held in LOW  
state, which prevents the overcurrent and short circuit fault from false triggering. The OC pin is in high-  
impedance state when the output is in high state, which means the overcurrent and short circuit protection  
feature only works when the power semiconductor is in ON state. The internal pulldown MOSFET helps to  
discharge the voltage of OC pin when the power semiconductor is turned off.  
The overcurrent and short circuit protection feature can be used to SiC MOSFET module or IGBT module with  
SenseFET, traditional desaturation circuit, and shunt resistor in series with the power loop for lower power  
applications. For the SiC MOSFET module or IGBT module with SenseFET, the SenseFET integrated in the  
module can scale down the drain current or collector current. With an external high precision sense resistor, the  
drain current or collector current can be accurately measured. If voltage of the sensed resistor higher than the  
overcurrent threshold VOCTH is detected, a soft turn-off is initiated. A fault is reported to the input side FLT pin to  
the DSP/MCU. The output is held to LOW after the fault is detected, and can only be reset by the RST/EN pin.  
The state-of-art overcurrent and short circuit detection time helps to ensure a short shutdown time for the SiC  
MOSFET and IGBT.  
The overcurrent and short circuit protection feature can also be paired with desaturation circuit and shunt  
resistors. The DESAT threshold can be programmable in this case, which increases the versatility of the device.  
Detailed application diagrams of the desaturation circuit and shunt resistor are given in 8-5.  
High current and high dI/dt during the overcurrent and short circuit fault can cause a voltage bounce on the  
shunt resistors parasitic inductance and board layout parasitic, which results in a false trigger of the OC  
pin. A high precision, low ESL, and small value resistor must be used in this approach.  
A shunt resistor approach is not recommended for high power applications and short circuit protection of low  
power applications.  
Detailed applications of the overcurrent and short circuit feature are discussed in 9.  
OUTL  
ROFF  
OC  
RFLT  
FLT  
+
DEMOD  
MOD  
+
RS  
CFLT  
VOCTH  
GND  
Control  
Logic  
COM  
VEE  
8-5. Overcurrent and Short Circuit Protection  
8.3.8 Soft Turn-off  
The UCC21737-Q1 initiates a soft turn-off when the overcurrent and short circuit protection are triggered, or  
when the RST/EN is pulled low for longer than tRSTPD. When the overcurrent and short circuit faults occur, the  
power semiconductor transitions from the linear region to the saturation region very quickly. The gate voltage  
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controls the channel current. By pulling down the gate voltage with a soft turn-off current, the dI/dt of the channel  
current is controlled by the gate voltage and decreases softly; thus, overshooting the power semiconductor is  
limited, preventing overvoltage breakdown. 7-11 shows the the soft turn-off timing diagram.  
UCC217xx  
SenseFET  
Kelvin connection  
OC  
+
Deglitch filter  
+
VOCTH  
RS  
C_FLT  
COM  
Control  
logic  
OUTL  
VEE  
Soft turn-off  
8-6. Soft Turn-off  
8.3.9 Fault (FLT), Reset, and Enable (RST/EN)  
The FLT pin is open drain and can report a fault signal to the DSP/MCU when overcurrent and short circuit faults  
are detected through the OC pin. The FLT pin is pulled down to GND, and is held in a low state unless a reset  
signal is received from RST/EN. The device has a fault mute time, tFLTMUTE, within which the device ignores any  
reset signal.  
RST/EN is pulled down internally. The device is disabled by default if the RST/EN pin is floating. The pin has two  
purposes:  
Resets the overcurrent and short circuit fault signaled on the FLT pin. The RST/EN pin is active low. If the pin  
is set and held in a low state for more than tRSTFIL, the fault signal is reset and FLT is reset back to the high  
impedance status at the rising edge of the RST/EN pin.  
Enables and shuts down the device. If the RST/EN pin is pulled low, the driver is disabled and shut down by  
the regular turn off. The pin must be pulled up externally to enable the part; otherwise, the device is disabled  
by default.  
8.3.10 ASC Support and APWM Monitor  
When VCC loses power, or the MCU is malfunctioning, the motor can lose control and reversely charge the  
battery. Overvoltage of the battery can cause battery break down, or even a fire hazard. In this case, the active  
short circuit (ASC) function is used to protect the system by forcing the output signal high, turning on the switch,  
and creating an active short circuit loop between the phases to bypass the battery. The timing diagram of ASC  
support with VCC UVLO, VDD UVLO, and OC fault are shown in 7-12, 7-13, and 7-14.  
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The UCC21737-Q1 encodes the voltage signal VASC to a PWM signal, passing through the reinforced isolation  
barrier, and output to the APWM pin on the input side. Thus, the ASC pin status can be monitored. The PWM  
signal can either be transferred directly to the DSP/MCU to calculate the duty cycle, or filtered by a simple RC  
filter as an analog signal. The ASC input voltage varies from 0 V to 5 V, and the corresponding duty cycle of the  
APWM output ranges from 5% to 95% with a 400-kHz frequency.  
8.4 Device Functional Modes  
8-1 lists the device function.  
8-1. Function Table  
INPUT  
OUTPUT  
OUTH/OUTL  
VCC  
X
VDD  
PU  
VEE  
PU  
PU  
PD  
X
IN+  
IN-  
X
RST/EN  
X
ASC  
High  
X
RDY  
X
FLT  
HiZ  
HiZ  
HiZ  
HiZ  
HiZ  
HiZ  
HiZ  
HiZ  
HiZ  
HiZ  
HiZ  
CLMPE  
Low  
X
X
High  
Low  
Low  
Low  
Low  
Low  
HiZ  
PU  
PU  
PU  
PD  
PU  
PU  
PU  
PU  
PU  
PU  
PD  
X
High  
High  
X
Low  
Low  
Low  
Low  
HiZ  
Low  
Low  
HiZ  
HiZ  
HiZ  
High  
High  
Low  
PU  
X
X
X
PD  
X
X
Low  
Low  
Low  
Low  
Low  
Low  
Low  
Low  
PU  
PU  
PU  
PU  
Open  
PU  
PU  
PU  
X
X
X
High  
High  
HiZ  
PU  
X
X
Low  
X
Open  
PU  
X
X
X
X
X
Low  
Low  
Low  
High  
High  
High  
High  
Low  
PU  
Low  
X
X
High  
High  
High  
PU  
High  
Low  
PU  
High  
PU: Power Up (VCC 3 V, VDD 12.8 V; VEE ≤ –3.3 V); PD: Power Down (VCC 2.2 V, VDD 10.4 V,  
VEE 2.3 V); X: Irrelevant; P*: PWM Pulse; HiZ: High Impedance  
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9 Applications and Implementation  
备注  
Information in the following applications sections is not part of the TI component specification, and TI  
does not warrant its accuracy or completeness. TIs customers are responsible for determining  
suitability of components for their purposes. Customers should validate and test their design  
implementation to confirm system functionality.  
9.1 Application Information  
The device is very versatile because of the strong drive strength, wide range of the output power supply, high  
isolation ratings, high CMTI, and superior protection and sensing features. The 1.5-kVRMS working voltage and  
12.8-kVPK surge immunity can support both SiC MOSFET and IGBT modules with DC bus voltage up to 2121 V.  
The device can be used in both low power and high power applications such as traction inverter in HEV/EV, on-  
board charger and charging pile, motor driver, solar inverter, industrial power supplies, and so forth. The device  
can drive the high power SiC MOSFET module, IGBT module, or paralleled discrete device directly without  
external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which allows the driver  
to have more control to the power semiconductor and saves cost and space of the board design. The  
UCC21737-Q1 can also be used to drive very high power modules or paralleled modules with external buffer  
stage. The input side can support power supply and microcontroller signals from 3.3 V to 5 V, and the device  
level shifts the signal to the output side through the reinforced isolation barrier. The device has a wide output  
power supply range from 13 V to 33 V and supports a wide range of negative power supply. This allows the  
driver to be used in SiC MOSFET applications, IGBT applications, and many others. The 12-V UVLO benefits  
the power semiconductor with lower conduction loss and improves system efficiency. As a reinforced isolated  
single channel driver, the device can be used to drive either a low-side or high-side driver.  
The device features extensive protection and monitoring features, which can monitor, report, and protect the  
system from various fault conditions.  
Fast detection and protection for an overcurrent and short circuit fault. The feature is preferable in a split  
source SiC MOSFET module or a split emitter IGBT module. For modules with no integrated current mirror or  
paralleled discrete semiconductors, the traditional desaturation circuit can be modified to implement short  
circuit protection. The semiconductor is shut down when a fault is detected and the FLT pin is pulled down to  
indicate the fault detection. The device is latched unless a reset signal is received from the RST/EN pin.  
Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during an overcurrent  
and short circuit fault. The shutdown energy can be controlled while the overshoot of the power  
semiconductor is limited.  
UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to  
be in UVLO mode, the output is pulled down and the RDY pin indicates the power supply is lost. The device  
is back to normal operation mode once the power supply is out of the UVLO status. The power-good status  
can be monitored from the RDY pin.  
Active short circuit feature creates phase-to-phase short circuit in the three-phase inverter to protect the  
battery from overvoltage breakdown.  
Active Miller clamp feature protects the power semiconductor from false turn on by driving an external  
MOSFET. This feature allows flexibility of board layout design and the pulldown strength of the Miller clamp  
FET.  
Enable and disable function through the RST/EN pin.  
Short circuit clamping  
Active pulldown  
9.2 Typical Application  
9-1 shows the typical application of a half bridge using two UCC21737-Q1 isolated gate drivers. The half  
bridge is a basic element in various power electronics applications, such as a traction inverter in a HEV/EV to  
convert DC current of the electric battery of the vehicle to AC current to drive the electric motor in the propulsion  
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system. The topology can also be used in motor drive applications to control the operating speed and torque of  
the AC motors.  
UCC  
UCC  
UCC  
UCC  
217XX  
217XX  
217XX  
217XX  
1
2
3
4
5
6
PWM  
3-Phase  
Input  
1
2
3
4
5
6
µC  
M
APWM  
FLT  
UCC  
UCC  
217XX  
217XX  
9-1. Typical Application Schematic  
9.2.1 Design Requirements  
Design of the power system for end equipment should consider some design requirements to ensure reliable  
operation of the UCC21737-Q1 throughout the load range. The design considerations include peak source and  
sink current, power dissipation, overcurrent, and short circuit protection and so forth.  
A design example for a half bridge based on IGBT is given in this subsection. The design parameters are shown  
in 9-1.  
9-1. Design Parameters  
PARAMETER  
Input Supply Voltage  
IN-OUT Configuration  
Positive Output Voltage VDD  
Negative Output Voltage VEE  
DC Bus Voltage  
VALUE  
5 V  
Noninverting  
15 V  
5 V  
800 V  
Peak Drain Current  
300 A  
Switching Frequency  
Switch Type  
50 kHz  
IGBT Module  
9.2.2 Detailed Design Procedure  
9.2.2.1 Input Filters for IN+, IN-, and RST/EN  
In the applications of a traction inverter or motor drive, the power semiconductors are in hard switching mode.  
With the strong device drive strength, the dV/dt can be high, especially for a SiC MOSFET. Noise cannot only be  
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coupled to the gate voltage due to the parasitic inductance, but also to the input side as the nonideal PCB layout  
and coupled capacitance.  
The UCC21737-Q1 features a 40-ns internal deglitch filter to the IN+, IN-, and RST/EN pins. Any signal less than  
40 ns can be filtered out from the input pins. For noisy systems, an external low-pass filter can be added  
externally to the input pins. Adding low-pass filters to the IN+, IN-, and RST/EN pins can effectively increase  
noise immunity and increase signal integrity. When not in use, the IN+, IN-, and RST/EN pins should not be  
floating. IN- should be tied to GND if only IN+ is used for a noninverting input to output configuration. The  
purpose of the low-pass filter is to filter out high frequency noise generated by the layout parasitics. While  
choosing the low-pass filter resistors and capacitors, both the noise immunity effect and delay time should be  
considered according to the system requirements.  
9.2.2.2 PWM Interlock of IN+ and IN-  
The UCC21737-Q1 features a PWM interlock for the IN+ and IN- pins, which can be used to prevent a phase leg  
shoot-through issue. As shown in 8-1, the output is logic low while both IN+ and IN- are logic high. When only  
IN+ is used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other switch in  
the phase leg can be sent to the IN- pin. As shown in 9-2, PWM_T is the PWM signal to the top-side switch,  
and PWM_B is the PWM signal to the bottom-side switch. For the top-side gate driver, the PWM_T signal is  
given to the IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom-side gate driver, the PWM_B  
signal is given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and PWM_B  
signals are high, the outputs of both gate drivers are logic low to prevent the shoot-through condition.  
IN+  
IN-  
RON  
OUTH  
OUTL  
ROFF  
PWM_T  
PWM_B  
RON  
IN+  
IN-  
OUTH  
OUTL  
ROFF  
9-2. PWM Interlock for a Half Bridge  
9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry  
The FLT and RDY pins are open-drain outputs. The RST/EN pin has a 50-kΩ internal pulldown resistor, so the  
driver is in the OFF status if the RST/EN pin is not pulled up externally. A 5-kΩ resistor can be used as pullup  
resistor for the FLT, RDY, and RST/EN pins.  
To improve noise immunity due to parasitic coupling and common-mode noise, low-pass filters can be added  
between the FLT, RDY, and RST/EN pins and the microcontroller. A filter capacitor between 100 pF to 300 pF  
can be added.  
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3.3V to 5V  
VCC  
15  
9
1µF  
0.1µF  
GND  
IN+  
10  
INt  
11  
5kQ  
5kQ 5kQ  
FLT  
12  
13  
100pF  
RDY  
100pF  
RST/EN  
14  
16  
100pF  
APWM  
9-3. FLT, RDY and RST/EN Pins Circuitry  
9.2.2.4 RST/EN Pin Control  
The RST/EN pin has two functions. It can be used to enable and shut down the outputs of the driver and reset  
the fault signaled on the FLT pin. The RST/EN pin needs to be pulled up to enable the device; when the pin is  
pulled down, the device is in disabled status. With a 50-kΩ pulldown resistor existing, the driver is disabled by  
default.  
When the driver is latched after an overcurrent or short circuit fault is detected, the FLT pin and output are  
latched low and need to be reset by the RST/EN pin. The RST/EN pin is active low. The microcontroller needs to  
send a signal to the RST/EN pin after the fault mute time tFLTMUTE to reset the driver. This pin can also be used  
to automatically reset the driver. The continuous input signals IN+ or IN- can be applied to the RST/EN pin, so  
the microcontroller does not need to generate another control signal to reset the driver. If the noninverting input  
IN+ is used, then IN+ can be tied to the RST/EN pin. If inverting input IN- is used, then a NOT logic is needed  
between the inverting PWM signal from the microcontroller and the RST/EN pin. In this case, the driver can be  
reset in every switching cycle without an extra control signal from the microcontroller to the RST/EN pin.  
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3.3V to 5V  
0.1µF  
3.3V to 5V  
VCC  
VCC  
15  
15  
1µF  
1µF  
0.1µF  
GND  
IN+  
GND  
IN+  
9
9
10  
10  
INt  
INt  
5kQ  
11  
5kQ  
5kQ  
11  
5kQ  
FLT  
FLT  
12  
13  
12  
13  
100pF  
100pF  
100pF  
100pF  
RDY  
RDY  
RST/EN  
APWM  
RST/EN  
APWM  
14  
16  
14  
16  
9-4. Automatic Reset Control  
9.2.2.5 Turnon and Turnoff Gate Resistors  
The UCC21737-Q1 features split outputs OUTH and OUTL, which enables independent control of the turn-on  
and turn-off switching speed. The turn-on and turn-off resistances determine the peak source and sink currents,  
which controls the switching speed in turn. Meanwhile, the power dissipation in the gate driver should be  
considered to ensure the device is in the thermal limit. Initially, the peak source and sink currents are calculated  
as:  
VDD - VEE  
ROH_EFF +RON +RG _Int  
Isource _ pk = min(10A,  
Isink _ pk = min(10A,  
)
VDD - VEE  
ROL +ROFF +RG _Int  
)
(1)  
Where  
ROH_EFF is the effective internal pullup resistance of the hybrid pullup structure, which is approximately 2 ×  
OL, about 0.7 .  
R
ROL is the internal pulldown resistance, about 0.3 .  
RON is the external turn-on gate resistance.  
ROFF is the external turn-off gate resistance.  
RG_Int is the internal resistance of the SiC MOSFET or IGBT module.  
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VDD  
Cies=Cgc+Cge  
+
Cgc  
VDD  
ROH_EFF  
OUTH  
t
RON  
RG_Int  
OUTL  
ROFF  
Cge  
+
VEE  
ROL  
t
VEE  
COM  
9-5. Output Model for Calculating Peak Gate Current  
For example, for an IGBT module-based system with the following parameters:  
Qg = 3300 nC  
RG_Int = 1.7 Ω  
RON = ROFF= 1 Ω  
The peak source and sink currents in this case are:  
VDD - VEE  
ROH_EFF +RON +RG _Int  
Isource _ pk = min(10A,  
) ö 5.9A  
VDD - VEE  
ROL +ROFF +RG _Int  
Isink _ pk = min(10A,  
) ö 6.7A  
(2)  
Thus by using 1-Ω external gate resistance, the peak source current is 5.9 A, and the peak sink current is 6.7A.  
The collector-to-emitter dV/dt during the turn-on switching transient is dominated by the gate current at the Miller  
plateau voltage. The hybrid pullup structure ensures peak source current at the Miller plateau voltage, unless the  
turn-on gate resistor is too high. The faster the collector-to-emitter, Vce, voltage rises to VDC, the smaller the turn-  
on switching loss. The dV/dt can be estimated as Qgc/Isource_pk. For the turn-off switching transient, the drain-to-  
source dV/dt is dominated by the load current, unless the turn-off gate resistor is too high. After Vce reaches the  
dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled by Vge. The  
peak sink current determines the dI/dt, which dominates the Vce voltage overshoot accordingly. If using relatively  
large turn-off gate resistance, Vce overshoot can be limited. The overshoot can be estimated by:  
DV = Lstray Iload / ((ROFF +ROL +RG_Int )Cies ln(Vplat / V ))  
ce  
th  
(3)  
Where  
Lstray is the stray inductance in the power switching loop, as shown in 9-6.  
Iload is the load current, which is the turn-off current of the power semiconductor.  
Cies is the input capacitance of the power semiconductor.  
Vplat is the plateau voltage of the power semiconductor.  
Vth is the threshold voltage of the power semiconductor.  
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LDC  
Lc1  
Lstray=LDC+Le1+Lc1+Le1+Lc1  
RG  
Lload  
t
+
Le1  
+
VDC  
t
Lc2  
VDD  
Cgc  
Cies=Cgc+Cge  
RG  
OUTH  
OUTL  
COM  
Cge  
Le2  
9-6. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration  
Power dissipation should be taken into account to maintain the gate driver within the thermal limit. The power  
loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:  
P
= PQ +P  
DR  
SW  
(4)  
PQ is the quiescent power loss for the driver, which is Iq x (VDD-VEE) = 5 mA x 20 V = 0.100 W. The quiescent  
power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic  
circuits, protection circuits when the driver is switching when the driver is biased with VDD and VEE, and also  
the charging and discharging current of the internal circuit when the driver is switching. The power dissipation  
when the driver is switching can be calculated as:  
ROH_EFF  
2 ROH_EFF +RON +RG _Int ROL +ROFF +RG _Int  
ROL  
1
P
=
(  
+
)(VDD - VEE)fsw Qg  
SW  
(5)  
Where  
Qg is the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD.  
fsw is the switching frequency.  
In this example, the PSW can be calculated as:  
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ROH_EFF  
2 ROH_EFF + RON + RG _Int ROL +ROFF +RG _Int  
ROL  
1
P
=
(  
+
)(VDD - VEE)fsw Qg = 0.505W  
SW  
(6)  
Thus, the total power loss is:  
P =P +P = 0.10W +0.505W = 0.605W  
DR  
Q
SW  
(7)  
When the board temperature is 125°C, the junction temperature can be estimated as:  
Tj = T + yjb P ö 150oC  
b
DR  
(8)  
Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency  
is ~50 kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing  
external gate resistance, the gate driver can be operated at a higher switching frequency.  
9.2.2.6 External Active Miller Clamp  
The external active Miller clamp feature allows the gate driver to stay at the low status when the gate voltage is  
detected below VCLMPTH. When the other switch of the phase leg turns on, the dV/dt can cause a current through  
the parasitic Miller capacitance of the switch and sink in the gate driver. The sinking current causes a negative  
voltage drop on the turn-off gate resistance, and bumps up the gate voltage to cause a false turn on. The  
external active Miller clamp features allow flexibility of board layout and active Miller clamp pulldown strength.  
Limited by the board layout, if the driver cannot be placed close enough to the switch, an external active Miller  
clamp MOSFET can be placed close to the switch and the MOSFET can be chosen according to the peak  
current needed. Caution must be exercised when the driver is placed far from the power semiconductor. Since  
the device has high peak sink and source currents, the high dI/dt in the gate loop can cause a ground bounce on  
the board parasitics. The ground bounce can cause a positive voltage bump on the CLMPE pin during the turn-  
off transient, and results in the external active Miller clamp MOSFET to turn on shortly and add extra drive  
strength to the sink current. To reduce the ground bounce, a 2-resistance is recommended to the gate of the  
external active clamp MOSFET.  
When VOUTH is detected to be lower than VCLMPTH above VEE, the CLMPE pin outputs a 5-V voltage with  
respect to VEE, the external clamp FET is in linear region and the pulldown current is determined by the peak  
drain current, unless the on-resistance of the external clamp FET is large.  
VDS  
ICLMPE _PK = min(ID _PK  
,
)
RDS _ ON  
(9)  
Where  
ID_PK is the peak drain current of the external clamp FET  
VDS is the drain-to-source voltage of the clamp FET when the CLMPE is activated  
RDS_ON is the on-resistance of the external clamp FET  
The total delay time of the active Miller clamp circuit from the gate voltage detection threshold VCLMPTH can be  
calculated as tDCLMPE+tCLMPER. tCLMPER depends on the parameter of the external active Miller clamp MOSFET.  
As long as the total delay time is longer than the dead time of high-side and low-side switches, the driver can  
effectively protect the switch from a false turn-on issue caused by the Miller effect.  
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VCLMPTH  
VCC  
OUTH  
+
3V to 5.5V  
IN+  
œ
CLMPE  
Control  
Circuitry  
OUTL  
µC  
MOD  
DEMOD  
IN-  
VEE  
COM  
VCC  
9-7. External Active Miller Clamp Configuration  
9.2.2.7 Overcurrent and Short Circuit Protection  
Fast and reliable overcurrent and short circuit protection is important to protect the catastrophic break down of  
the SiC MOSFET and IGBT modules, and improve the system reliability. The UCC21737-Q1 features a state-of-  
art overcurrent and short circuit protection, which can be applied to both SiC MOSFET and IGBT modules with  
various detection circuits.  
9.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET  
The overcurrent and short circuit protection function is suitable for the SiC MOSFET and IGBT modules with  
integrated SenseFET. The SenseFET scales down the main power loop current and outputs the current with a  
dedicated pin of the power module. With the external high precision sensing resistor, the scaled down current  
can be measured and the main power loop current can be calculated. The value of the sensing resistor RS sets  
the protection threshold of the main current. For example, with a ratio of 1:N = 1:50000 of the integrated current  
mirror, by using RS as 20 , the threshold protection current is:  
VOCTH  
IOC _ TH  
=
N = 1750A  
RS  
(10)  
The overcurrent and short circuit protection based on the integrated SenseFET has high precision, as it is  
sensing the current directly. The accuracy of the method is related to two factors: the scaling down ratio of the  
main power loop current and the SenseFET, and the precision of the sensing resistor. Since the current is  
sensed from the SenseFET, which is isolated from the main power loop, and the current is scaled down  
significantly with much less dI/dt, the sensing loop has good noise immunity. To further improve the noise  
immunity, a low-pass filter can be added. A 100-pF to 10-nF filter capacitor can be added. The delay time  
caused by the low-pass filter should also be considered for the protection circuitry design.  
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OUTL  
ROFF  
SenseFET  
OC  
RFLT  
FLT  
+
DEMOD  
MOD  
+
RS  
CFLT  
VOCTH  
Kelvin  
connection  
GND  
Control  
Logic  
COM  
VEE  
9-8. Overcurrent and Short Circuit Protection Based on IGBT Module with SenseFET  
9.2.2.7.2 Protection Based on Desaturation Circuit  
For SiC MOSFET and IGBT modules without SenseFET, the desaturation (DESAT) circuit is the most popular  
circuit which is adopted for overcurrent and short circuit protection. The circuit consists of a current source, a  
resistor, a blanking capacitor and a diode. Normally the current source is provided from the gate driver, when the  
device turns on, a current source charges the blanking capacitor and the diode forward biased. During normal  
operation, the capacitor voltage is clamped by the switch VCE voltage. When a short circuit happens, the  
capacitor voltage is quickly charged to the threshold voltage which triggers device shutdown. For the  
UCC21737-Q1, the OC pin does not feature an internal current source. The current source should be generated  
externally from the output power supply. When UCC21737-Q1 is in the OFF state, the OC pin is pulled down by  
an internal MOSFET, which creates an offset voltage on the OC pin. By choosing R1 and R2 significantly higher  
than the pulldown resistance of the internal MOSFET, the offset can be ignored. When the UCC21737-Q1 is in  
the ON state, the OC pin is high impedance. The current source is generated by the output power supply VDD  
and the external resistor divider R1, R2, and R3. The overcurrent detection threshold voltage of the IGBT is:  
R2 + R3  
R3  
VDET =VOCTH  
-VF  
(11)  
(12)  
The blanking time of the detection circuit is:  
R1 + R2  
R1 + R2 + R3  
R1 + R2 + R3 VOCTH  
tBLK = -  
R3 CBLK ln(1-  
)
R3  
VDD  
Where:  
VOCTH is the detection threshold voltage of the gate driver  
R1, R2, and R3 are the resistances of the voltage divider  
CBLK is the blanking capacitor  
VF is the forward voltage of the high voltage diode DHV  
The modified desaturation circuit has all the benefits of the conventional desaturation circuit. The circuit has  
negligible power loss and is easy to implement. The detection threshold voltage of IGBT and blanking time can  
be programmed by external components. Different with the conventional desaturation circuit, the overcurrent  
detection threshold voltage of the IGBT can be modified to any voltage level, either higher or lower than the  
detection threshold voltage of the driver. A parallel schottky diode can be connected between the OC and COM  
pins to prevent negative voltage on the OC pin in a noisy system. Since the desaturation circuit measures the  
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VCE of the IGBT or VDS of the SiC MOSFET, not directly the current, the accuracy of the protection is not as high  
as the SenseFET based protection method. The current threshold cannot be accurately controlled in the  
protection.  
ROFF  
OUTL  
DHV  
VDD  
R
1
R2  
OC  
+
DEMOD  
MOD  
FLT  
+
CBLK  
VOCTH  
R3  
Control  
Logic  
GND  
COM  
VEE  
9-9. Overcurrent and Short Circuit Protection Based on Desaturation Circuit  
9.2.2.7.3 Protection Based on Shunt Resistor in Power Loop  
In lower power applications, to simplify the circuit and reduce cost, a shunt resistor can be used in series in the  
power loop and measure the current directly. Since the resistor is in series in the power loop, it directly measures  
the current and can have high accuracy by using a high precision resistor. The resistance needs to be small to  
reduce the power loss, and should have large enough voltage resolution for the protection. Since the sensing  
resistor is also in series in the gate driver loop, the voltage drop on the sensing resistor can cause the voltage  
drop on the gate voltage of the IGBT or SiC MOSFET modules. The parasitic inductance of the sensing resistor  
and the PCB trace of the sensing loop cause a noise voltage source during switching transient, which makes the  
gate voltage oscillate. Thus, this method is not recommended for a high power application, or when dI/dt is high.  
To use it in low power application, the shunt resistor loop should be designed to have the optimal voltage drop  
and minimum noise injection to the gate loop.  
OUTL  
ROFF  
OC  
RFLT  
FLT  
+
DEMOD  
MOD  
+
RS  
CFLT  
VOCTH  
GND  
Control  
Logic  
COM  
VEE  
9-10. Overcurrent and Short Circuit Protection Based on Shunt Resistor  
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9.2.2.8 Higher Output Current Using an External Current Buffer  
To increase the IGBT gate drive current, a noninverting current buffer (such as the NPN/PNP buffer shown in 图  
9-11) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be  
avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the D44VH10/ D45VH10  
pair is for up to a 20-A peak.  
In the case of an overcurrent detection, a soft turn off (STO) is activated. External components must be added to  
implement STO instead of normal turn-off speed when an external buffer is used. CSTO sets the timing for soft  
turn off and RSTO limits the inrush current to below the current rating of the internal FET (10 A). RSTO should be  
at least (VDD-VEE)/10. The soft turn-off timing is determined by the internal current source of 400 mA and the  
capacitor CSTO. CSTO is calculated using Equation 13.  
ISTO tSTO  
VDD
-
VEE  
CSTO  
=
(13)  
ISTO is the the internal STO current source, 400 mA  
tSTO is the desired STO timing  
VDD  
VDD  
ROH  
Cies=Cgc+Cge  
RNMOS  
OUTH  
Cgc  
Cgc  
RG_2  
RG_1  
RG_Int  
RG_Int  
OUTL  
Cge  
Cge  
ROL  
CSTO  
COM  
VEE  
RSTO  
9-11. Current Buffer for Increased Drive Strength  
9.2.3 Application Curves  
9-12. PWM Input (yellow) and Driver Output  
9-13. PWM Input (yellow) and Driver Output  
(blue) Rising Edge  
(blue) Falling Edge  
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10 Power Supply Recommendations  
During the turn-on and turn-off switching transient, peak source and sink currents are provided by the VDD and  
VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause a  
voltage droop on the power supplies. To stabilize a power supply and ensure reliable operation, a set of  
decoupling capacitors are recommended at the power supplies. Considering the UCC21737-Q1 has ±10-A peak  
drive strength and can generate high dV/dt, a 10-µF bypass capacitor is recommended between VDD and COM,  
VEE and COM. A 1-µF bypass capacitor is recommended between VCC and GND due to less current  
comparing with output side power supplies. A 0.1-µF decoupling capacitor is also recommended for each power  
supply to filter out high frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high  
frequency noise, and should be placed as close as possible to the VCC, VDD, and VEE pins to prevent noise  
coupling from the system parasitics of PCB layout.  
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11 Layout  
11.1 Layout Guidelines  
Due to the strong drive strength of the UCC21737-Q1, careful considerations must be taken in PCB design.  
Below are some key points:  
The driver should be placed as close as possible to the power semiconductor to reduce the parasitic  
inductance of the gate loop on the PCB traces.  
The decoupling capacitors of the input and output power supplies should be placed as close as possible to  
the power supply pins. The peak current generated at each switching transient can cause high dI/dt and  
voltage spike on the parasitic inductance of the PCB traces.  
The driver COM pin should be connected to the Kelvin connection of the SiC MOSFET source or IGBT  
emitter. If the power device does not have a split Kelvin source or emitter, the COM pin should be connected  
as close as possible to the source or emitter terminal of the power device package to separate the gate loop  
from the high power switching loop.  
Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the  
high frequency noise generated by the output side switching transients. The ground plane provides a low-  
inductance filter for the return current flow.  
If the gate driver is used for the low-side switch, which the COM pin is connected to the dc bus negative, use  
the ground plane on the output side to shield the output signals from the noise generated by the switch node;  
if the gate driver is used for the high-side switch, which the COM pin is connected to the switch node, use of  
the ground plane is not recommended.  
If the ground plane is not used on the output side, separate the return path of the OC and AIN ground loop  
from the gate loop ground which has large peak source and sink currents.  
No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise  
coupling between the input and output side which can contaminate the isolation barrier.  
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11.2 Layout Example  
11-1. Layout Example  
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12 Device and Documentation Support  
12.1 Device Support  
12.1.1 第三方产品免责声明  
TI 发布的与第三方产品或服务有关的信息不能构成与此类产品或服务或保修的适用性有关的认可不能构成此  
类产品或服务单独或与任TI 产品或服务一起的表示或认可。  
12.2 Documentation Support  
12.2.1 Related Documentation  
For related documentation see the following:  
Isolation Glossary  
12.3 支持资源  
TI E2E支持论坛是工程师的重要参考资料可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解  
答或提出自己的问题可获得所需的快速设计帮助。  
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范并且不一定反映 TI 的观点请参阅  
TI 《使用条款》。  
12.4 Trademarks  
TI E2Eis a trademark of Texas Instruments.  
所有商标均为其各自所有者的财产。  
12.5 静电放电警告  
静电放(ESD) 会损坏这个集成电路。德州仪(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理  
和安装程序可能会损坏集成电路。  
ESD 的损坏小至导致微小的性能降级大至整个器件故障。精密的集成电路可能更容易受到损坏这是因为非常细微的参  
数更改都可能会导致器件与其发布的规格不相符。  
12.6 术语表  
TI 术语表  
本术语表列出并解释了术语、首字母缩略词和定义。  
13 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical packaging and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
Copyright © 2023 Texas Instruments Incorporated  
46  
Submit Document Feedback  
Product Folder Links: UCC21737-Q1  
 
 
 
 
 
 
 
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Jan-2023  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
UCC21737QDWRQ1  
ACTIVE  
SOIC  
DW  
16  
2000 RoHS & Green  
NIPDAU  
Level-3-260C-168 HR  
-40 to 125  
UCC21737Q  
Samples  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Jan-2023  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
UCC21737QDWRQ1  
SOIC  
DW  
16  
2000  
330.0  
16.4  
10.75 10.7  
2.7  
12.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Jan-2023  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SOIC DW 16  
SPQ  
Length (mm) Width (mm) Height (mm)  
350.0 350.0 43.0  
UCC21737QDWRQ1  
2000  
Pack Materials-Page 2  
GENERIC PACKAGE VIEW  
DW 16  
7.5 x 10.3, 1.27 mm pitch  
SOIC - 2.65 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
This image is a representation of the package family, actual package may vary.  
Refer to the product data sheet for package details.  
4224780/A  
www.ti.com  
PACKAGE OUTLINE  
DW0016B  
SOIC - 2.65 mm max height  
S
C
A
L
E
1
.
5
0
0
SOIC  
C
10.63  
9.97  
SEATING PLANE  
TYP  
PIN 1 ID  
AREA  
0.1 C  
A
14X 1.27  
16  
1
2X  
10.5  
10.1  
NOTE 3  
8.89  
8
9
0.51  
0.31  
16X  
7.6  
7.4  
B
2.65 MAX  
0.25  
C A  
B
NOTE 4  
0.33  
0.10  
TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.3  
0.1  
0 - 8  
1.27  
0.40  
DETAIL A  
TYPICAL  
(1.4)  
4221009/B 07/2016  
NOTES:  
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm, per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.  
5. Reference JEDEC registration MS-013.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DW0016B  
SOIC - 2.65 mm max height  
SOIC  
SYMM  
SYMM  
16X (2)  
1
16X (1.65)  
SEE  
DETAILS  
SEE  
DETAILS  
1
16  
16  
16X (0.6)  
16X (0.6)  
SYMM  
SYMM  
14X (1.27)  
14X (1.27)  
R0.05 TYP  
9
9
8
8
R0.05 TYP  
(9.75)  
(9.3)  
HV / ISOLATION OPTION  
8.1 mm CLEARANCE/CREEPAGE  
IPC-7351 NOMINAL  
7.3 mm CLEARANCE/CREEPAGE  
LAND PATTERN EXAMPLE  
SCALE:4X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
METAL  
0.07 MAX  
ALL AROUND  
0.07 MIN  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4221009/B 07/2016  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DW0016B  
SOIC - 2.65 mm max height  
SOIC  
SYMM  
SYMM  
16X (1.65)  
16X (2)  
1
1
16  
16  
16X (0.6)  
16X (0.6)  
SYMM  
SYMM  
14X (1.27)  
14X (1.27)  
8
9
8
9
R0.05 TYP  
R0.05 TYP  
(9.75)  
(9.3)  
HV / ISOLATION OPTION  
8.1 mm CLEARANCE/CREEPAGE  
IPC-7351 NOMINAL  
7.3 mm CLEARANCE/CREEPAGE  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:4X  
4221009/B 07/2016  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
重要声明和免责声明  
TI“按原样提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,  
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