UCC21521ADWR_技术文档

UCC21521

ZHCSFM4B –SEPTEMBER 2016 –REVISED DECEMBER 2021

UCC21521 具有使能功能的4A/6A、5.7 kV_RMS隔离式双通道栅极驱动器

1 特性

3 说明

• 通用：双路低侧、双路高侧或半桥驱动器

• 工作温度范围：–40°C 至+125°C

• 开关参数：

UCC21521 是一款隔离式双通道栅极驱动器，具有 4A

峰值拉电流和 6A 峰值灌电流。该器件设计用于驱动高

达 5MHz 的功率 MOSFET、IGBT 和 SiC MOSFET，

具有一流的传播延迟和脉宽失真度。

– 19ns 典型传播延迟

– 10ns 最小脉冲宽度

– 5ns 最大延迟匹配

– 6ns 最大脉宽失真

输入侧通过一个 5.7kV_RMS增强型隔离层与两个输出驱

动器隔离，共模瞬态抗扰度 (CMTI) 的最小值为

100V/ns。两个二次侧驱动器之间采用内部功能隔离，

支持高达1500 V_DC的工作电压。

• 共模瞬态抗扰度(CMTI) 大于100V/ns

• 浪涌抗扰度高达12.8kV

• 隔离层寿命> 40 年

• 4A 峰值拉电流、6A 峰值灌电流输出

• TTL 和CMOS 兼容输入

• 3V 至18V 输入VCCI 范围，可与数字控制器和模

拟控制器连接

每个驱动器可配置为两个低侧驱动器、两个高侧驱动器

或一个死区时间 (DT) 可编程的半桥驱动器。EN 引脚

拉低时会同时关闭两个输出，悬空或拉高时可使器件恢

复正常运行。作为一种失效防护机制，初级侧逻辑故障

会强制两个输出为低电平。

• 高达25V 的VDD 输出驱动电源

此器件接受高达 25V 的VDD 电源电压。3V 到18V 的

宽输入电压 VCCI 范围使得该驱动器适用于连接数字和

模拟控制器。所有电源电压引脚都具有欠压锁定

(UVLO) 保护功能。

– 5V、8V、12V VDD UVLO 选项

• 可通过编程的重叠和死区时间

• 抑制短于5ns 的输入脉冲和噪声瞬态

• 电源时序快速启用

• 宽体SOIC-16 (DW) 封装

• 安全相关认证：

凭借所有这些高级特性，UCC21521 能够满足各类电

源应用中对于高效率、高电源密度和稳健性的需求。

器件信息⁽¹⁾

– 符合DIN V VDE V 0884-11:2017-01 标准的

8000V_PK增强型隔离

– 符合UL 1577 标准且长达1 分钟的5700 V_RMS

隔离

– 符合IEC 60950-1、IEC 62368-1、IEC 61010-1

和IEC 60601-1 终端设备标准的CSA 认证

– 符合GB4943.1-2011 标准的CQC 认证

封装尺寸（标称值）

器件型号

UCC21521ADW DW SOIC (16)

UCC21521DW DW SOIC (16)

UCC21521CDW DW SOIC (16)

封装

10.30mm x 7.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

VCCI 3,8

16 VDDA

15 OUTA

14 VSSA

Driver

DEMOD UVLO

• 隔离式转换器（离线交流-直流电源中）

• 服务器、电信、IT 和工业基础设施

• 电机驱动和直流/交流光伏逆变器

• LED 照明

• 感应加热

• 不间断电源(UPS)

MOD

INA

EN

NC

DT

1

5

7

6

EN,

UVLO

and

13 NC

12 NC

Functional Isolation

Deadtime

11 VDDB

10 OUTB

Driver

INB

2

4

MOD

DEMOD UVLO

GND

9

VSSB

Copyright

功能方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSCO3

UCC21521

www.ti.com.cn

ZHCSFM4B –SEPTEMBER 2016 –REVISED DECEMBER 2021

Table of Contents

7.6 CMTI Testing.............................................................17

8 Detailed Description......................................................19

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................23

9 Application and Implementation..................................25

9.1 Application Information............................................. 25

9.2 Typical Application.................................................... 25

10 Power Supply Recommendations..............................37

11 Layout...........................................................................38

11.1 Layout Guidelines................................................... 38

11.2 Layout Example...................................................... 39

12 Device and Documentation Support..........................41

12.1 第三方产品免责声明................................................41

12.2 Documentation Support.......................................... 41

12.3 Certifications........................................................... 41

12.4 接收文档更新通知................................................... 41

12.5 支持资源..................................................................41

12.6 Trademarks.............................................................41

12.7 静电放电警告.......................................................... 41

12.8 术语表..................................................................... 41

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 5

6.7 Safety-Related Certifications...................................... 6

6.8 Safety-Limiting Values................................................ 7

6.9 Electrical Characteristics.............................................7

6.10 Switching Characteristics..........................................9

6.11 Insulation Characteristics Curves............................10

6.12 Typical Characteristics............................................ 11

7 Parameter Measurement Information..........................16

7.1 Propagation Delay and Pulse Width Distortion.........16

7.2 Rising and Falling Time.............................................16

7.3 Input and Enable Response Time.............................16

7.4 Programmable Dead Time........................................17

7.5 Powerup UVLO Delay to OUTPUT...........................17

Information.................................................................... 41

4 Revision History

Changes from Revision A (October 2021) to Revision B (December 2021)

Page

• 将特性中的最大脉宽失真从“5ns”更改为“6ns”.......................................................................................... 1

• Changed maximum pulse-width distortion specification from "5-ns" to "6-ns" in Switching Characteristics ......9

Changes from Revision * (October 2016) to Revision A (October 2021)

Page

• 更新了安全相关及监管批准................................................................................................................................ 1

• Updated DT pin description................................................................................................................................ 3

• Updated Certifications........................................................................................................................................ 6

• Added the powerup delay time specifications.....................................................................................................9

• Added Powerup UVLO Delay to OUTPUT ...................................................................................................... 17

• Updated for bootstrap recommendation........................................................................................................... 26

• Added Ferrite bead recommendation............................................................................................................... 27

• Added Gate to Source Resistor Selection ....................................................................................................... 29

• Updated Certifications...................................................................................................................................... 41

English Data Sheet: SLUSCO3

2

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ZHCSFM4B –SEPTEMBER 2016 –REVISED DECEMBER 2021

5 Pin Configuration and Functions

INA

INB

1

2

3

4

5

6

7

8

16

VDDA

OUTA

VSSA

NC

15

14

13

12

11

10

9

VCCI

GND

EN

NC

DT

VDDB

OUTB

VSSB

NC

VCCI

Not to scale

图5-1. DW Package 16-Pin SOIC Top View

表5-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Enable both driver outputs if asserted high or left open, disable the output if set low. This pin

is pulled high internally if left open. It is recommended to tie this pin to VCCI if not used to

achieve better noise immunity.

EN

5

I

Programmable dead time function.

Tying DT to VCCI allows the outputs to overlap. Placing a 500-Ωto 500-kΩresistor (R_DT

between DT and GND adjusts dead time according to: DT (in ns) = 10 x R_DT(in kΩ). It is

)

DT

6

I

recommended to parallel a ceramic capacitor, 2.2nF or above, close to the DT pin with R_DT

to achieve better noise immunity. It is not recommended to leave DT floating.

GND

INA

4

1

P

I

Primary-side ground reference. All signals in the primary side are referenced to this ground.

Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin

is pulled low internally if left open. It is recommended to tie this pin to ground if not used to

achieve better noise immunity.

INB

2

I

NC

7

No internal connection.

–

O

NC

12

13

15

10

No internal connection.

NC

No internal connection.

OUTA

OUTB

Output of driver A. Connect to the gate of the A channel FET or IGBT.

Output of driver B. Connect to the gate of the B channel FET or IGBT.

O

Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor

located as close to the device as possible.

VCCI

VDDA

3

8

P

Primary-side supply voltage. This pin is internally shorted to pin 3.

Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL

capacitor located as close to the device as possible.

16

Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL

capacitor located as close to the device as possible.

VDDB

11

P

VSSA

VSSB

14

9

P

Ground for secondary-side driver A. Ground reference for secondary side A channel.

Ground for secondary-side driver B. Ground reference for secondary side B channel.

(1) P =Power, G= Ground, I= Input, O= Output

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English Data Sheet: SLUSCO3

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ZHCSFM4B –SEPTEMBER 2016 –REVISED DECEMBER 2021

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

20

UNIT

V

Input bias pin supply voltage

Driver bias supply

VCCI to GND

VDDA-VSSA, VDDB-VSSB

30

V

V_VDDA+0.3,

V_VDDB+0.3

OUTA to VSSA, OUTB to VSSB

V

–0.3

–2

Output signal voltage

OUTA to VSSA, OUTB to VSSB,

Transient for 200 ns

V_VDDA+0.3,

V_VDDB+0.3

INA, INB, EN, DT to GND

INA, INB Transient for 50ns

VSSA-VSSB, VSSB-VSSA

V_VCCI+0.3

1500

V

–0.3

–5

Input signal voltage

Channel to channel voltage

V

(2)

Junction temperature, T_J

150

°C

–40

–65

Storage temperature, T_stg

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime. See 节9 for more information on the typical

application and how to avoid device overstress.

(2) To maintain the recommended operating conditions for T_J, see the Thermal Information.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

18

UNIT

V

VCCI

VCCI Input supply voltage

Driver output bias supply

3

6.5

5-V UVLO version - UCC21521ADW

8-V UVLO version - UCC21521DW

12-V UVLO version - UCC21521CDW

25

V

VDDA,

VDDB

9.2

25

V

14.7

–40

25

V

T_A

T_J

Ambient Temperature

Junction Temperature

125

130

°C

English Data Sheet: SLUSCO3

4

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6.4 Thermal Information

UCC21521

UNIT

DW-16 (SOIC)

THERMAL METRIC⁽¹⁾

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

78.1

11.1

48.4

12.5

48.4

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Power Ratings

VALUE

1.05

UNIT

W

P_D

Power dissipation by UCC21521

P_DI

Power dissipation by transmitter side of

UCC21521

VCCI = 18 V, VDDA/B = 12 V, INA/B = 3.3 V,

3 MHz 50% duty cycle square wave 1-nF

load

0.05

W

P_DA, P_DB

Power dissipation by each driver side of

UCC21521

0.5

W

6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

> 8

UNIT

mm

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin to pin distance through air

Shortest pin to pin distance across the package surface

> 8

mm

Minimum internal gap (internal clearance) of the double

insulation (2 x 10.5 µm)

DTI

CTI

Distance through insulation

>21

µm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

> 600

I

I-IV

I-III

Rated mains voltage ≤600 V_RMS

Rated mains voltage ≤1000 V_RMS

Overvoltage category per

IEC 60664-1

DIN V VDE 0884-11 (VDE V 0884-11): 2017-01⁽²⁾

Maximum repetitive peak

isolation voltage

V_IORM

AC voltage (bipolar)

2121

V_PK

AC voltage (sine wave); time dependent dielectric breakdown

(TDDB), test (See 图6-1)

1500

2121

8000

V_RMS

V_DC

V_PK

Maximum isolation working

voltage

V_IOWM

DC voltage

Maximum transient isolation V_TEST= V_IOTM, t = 60 sec (qualification)

V_IOTM

V_IOSM

voltage

V_TEST= 1.2 x V_IOTM, t = 1 s (100% production)

Maximum surge isolation

voltage⁽³⁾

Test method per IEC 62368-1, 1.2/50 µs waveform,V_TEST

1.6 × V_IOSM= 12800 V_PK(qualification)

=

8000

<5

V_PK

Method a, After Input/Output safety test subgroup 2/3. V_ini

V_IOTM, t_ini= 60s;

=

V_pd(m)= 1.2 X V_IORM= 2545 V_PK, t_m= 10s

Method a, After environmental tests subgroup 1. V_ini= V_IOTM

,

t_ini= 60s;

<5

q_pd

Apparent charge⁽⁴⁾

pC

V_pd(m)= 1.6 X V_IORM= 3394, V_PK, t_m= 10s

Method b1; At routine test (100% production) and

preconditioning (type test)

V_ini= V_IOTM; t_ini= 1s;

V_pd(m)= 1.875 × V_IORM= 3977 V_PK, t_m= 1s

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ZHCSFM4B –SEPTEMBER 2016 –REVISED DECEMBER 2021

6.6 Insulation Specifications (continued)

PARAMETER

TEST CONDITIONS

VALUE

UNIT

Barrier capacitance, input to

C_IO

1.2

pF

V_IO= 0.4 sin (2πft), f =1 MHz

output⁽⁵⁾

V_IO= 500 V at T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Isolation resistance, input to

output

R_IO

V_IO= 500 V at 100°C ≤T_A≤125°C

V_IO= 500 V at T_S=150°C

Ω

Pollution degree

Climatic category

2

40/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 sec. (qualification),

V_TEST= 1.2 × V_ISO= 6840V_RMS, t = 1 sec (100% production)

V_ISO

Withstand isolation voltage

5700

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in

certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these

specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

6.7 Safety-Related Certifications

VDE

CSA

UL

CQC

Recognized under

UL 1577

Component

Recognition

Program

Certified according to DIN

VDE V 0884-11 :2017-01

and DIN EN 60950-1 (VDE 60601-1

0805 Teil 1):2014-08

Certified according to IEC 60950-1 and IEC

Certified according to GB 4943.1-2011

Reinforced insulation per CSA 60950-1-

07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2,

800 VRMS maximum working voltage (pollution

degree 2, material group I)

Reinforced insulation per CSA 62368-1-14 and

Reinforced Insulation

Maximum Transient

Isolation voltage, 8000 V_PK

Maximum Repetitive Peak

IEC 62368-1 2nd Ed., 800 VRMS maximum

working voltage (pollution degree 2, material

group I);

;

Reinforced Insulation,Altitude ≤5000m,

Tropical Climate, 660 V_RMSmaximum

working voltage

Single protection,

5700 V_RMS

Basic insulation per CSA 61010-1-12+A1 and

IEC 61010-1 3rd Ed., 600 VRMS maximum

working voltage (pollution degree 2, material

group III);

Isolation Voltage, 2121 V_PK

Maximum Surge Isolation

Voltage, 8000 V_PK

;

2 MOPP (Means of Patient Protection) per CSA

60601- 1:14 and IEC 60601-1 Ed. 3.1, 250

VRMS (354 VPK) max working voltage

Certification number:

40040142

File number:

E181974

Master contract number: 220991

Certificate number: CQC16001155011

English Data Sheet: SLUSCO3

6

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6.8 Safety-Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

TEST CONDITIONS

SIDE

MIN

TYP

MAX

UNIT

R

_θJA= 78.1°C/W, VDDA/B = 12 V⁽¹⁾, T_A=

DRIVER A,

DRIVER B

25°C, T_J= 150°C

64

mA

See 图6-2

Safety output supply

current

I_S

R

_θJA= 78.1°C/W, VDDA/B = 25 V⁽¹⁾, T_A=

DRIVER A,

DRIVER B

25°C, T_J= 150°C

31

mA

See 图6-2

INPUT

DRIVER A

DRIVER B

TOTAL

50

775

R

_θJA= 78.1°C/W, T_A= 25°C, T_J= 150°C

P_S

T_S

Safety supply power

Safety temperature⁽²⁾

mW

°C

See 图6-3

775

1600

150

(1) VDDA=VDDB=12V is used for the test condition of 5V and 8V UVLO, and VDDA=VDDB=25V is used for 12V UVLO.

(2) The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-

air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-

to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K test board for leaded surface mount

packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature.

P_S= I_S× V_I, where V_Iis the maximum input voltage.

6.9 Electrical Characteristics

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V or 15 V⁽¹⁾, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENTS

I_VCCI

VCCI quiescent current

V_INA= 0 V, V_INB= 0 V

1.5

1.0

2.0

1.8

mA

I_VDDA

I_VDDB

,

VDDA and VDDB quiescent current V_INA= 0 V, V_INB= 0 V

(f = 500 kHz) current per channel,

C_OUT= 100 pF

I_VCCI

VCCI per channel operating current

VDDA and VDDB operating current

2.0

2.5

3.0

mA

(f = 500 kHz) current per channel,

C_OUT= 100 pF, VDD=12 V

I_VDDA

I_VDDB

(f = 500 kHz) current per channel,

C_OUT= 100 pF, VDD=15 V

VCCI UVLO THRESHOLDS

V_{VCCI_ON}

V_{VCCI_OFF}

V_{VCCI_HYS}

Rising threshold

2.55

2.35

2.7

2.5

0.2

2.85

2.65

V

Falling threshold VCCI_OFF

Threshold hysteresis

UCC21521ADW VDD UVLO THRESHOLDS (5-V UVLO VERSION)

V_{VDDA_ON}

V_{VDDB_ON}

,

Rising threshold VDDA_ON,

VDDB_ON

5.2

4.9

5.8

5.5

0.3

6.3

6

V

V_{VDDA_OFF}

V_{VDDB_OFF}

,

Falling threshold VDDA_OFF,

VDDB_OFF

V_{VDDA_HYS}

V_{VDDB_HYS}

,

Threshold hysteresis

UCC21521DW VDD UVLO THRESHOLDS (8-V UVLO VERSION)

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6.9 Electrical Characteristics (continued)

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V or 15 V⁽¹⁾, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{VDDA_ON,}

V_{VDDB_ON}

Rising threshold VDDA_ON,

VDDB_ON

8

8.5

9

V

V_{VDDA_OFF,}

V_{VDDB_OFF}

Falling threshold VDDA_OFF,

VDDB_OFF

7.5

8

8.5

V

V_{VDDA_HYS,}

V_{VDDB_HYS}

Threshold hysteresis

0.5

UCC21521CDW VDD UVLO THRESHOLDS (12-V UVLO VERSION)

V_{VDDA_ON}

V_{VDDB_ON}

,

Rising threshold VDDA_ON,

VDDB_ON

12.5

11.5

13.5

12.5

1.0

14.5

13.5

V

V_{VDDA_OFF,}

V_{VDDB_OFF}

Falling threshold VDDA_OFF,

VDDB_OFF

V_{VDDA_HYS,}

V_{VDDB_HYS}

Threshold hysteresis

INA and INB

V_INAH, V_INBHInput high voltage

1.6

0.8

1.8

1

2

V

V_INAL, V_INBL

V_{INA_HYS}

V_{INB_HYS}

Input low voltage

1.2

,

Input hysteresis

0.8

V

Negative transient, ref to GND, 50 ns Not production tested, bench test

pulse

V_INA, V_INB

–5

only

EN THRESHOLDS

V_ENH

V_ENL

Enable high voltage

2.0

V

Enable low voltage

0.8

English Data Sheet: SLUSCO3

8

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6.9 Electrical Characteristics (continued)

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V or 15 V⁽¹⁾, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

C_VDD= 10 µF, C_LOAD= 0.18 µF, f =

1 kHz, bench measurement

I_OA+, I_OB+

Peak output source current

Peak output sink current

4

6

A

C_VDD= 10 µF, C_LOAD= 0.18 µF, f =

1 kHz, bench measurement

I_OA-, I_OB-

I_OUT= –10 mA, T_A= 25°C, R_OHA

,

R_OHBdo not represent drive pull-up

performance. See t_RISEin

R_OHA, R_OHB

Output resistance at high state

5

Ω

Switching Characteristics and

Output Stage for details.

R_OLA, R_OLB

V_OHA, V_OHB

Output resistance at low state

Output voltage at high state

I_OUT= 10 mA, T_A= 25°C

0.55

Ω

V_VDDA, V_VDDB= 12 V, I_OUT= –10

mA, T_A= 25°C

11.95

V

V_VDDA, V_VDDB= 12 V, I_OUT= 10

mA, T_A= 25°C

V_OLA, V_OLB

Output voltage at low state

5.5

mV

DEADTIME AND OVERLAP PROGRAMMING

Pull DT pin to VCCI

Overlap determined by INA INB

-

DT pin is left open, min spec

characterized only, tested for

outliers

0

8

15

ns

Dead time

160

200

240

R_DT= 20 kΩ

(1) VDDA=VDDB=12 V is used for the test condition of 5-V and 8-V UVLO, and VDDA=VDDB = 15 V is used for 12-V UVLO.

6.10 Switching Characteristics

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V or 15V⁽¹⁾, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_RISE

Output rise time, 20% to 80%

measured points

6

16

ns

C_OUT= 1.8 nF

t_FALL

Output fall time, 90% to 10%

measured points

7

12

20

30

ns

C_OUT= 1.8 nF

t_PWmin

t_PDHL

t_PDLH

Minimum pulse width

Output off for less than minimum,

C_OUT= 0 pF

Propagation delay from INx to OUTx

falling edges

19

Propagation delay from INx to OUTx

rising edges

t_PWD

t_DM

6

5

ns

Pulse width distortion |t_PDLH–t_PDHL

|

Propagation delays matching

between VOUTA, VOUTB

f = 100 kHz

t_{VCCI+ to OUT}VCCI Power-up Delay Time: UVLO

40

50

us

INA or INB tied to VCCI

Rise to OUTA, OUTB (See 图7-5 )

t_{VDD+ to OUT}VDDA, VDDB Power-up Delay Time:

UVLO Rise to OUTA, OUTB (See 图

7-6)

100

INA or INB tied to VCCI

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6.10 Switching Characteristics (continued)

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V or 15V⁽¹⁾, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INA and INB both are tied to VCCI;

V_CM=1500 V; (See CMTI Testing.)

High-level common-mode transient

immunity

|CM_H|

|CM_L|

100

V/ns

INA and INB both are tied to GND;

V_CM=1500 V; (See CMTI Testing.)

Low-level common-mode transient

immunity

100

(1) VDDA=VDDB = 12 V is used for the test condition of 5 V and 8V UVLO, and VDDA=VDDB=15 V is used for 12-V UVLO.

6.11 Insulation Characteristics Curves

1.E+11

Safety Margin Zone: 1800 V_RMS, 254 Years

Operating Zone: 1500 V_RMS, 135 Years

1.E+10

1.E+9

1.E+8

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3

1.E+2

1.E+1

TDDB Line (<1 PPM Fail Rate)

87.5%

20%

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

Stress Voltage (V_RMS

)

图6-1. Reinforced Isolation Capacitor Life Time Projection

80

70

60

50

40

30

20

10

0

1800

I_VDDA/Bfor VDD=12V

I_VDDA/Bfor VDD=25V

1500

1200

900

600

300

0

50

100

Ambient Temperature (èC)

150

200

0

50

100

Ambient Temperature (èC)

150

200

D001

图6-3. Thermal Derating Curve for Safety-Related

图6-2. Thermal Derating Curve for Safety-Related

Limiting Current (Current in Each Channel with

Both Channels Running Simultaneously)

Limiting Power

10

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6.12 Typical Characteristics

VDDA = VDDB = 12 V for 5 V and 8V UVLO, VDDA = VDDB = 15 V for 12V UVLO, VCCI = 3.3 V, T_A= 25°C, No

load unless otherwise noted.

20

16

12

8

50

40

30

20

10

0

4

VDD=12v

VDD=25v

VDD= 12V

VDD= 25V

0

800

1600

2400 3200

Frequency (kHz)

4000

4800

5600

0

500

1000

1500

Frequency (kHz)

2000

2500

3000

D001

图6-4. Per Channel Current Consumption vs.

图6-5. Per Channel Current Consumption (I_VDDA/B)

Frequency (No Load, VDD = 12 V or 25 V)

vs. Frequency (1-nF Load, VDD = 12 V or 25 V)

30

24

18

12

6

50kHz

250kHz

500kHz

1MHz

5

4

3

2

1

0

VDD= 12V

VDD= 25V

0

10

25

40

55

Frequency (kHz)

70

85 100

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (èC)

D001

图6-6. Per Channel Current Consumption (I_VDDA/B

vs. Frequency (10-nF Load, VDD = 12 V or 25 V)

)

图6-7. Per Channel (I_VDDA/B) Supply Current Vs.

Temperature (VDD=12V, No Load, Different

Switching Frequencies)

2

1.6

1.2

0.8

0.4

2

1.8

1.6

1.4

1.2

VDD= 12V

VDD= 25V

VCCI= 3.3V

VCCI= 5V

0

-40

1

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

图6-8. Per Channel (I_VDDA/B) Quiescent Supply

Current vs Temperature (No Load, Input Low, No

Switching)

图6-9. I_VCCIQuiescent Supply Current vs

Temperature (No Load, Input Low, No Switching)

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25

20

15

10

5

10

8

6

Output Pull-Up

Output Pull-Down

4

2

t_RISE

t_FALL

0

2

4

6

8

10

-40

-20

0

20

40

60

80

100 120 140

Load (nF)

Temperature (èC)

D001

图6-10. UCC21521ADW and UCC21521DW Rising

图6-11. Output Resistance vs. Temperature

and Falling Times vs. Load (VDD = 12 V)

28

24

20

16

12

20

19

18

17

16

Rising Edge (t_PDLH

Falling Edge (t_PDHL

)

Rising Edge (t_PDLH)

Falling Edge (t_PDHL

)

8

15

-40

-20

0

20

40

60

80

100 120 140

3

6

9

12

15 18

Temperature (èC)

VCCI (V)

D001

图6-12. Propagation Delay vs. Temperature

图6-13. Propagation Delay vs. VCCI

5

3

1

2.5

0

-1

-3

-5

-2.5

Rising Edge

Falling Edge

-5

10

13

16

19

22

25

-40

-20

0

20

40

60

80

100 120 140

VDDA/B (V)

Temperature (èC)

D001

图6-15. Propagation Delay Matching (t_DM) vs. VDD

图6-14. Pulse Width Distortion vs. Temperature

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5

350

330

310

290

270

250

2.5

0

-2.5

Rising Edge

Falling Edge

-5

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

图6-16. Propagation Delay Matching (t_DM) vs.

图6-17. UCC21521ADW UVLO Hysteresis vs.

Temperature

6.5

550

530

510

490

470

450

6

5.5

V_{VDD_ON}

V_{VDD_OFF}

5

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

图6-19. UCC21521DW UVLO Hysteresis vs.

图6-18. UCC21521ADW UVLO Threshold vs.

Temperature

10

9

1100

1080

1060

1040

1020

1000

980

8

7

960

940

6

920

V_{VDD_ON}

V_{VDD_OFF}

900

5

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Temperature (èC)

D001

图6-21. UCC21521CDW UVLO Hysteresis vs.

图6-20. UCC21521DW UVLO Threshold vs.

Temperature

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15

14

13

12

11

900

860

820

780

740

700

VCC=3.3V

VCC=5V

VCC=12V

V_{VDD_ON}

V_{VDD_OFF}

10

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

图6-23. INA/B Hysteresis vs. Temperature

图6-22. UCC21521CDW UVLO Threshold vs.

Temperature

1.2

1.14

1.08

1.02

2

1.92

1.84

1.76

0.96

1.68

VCC=3.3V

VCC= 5V

VCC=12V

VCC=3.3V

VCC= 5V

VCC=12V

0.9

-40

1.6

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

图6-24. INA/B Low Threshold

图6-25. INA/B High Threshold

1200

1.1

VCC=3.3V

VCC=5V

VCC=18V

1000

800

600

400

200

1

0.9

VCC=3.3V

VCC=5.0V

VCC=18V

0.8

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D001

图6-26. EN Threshold Hysteresis vs. Temperature

图6-27. EN Low Threshold

English Data Sheet: SLUSCO3

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2

1500

1200

900

600

300

0

R_DT= 20kW

R_DT= 100kW

1.8

1.6

1.4

1.2

VCC=3.3V

VCC=5.0V

VCC=18V

1

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40 60

Temperature (°C)

80

100 120 140

Temperature (èC)

D001

图6-29. Dead Time vs. Temperature (with R_DT= 20

kΩand 100 kΩ)

图6-28. EN High Threshold

5

-6

18

14

10

6

-17

-28

-39

2

-2

R_DT= 20kW

R_DT= 100kW

1 nF Load

10 nF Load

-50

-40

-6

-20

0

20

40

60

80

100 120 140

0

100

200

300

400

Time (ns)

500

600

700

800

Temperature (èC)

D001

图6-30. Dead Time Matching vs. Temperature (with

R_DT= 20 kΩand 100 kΩ)

图6-31. Typical Output Waveforms (VDD=12V)

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7 Parameter Measurement Information

7.1 Propagation Delay and Pulse Width Distortion

图 7-1 shows how one calculates pulse width distortion (t_PWD) and delay matching (t_DM) from the propagation

delays of channels A and B. It can be measured by ensuring that both inputs are in phase and disabling the

dead time function by shorting the DT Pin to VCC.

INA/B

tPDHLA

tPDLHA

tDM

OUTA

tPDLHB

tPDHLB

tPWDB = |tPDLHB t tPDHLB|

OUTB

图7-1. Overlapping Inputs, Dead Time Disabled

7.2 Rising and Falling Time

图 7-2 shows the criteria for measuring rising (t_RISE) and falling (t_FALL) times. For more information on how short

rising and falling times are achieved see Output Stage.

90%

80%

t_RISE

t_FALL

20%

10%

图7-2. Rising and Falling Time Criteria

7.3 Input and Enable Response Time

图7-3 shows the response time of the enable function. For more information, see Enable Pin.

INx

EN

EN Low

Response Time

EN High

Response Time

OUTx

t_PDLH

90%

t_PDHL

10%

图7-3. Enable Pin Timing

English Data Sheet: SLUSCO3

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7.4 Programmable Dead Time

Tying the DT pin to GND through an appropriate resistor (R_DT) sets a dead-time interval. For more details on

dead time, refer to Programmable Dead Time (DT) Pin.

INA

INB

90%

OUTA

10%

tPDHL

tPDLH

90%

OUTB

10%

tPDHL

Dead Time

(Set by RDT

Dead Time

(Determined by Input signals if

)

longer than DT set by RDT

)

图7-4. Dead-Time Switching Parameters

7.5 Powerup UVLO Delay to OUTPUT

Before the driver is ready to deliver a correct output state, there is a powerup delay from the UVLO rising edge to

output and it is defined as t_{VCCI+ to OUT}for VCCI UVLO (typically 40 μs) and t_{VDD+ to OUT}for VDD UVLO (typically

50 μs). Consider the correct margin before launching the PWM signal after the driver's VCCI and VDD bias

supplies are ready. 图7-5 and 图7-6 show the powerup UVLO delay timing diagram for VCCI and VDD.

If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output does

not update until t_{VCCI+ to OUT}or t_{VDD+ to OUT}after VCCI or VDD crossing its UVLO rising threshold. However, when

either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1-μs delay, depending

on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay helps to

ensure safe operation during VCCI or VDD brownouts.

VCCI,

INx

VCCI,

INx

V_{VCCI_ON}

V_{VCCI_OFF}

VDDx

OUTx

VDDx

OUTx

t_{VCCI+ to OUT}

t_{VDD+ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

图7-5. VCCI Powerup UVLO Delay

图7-6. VDDA/B Powerup UVLO Delay

7.6 CMTI Testing

图7-7 is a simplified diagram of the CMTI testing configuration.

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VCC

VDD

VDDA

OUTA

VSSA

INA

1

16

15

14

OUTA

INB

2

VCC

VCCI

3

GND

4

Functional

Isolation

EN

5

VDDB

11

10

9

OUTB

GND

DT

OUTB

VSSB

6

VCCI

8

VSS

Common Mode Surge

Generator

图7-7. Simplified CMTI Testing Setup

English Data Sheet: SLUSCO3

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8 Detailed Description

8.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are

often placed between the output of control devices and the gates of power transistors. There are several

instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.

This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V

logic signal capable of only delivering a few mA.

The UCC21521 is a flexible dual gate driver which can be configured to fit a variety of power supply and motor

drive topologies, as well as drive several types of transistors, including SiC MOSFETs. UCC21521 has many

features that allow it to integrate well with control circuitry and protect the gates it drives such as: resistor-

programmable dead time (DT) control, an EN pin, and under voltage lock out (UVLO) for both input and output

voltages. The UCC21521 also holds its outputs low when the inputs are left open or when the input pulse is not

wide enough. The driver inputs are CMOS and TTL compatible for interfacing to digital and analog power

controllers alike. Each channel is controlled by its respective input pins (INA and INB), allowing full and

independent control of each of the outputs.

8.2 Functional Block Diagram

INA

1

16 VDDA

200 kW

Driver

MOD

DEMOD

VCCI

15 OUTA

14 VSSA

UVLO

VCCI 3,8

UVLO

GND

DT

4

6

13 NC

12 NC

Deadtime

Control

Functional Isolation

VCCI

200 kW

11 VDDB

EN

INB

NC

5

2

7

Driver

MOD

DEMOD

10 OUTB

UVLO

9

VSSB

200 kW

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8.3 Feature Description

8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC21521 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks

between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than V_{VDD_ON}at device

start-up or lower than V_{VDD_OFF}after start-up, the VDD UVLO feature holds the effected output low, regardless of

the status of the input pins (INA and INB).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an

active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in 图 8-1). In this condition, the

upper PMOS is resistively held off by R_Hi-Zwhile the lower NMOS gate is tied to the driver output through

R_CLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS

device, typically less than 1.5 V, when no bias power is available.

VDD

R_{HI_Z}

Output

Control

OUT

R_CLAMP

R_CLAMPis activated

during UVLO

VSS

图8-1. Simplified Representation of Active Pulldown Feature

The VDD UVLO protection has a hysteresis feature (V_{VDD_HYS}). This hysteresis prevents chatter when there is

ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is

bound to happen when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC21521 also has an internal under voltage lock out (UVLO) protection feature. The

device isn't active unless the voltage, VCCI, is going to exceed V_{VCCI_ON}on start up. And a signal will cease to

be delivered when that pin receives a voltage less than V_{VCCI_OFF}. Also, like the UVLO for VDD, there is

hysteresis (V_{VCCI_HYS}) to ensure stable operation.

English Data Sheet: SLUSCO3

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All versions of the UCC21521 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.

表8-1. UCC21521 VCCI UVLO Feature Logic

INPUTS

OUTPUTS

CONDITION

INA

H

L

INB

L

OUTA

OUTB

VCCI-GND < V_{VCCI_ON}during device start up

VCCI-GND < V_{VCCI_OFF}after device start up

L

H

L

H

L

H

L

H

L

H

L

表8-2. UCC21521 VDD UVLO Feature Logic

INPUTS

OUTPUTS

CONDITION

INA

H

L

INB

L

OUTA

OUTB

VDD-VSS < V_{VDD_ON}during device start up

VDD-VSS < V_{VDD_OFF}after device start up

L

H

L

H

L

H

L

H

L

H

L

8.3.2 Input and Output Logic Table

Assume VCCI, VDDA, VDDB are powered up. See VDD, VCCI, and Under Voltage Lock Out (UVLO) for more

information on UVLO operation modes.

表8-3. INPUT/OUTPUT Logic Table⁽¹⁾

INPUTS

OUTPUTS

EN

NOTE

INA

L

INB

L

OUTA

OUTB

H or Left Open

L

H

L

If Dead Time function is used, output transitions occur after the

dead time expires. See Programmable Dead Time (DT) Pin.

L

H

L

H

L

H

L

DT is left open or programmed with R_DT.

H

L

H

L

DT pin pulled to VCCI

Left Open Left Open H or Left Open

—

X

L

(1) "X" means L, H, or left open.

8.3.3 Input Stage

The input pins (INA and INB) of UCC21521 are based on a TTL and CMOS compatible input-threshold logic that

is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-level control signals

(Such as those from 3.3-V micro-controllers), since UCC21521 has a typical high threshold (V_INA/BH) of 1.8 V

and a typical low threshold of 1 V, which vary little with temperature (see 图 6-24,图 6-25). A wide hysteresis

(V_{INA/B_HYS}) of 0.8 V makes for good noise immunity and stable operation. If any of the inputs are ever left open,

internal pull-down resistors force the pin low. These resistors are typically 200 kΩ (see Functional Block

Diagram). However, it is still recommended to ground an input if it is not being used.

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Since the input side of UCC21521 is isolated from the output drivers, the input signal amplitude can be larger or

smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility when

integrating with control signal sources, and allows the user to choose the most efficient VDD for their chosen

gate. That said, the amplitude of any signal applied to INA or INB must never be at a voltage higher than VCCI.

8.3.4 Output Stage

The UCC21521 output stages feature a pull-up structure which delivers the highest peak-source current when it

is most needed, during the Miller plateau region of the power-switch turn on transition (when the power switch

drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel MOSFET

and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a

brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning on the N-

channel MOSFET during a narrow instant when the output is changing states from low to high. The on-

resistance of this N-channel MOSFET (R_NMOS) is approximately 1.47 Ωwhen activated.

The R_OHparameter is a DC measurement and it is representative of the on-resistance of the P-channel device

only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only

for a brief instant when the output is changing states from low to high. Therefore, the effective resistance of the

UCC21521 pull-up stage during this brief turn-on phase is much lower than what is represented by the R_OH

parameter. Therefore, the value of R_OHbelies the fast nature of the UCC21521's turn-on time.

The pull-down structure in UCC21521 is simply composed of an N-channel MOSFET. The R_OLparameter, which

is also a DC measurement, is representative of the impedance of the pull-down state in the device. Both outputs

of the UCC21521 are capable of delivering 4-A peak source and 6-A peak sink current pulses. The output

voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the MOS-out stage which

delivers very low drop-out.

VDD

R_OH

Shoot-

R_NMOS

Input

Signal

Through

Prevention

Circuitry

OUT

VSS

R_OL

Pull Up

图8-2. Output Stage

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8.3.5 Diode Structure in UCC21521

图8-3 illustrates the multiple diodes involved in the ESD protection components of the UCC21521. This provides

a pictorial representation of the absolute maximum rating for the device.

VCCI

3,8

VDDA

16

30 V

15 OUTA

14 VSSA

20 V 20 V 20 V 20 V 20 V 20 V

30 V

INA

INB

EN

DT

1

2

5

6

11 VDDB

10 OUTB

30 V

20 V 20 V 20 V 20 V

4

9

GND

VSSB

图8-3. ESD Structure

8.4 Device Functional Modes

8.4.1 Enable Pin

Setting the EN pin low, V_EN≤0.8 V, shuts down both outputs simultaneously. Pull the EN pin high (or left open),

V_EN≥2.0 V, allows UCC21521 to operate normally. The EN pin response time is in the range of 20ns and quite

responsive, which is as fast as propagation delay. The EN pin is only functional (and necessary) when VCCI

stays above the UVLO threshold. It is recommended to tie this pin to VCCI if the EN pin is not used to achieve

better noise immunity.

8.4.2 Programmable Dead Time (DT) Pin

UCC21521 enables users to adjust dead time (DT) as detailed in the following sections.

8.4.2.1 Tying the DT Pin to VCC

Outputs completely match inputs, so no dead time is asserted. This allows outputs to overlap.

8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins

To program t_DT, place a resistor, R_DT, between the DT pin and GND. The appropriate R_DTvalue can be

determined from 方程式1, where R_DTis in kΩ and t_DTin ns:

t_DT» 10 ´ R_DT

(1)

The steady state voltage at the DT pin is around 0.8 V, and the DT pin current is less than 10 μA when R_DT

=

100 kΩ. Therefore, it is recommended to parallel a ceramic capacitor, 2.2 nF or above, close to the chip with

R_DTto achieve better noise immunity and better dead time matching between two channels. Do not leave the DT

pin floating.

An input signal’s falling edge activates the programmed dead time for the other signal. The output signals’

dead time is always set to the longer of either the driver’s programmed dead time or the input signal’s own

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dead time. If both inputs are high simultaneously, both outputs are immediately set low. This feature is used to

prevent shoot-through, and it does not affect the programmed dead time setting for normal operation. Various

driver dead time logic operating conditions are illustrated in 图8-4 .

INA

INB

DT

OUTA

OUTB

A

B

C

D

E

F

图8-4. Input and Output Logic Relationship with Input Signals

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead

time to OUTA. OUTA is allowed to go high after the programmed dead time.

Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed

dead time to OUTB. OUTB is allowed to go high after the programmed dead time.

Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead

time for OUTA. In this case, the input signal’s own dead time is longer than the programmed dead time. Thus,

when INA goes high, it immediately sets OUTA high.

Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead

time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, it

immediately sets OUTB high.

Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls

OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to

OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls

OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to

OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The UCC21521 effectively combines both isolation and buffer-drive functions. The flexible, universal capability of

the UCC21521 (with up to 18-V VCCI and 25-V VDDA/VDDB) allows the device to be used as a low-side, high-

side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs. With integrated

components, advanced protection features (UVLO, dead time, and enable) and optimized switching

performance; the UCC21521 enables designers to build smaller, more robust designs for enterprise, telecom,

automotive, and industrial applications with a faster time to market.

9.2 Typical Application

The circuit in 图 9-1 shows a reference design with UCC21521 driving a typical half-bridge configuration which

could be used in several popular power converter topologies such as synchronous buck, synchronous boost,

half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.

VDD

VCC

R_BOOT

HV DC-Link

VCC

VDDA

INA

INB

R_OFF

R_ON

16

15

14

PWM-A

1

2

3

4

5

6

8

R_IN

OUTA

VSSA

C_IN

PWM-B

R_GS

C_BOOT

VCCI

GND

EN

C_IN

mC

C_VCC

SW

Functional

Isolation

VDD

EN

VDDB

I/O

R_OFF

R_ON

11

10

9

R_EN

DT

≥2.2nF

OUTB

VSSB

R_GS

VCCI

C_VDD

R_DT

VSS

图9-1. Typical Application Schematic

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9.2.1 Design Requirements

表 9-1 lists reference design parameters for the example application: UCC21521 driving 1200-V SiC-MOSFETs

in a high side-low side configuration.

表9-1. UCC21521 Design Requirements

PARAMETER

Power transistor

VCC

VALUE

UNITS

C2M0080120D

-

V

5.0

20

VDD

V

Input signal amplitude

Switching frequency (f_s)

DC link voltage

3.3

100

800

V

kHz

V

9.2.2 Detailed Design Procedure

9.2.2.1 Designing INA/INB Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)

the signal at the output. However, a small input R_IN-C_INfilter can be used to filter out the ringing introduced by

non-ideal layout or long PCB traces.

Such a filter should use an R_INin the range of 0 Ω to 100 Ω and a C_INbetween 10 pF and 100 pF. In the

example, an R_IN= 51 Ωand a C_IN= 33 pF are selected, with a corner frequency of approximately 100 MHz.

When selecting these components, it is important to pay attention to the trade-off between good noise immunity

and propagation delay.

9.2.2.2 Select External Bootstrap Diode and its Series Resistor

VDD charges the bootstrap capacitor through an external bootstrap diode every cycle when the low-side

transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation

in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.

Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver

circuit.

When selecting external bootstrap diodes, choose high-voltage, fast recovery diodes or SiC Schottky diodes with

a low forward voltage drop and low junction capacitance to minimize the loss introduced by reverse recovery and

related grounding noise bouncing. In the example, the DC-link voltage is 800 V_DC. The voltage rating of the

bootstrap diode should be higher than the DC-link voltage with a good margin. Therefore, a 1200-V SiC diode,

C4D02120E, is chosen in this example.

When designing a bootstrap supply, it is recommended to use bootstrap resistor, R_BOOT. A bootstrap resistor is

also used to reduce the inrush current in D_BOOTand limit the ramp up slew rate of voltage of VDDA-VSSA during

each switching cycle. A bootstrap resistor also helps reduce a bootstrap voltage overshoot due to large a switch

node undershoot.

WARNING

Failure to limit the voltage to VDDx-VSSx to less than the Absolute Maximum Ratings of the FET

and UCC21521 may result in permanent damage to the device in certain cases.

The recommended value for R_BOOTis between 1 Ω and 20 Ω depending on the diode used. In the example, a

current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode. The estimated worst-

case peak current through D_Bootis as follows:

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V_DD- V_BDF

R_Boot

20V - 2.5V

2.2W

I_{DBoot pk}

=

ö 8A

(

)

(2)

where

• V_BDFis the estimated bootstrap diode forward voltage drop at 8 A.

9.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, R_ON/R_OFF, are used to:

1. Limit ringing caused by parasitic inductances/capacitances.

2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.

3. Fine-tune gate drive strength, that is, peak sink and source current to optimize the switching loss.

4. Reduce electromagnetic interference (EMI).

As mentioned in Output Stage, the UCC21521 has a pull-up structure with a P-channel MOSFET and an

additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak

source current can be predicted with:

≈

∆

«

’

V_DD- V_BDF

R_NMOS||R_OH+R_ON+R_{GFET _Int}

I_OA+= min 4A,

∆

÷

◊

(3)

(4)

≈

∆

«

’

V_DD

I_OB+= min 4A,

∆

÷

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}

◊

where

• R_ON: External turn-on resistance.

• R_{GFET_INT}: Power transistor internal gate resistance, found in the power transistor datasheet.

• I_O+= Peak source current –The minimum value between 4 A, the gate driver peak source current, and the

calculated value based on the gate drive loop resistance.

In this example:

V_DD- V_BDF

20V - 0.8V

I_OA+

=

ö 2.4A

ö 2.5A

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W + 4.6W

(5)

(6)

V_DD

20V

I_OB+

=

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W + 4.6W

Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peak

sink current can be calculated with:

≈

∆

«

’

V_DD- V_BDF- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET_Int}

I_OA-= min 6A,

∆

÷

◊

(7)

(8)

≈

∆

«

’

V_DD- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET _Int}

I_OB-= min 6A,

∆

÷

◊

where

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• R_OFF: External turn-off resistance;

• V_GDF: The anti-parallel diode forward voltage drop which is in series with R_OFF. The diode in this example is

an MSS1P4.

• I_O-: Peak sink current –the minimum value between 6 A, the gate driver peak sink current, and the

calculated value based on the gate drive loop resistance.

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In this example,

V_DD- V_BDF- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET _Int}

20V - 0.8V - 0.75V

0.55W + 0W + 4.6W

I_OA-

=

ö 3.6A

(9)

V_DD- V_GDF

20V-0.75V

I_OB-=

=

ö 3.7A

R_OL+ R_OFF||R_ON+ R_{GFET _Int}0.55W + 0W + 4.6W

(10)

Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively.

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and

undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other

hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (C_ISS) of the

power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close

to the parasitic ringing period.

Failure to control OUTx voltage to less than the Absolute Maximum Ratings in the datasheet (including

transients) may result in permanent damage to the device in certain cases. To reduce excessive gate ringing, it

is recommended to use a ferrite bead near the gate of the FET. External clamping diodes can also be added in

the case of extended overshoot/undershoot, in order to clamp the OUTx voltage to the VDDx and VSSx

voltages.

9.2.2.4 Gate to Source Resistor Selection

A gate to the source resistor, R_GS, is recommended to pull down the gate to the source voltage when the gate

driver is unpowered and in an indeterminate state. This resistor also helps to mitigate the risk of a dv/dt induced

turn-on due to Miller current before the gate driver is able to turn on and actively pull low. This resistor is typically

sized between 5.1 kΩand 20 kΩ, depending on the Vth and ratio of C_GDto C_GSof the power device.

9.2.2.5 Estimate Gate Driver Power Loss

The total loss, P_G, in the gate driver subsystem includes the power losses of the UCC21521 (P_GD) and the

power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not

included in P_Gand not discussed in this section.

P_GDis the key power loss which determines the thermal safety-related limits of the UCC21521, and it can be

estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes quiescent power loss on the driver as well as

driver self-power consumption when operating with a certain switching frequency. P_GDQis measured on the

bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and

ambient temperature. 图 6-4 shows the per output channel current consumption vs. operating frequency with no

load. In this example, V_VCCI= 5 V and V_VDD= 20 V. The current on each power supply, with INA/INB switching

from 0 V to 3.3 V at 100 kHz is measured to be I_VCCI= 2.5 mA, and I_VDDA= I_VDDB= 1.5 mA. Therefore, the P_GDQ

can be calculated with

P

= V_VCCIìI_VCCI+ V_VDDAìI_DDA+ V_VDDBìI_DDBö 72mW

GDQ

(11)

The second component is switching operation loss, P_GDO, with a given load capacitance which the driver

charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, P_GSW

can be estimated with

,

P_GSW= 2 ì V_DDì Q_Gì f_SW

(12)

where

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• Q_Gis the gate charge of the power transistor.

If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail

to the negative rail.

So, for this example application:

P_GSW= 2 ì 20V ì 60nC ì100kHz = 240mW

(13)

Q_Grepresents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to change

with different testing conditions. The UCC21521 gate driver loss on the output stage, P_GDO, is part of P_GSW

.

P_GDOwill be equal to P_GSWif the external gate driver resistances are zero, and all the gate driver loss is

dissipated inside the UCC21521. If there are external turn-on and turn-off resistances, the total loss will be

distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the pull-

up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however,

it will be non-linear if the source/sink current is saturated. Therefore, P_GDOis different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

≈

’

P_GSW

2

R_OH||R_NMOS

R_OL

P_GDO

=

ì

+

∆

«

÷

◊

R_OH||R_NMOS+R_ON+R_{GFET _Int}R_OL+R_OFF||R_ON+ R_{GFET _Int}

(14)

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21521

gate driver loss can be estimated with:

≈

∆

«

’

÷

◊

240mW

2

5W ||1.47W

0.55W

P_GDO

=

ì

+

ö 30mW

5W ||1.47W + 2.2W + 4.6W 0.55W + 0W + 4.6W

(15)

Case 2 - Nonlinear Pull-Up/Down Resistor:

T_{R _ Sys}

T_{F_ Sys}

»

ÿ

Ÿ

P_GDO= 2 ì f_SWì 4A ì

V - V

t dt + 6A ì

( )

V_OUTA/Bt dt

( )

…

(

)

DD

OUTA/B

—

…

Ÿ

⁄

0

(16)

where

• V_OUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be

simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load

capacitor. Then, the V_OUTA/B(t) waveform will be linear and the T_{R_Sys}and T_{F_Sys}can be easily predicted.

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the P_GDO

will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-

down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21521,

P_GD, is:

P_GD= P + P

GDQ

GDO

(17)

which is equal to 102 mW in the design example.

9.2.2.6 Estimating Junction Temperature

The junction temperature (T_J) of the UCC21521 can be estimated with:

T_J= T_C+ Y_JT´ P_GD

(18)

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where

• T_Cis the UCC21521 case-top temperature measured with a thermocouple or some other instrument, and

• Ψ_JTis the Junction-to-case-top thermal resistance from the Thermal Information table.

Using the junction-to-top characterization parameter (Ψ_JT) instead of the junction-to-case thermal resistance

(R_ΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

R_ΘJCcan only be used effectively when most of the thermal energy is released through the case, such as with

metal packages or when a heatsink is applied to an IC package. In all other cases, use of R_ΘJCwill inaccurately

estimate the true junction temperature. Ψ_JTis experimentally derived by assuming that the amount of energy

leaving through the top of the IC will be similar in both the testing environment and the application environment.

As long as the recommended layout guidelines are observed, junction temperature estimates can be made

accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package

Thermal Metrics application report.

9.2.2.7 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is

recommended that one choose low ESR and low ESL surface-mount multilayer ceramic capacitors (MLCC) with

sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC

will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500

nF when a DC bias of 15 V_DCis applied.

9.2.2.7.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total

current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for this

application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or

electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.

9.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for

gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.

The total charge needed per switching cycle can be estimated with

I_VDD@100kHz No Load

(

f_SW

)

1.5mA

Q_Total= Q_G+

= 60nC +

= 75nC

100kHz

(19)

where

• Q_Total: Total charge needed

• Q_G: Gate charge of the power transistor.

• I_VDD: The channel self-current consumption with no load at 100kHz.

• f_SW: The switching frequency of the gate driver

Therefore, the absolute minimum C_Bootrequirement is:

Q_Total

75nC

C_Boot

=

= 150nF

DV_VDDA0.5V

(20)

where

• ΔV_VDDAis the voltage ripple at VDDA, which is 0.5 V in this example.

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In practice, the value of C_Bootis greater than the calculated value. This allows for the capacitance shift caused by

the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.

Therefore, it is recommended to include a safety-related margin in the C_Bootvalue and place it as close to the

VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

C_Boot= 1ꢀF

(21)

Care should be taken when selecting the bootstrap capacitor to ensure that the VDD to VSS voltage does not

drop below the recommended minimum operating level listed in 节 6.3. The value of the bootstrap capacitor

should be sized such that it can supply the initial charge to switch the power device, and then continuously

supply the gate driver quiescent current for the duration of the high-side on-time.

If the high-side supply voltage drops below the UVLO falling threshold, the high-side gate driver output will turn

off and switch the power device off. Uncontrolled hard-switching of power devices can cause high di/dt and high

dv/dt transients on the output of the driver and may result in permanent damage to the device.

To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor

placed very close to VDDx - VSSx pins with a low ESL/ESR. In this example a 100 nF, X7R ceramic capacitor, is

placed in parallel with C_Bootto optimize the transient performance.

备注

Too large C_BOOTis not good. C_BOOTmay not be charged within the first few cycles and V_BOOTcould

stay below UVLO. As a result, the high-side FET does not follow input signal command. Also during

initial C_BOOTcharging cycles, the bootstrap diode has highest reverse recovery current and losses.

9.2.2.7.3 Select a VDDB Capacitor

Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as C_VDDin 图

9-1) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current for

VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for C_VDD. If the

bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor,

with a value over 10 µF, should be used in parallel with CVDD.

9.2.2.8 Dead Time Setting Guidelines

For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor

is important for preventing shoot-through during dynamic switching.

The UCC21521 dead time specification in the electrical table is defined as the time interval from 90% of one

channel’s falling edge to 10% of the other channel’s rising edge (see 图 7-4). This definition ensures that the

dead time setting is independent of the load condition, and guarantees linearity through manufacture testing.

However, this dead time setting may not reflect the dead time in the power converter system, since the dead

time setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as

well as the input capacitance of the load transistor.

Here is a suggestion on how to select an appropriate dead time for UCC21521:

DT_Setting= DT_Req+ T_{F_Sys}+ T_{R _Sys}- T_{D on}

(

)

(22)

where

• DT_setting: UCC21521 dead time setting in ns, DT_Setting= 10 × RDT(in kΩ).

• DT_Req: System required dead time between the real V_GSsignal of the top and bottom switch with enough

margin, or ZVS requirement.

• T_{F_Sys}: In-system gate turn-off falling time at worst case of load, voltage/current conditions.

• T_{R_Sys}: In-system gate turn-on rising time at worst case of load, voltage/current conditions.

• T_D(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.

English Data Sheet: SLUSCO3

32

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In the example, DT_Settingis set to 250 ns.

It should be noted that the UCC21521 dead time setting is decided by the DT pin configuration (See

Programmable Dead Time (DT) Pin), and it cannot automatically fine-tune the dead time based on system

conditions. And it is recommended to parallel a ceramic capacitor, 2.2nF or above, with R_DTto achieve better

noise immunity.

9.2.2.9 Application Circuits with Output Stage Negative Bias

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (for example,

TO-220 and TO-247 type packages), there could be ringing in the gate-source drive voltage of the power

transistor during high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of an

unintended turn-on and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep

such ringing below the threshold. Below are a few examples of implementing negative gate drive bias.

图 9-2 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the

isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power

supply, V_A, is equal to 25 V, the turn-off voltage is –5.1 V and turn-on voltage is 25 V – 5.1 V ≈ 20 V. The

channel-B driver circuit is the same as channel-A; therefore, this configuration needs two power supplies for a

half-bridge configuration, so there is a steady state power consumption from R_Z.

HV DC-Link

VDDA

R_OFF

16

1

C_A1

+

V_A

œ

C_IN

R_Z

25 V

R_ON

OUTA

VSSA

15

14

2

3

4

5

6

8

C_A2

V_Z= 5.1 V

SW

Functional

Isolation

VDDB

11

10

9

OUTB

VSSB

图9-2. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

图 9-3 shows another example that uses two supplies (or single-input-double-output power supply). Power

supply V_A+determines the positive drive output voltage and V_A–determines the negative turn-off voltage. The

configuration for channel B is the same as channel A. This solution requires more power supplies than the first

example, however, it provides more flexibility when setting the positive and negative rail voltages.

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ZHCSFM4B –SEPTEMBER 2016 –REVISED DECEMBER 2021

HV DC-Link

C_IN

VDDA

R_OFF

R_ON

16

15

1

2

3

4

5

6

8

C_A1

+

V_A+

œ

OUTA

VSSA

C_A2

+

V_A-

œ

14

Functional

Isolation

SW

VDDB

11

10

9

OUTB

VSSB

图9-3. Negative Bias with Two Iso-Bias Power Supplies

The last example, shown in 图9-4, is a single power supply configuration and generates negative bias through a

Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the

bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort

among the three solutions. However, this solution has limitations:

1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which

means the negative bias voltage changes when the duty cycle changes. Therefore, converters with a fixed

duty cycle (approximately 50%) such as variable frequency resonant convertors or phase shift convertors

favor this solution.

2. The high-side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,

which means the low side switch must turn on or have free-wheeling current on the body (or anti-parallel)

diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%

duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in

the other two example circuits. It is important to ensure RGS is properly selected to correctly bias the Zener

diode. In addition, it is recommended to keep RGS small to ensure that the negative gate drive bias circuitry

reaches steady state in a short time. Increasing RGS increases the charging time for capacitor C_Z, and

therefore increases the time for the negative bias to reach steady state.

English Data Sheet: SLUSCO3

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VDD

R_BOOT

HV DC-Link

VDDA

C_Z

V_Z

R_OFF

R_ON

16

15

14

1

2

3

4

5

6

8

OUTA

VSSA

C_IN

C_BOOT

R_GS

SW

Functional

Isolation

VDD

VDDB

C_Z

V_Z

R_OFF

R_ON

11

10

9

OUTB

VSSB

C_VDD

R_GS

VSS

图9-4. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

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9.2.3 Application Curves

图 9-5 and 图 9-6 shows the bench test waveforms for the design example shown in 图 9-1 under these

conditions: VCC = 5 V, VDD = 20 V, f_SW= 100 kHz, V_DC-Link= 0 V.

Channel 1 (Yellow): UCC21521 INA pin signal.

Channel 2 (Blue): UCC21521 INB pin signal.

Channel 3 (Pink): Gate-source signal on the high side power transistor.

Channel 4 (Green): Gate-source signal on the low side power transistor.

In 图 9-5, INA and INB are sent complimentary 3.3-V, 50% duty-cycle signals. The gate drive signals on the

power transistor have a 250-ns dead time, shown in the measurement section of 图9-5. The dead-time matching

is less than 1 ns with the 250-ns dead-time setting.

图 9-6 shows a zoomed-in version of the waveform of 图 9-5, with measurements for propagation delay and

rising/falling time. Cursors are also used to measure dead time. Importantly, the output waveform is measured

between the power transistors’ gate and source pins, and is not measured directly from the driver OUTA and

OUTB pins. Due to the split on and off resistors (R_on,R_off) and different sink and source currents, different rising

(16 ns) and falling time (9 ns) are observed in 图9-6.

图9-5. Bench Test Waveform for INA/B and

图9-6. Zoomed-In bench-test waveform

OUTA/B

36

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10 Power Supply Recommendations

The recommended input supply voltage (VCCI) for UCC21521 is between 3 V and 18 V. The output bias supply

voltage (VDDA/VDDB) range depends on which version of UCC21521 one is using. The lower end of this bias

supply range is governed by the internal under voltage lockout (UVLO) protection feature of each device. One

mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on UVLO see VDD,

VCCI, and Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends on the

maximum gate voltage of the power device being driven by UCC21521. All versions of UCC21521 have a

recommended maximum VDDA/VDDB of 25 V.

A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned

as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further

suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional

≤100-nF capacitor in parallel for high frequency filtering.

Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of

current drawn by the logic circuitry within the input side of UCC21521, this bypass capacitor has a minimum

recommended value of 100 nF.

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ZHCSFM4B –SEPTEMBER 2016 –REVISED DECEMBER 2021

11 Layout

11.1 Layout Guidelines

One must pay close attention to PCB layout in order to achieve optimum performance for the UCC21521. Below

are some key points.

Component Placement:

• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins

and between the VDD and VSS pins to support high peak currents when turning on the external power

transistor.

• To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the

source of the top transistor and the source of the bottom transistor must be minimized.

• It is recommended to place the dead-time setting resistor, RDT, and its bypassing capacitor close to DT pin of

the UCC21521.

Grounding Considerations:

• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal

physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the

transistors. The gate driver must be placed as close as possible to the transistors.

• Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-

referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is

recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This

recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and

area on the circuit board is important for ensuring reliable operation.

High-Voltage Considerations:

• To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB

traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination

that may compromise the UCC21521’s isolation performance.

• For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could

operate with a DC-link voltage up to 1500 V_DC, one should try to increase the creepage distance of the PCB

layout between the high and low-side PCB traces.

Thermal Considerations:

• A large amount of power may be dissipated by the UCC21521 if the driving voltage is high, the load is heavy,

or the switching frequency is high (Refer to Estimate Gate Driver Power Loss for more details). Proper PCB

layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance

(θ_JB).

• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended (See 图11-2

and 图11-3). However, high voltage PCB considerations mentioned above must be maintained.

• If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and

VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind

that there shouldn’t be any traces/coppers from different high voltage planes overlapping.

English Data Sheet: SLUSCO3

38

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11.2 Layout Example

图11-1 shows a 2-layer PCB layout example with the signals and key components labeled.

Bootstrap Diode

(Bot. Layer)

Input Filters

(Top Layer)

PCB Cutout

To High Side

Transistor

PWM Inputs

(Top Layer)

VCCI Caps.

(Top Layer)

GND plane

(Bot. Layer)

To Low Side

Transistor

VDD Caps.

(Bot. Layer)

图11-1. Layout Example

图11-2 and 图11-3 shows top and bottom layer traces and copper.

备注

There are no PCB traces or copper between the primary and secondary side, which ensures isolation

performance.

PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the

creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node

VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

图11-2. Top Layer Traces and Copper

图11-3. Bottom Layer Traces and Copper

图11-4 and 图11-5 are 3D layout pictures with top view and bottom views.

备注

The location of the PCB cutout between the primary side and secondary sides, which ensures

isolation performance.

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ZHCSFM4B –SEPTEMBER 2016 –REVISED DECEMBER 2021

图11-4. 3-D PCB Top View

图11-5. 3-D PCB Bottom View

English Data Sheet: SLUSCO3

40

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ZHCSFM4B –SEPTEMBER 2016 –REVISED DECEMBER 2021

12 Device and Documentation Support

12.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• Isolation Glossary

12.3 Certifications

UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate

Number: 20160516-E181974

VDE Pruf- und Zertifizierungsinstitut Certification, Certificate of Conformity with Factory Surveillance

CQC Online Certifications Directory, "GB4943.1-2011, Digital Isolator Certificate" Certificate

Number:CQC16001155011

CSA Online Certifications Directory, "CSA Certificate of Compliance" Certificate Number:70097761, Master

Contract Number:220991

12.4 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.5 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.6 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.7 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.8 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: UCC21521

English Data Sheet: SLUSCO3

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC21521ADWR

UCC21521CDWR

UCC21521DWR

SOIC

DW

16

2000

330.0

16.4

10.75 10.7

2.7

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC21521ADWR

UCC21521CDWR

UCC21521DWR

SOIC

DW

16

2000

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

UCC21521ADW

UCC21521CDW

UCC21521DW

DW

SOIC

16

40

506.98

12.7

4826

6.6

Pack Materials-Page 3

GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

www.ti.com

PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

www.ti.com

EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

1

16X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

9

8

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

1

16

16X (0.6)

SYMM

14X (1.27)

8

9

8

9

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC21521ADWR
厂家：	TEXAS INSTRUMENTS
描述：	具有双输入、使能引脚、8V UVLO 且采用 LGA 封装的 5.7kVrms、4A/6A 双通道隔离式栅极驱动器 \| DW \| 16 \| -40 to 125 栅极驱动双极性晶体管光电二极管接口集成电路驱动器
文件：	总51页 (文件大小：3121K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC21521ADWR [TI]

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