UC3855ADWTRG4 [TI]
High Performance Power Factor Preregulator; 高性能功率因数前置稳压器
| 型号： | UC3855ADWTRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Performance Power Factor Preregulator |
| 文件： | 总17页 (文件大小：1063K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UC2855A/B
UC3855A/B
available
High Performance Power Factor Preregulator
FEATURES
DESCRIPTION
• Controls Boost PWM to Near Unity
Power Factor
The UC3855A/B provides all the control features necessary for high
power, high frequency PFC boost converters. The average current mode
control method allows for stable, low distortion AC line current program-
ming without the need for slope compensation. In addition, the UC3855
utilizes an active snubbing or ZVT (Zero Voltage Transition technique) to
dramatically reduce diode recovery and MOSFET turn-on losses, result-
ing in lower EMI emissions and higher efficiency. Boost converter switch-
ing frequencies up to 500kHz are now realizable, requiring only an
additional small MOSFET, diode, and inductor to resonantly soft switch
the boost diode and switch. Average current sensing can be employed us-
ing a simple resistive shunt or a current sense transformer. Using the cur-
rent sense transformer method, the internal current synthesizer circuit
buffers the inductor current during the switch on-time, and reconstructs the
inductor current during the switch off-time. Improved signal to noise ratio
and negligible current sensing losses make this an attractive solution for
higher power applications.
• Fixed Frequency Average Current
Mode Control Minimizes Line Current
Distortion
• Built-in Active Snubber (ZVT) allows
Operation to 500kHz, improved EMI
and Efficiency
• Inductor Current Synthesizer allows
Single Current Transformer Current
Sense for Improved Efficiency and
Noise Margin
• Accurate Analog Multiplier with Line
Compensator allows for Universal
Input Voltage Operation
The UC3855A/B also features a single quadrant multiplier, squarer, and
divider circuit which provides the programming signal for the current loop.
The internal multiplier current limit reduces output power during low line
conditions. An overvoltage protection circuit disables both controller out-
puts in the event of a boost output OV condition.
• High Bandwidth (5MHz), Low Offset
Current Amplifier
• Overvoltage and Overcurrent
protection
• Two UVLO Threshold Options
• 150µA Startup Supply Current Typical
• Precision 1% 7.5V Reference
Low startup supply current, UVLO with hysteresis, a 1% 7.5V reference,
voltage amplifier with softstart, input supply voltage clamp, enable com-
parator, and overcurrent comparator complete the list of features. Avail-
able packages include: 20 pin N, DW, Q, J, and L.
BLOCK DIAGRAM
UDG-94001-2
License Patent from Pioneer Magnetics. Pin numbers refer to DIL-20 J or N packages.
SLUS328B JUNE 1998 - REVISED October 2005
UC2855A/B
UC3855A/B
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC. . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited
VCC Supply Clamp Current . . . . . . . . . . . . . . . . . . . . . . . 20mA
PFC Gate Driver Current (continuous) . . . . . . . . . . . . . . ± 0.5A
PFC Gate Driver Current (peak) . . . . . . . . . . . . . . . . . . . ± 1.5A
ZVT Drive Current (continuous) . . . . . . . . . . . . . . . . . . . ± 0.25A
ZVT Drive Current (peak). . . . . . . . . . . . . . . . . . . . . . . . ± 0.75A
Input Current (IAC, RT, RVA) . . . . . . . . . . . . . . . . . . . . . . . 5mA
Analog Inputs (except Peak Limit). . . . . . . . . . . . . . −0.3 to 10V
Peak Limit Input . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 6.5V
Softstart Sinking Current . . . . . . . . . . . . . . . . . . . . . . . . . 1.5mA
Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . −55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
PLCC-20 & LCC-20 (Top View)
Q or L Package
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages. All voltages are
referenced to GND.
DIL–20 (Top View)
J or N Package
SOIC-20 (Top View)
DW Package
ELECTRICAL CHARACTERISTICS:Unless otherwise specified: VCC = 18V, RVS = 23k, CT = 470pF, CI = 150pF, VRMS
= 1.5V, IAC = 100µA, ISENSE = 0V, CAO = 4V, VAOUT= 3.5V, VSENSE = 3V. –40°C to 85°C (UC2855A/B), 0°C to 70°C
(UC3855A/B).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Overall
Supply Current, OFF
CAO, VAOUT = 0V, VCC = UVLO −0.3V
150
17
500
25
µA
mA
V
Supply Current, OPERATING
VCC Turn-On Threshold
VCCTurn-Off Threshold
VCC Turn-On Threshold
VCC Clamp
UC3855A
15.5
10
17.5
UC3855A,B
9
V
UC3855B
10.5
20
10.8
22
V
I(VCC) = ICC(on) + 5mA
18
V
Voltage Amplifier
Input Voltage
2.9
−500
65
3.1
V
nA
dB
V
VSENSE Bias Current
Open Loop Gain
25
80
6
500
VOUT = 2 to 5V
ILOAD = –300µA
ILOAD = 300µA
VOUT = 0V
VOUT High
5.75
6.25
0.5
3
V
OUT Low
0.3
0.6
V
Output Short Circuit Current
mA
2
UC2855A/B
UC3855A/B
ELECTRICAL CHARACTERISTICS:Unless otherwise specified: VCC = 18V, RVS = 23k, CT = 470pF, CI = 150pF, VRMS
= 1.5V, IAC = 100µA, ISENSE = 0V, CAO = 4V, VAOUT= 3.5V, VSENSE = 3V. –40°C to 85°C (UC2855A/B), 0°C to 70°C
(UC3855A/B).
PARAMETER
Current Amplifier
TEST CONDITIONS
MIN
TYP
MAX UNITS
Input Offset Voltage
Input Bias Current (Sense)
Open Loop Gain
VCM = − 2.5V
−4
−500
80
4
mV
nA
dB
V
VCM = 2.5V
500
VCM = 2.5V, VOUT = 2 to 6V
ILOAD = −500µA
ILOAD = 500µA
110
6
VOUT High
VOUT Low
0.3
1
0.5
3
V
Output Short Circuit Current
Common Mode Range
Gain Bandwidth Product
Reference
VOUT = 0V
mA
V
−0.3
5
FIN = 100kHz, 10mV, P–P, TA = 25°C
2.5
5
MHz
Output Voltage
IREF = 0mA, TA = 25°C
IREF = 0mA
7.388
7.313
−15
7.5
7.5
7.613
7.688
15
V
V
Load Regulation
Line Regulation
IREF = 1 to 10 mA
VCC = 15 to 35V
REF = 0V
mV
mV
mA
−10
10
Short Circuit Current
Oscillator
20
45
65
Initial Accuracy
TA = 25°C
170
200
1
230
kHz
%
Voltage Stability
VCC = 12 to 18V
Line, Temp.
Total Variation
160
4.7
1.1
240
5.7
1.6
kHz
V
Ramp Amplitude (P–P)
Ramp Valley Voltage
Enable/OVP/Current Limit
Enable Threshold
Outputs at 0% duty cycle
V
1.8
7.5
400
200
1
2.2
7.66
600
V
V
OVP Threshold
OVP Hysteresis
200
mV
ns
µA
V
OVP Propagation Delay
OVP Input Bias Current
PKLIMIT Threshold
PKLIMIT Input Current
PKLIMIT Prop. Delay
Soft Start
V= 7.5V
10
1.25
1.5
100
100
1.75
VPKLIMIT = 1.5V
µA
ns
Soft Start Charge Current
Soft Start Discharge Current
Multiplier
-10
2
-13
10
-20
20
mA
mA
Output Current - IAC Limited
Output Current - Zero
Output Current - Power Limited
Output Current
IAC = 100µA, VRMS = 1V
IAC = 0µA
−235 −205 −175
−2 −0.2
µA
µA
µA
µA
µA
µA
µA
1/V
2
VRMS = 1.5V, VAOUT = 5.5V
VRMS = 1.5V, VAOUT = 2V
VRMS = 1.5V VAOUT = 5V
VRMS = 5V, VAOUT = 2V
VRMS = 5V, VAOUT = 5V
Refer to Note 1
−250 −209 −160
−26
−190
−3
−17
Gain Constant
−0.95 −0.85 −0.75
3
UC2855A/B
UC3855A/B
ELECTRICAL CHARACTERISTICS:Unless otherwise specified: VCC = 18V, RVS = 23k, CT = 470pF, CI = 150pF, VRMS
= 1.5V, IAC = 100µA, ISENSE = 0V, CAO = 4V, VAOUT= 3.5V, VSENSE = 3V. –40°C to 85°C (UC2855A/B), 0°C to 70°C
(UC3855A/B).
PARAMETER
Gate Driver Output
TEST CONDITIONS
MIN
TYP
MAX UNITS
Output High Voltage
Output Low Voltage
Output Low Voltage
Output Low (UVLO)
Output RISE/FALL Time
Output Peak Current
lOUT = −200mA, VCC = 15V
12
12.8
1
V
lOUT = 200mA
2.2
500
1.5
V
mV
V
lOUT = 10mA
300
0.9
35
lOUT = 50mA, VCC = 0V
CLOAD = 1nF
ns
A
CLOAD = 10nF
0.5
2.3
1.5
ZVT
ZVS Threshold
2.6
6
2.9
20
V
µA
ns
ns
V
Input Bias Current
Propagation Delay
Maximum Pulse Width
Output High Voltage
Output Low Voltage
V = 2.5V, VCT = 0
Measured at ZVTOUT
100
400
12.8
1
l
l
l
l
OUT = −100mA, VCC = 15V
12
OUT = 100mA
2.2
900
1.5
V
OUT = 10mA
300
0.9
35
mV
V
Output Low (UVLO)
Output RISE/FALL Time
Output Peak Current
Current Synthesizer
ION to CS Offset
OUT = 50mA, VCC = 0V
C
C
LOAD = 1nF
ns
A
LOAD = 10nF
0.25
0.75
VION = 0V
IAC = 50µA
IAC = 500µA
30
118
5
50
mV
µA
µA
V
Cl Discharge Current
105
0.3
140
IAC Offset Voltage
0.65
10
2
1.1
ION Buffer Slew Rate
ION Input Bias Current
RVS Output Voltage
V/µs
µA
V
V
ION = 2V
15
23k from RVS to GND
2.87
3
3.13
IAC •(VAOUT – 1.5V )
Note 1: Gain constant (K) =
at VRMS = 1.5V, VAOUT = 5.5V.
(V
2 •IMO)
RMS
PIN DESCRIPTIONS
CI: The level shifted current sense signal is impressed
upon a capacitor connected between this pin and GND.
The buffered current sense transformer signal charges
the capacitor when the boost switch is on. When the
switch is off, the current synthesizer discharges the ca-
pacitor at a rate proportional to the dI/dt of the boost in-
ductor current. In this way, the discharge current is
approximately equal to
CA This is the inverting input to the current amplifier.
Connect the required compensation components be-
tween this pin and CAOUT. The common mode operating
range for this input is between −0.3V and 5V.
CAO: This is the output of the wide bandwidth current
amplifier and one of the inputs to the PWM duty cycle
comparator. The output signal generated by this amplifier
commands the PWM to force the correct input current.
The output can swing from 0.1V to 7.5V.
3V
IAC
–
.
RRVS
4
Discharging the CI capacitor in this fashion, a “recon-
structed” version of the inductor current is generated us-
ing only one current sense transformer.
4
UC2855A/B
UC3855A/B
PIN DESCRIPTIONS (cont.)
CS: The reconstructed inductor current waveform gener-
ated on the CI pin is level shifted down a diode drop to
this pin. Connect the current amplifier input resistor be-
tween CS and the inverting input of the current amplifier.
The waveform on this pin is compared to the multiplier
output waveform through the average current sensing
current amplifier. The input to the peak current limiting
comparator is also connected to this pin. A voltage level
greater than 1.5 volts on this pin will trip the comparator
and disable the gate driver output.
ION: This pin is the current sensing input. It should be
connected to the secondary side output of a current
sensing transformer whose primary winding is in series
with the boost switch. The resultant signal applied to this
input is buffered and level shifted up a diode to the CI ca-
pacitor on the CI pin. The ION buffer has a source only
output. Discharge of the CI cap is enabled through the
current synthesizer circuitry. The current sense trans-
former termination resistor should be designed to obtain
a 1V input signal amplitude at peak switch current.
OVP: This pin senses the boost output voltage through a
voltage divider. The enable comparator input is TTL com-
patible and can be used as a remote shutdown port. A
voltage level below 1.8V, disables VREF, oscillator, and
the PWM circuitry via the enable comparator. Between
1.8V and VREF (7.5V) the UC is enabled. Voltage levels
above 7.5V will set the PWM latch via the hysteretic OVP
comparator and disable both ZVTOUT and GTOUT until
the OVP level has decayed by the nominal hysteresis of
400mV. If the voltage divider is designed to initiate an
OVP fault at 5% of OV, the internal hysteresis enables
normal operation again when the output voltage has
reached its nominal regulation level. Both the OVP and
enable comparators have direct logical connections to
the PWM output and exhibit typical propagation delays of
200ns.
CT: A capacitor from CT to GND sets the PWM oscillator
frequency according to the following equation:
1
f ≈
.
11200 • CT
Use a high quality ceramic capacitor with low ESL and
ESR for best results. A minimum CT value of 200pF in-
sures good accuracy and less susceptibility to circuit lay-
out parasitics. The oscillator and PWM are designed to
provide practical operation to 500kHz.
GND: All voltages are measured with respect to this pin.
All bypass and timing capacitors connected to GND
should have leads as short and direct as possible.
GTOUT: The output of the PWM is a 1.5A peak totem
pole MOSFET gate driver on GTOUT. A series resistor
between GTOUT and the MOSFET gate of at least 10
ohms should be used to limit the overshoot on GTOUT.
In addition, a low VF Schottky diode should be connected
between GTOUT and GND to limit undershoot and possi-
ble erratic operation.
REF: REF is the output of the precision reference. The
output is capable of supplying 25mA to peripheral cir-
cuitry and is internally short circuit current limited. REF is
disabled and low whenever VCC is below the UVLO
threshold, and when OVP is below 1.8V. A REF “GOOD”
comparator senses REF and disables the stage until
REF has attained approximately 90% of its nominal
value. Bypass REF to GND with a 0.1µF or larger ce-
ramic capacitor for best stability.
IAC: This is a current input to the multiplier. The current
into this pin should correspond to the instantaneous
value of the rectified AC input line voltage. This is ac-
complished by connecting a resistor directly between IAC
and the rectified input line voltage. The nominal 650mV
level present on IAC negates the need for any additional
compensating resistors to accommodate for the zero
crossings of the line. A current equal to one fourth of the
IAC current forms one of the inductor current synthesizer
inputs.
RVS: The nominal 3V signal present on the VSENSE pin
is buffered and brought out to the RVS pin. A current pro-
portional to the output voltage is generated by connect-
ing a resistor between this pin and GND. This current
forms the second input to the current synthesizer.
SS: Soft-start VSS is discharged for VVCC low conditions.
When enabled, SS charges an external capacitor with a
current source. This voltage is used as the voltage error
signal during start-up, enabling the PWM duty cycle to in-
crease slowly. In the event of a VVCC dropout, the
OVP/EN is forced below 1.8V (typ), SS quickly dis-
charges to disable the PWM.
IMO: This is the output of the multiplier, and the non-
inverting input of the current amplifier. Since this output
is a current, connect a resistor between this pin and
ground equal in value to the input resistor of the current
amplifier. The common mode operating range for this pin
is −0.3V to 5V.
5
UC2855A/B
UC3855A/B
PIN DESCRIPTIONS (cont.)
VAO: This is the output of the voltage amplifier. At a VSENSE: This pin is the inverting input of the voltage
given input RMS voltage, the voltage on this pin will vary amplifier and serves as the output voltage feedback point
directly with the output load. The output swing is limited for the PFC boost converter. It senses the output voltage
from approximately 100mV to 6V. Voltage levels below through a voltage divider which produces a nominal 3V.
1.5V on this pin will inhibit the multiplier output.
The voltage loop compensation is normally connected
between this pin and VAO. The VSENSE pin must be
above 1.5V at 25°C, (1.9V at –55°C) for the current syn-
thesizer to work properly.
VCC: Positive supply rail for the IC. Bypass this pin to
GND with a 1µF low ESL, ESR ceramic capacitor. This
pin is internally clamped to 20V. Current into this clamp
should be limited to less than 10mA. The UC3855A has a
15.5V (nominal) turn on threshold with 6 volts of hyster-
esis while the UC3855B turns on at 10.5V with 500mV of
hysteresis.
ZVS: This pin senses when the drain voltage of the main
MOSFET switch has reached approximately zero volts,
and resets the ZVT latch via the ZVT comparator. A mini-
mum and maximum ZVTOUT pulse width are program-
mable from this pin. To directly sense the ≈400V drain
voltage of the main switch, a blocking diode is connected
between ZVS and the high voltage drain. When the drain
reaches 0V, the level on ZVS is ≈0.7V which is below the
2.6V ZVT comparator threshold. The maximum ZVTOUT
pulse width is approximately equal to the oscillator blank-
ing period time.
VRMS: This pin is the feedforward line voltage compen-
sation input to the multiplier. A voltage on VRMS propor-
tional to the AC input RMS voltage commands the
multiplier to alter the current command signal by
1/VRMS2 to maintain a constant power balance. The in-
put to VRMS is generally derived from a two pole low
pass filter/voltage divider connected to the rectified AC
input voltage. This feature allows universal input supply
voltage operation and faster response to input line fluc-
tuations for the PFC boost preregulator. For most de-
signs, a voltage level of 1.5V on this pin should
correspond to low line, and 4.7V for high line. The input
range for this pin extends from 0 to 5.5V.
ZVTOUT: The output of the ZVT block is a 750mA peak
totem pole MOSFET gate driver on ZVTOUT. Since the
ZVT MOSFET switch is typically 3X smaller than the
main switch, less peak current is required from this out-
put. Like GTOUT, a series gate resistor and Schottky di-
ode to GND are recommended. This pin may also be
used as a high current synchronization output driver.
For more information see Unitrode Applications Note U-153.
5.992 496 516 MHz
120
Gain
-90
100
80
60
40
20
0
120
Phase
Phase
Margin
degrees
100
-45 Phase
Degrees
0
80
60
40
20
0
Open-Loop
Gain
dB
-20
0.1
1
10
100
1000
10000
-20
-40
-60
Frequency
kHz
10kHz
100kHz
1MHz
log f
10MHz
Figure 1. Current Amplifier Frequency Response
Figure 2. Voltage Amplifier Gain Phase vs Frequency
6
UC2855A/B
UC3855A/B
24
22
20
18
16
14
12
10
3.10
3.08
3.06
3.04
3.02
3.00
2.98
2.96
2.94
2.92
2.90
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
TEMPERATURE °C
TEMPERATURE °C
Figure 3. Voltage Amplifier Input Threshold
Figure 4. Supply Current ON
230
225
220
215
210
205
200
195
190
185
180
175
170
-0.75
-0.77
-0.79
-0.81
-0.83
-0.85
-0.87
-0.89
-0.91
-0.93
-0.95
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
TEMPERATURE °C
TEMPERATURE °C
Figure 5. Multiplier Current Gain Constant
Figure 6. Oscillator Initial Accuracy
7
UC2855A/B
UC3855A/B
TYPICAL APPLICATION
UDG-95165-1
Figure 7. Typical Application
8
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
UC2855ADW
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
DW
20
20
20
20
20
20
20
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
UC2855ADW
UC2855ADW
UC2855AN
UC2855ADWG4
UC2855AN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
N
Green (RoHS
& no Sb/Br)
20
Green (RoHS
& no Sb/Br)
UC2855ANG4
UC2855BDW
N
20
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
UC2855AN
DW
DW
DW
25
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
UC2855BDW
UC2855BDW
UC2855BDW
UC2855BDWG4
UC2855BDWTR
25
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
UC2855BDWTR/81363G4
UC2855BDWTRG4
PREVIEW
ACTIVE
SOIC
SOIC
DW
DW
20
20
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
UC2855BDW
UC2855BN
UC2855BN
UC2855BNG4
UC3855ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
N
N
20
20
20
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
N / A for Pkg Type
-40 to 85
-40 to 85
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
20
Green (RoHS
& no Sb/Br)
UC2855BN
DW
DW
DW
DW
N
25
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
UC3855ADW
UC3855ADW
UC3855ADW
UC3855ADW
UC3855AN
UC3855ADWG4
UC3855ADWTR
UC3855ADWTRG4
UC3855AN
25
Green (RoHS
& no Sb/Br)
2000
2000
20
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC3855ANG4
N
20
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
UC3855AN
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
UC3855BDW
UC3855BDWG4
UC3855BDWTR
UC3855BDWTRG4
UC3855BN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
DW
N
20
20
20
20
20
20
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
UC3855BDW
UC3855BDW
UC3855BDW
UC3855BDW
UC3855BN
Green (RoHS
& no Sb/Br)
0 to 70
2000
2000
20
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
UC3855BNG4
N
20
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
UC3855BN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC3855A, UC3855B :
Military: UC1855A, UC1855B
•
NOTE: Qualified Version Definitions:
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC3855ADWTR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
UC3855ADWTR
2000
Pack Materials-Page 2
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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