UC3709J [TI]

1A 2 CHANNEL, BUF OR INV BASED MOSFET DRIVER, CDIP8, CERAMIC, DIP-8;
UC3709J
型号: UC3709J
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

1A 2 CHANNEL, BUF OR INV BASED MOSFET DRIVER, CDIP8, CERAMIC, DIP-8

驱动 CD 接口集成电路 驱动器
文件: 总14页 (文件大小:548K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
UC1709, UC2709, UC3709  
DUAL HIGH-SPEED FET DRIVER  
SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008  
D
D
D
D
D
D
1.5 Amp Source/Sink Drive  
Pin Compatible with 0026 Products  
40 ns Rise and Fall into 1000pF  
Low Quiescent Current  
simplified schematic (only one driver shown)  
V
CC  
5 V to 40 V Operation  
Thermal Protection  
5 VOLT  
REGULATOR  
THERMAL  
SENSE  
description  
The UC3709 family of power drivers is an  
effective low-cost solution to the problem of  
providing fast turn-on and off for the  
capacitive gates of power MOSFETs. Made  
with a high-speed Schottky process, these  
devices will provide up to 1.5 A of either  
source or sink current from a totem--pole  
output stage configured for minimal  
cross-conduction current spike.  
INPUT  
A OR B  
6 k  
INPUT  
A OR B  
5.6 V  
The UC3709 is pin compatible with the  
MMH0026 or DS0026, and while the delay  
times are longer, the supply current is much  
less than these older devices.  
GND  
UDG--00068  
With inverting logic, these units feature complete TTL compatibility at the inputs with an output stage that can  
swing over 30 V. This design also includes thermal shutdown protection.  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)}  
Parameter  
DW PACKAGE  
J PACKAGE  
L PACKAGE  
N PACKAGE  
UNIT  
Supply Voltage, V  
40  
40  
40  
40  
V
CC  
Output Current (Source or Sink)  
. . . . . . . . Steady--State  
±500  
±500  
±500  
±500  
mA  
A
. . . . . . . . Peak Transient  
. . . . . . . . Capacitive Discharge Energy  
Digital Inputs}  
±1.5  
±1.0  
±1.0  
±1.5  
20  
15  
15  
20  
mJ  
V
5.5  
5.5  
5.5  
5.5  
Power Dissipation at T = 25°C  
1
3
1
2
1
2
1
3
W
A
Power Dissipation at T = 25°C  
W
C
Operating Junction Temperature Range (T )  
--55 to 125  
--65 to 150  
300  
--55 to 125  
--65 to 150  
300  
--55 to 125  
--65 to 150  
300  
--55 to 125  
--65 to 150  
300  
°C  
°C  
°C  
J
Storage Temperature Range  
Lead Temperature (Soldering, 10 Seconds)  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
All currents are positive into and negative out of the specified terminals. Digital drive can exceed 5.5V if input is limited to 10mA. Consult the  
Packaging Section of the Databook for thermal limitations and considerations of the package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
Copyright © 2004 -- 2008, Texas Instruments Incorporated  
1
www.ti.com  
UC1709, UC2709, UC3709  
DUAL HIGH-SPEED FET DRIVER  
SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008  
THERMAL RESISTANCE TABLE  
PACKAGE  
SOIC--16 (DW)  
DIL--16 (J)  
θjc(°C/W)  
θja(°C/W)  
(1)  
(3)  
20  
35 to 58  
(2)  
28  
125 to 160  
70 to 80  
(2)  
LCC--16 (L)  
DIL--16 (N)  
20  
(3)  
45  
90  
NOTES: (1) Specified thermal resistance is θjl (junction to lead)where noted.  
(2) θjc data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states, “The baseline values  
shownareworst case(mean+2s)fora60x60mil microcircuit devicesilicondie and applicable fordevices  
with die sizes up to 14400 square mils. For device die sizes greater than 14400 square mils use the  
following values; dual-in-line, 11°C/W; flat pack, .10°C/W; pin grid array, 10°C/W”.  
2
(3) Specified θja (junction to ambient)is fordevices mounted to 5-inch FR4 PCboard withone ouncecopper  
2
where noted. When resistance range is given, lower values are for 5 inch aluminum PC board. Test PWB  
was 0.062 inch thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace  
widths for non-power packages with a 100-mil x 100-mil probe land area at the end of each trace.  
LCC--20 (TOP VIEW)  
L PACKAGES  
8 PIN DIL N OR J PACKAGE  
(TOP VIEW)  
SOIC--16 (TOP VIEW)  
DW PACKAGE  
N/C  
INPUT A  
GROUND  
INPUT B  
N/C  
1
2
3
4
8
7
6
5
N/C  
N/C  
16  
V
1
2
3
4
5
6
7
8
CC  
OUTPUT
15 N/C  
V
CC  
N/C  
14 N/C  
OUTPUT
3
2
1
20 19  
OUTPUT A  
N/C  
13 OUTPUT B  
12 N/C  
N/C  
N/C  
4
5
6
7
8
18 N/C  
17 N/C  
N/C -- No internal connection  
INPUT A  
N/C  
11 INPUT B  
10 N/C  
GROUND  
N/C  
16  
VCC  
15 N/C  
14 N/C  
N/C  
GROUND  
9 N/C  
9
10 11 12 13  
2
www.ti.com  
UC1709, UC2709, UC3709  
DUAL HIGH-SPEED FET DRIVER  
SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008  
electrical characteristics over recommended operating free-air temperature range, TA = 55°C to  
125°C for the UC1709, --40°C to 85°C for the UC2709, and 0°C to 70°C for the UC3709;  
VCC = 20 V, TA = TJ.  
PARAMETER  
TEST CONDITIONS  
Both outputs low  
Both outputs high  
MIN  
TYP  
10  
MAX  
12  
UNIT  
mA  
mA  
V
Supply current  
7
10  
Logic 0 input voltage  
Logic 1 input voltage  
Input current  
0.8  
2.2  
V
V = 0  
-- 0 . 6  
0.05  
1.5  
-- 1 . 0  
0.1  
2.0  
2.5  
0.4  
2.5  
mA  
mA  
V
I
Input leakage  
V = 5 V  
I
I
I
I
I
= --50 mA  
= --500 mA  
= 50 mA  
O
O
O
O
Output high saturation V -- V  
CC  
O
2.0  
V
0.1  
V
Output low saturation V  
Thermal shutdown  
O
= 500 mA  
2.0  
V
155  
mA  
typical switching characteristics, VCC = 20 V, TA = 25°C, delays measured to 10% output change  
OUTPUT C  
=
L
PARAMETER  
TEST CONDITIONS  
UNITS  
0 nF  
2.2 nF  
80  
Rise time delay  
10% to 90% rise  
Fall time delay  
10% to 90% fall  
80  
20  
60  
20  
25  
0
ns  
ns  
ns  
ns  
ns  
ns  
40  
80  
40  
Output rise  
Output fall  
VCC cross-- conduction  
curent spike duration  
NOTE: Refer to UC1705 specifications for further information.  
3
www.ti.com  
UC1709, UC2709, UC3709  
DUAL HIGH-SPEED FET DRIVER  
SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008  
APPLICATION INFORMATION  
D1, D2: UC3611 Schottky Diodes  
Figure 1. Power bipolar drive circuit.  
D1, D2: UC3611 Schottky Diodes  
Figure 2. Power MOSFET drive circuit.  
Figure 3. Charge pump circuits.  
4
www.ti.com  
UC1709, UC2709, UC3709  
DUAL HIGH-SPEED FET DRIVER  
SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008  
D1, D2: UC3611 Schottky Diodes  
Figure 4. Transformer coupled push--pull MOSFET drive circuit.  
D1, D2: UC3611 Schottky Diodes  
Figure 5. Power MOSFET drive circuit using negative bias voltage  
and level shifting to ground referenced PWM  
5
www.ti.com  
UC1709, UC2709, UC3709  
DUAL HIGH-SPEED FET DRIVER  
SLUS196C -- NOVEMBER 1996 -- REVISED FEBRUARY 2008  
D1, D2: UC3611 Schottky Diodes  
Figure 6. Transformer coupled MOSFET drive circuit.  
6
www.ti.com  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Oct-2009  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
LCCC  
LCCC  
SOIC  
Drawing  
5962-0151201VPA  
UC1709J  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
JG  
8
8
1
1
1
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
A42  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
JG  
UC1709J883B  
UC1709L  
JG  
8
FK  
20  
20  
16  
POST-PLATE N / A for Pkg Type  
POST-PLATE N / A for Pkg Type  
UC1709L883B  
UC2709DW  
FK  
DW  
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
UC2709DWG4  
UC2709N  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
PDIP  
PDIP  
DW  
P
16  
8
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU N / A for Pkg Type  
no Sb/Br)  
UC2709NG4  
UC3709DW  
UC3709DWG4  
UC3709N  
P
8
50 Green (RoHS & CU NIPDAU N / A for Pkg Type  
no Sb/Br)  
DW  
DW  
P
16  
16  
8
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU N / A for Pkg Type  
no Sb/Br)  
UC3709NG4  
P
8
50 Green (RoHS & CU NIPDAU N / A for Pkg Type  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Oct-2009  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MCER001A – JANUARY 1995 – REVISED JANUARY 1997  
JG (R-GDIP-T8)  
CERAMIC DUAL-IN-LINE  
0.400 (10,16)  
0.355 (9,00)  
8
5
0.280 (7,11)  
0.245 (6,22)  
1
4
0.065 (1,65)  
0.045 (1,14)  
0.310 (7,87)  
0.290 (7,37)  
0.063 (1,60)  
0.015 (0,38)  
0.020 (0,51) MIN  
0.200 (5,08) MAX  
0.130 (3,30) MIN  
Seating Plane  
0.023 (0,58)  
0.015 (0,38)  
0°–15°  
0.100 (2,54)  
0.014 (0,36)  
0.008 (0,20)  
4040107/C 08/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a ceramic lid using glass frit.  
D. Index point is provided on cap for terminal identification.  
E. Falls within MIL STD 1835 GDIP1-T8  
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