UC1715-SP [TI]
具有互补 0.5A/1A 双路输出的耐辐射 QMLV、单通道输入栅极驱动器;
| 型号： | UC1715-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有互补 0.5A/1A 双路输出的耐辐射 QMLV、单通道输入栅极驱动器 栅极驱动 驱动器 |
| 文件： | 总13页 (文件大小：632K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1715-SP
www.ti.com.cn
ZHCSAU7 –MAY 2013
互补型开关场效应晶体管 (FET) 驱动器
查询样品: UC1715-SP
1
特性
•
•
•
•
•
单输入（脉宽调制 (PWM) 和晶体管-晶体管逻辑电
路 (TTL) 兼容）
W PACKAGE
(TOP VIEW)
高电流功率 FET 驱动器，
1A 拉电流 / 2A 灌电流
辅助输出 FET 驱动器，
0.5A 拉电流 / 1A 灌电流
电源与独立可编程辅助输出间的时间延迟范围
50ns 至 700ns
针对每个输出可单独配置时间延迟或真正零电压运
行
•
•
•
•
•
开关频率达到 1MHz
典型值为 50ns 的传播延迟
ENBL 引脚激活 220μA 睡眠模式
睡眠模式中电源输出低电平有效
同步整流器驱动器
XXX
XXX
说明
UC1715 是一款被设计成为互补型开关提供驱动波形的高速驱动器。 互补型开关配置通常用于同步整流电路和有源
钳位/复位电路，它可提供零电压切换。 为了便捷软开关转换，这个驱动器提供两个输出波形间的独立可编程延
迟。 此延迟引脚还具有真正零电压感测功能，这个功能可在采用零电压时实现相应开关的立即激活。 这个器件的
运行需要一个 PWM 类型输入，而且此器件可与常见的 PWM 控制器对接。
ORDERING INFORMATION(1)
TJ
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–55°C to 125°C
CFP (W)
5962-0052102VFA
5962-0052102VFA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
English Data Sheet: SLUSAU8
UC1715-SP
ZHCSAU7 –MAY 2013
www.ti.com.cn
DEVICE INFORMATION
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME
NO.
1, 7, 8,
9, 10,
12, 13
N/C
-
I
N/C pins are not bonded out. External connections will not affect device functionality.
The VCC input range is from 7 V to 20 V. This pin should be bypassed with a capacitor to GND consistent with
peak load current demands.
VCC
2
3
The PWR output waits for the T1 delay after the INPUT’s rising edge before switching on, but switches off
immediately at INPUT’s falling edge (neglecting propagation delays). This output is capable of sourcing 1-A
and sinking 2-A of peak gate drive current. PWR output includes a passive, self-biased circuit which holds this
pin active low, when ENBL ≥ 0.8 V regardless of VCC’s voltage.
PWR
O
-
This is the reference pin for all input voltages and the return point for all device currents. It carries the full
peak sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must be
damped or clamped such that GND remains the most negative potential.
GND
AUX
4, 5
6
The AUX switches immediately at INPUT’s rising edge but waits through the T2 delay after INPUT’s falling
edge before switching. AUX is capable of sourcing 0.5-A and sinking 1-A of drive current. During sleep mode,
AUX is inactive with a high impedance.
This pin functions in the same way as T1 but controls the time delay between PWR turn-off and activation of
the AUX switch.
The resistor on this pin sets the charging current on internal timing capacitors to provide independent time
control. The nominal voltage level at this pin is 3 V and the current is internally limited to 1 mA. The total delay
from INPUT to output includes a propagation delay in addition to the programmable timer but since the
propagation delays are approximately equal, the relative time delay between the two outputs can be assumed
to be solely a function of the programmed delays. The relationship of the time delay vs. RT is shown in the
Typical Characteristics curves.
T2
11
14
The input switches at TTL logic levels (approximately 1.4 V) but the allowable range is from 0 V to 20 V,
allowing direct connection to most common IC PWM controller outputs. The rising edge immediately switches
the AUX output, and initiates a timing delay, T1, before switching on the PWR output. Similarly, the INPUT
falling edge immediately turns off the PWR output and initiates a timing delay, T2, before switching the AUX
output.
INPUT
I
It should be noted that if the input signal comes from a controller with FET drive capability, this signal provides
another option. INPUT and PWR provide a delay only at the leading edge while INPUT and AUX provide the
delay at the trailing edge.
A resistor to ground programs the time delay between AUX switch turn-off and PWR turn-on.
The resistor on this pin sets the charging current on internal timing capacitors to provide independent time
control. The nominal voltage level at this pin is 3 V and the current is internally limited to 1 mA. The total delay
from INPUT to output includes a propagation delay in addition to the programmable timer but since the
propagation delays are approximately equal, the relative time delay between the two outputs can be assumed
to be solely a function of the programmed delays. The relationship of the time delay vs. RT is shown in the
Typical Characteristics curves.
T1
15
16
The ENBL input switches at TTL logic levels (approximately 1.2 V), and its input range is from 0 V to 20 V.
The ENBL input will place the device into sleep mode when it is a logical low. The current into VCC during the
sleep mode is typically 220 μA.
ENBL
I
2
Copyright © 2013, Texas Instruments Incorporated
UC1715-SP
www.ti.com.cn
ZHCSAU7 –MAY 2013
BLOCK DIAGRAM
3
PWR
50ns –700ns
TIMER
INPUT
T1
14
15
S
Q
R
V
REF
6
2
AUX
VCC
50ns –700ns
TIMER
S
Q
V
5V
3V
LOGIC
GATES
CC
T2
11
R
BIAS
V
REF
TIMER
REF
ENBL
GND
5
GND
1.4V
ENBL 16
ENABLE
ABSOLUTE MAXIMUM RATINGS(1) (2)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
20 V
Continuous
Peak(3)
-100 mA
-1 A
Power driver
IOH
Continuous
Peak(3)
-100 mA
-500 mA
100 mA
2 A
Auxiliary driver
Power driver
Continuous
Peak(3)
IOL
Continuous
Peak(3)
100 mA
1 A
Auxiliary driver
VI
Input voltage range (INPUT, ENBL)
Maximum operating junction temperature
Storage temperature range
–0.3 V to 20 V
150°C
TJ
Tstg
Tlead
–65°C to 150°C
300°C
Maximum lead temperature (soldering, 10 seconds)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal.
(3) RMS drive current on any pin to be restricted to 672 mA.
Copyright © 2013, Texas Instruments Incorporated
3
UC1715-SP
ZHCSAU7 –MAY 2013
www.ti.com.cn
THERMAL INFORMATION
UC1715-SP
W
THERMAL METRIC(1)
UNITS
16 PINS
72.9
θJA
θJC
θJB
Junction-to-ambient thermal resistance(2)
Junction-to-case thermal resistance(3)
Junction-to-board thermal resistance(4)
8.25
°C/W
43.4
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的指定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然 对流条件下的结至环
境热阻。
(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但 可在 ANSI SEMI 标准 G30-
88 中能找到内容接近的说明。
(4) 按照 JESD51-8 中的说明，通过 在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结板热阻。
4
Copyright © 2013, Texas Instruments Incorporated
UC1715-SP
www.ti.com.cn
ZHCSAU7 –MAY 2013
ELECTRICAL CHARACTERISTICS
VCC = 15 V, ENBL ≥ 2 V, RT1 = 100 kΩ from T1 to GND, RT2 = 100 kΩ from T2 to GND, TA = TJ = –55°C to 125°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Overall
VCC
7
18
25
V
ICC, nominal
ICC, sleep mode
ENBL = 3 V
mA
µA
ENBL = 0.8 V
300
Power Driver (PWR)
Pre turn-on PWR output, low
VCC = 0 V, IOUT = 10 mA, ENBL ≤ 0.8 V
INPUT = 0.8 V, IOUT = 40 mA
INPUT = 0.8 V, IOUT = 100 mA
INPUT = 3 V, IOUT = −40 mA
INPUT = 3 V, IOUT = −100 mA
CL = 2200 pF
2
1
V
V
PWR output low, sat. (VPWR
)
1.5
3
PWR output high, sat. (VCC − VPWR
)
V
3
Rise time
60
ns
ns
ns
ns
ns
Fall time
CL = 2200 pF
60
T1 delay, AUX to PWR(1)
T1 delay, AUX to PWR(1)
PWR prop delay
INPUT rising edge, RT1 = 10 kΩ, see
INPUT rising edge, RT1 = 100 kΩ, see
45
200
1300
300
(2)
(2)
250
(3)
INPUT falling edge, 50%, see
Auxiliary Driver (AUX)
AUX pre turn-on AUX output low (VPAUX
)
VCC = 0 V, ENBL ≤ 0.8 V, IOUT = 10 mA
VIN = 3 V, IOUT = 40 mA
VIN = 3 V, IOUT = 100 mA
VIN = 0.8 V, IOUT = -40 mA
VIN = 0.8 V, IOUT = -100 mA
CL = 2200 pF
2
1
V
V
AUX output low, sat. (VAUX
)
1.5
3
AUX output high, sat. (VCC – VAUX
)
V
3
Rise time
60
60
130
700
185
ns
ns
ns
ns
ns
Fall time
CL = 2200 pF
T2 delay, PWR to AUX(1)
T2 delay, PWR to AUX(1)
AUX prop delay
INPUT falling edge, RT2 = 10 kΩ, see
45
(2)
(2)
INPUT falling edge, RT2 = 100 kΩ, see
200
(3)
INPUT rising edge, 50%, see
Enable (ENBL)
Input threshold
Input current, IIH
Input current, IIL
2.8
10
15
V
ENBL = 15 V
ENBL = 0 V
-10
-15
µA
µA
T1
T2
Current limit
T1 = 0 V
-2
-0.5
3.3
80
mA
V
Nominal voltage at T1
Minimum T1 delay
2.7
(2)
T1 = 2.5 V, see
ns
Current limit
T2 = 0 V
-2
-0.5
3.3
80
mA
V
Nominal voltage at T12
Minimum T2 delay
2.7
(2)
T2 = 2.5 V, see
ns
Input (INPUT)
Input threshold
2.8
10
20
V
Input current, IIH
Input current, IIL
ENBL = 15 V
ENBL = 0 V
-10
-20
µA
µA
(1) The parameter is guaranteed to the limit specified by characterization, but not production tested.
(2) T1 and T2 delay is defined as the time between the 50% transition point of AUX (PWR) and the 50% transition point of PWR (AUX) with
no capacitive load on either output.
(3) Propagation delays are measured from the 50% point of the input signal to the 50% point of the output signal’s transition with no load on
outputs.
Copyright © 2013, Texas Instruments Incorporated
5
UC1715-SP
ZHCSAU7 –MAY 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
INPUT
PROPAGATION
DELAYS
PWR OUTPUT
T1 DELAY
T2 DELAY
UC1715 AUX OUTPUT
A. T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay
is defined from the 90% of the falling edge of PWR to the 50% point of the transition edge of AUX.
B. Propagation delay times are measured from the 50% point of the input signal to the 10% point of the output signal’s
transition with no load on outputs.
Figure 1. Time Relationships
T1 vs RT1
T2 vs RT2
21
20
19
18
17
16
500
400
300
200
100
0
0
10
20
30
40
50
60
70
80
90 100
RT (kW)
0
100 200 300 400 500 600 700 800 9001000
Switching Frequency (kHz)
Figure 2. T1 Delay, T2 Delay vs. RT
Figure 3. ICC vs Switching Frequency With No Load and
50% Duty Cycle RT1 = RT2 = 50 kΩ
6
Copyright © 2013, Texas Instruments Incorporated
UC1715-SP
www.ti.com.cn
ZHCSAU7 –MAY 2013
TYPICAL CHARACTERISTICS (continued)
600
18
RT1 = 100k
500
400
300
200
100
0
17
16
RT1 = 50k
RT1 = 10k
RT1 < 6k
15
0
-75
-50
-25
0
25
50
75
100
125
Temperature (°C)
10 20 30 40 50 60 70 80 90 100
RT (kΩ)
Figure 4. ICC vs RT With Opposite RT = 50 kΩ
Figure 5. T1 Deadband vs. Temperature
AUX to PWR
600
500
400
RT2 = 100k
300
200
100
0
RT2 = 50k
RT2 = 10k
RT2 < 6k
-75
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 6. T2 Deadband vs. Temperature
PWR to AUX
Copyright © 2013, Texas Instruments Incorporated
7
UC1715-SP
ZHCSAU7 –MAY 2013
www.ti.com.cn
TYPICAL APPLICATIONS
Figure 7. Typical Application With Timed Delays
UC1715
Figure 8. Using the Timer Input for Zero-Voltage Sensing
UC1715
Figure 9. Self-Actuated Sleep Mode With Absence of Input PWM Signal. Wake Up Occurs With First Pulse While Turn-Off is
Determined by the (RTO CTO) Time Constant
8
Copyright © 2013, Texas Instruments Incorporated
UC1715-SP
www.ti.com.cn
ZHCSAU7 –MAY 2013
TYPICAL APPLICATIONS (continued)
Figure 10. Using the UC1715 as a Complementary Synchronous Rectifier Switch Driver With N-Channel FETs
Figure 11. Synchronous Rectifier Application With Charge Pump to Drive High-Side N-Channel Buck Switch. VIN is Limited to
10 V as VCC Will Rise to Approximately 2VIN
UC1715
Figure 12. Typical Forward Converter Topology With Active Reset Provided by the UC1714 Driving N-channel switch (Q1) and
P-Channel Auxilliary Switch (Q2)
Copyright © 2013, Texas Instruments Incorporated
9
UC1715-SP
ZHCSAU7 –MAY 2013
www.ti.com.cn
TYPICAL APPLICATIONS (continued)
UC1715
Figure 13. Using N-Channel Active Reset Switch With Floating Drive Command
10
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962-0052102VFA
ACTIVE
CFP
W
16
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-0052102VF
A
UC1715W-SP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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