TX810_14 [TI]
8-Channel, Programmable T/R Switch for Ultrasound;
| 型号： | TX810_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Channel, Programmable T/R Switch for Ultrasound |
| 文件： | 总17页 (文件大小：2589K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TX810
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SLLS996A –SEPTEMBER 2009–REVISED APRIL 2010
8-Channel, Programmable T/R Switch for Ultrasound
Check for Samples: TX810
1
FEATURES
DESCRIPTION
2
•
Compact T/R Switch for Ultrasound
The TX810 provides an integrated solution for a wide
range of ultrasound applications. It is an 8 channel,
current programmable, transmit/receive switch in a
small 6mm × 6mm package.
•
Flexible Programmability
–
–
–
8 Bias Current Settings
8 Power/Performance Combinations
Easy Power-Up/Down control
The internal diodes limit the output voltage when high
voltage transmitter signals are applied to the input.
While the insertion loss of TX810 is minimized during
receive mode.
•
•
•
Fast Wake Up Time
Dual Supply Operation
Optimized Insertion Loss
Unlike conventional T/R switches, the TX810 contains
a 3-bit interface used to program bias current from
7mA to 0mA for different performance and power
requirements. When the TX810 bias current is set as
0mA (i.e., high-impedance mode), the device is
APPLICATIONS
•
•
Medical Ultrasound
Industrial Ultrasound
configured
as
power-down
mode.
In
the
high-impedance mode, TX810 does not add
additional load to high-voltage transmitters. In
addition, the device can wake up from power-down
mode in less than 1µs. With these advanced
programmability features, significant power saving
can be achieved in systems.
VP
1 Channel
of TX810
HV TX
LV RX
VN
Figure 1. Block Diagram of TX810
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
TX810
SLLS996A –SEPTEMBER 2009–REVISED APRIL 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TRANSPORT MEDIA,
QUANTITY
OPERATING TEMPERATURE
RANGE
PACKAGED DEVICES
PACKAGE TYPE
TX810IRHHT
TX810IRHHR
Tape and Reel, 250
Tape and Reel, 2500
S-PVQFN-N36
0~70°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
-0.3 ~ +6
-0.3 ~ +6
-6 ~ +0.3
-0.3 ~ +6
±100
UNIT
V
Supply Voltage, VD
Supply Voltage, VP
V
Supply Voltage, VN
V
Supply Voltage, VB
V
Input AC voltage, INn
V
Input at Vsub
-6 ~ +0.3
15
V
Output current, IO
mA
Maximum junction temperature, continuous operation, long term reliability(2) TJ
125°C
Storage temperature range, Tstg
HBM
-55°C to 150°C
500
V
V
V
ESD ratings
CDM
MM
750
200
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
(2) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
THERMAL INFORMATION
TX810
THERMAL METRIC(1)
(OLFM Airflow Assumed)
RHH
36 PINS
29.7
27
UNITS
qJA
Junction-to-ambient thermal resistance(2)
(3)
qJC(top)
qJB
Junction-to-case(top) thermal resistance
(4)
Junction-to-board thermal resistance
7.2
°C/W
(5)
yJT
Junction-to-top characterization parameter
0.1
(6)
yJB
Junction-to-board characterization parameter
7.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
2
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SLLS996A –SEPTEMBER 2009–REVISED APRIL 2010
DEVICE INFORMATION
PIN FUNCTIONS
PIN
NUMBER
DESCRIPTION
NAME
1, 3, 7, 9, 10, 12, 34,
36
INn
Inputs for Channel n
Outputs for Channel n
16, 18, 19, 21, 25, 27,
28, 30
OUTn
33
31
15
13
VD
VP
VN
VB
Logic Supply Voltage; +2.5 V to +5 V; bypass to ground with 0.1 µF and 10 µF capacitors
Positive Supply Voltage; +5 V; bypass to ground with 0.1 µF and 10 µF capacitors
Negative Supply Voltage; –5 V; bypass to ground with 0.1 µF and 10 µF capacitors
Bias voltage; connect to 0 V (GND) for ±5 V operation
2, 8, 11, 14, 17, 20, 26,
29, 32, 35
GND
Ground
24
23
B1
B2
B3
NC
Bit 1; Current program bit
Bit 2; Current program bit
Bit 3; Current program bit
No internal connection.
22
4, 5, 6
PowerPAD™ of the package. –5 V to 0 V for ±5 V operation. The thermal pad is needed for thermal
dissipation.
0
Vsub
PQFN (RHH) Package
6 × 6mm, 0.5mm Pitch
(Top View)
36 35 34 33 32 31 30
29
28
IN6
27
26
1
2
3
4
5
6
7
8
9
OUT6
GND
GND
OUT5
25
24
23
22
21
20
IN5
NC
NC
NC
B1
B2
B3
TX810
PowerPAD™
IN4
GND
IN3
OUT4
GND
19 OUT3
10 11 12 13 14 15 16
17 18
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ELECTRICAL CHARACTERISTICS
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, Vsub= -5V, RLOAD = 400Ω; f = 5MHz, B3B2B1 = 111, VIN
=
0.25VPP, unless otherwise noted. Test Level: A: Final tester limits; B: bench evaluation/simulation; C: Simulation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Test
Level
DC POWER SPECIFICATIONS
Positive Supply VP
5
V
B
Negative Supply VN
-5
Quiescent current, VP, VN
Substrate Voltage, VSUB
Digital Supply, VD
No Signal
50
0
µA
V
A
B
B
A
A
A
PowerPAD™
VN
5
2.5
V
Quiescent current, VD
Bias current, VP, VN path
Bias current, VP, VN path
No Signal
50
µA
B3B2B1 = 001
B3B2B1 = 111
1.25
5.95
1
7
0.75 mA/CH
8.05 mA/CH
Any output; B3B2B1 = 000; No
Input
Leakage Current
0.5
µA
A
LOGIC INPUTS
Logic High Input Voltage; VIH
Logic High Input Current; IIH
Logic Low Input Voltage; VIL
Logic Low Input Current; IIL Input
Capacitance, CIN
2
0
VD
20
V
µA
V
A
A
A
A
C
0.4
20
µA
pF
5
POWER DISSIPATION
Power-Down Dissipation
All channels
B3B2B1 = 000; no signal
B3B2B1 = 001; no signal
B3B2B1 = 111; no signal
200
92
µW
mW
mW
A
A
A
80
Total Power Dissipation
560
644
AC SPECIFICATIONS
1 µs positive and negative pulse
applied seperately at
PRF = 10 kHz
-90
-10
90
V
A
Input Amplitude, VIN
Insertion loss, IL
CW mode (continuous wave)
B3B2B1 = 111
10
-1.8
-1.8
-2
V
dB
dB
dB
dB
dB
dB
dB
Ω
B
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
-0.9
-1.1
-1.3
-4.1
-7
B3B2B1 = 100
B3B2B1 = 001
B3B2B1 = 111, RLOAD = 50Ω
B3B2B1 = 001, RLOAD = 50Ω
B3B2B1 = 111
Channel to channel IL matching
Insertion Loss, IL
0.06
-0.9
30
B3B2B1 = 111, at 20MHz
B3B2B1 = 111, RLOAD = 50 Ω
B3B2B1 = 001, RLOAD = 50 Ω
B3B2B1 = 111
62
Ω
Equivalent Resistance, RON
-3dB Bandwidth, BW
44
Ω
B3B2B1 = 001
67
Ω
B3B2B1 = 111
140
115
65
MHz
MHz
MHz
dBc
B3B2B1 = 100
B3B2B1 = 001
B3B2B1 = 111, VIN = 0.5VPP
5MHz
-74
B3B2B1 = 100, VIN = 0.5VPP
5MHz
-74
-73
dBc
dBc
B
B
2nd Harmonic Distortion, HD2, 5MHz
B3B2B1 = 001, VIN = 0.5VPP
5MHz
4
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ELECTRICAL CHARACTERISTICS (continued)
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, Vsub= -5V, RLOAD = 400Ω; f = 5MHz, B3B2B1 = 111, VIN
0.25VPP, unless otherwise noted. Test Level: A: Final tester limits; B: bench evaluation/simulation; C: Simulation
=
PARAMETER
TEST CONDITIONS
MIN
TYP
-78
-77
-74
MAX
UNIT
dBc
dBc
dBc
Test
Level
B3B2B1 = 111, VIN = 0.5 VPP
10MHz
B
B
B
B3B2B1 = 100, VIN = 0.5 VPP
10MHz
2nd Harmonic Distortion, HD2, 10MHz
B3B2B1 = 001, VIN = 0.5 VPP
10MHz
B3B2B1 = 111 at 10MHz
B3B2B1 = 100 at 10MHz
B3B2B1 = 001 at 10MHz
B3B2B1 = 111
-70
-69
-61
-68
-65
-50
-76
-76
-76
-64
0.91
1.05
1.12
1
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/rtHz
nV/rtHz
nV/rtHz
µs
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
Cross-talk, Xtalk
(1)
3rd order Intermodulation, IMD3
B3B2B1 = 100
B3B2B1 = 001
B3B2B1 = 111
(2)
Power Supply Modulation Ratio, PSMR
Power Supply Rejection Ratio, PSRR
Input Referred Noise, IRN
B3B2B1 = 100
B3B2B1 = 001
B3B2B1 = 111, 1KHz and 1MHz
B3B2B1 = 111
B3B2B1 = 100
B3B2B1 = 001
B3B2B1 = 111
Recovery Time 140 VPP IN, VOUT < 20mVPP
Turn-on Delay Time (3), tEN_ON
B3B2B1 = 100
0.5
0.3
0.6
0.5
0.5
2.4
2.7
2.2
0.7
1.3
1.6
1.7
1.9
1.7
1.4
µs
B3B2B1 = 001
µs
B3B2B1 = 000→111
B3B2B1 = 000→100
B3B2B1 = 000→001
B3B2B1 = 111→000
B3B2B1 = 100→000
B3B2B1 = 001→000
B3B2B1 = 001→111
B3B2B1 = 111
µs
µs
µs
µs
Turn-off Delay Time (3), tEN_OFF
Bias Current Switching Time
µs
µs
µs
ns
Propagation Delay Time (3), tDELAY
B3B2B1 = 100
ns
B3B2B1 = 001
ns
B3B2B1 = 111
VPP
VPP
VPP
Clamp Voltage, excludes overshoot
B3B2B1 = 001
B3B2B1 = 000
(1) 5MHz 1VPP, and 5.01MHz 0.5VPP input.
(2) PSMR is defined as the ratio between carrier 5MHz and side band signals with 1KHz and 1MHz 50mVPP Noise applied on supply pins.
(3) See the timing diagram show in Figure 2.
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INPUT
tEN_ON
tEN_OFF
tDELAY
B3/B2/B1
OUTPUT
Figure 2. Timing Diagram
TYPICAL CHARACTERISTICS
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, VSUB = -5V, RIN = 75Ω, RLOAD = 400Ω;
f = 5MHz, B3B2B1=111, VIN = 0.25VPP, unless otherwise noted.
A typical bench setup is shown in Figure 3.
VP
1 Channel
of TX810
Signal
Source
Test
Equipment
RIN
RLOAD
VN
Figure 3. Typical Test Setup
400
350
300
250
200
150
100
100
80
2
1.5
1
1890 Units,
Bias = 7 mA,
Bias = 7 mA
R
= N/A
IN
Input
60
40
Output
0.5
20
0
0
-20
-40
-60
-80
-0.5
-1
-1.5
50
0
-100
3
-2
-0.5
0
0.5
1
1.5
2
2.5
t − Time − ms
Insertion Loss − dB
AC coupling is used between High voltage pulser and TX810. The
input signal is a combination of 0.25Vpp signal followed by a 1-cycle
140Vpp pulse
Figure 4. Insertion Loss Distribution
Figure 5. Recovery Time With Small Input Signal
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TYPICAL CHARACTERISTICS (continued)
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, VSUB = -5V, RIN = 75Ω, RLOAD = 400Ω;
f = 5MHz, B3B2B1=111, VIN = 0.25VPP, unless otherwise noted.
100
80
60
40
20
0
0.05
0.04
0.03
0.02
0.01
0
-60
-62
-64
-66
-68
-70
-72
-74
Bias = 7 mA,
= 50 W
R
LOAD
Input
5MHz
-20
-40
-60
-80
-100
-0.01
-0.02
-0.03
-0.04
-0.05
Output
10MHz
-5
0
5
10
15
20
25
30
1
2
3
4
5
6
7
t − Time − ms
Bias Current − mA
AC coupling is used between High voltage pulser and TX810. The
input signal is a 1-cycle 140Vpp pulse
Figure 6. Recovery Time Without Signal
Figure 7. Cross-talk vs. Bias Currents vs. Frequency
-60
-62
1.4
V
= 500 mV
PP
1.2
IN
10MHz
-64
-66
-68
-70
1
1MHz
0.8
0.6
5MHz
5MHz
-72
-74
-76
0.4
0.2
0
10MHz
-78
-80
1
2
3
4
5
6
7
1
2
3
4
5
6
7
Bias Current − mA
Bias Current − mA
Figure 8. HD2 vs. Bias Current vs. Frequency
Figure 9. Input Referred Noise vs. Bias Current vs. Frequency
6
5
4
3
2
1
6
5
0.3
0.2
0.3
0.2
Trigger
Trigger
4
3
2
1
0
0.1
0
0.1
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
TX810 Output
0
TX810 Output
-1
-2
-1
0
1
2
3
4
5
6
7
8
0
0.5
1
1.5
2
2.5
3
3.5
4
t − Time − ms
t − Time − ms
Figure 10. Power On Response Time (0mA to 7mA)
Figure 11. Power Down Response Time (7mA to 0mA)
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TYPICAL CHARACTERISTICS (continued)
All Specifications at TA = 25°C, VP = 5V, VN = -5V, VB = 0V, VSUB = -5V, RIN = 75Ω, RLOAD = 400Ω;
f = 5MHz, B3B2B1=111, VIN = 0.25VPP, unless otherwise noted.
5
4
3
2
1
0.2
0.15
0.1
Trigger
0.05
0
-0.5
-0.1
-0.15
-0.2
TX810 Output
0
-0.25
-0.3
-1
0
0.5
1
1.5
2
2.5
3
3.5
4
t − Time − ms
Figure 12. Bias Current Adjustment Response Time (1mA to 7mA)
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THEORY OF OPERATION
A typical ultrasound block diagram is shown in Figure 13.
Figure 13. Ultrasound System Block Diagram
A transducer is excited by high voltage pulsers. It converts the electrical energy to mechanical energy. After each
excitation, the transducer sends out ultrasonic wave to medium. Partial ultrasonic wave gets reflected by
inhomogeneous medium and received by the transducer again, i.e. echo signal. Thus, the transducer is a duplex
device on which both high voltage and low voltage signals exist. The transducer can not be connected to
amplifier stages directly; otherwise, the high voltage signal can permanently destroy amplifiers. The TX810, i.e.
T/R switches, is sitting between integrated HV pulser and low noise amplifier (LNA). The main function of TX810
is to isolate the LNA from high-voltage transmitter. TX810 limits the high voltage pulse and let echo signals
reaching amplifier. Therefore, an ideal T/R switch should completely block high voltage signals and maintain all
information from echoes.
The detail architecture of the TX810 is listed in Figure 14.
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VP
D6
D0
D1
D2
D3
D4
D5
1 Channel
of TX810
HV TX
LV RX
D0~D6 is determined by
B1~B3 pins
RLOAD
L
VB
D6
D0
D1
D2
D3
D4
D5
VN
Figure 14. TX810 Block Diagram
TX810 includes four parts: Diode Bridge, bias network, clamp diodes, and logic controller. A decoder is used to
convert 3-bit logic (B1 to B3) input to 7 control signals (D0 to D6) for 7 MOSFET switches. +2.5V to +5V logic
input is level shifted internally to drive the switches. The bias current of the bridge diode is adjusted
proportionally by these switches. When all switches are on, the bias current is 7mA. Each bit difference will
adjust the bias current approximately 1mA. When all switches are off, the TX810 enters the power down mode.
Comparing to discrete T/R switches, TX810 can be shut down and turned on quickly as shown in the typical
characteristics plots. Considering the low duty cycle of ultrasound imaging, significant power saving can be
achieved.
All 6 diodes are high-voltage Schottky diodes to achieve fast recovery time. Following the bridge, a pair of
back-to-back diode limits the output voltage of TX810 to about 2Vpp. Different power/performance combination
can be selected by users. The TX810 is specified to operate at ±5V and VB is biased at 0V. The characteristics
of the T/R switch are mainly determined by bias currents. Lower power can be achieved with lower supply
voltages. Also, Table 1 shows the relationship among bias current, insertion loss, input noise, power
consumption and equivalent resistance.
Table 1. Bias current vs Performance
Test Conditions: VP = 5V, VN = -5V; VB = 0V; RLOAD = 50Ω
B3
0
B2
0
B1
0
I (mA)
IL (dB)
N/A
-7
IRN (nV/rtHz)
N/A
RON (Ω)
Power (mW/CH)
0
1
2
3
4
5
6
7
High Impedance
0
0
0
1
1.12
62
45
39
35
33
31
30
10
20
30
40
50
60
70
0
1
0
-5.6
-5
1.10
0
1
1
1.09
1
0
0
-4.6
-4.4
-4.2
-4.1
1.05
1
0
1
0.99
1
1
0
0.95
1
1
1
0.91
10
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APPLICATION INFORMATION
Similar to discrete T/R switch solutions, external components can be used to optimize system performance.
Inductor L and resistor RLOAD before the low voltage receiver amplifier (LVRx) can improve overload recovery
time and reduce reflection. The L acts as a high pass filter thus overshoot or recovery response spikes can be
suppressed to minimal. The L and RLOAD terminate the entire signal path and can reduce reflection; therefore
axial resolution in ultrasound image might be improved. However, the combined impedance of L and RLOAD may
affect the system sensitivity. The insertion loss of T/R switch is determined by the input impedance of receiver
amplifier and RON of the TX810. L also creates a DC path for any offset caused by mismatching.The inductor can
be as low as 10s µH to suppress low frequency signals from transmitter, transducer, multiplexer, and TX810. The
optimization of L and RLOAD is always an important topic for system designers. AC coupling are typically used
between transmitter and T/R switch or T/R switch and amplifier. Thus amplifiers with DC biased inputs will not
interference with T/R switch.
One challenge for integrating multiple channel circuits on a small package is how to reduce cross talk. In
ultrasound systems, acoustic cross talk from adjacent transducer elements is a dominant source. The cross talk
from transducer elements is in a range of -30 to -35dBc for array transducers. Circuit cross talk is usually at least
20dB better than the transducer cross talk. The special considerations were implemented in both TX810 design
and layout. The cross talk among TX810 channels is reduced to below -60 dBc as show in the specification
table.
In ultrasound Doppler applications, modulation effect in system can influence image quality and sensitivity.
Ultrasound system is a complex mixed-signal system with all kinds of digital and analog circuits. Digital signals
and clock signals can contaminate analog signals on system level or on chip level. Nonlinear components, such
as transistors and diodes, can modulate noise and contaminate signals. In Doppler applications, the Doppler
signal frequency could range from 20Hz to >50KHz. Meanwhile, multiple system clocks are also in this range,
such as frame clock, image line clock, and etc. These noise signals could enter chip through ground and power
supply pins. It is important to study the power supply modulation ratio (PSMR) at chip level. Noise signal with
certain frequency and amplitude can be applied on supply pins. Side band signals could be found if modulation
effect exists. The PSMR is expressed as an amplitude ratio between carrier and side band signals. Beside
PSMR, 3rd order intermodulation ratio (IMD3) is a standard specification for mixed-signal ICs. Users can use
IMD3 to estimate the potential artifact Doppler mirror signals. Both specs can be found in the specification table.
The schematic of the basic connection for TX810 is shown in Figure 15. Optional inductors and resistors can be
used at TX810 outputs depending on transducer characteristics as discussed above. Standard decoupling
capacitors 0.1µF should be placed close to power supply pins. The pin out of TX810 is optimized for PCB layout.
All signals are going from left to right straightly.
Copyright © 2009–2010, Texas Instruments Incorporated
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Product Folder Link(s) :TX810
TX810
SLLS996A –SEPTEMBER 2009–REVISED APRIL 2010
www.ti.com
TX CH8
RX CH8
RX CH7
3.3V
5V
Optional
Optional
0.1uF
0.1uF
0.1uF
TX CH7
0.1uF
IN6
OUT6
GND
OUT5
B1
TX CH6
RX CH6
RX CH5
GND
Optional
0.1uF
0.1uF
0.1uF
IN5
TX CH5
TX810
NC
B1
Optional
0.1uF
Pull Down
PowerPAD
Vsub
(-5V)
NC
NC
B2
B2
B3
20K×3
B3
IN4
OUT4
GND
OUT3
TX CH4
RX CH4
RX CH3
GND
Optional
Optional
0.1uF
0.1uF
0.1uF
IN3
TX CH3
0.1uF
TX CH2
RX CH2
RX CH1
Optional
Optional
0.1uF
0.1uF
0.1uF
5V
TX CH1
0.1uF
Figure 15. Schematic of TX810
REVISION HISTORY
SPACER
Changes from Original (September 2009) to Revision A
Page
•
Changed From: Product Preview To: Production. The Product Preview was a two page data sheet containing the
front page and the pin out section ........................................................................................................................................ 1
12
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TX810
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2010
PACKAGING INFORMATION
Orderable Device
TX810IRHHR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VQFN
RHH
36
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TX810IRHHT
VQFN
RHH
36
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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