TWL1200ZQCR [TI]
SDIO, UART, AND AUDIO VOLTAGE-TRANSLATION TRANSCEIVER; SDIO ， UART和音频电压转换收发器
| 型号： | TWL1200ZQCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SDIO, UART, AND AUDIO VOLTAGE-TRANSLATION TRANSCEIVER |
| 文件： | 总31页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TWL1200
www.ti.com ...................................................................................................................................................................................................... SCES786–JUNE 2009
SDIO, UART, AND AUDIO VOLTAGE-TRANSLATION TRANSCEIVER
1
FEATURES
23
•
Level Translator
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
–
VCCA and VCCB Range of 1.1 V to 3.6 V
ESD Protection Exceeds JESD 22
•
Seamlessly Bridges 1.8-V/2.6-V
Digital-Switching Compatibility Gap Between
2.6-V processors and TI’s Wi-Link (WL1271
and WL1273)
–
–
–
2500-V Human-Body Model (A114-B)
250-V Machine Model (A115-A)
1500-V Charged-Device Model (C101)
YFF PACKAGE
(TOP VIEW)
ZQC PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
1 2
4
3 6 7
5
A
B
C
D
E
F
A
B
C
D
E
F
G
G
BGA PACKAGE TERMINAL ASSIGNMENTS
1
2
3
4
AUD_DIR
OE
5
6
7
A
B
C
D
E
F
SDIO_CLK(A)
SDIO_DATA3(A)
SDIO_DATA2(A)
WLAN_EN(A)
SDIO_CMD(A)
SDIO_DATA0(A)
SDIO_DATA1(A)
WLAN_IRQ(A)
BT_EN(A)
AUDIO_CLK(A)
AUDIO_F-SYN(A)
AUDIO_CLK(B)
AUDIO_F-SYN(B)
VCCB
SDIO_CMD(B)
SDIO_DATA0(B)
SDIO_DATA1(B)
WLAN_EN(B)
SDIO_CLK(B)
SDIO_DATA3(B)
SDIO_DATA2(B)
WLAN_IRQ(B)
CLK_REQ(B)
VCCA
GND
GND
VCCA
VCCB
CLK_REQ(A)
GND
GND
BT_EN(B)
BT_UART_CTS(A)
BT_UART_RX(A)
BT_UART_RTS(A)
BT_UART_TX(A)
AUDIO_IN(A)
AUDIO_OUT(A)
SLOW_CLK(B)
SLOW_CLK(A)
AUDIO_IN(B)
AUDIO_OUT(B)
BT_UART_RTS(B)
BT_UART_TX(B)
BT_UART_CTS(B)
BT_UART_RX(B)
G
WCS PACKAGE TERMINAL ASSIGNMENTS
1
2
3
4
AUD_DIR
OE
5
6
7
A
B
C
D
E
F
SDIO_CLK(A)
SDIO_DATA3(A)
SDIO_DATA2(A)
WLAN_EN(A)
SDIO_CMD(A)
SDIO_DATA0(A)
SDIO_DATA1(A)
WLAN_IRQ(A)
BT_EN(A)
AUDIO_CLK(A)
AUDIO_F-SYN(A)
NC(1)
AUDIO_CLK(B)
AUDIO_F-SYN(B)
VCCB
SDIO_CMD(B)
SDIO_DATA0(B)
SDIO_DATA1(B)
WLAN_EN(B)
BT_EN(B)
SDIO_CLK(B)
SDIO_DATA3(B)
SDIO_DATA2(B)
WLAN_IRQ(B)
CLK_REQ(B)
VCCA
GND
VCCA
VCCB
CLK_REQ(A)
GND
GND
GND
BT_UART_CTS(A)
BT_UART_RX(A)
BT_UART_RTS(A)
BT_UART_TX(A)
AUDIO_IN(A)
AUDIO_OUT(A)
SLOW_CLK(B)
SLOW_CLK(A)
AUDIO_IN(B)
AUDIO_OUT(B)
BT_UART_RTS(B)
BT_UART_TX(B)
BT_UART_CTS(B)
BT_UART_RX(B)
G
(1) NC – No internal connection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
MicroStar Junior is a trademark of Texas Instruments.
MicroStar Junior, are trademarks of ~ Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TWL1200
SCES786–JUNE 2009...................................................................................................................................................................................................... www.ti.com
DESCRIPTION/ORDERING INFORMATION
The TWL1200 is an 19-bit voltage translator specifically designed to seamlessly bridge the 1.8-V/2.6-V
digital-switching compatibility gap between 2.6-V baseband and the TI Wi-Link-6 (WL1271/3). It is optimized for
SDIO, UART, and audio functions. The TWL1200 has two supply-voltage pins, VCCA and VCCB, that can be
operated over the full range of 1.1 V to 3.6 V. The TWL1200 enables system designers to easily interface
applications processors or digital basebands to peripherals operating at a different I/O voltage levels, such as the
TI Wi-Link-6 (WL1271/3) or other SDIO/memory cards.
The TWL1200 is offered in both 48-ball 0.5-mm ball grid array (BGA) and 49-bump 0.4-mm wafer chip scale
package (WCSP) packages. Low static power consumption and small package size make the TWL1200 an ideal
choice for mobile-phone applications.
ORDERING INFORMATION(1)
ORDERABLE
TA
PACKAGE(2)
TOP-SIDE MARKING
PART NUMBER
TWL1200ZQCR
TWL1200YFFR
BGA MicroStar Junior™ – ZQC (Pb-free)
WCSP™ – YFF (Pb-free)
Tape and reel
Tape and reel
YW200
–40°C to 85°C
PREVIEW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
TERMINAL FUNCTIONS
TERMINAL
ZQC
BALL
NO.
YFF
BUMP
NO.
TYPE
DESCRIPTION
NAME
C4, D4
B2
C4, D4
B2
VCCA
Power
I/O
A-side supply voltage (1.1 V to 3.6 V)
SDIO_DATA0(A)
SDIO_DATA1(A)
SDIO_DATA2(A)
SDIO_DATA3(A)
SDIO_CMD(A)
Data bit 1 connected to baseband SDIO controller
Data bit 2 connected to baseband SDIO controller
Data bit 3 connected to baseband SDIO controller
Data bit 4 connected to baseband SDIO controller
Command bit connected to baseband SDIO controller. Referenced to VCCA.
C2
C2
I/O
C1
C1
I/O
B1
B1
I/O
A2
A2
I/O
Command bit connected to SD/SDIO peripheral. Includes a 15-kΩ pullup resistor
A6
A6
SDIO_CMD(B)
GND
I/O
to VCCB
.
D3, E3,
E4, E5
D3, E3,
E4, E5
Ground
B6
C6
C7
B7
A1
B6
C6
C7
B7
A1
SDIO_DATA0(B)
SDIO_DATA1(B)
SDIO_DATA2(B)
SDIO_DATA3(B)
SDIO_CLK(A)
I/O
I/O
I/O
I/O
I
Data bit 1 connected to SD/SDIO peripheral
Data bit 2 connected to SD/SDIO peripheral
Data bit 3 connected to SD/SDIO peripheral
Data bit 4 connected to SD/SDIO peripheral
Clock signal connected to baseband SDIO controller. Referenced to VCCA
.
Clock signal connected to SD/SDIO peripheral. Referenced to VCCB; drive
strength = 8 mA
A7
A7
SDIO_CLK(B)
O
C5, D5
C3
C5, D5
C3
VCCB
–
Pwr
B-side supply voltage (1.1 V to 3.6 V)
–
I
No ball (for ZQC) and No-Connect (for YFF)
B4
B4
OE
Output enable (active low)
A4
A4
AUD_DIR
I
Direction control signal for AUDIO_CLK and AUDIO_F-SYNC signals
Connected to baseband audio subsystem; drive strength = 4 mA
Connected to Wi-Link-6 PCM subsystem
G3
G3
AUDIO_OUT(A)
AUDIO_OUT(B)
WLAN_EN(A)
WLAN_EN(B)
BT_UART_TX(A)
BT_UART_TX(B)
O
I
G5
G5
D1
D1
I
Connected to baseband SDIO controller
D6
D6
O
O
I
Connected to SD/SDIO peripheral; drive strength = 2 mA
Connected to baseband UART subsystem; drive strength = 8 mA
Connected to BT UART subsystem of Wi-Link-6
G2
G2
G6
G6
2
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TWL1200
www.ti.com ...................................................................................................................................................................................................... SCES786–JUNE 2009
TERMINAL FUNCTIONS (continued)
TERMINAL
ZQC
BALL
NO.
YFF
BUMP
NO.
TYPE
DESCRIPTION
NAME
D2
D7
G4
D2
D7
G4
WLAN_IRQ(A)
WLAN_IRQ(B)
SLOW_CLK(A)
O
I
Connected to baseband SDIO controller; drive strength = 4 mA
Connected to SD/SDIO peripheral
I
Low frequency 32-kHz clock connected to baseband device
Low frequency 32-kHz clock connected to Wi-Link-6 device; drive strength = 2
mA
F4
F4
SLOW_CLK(B)
O
G1
G7
E1
E7
F1
F3
F5
A3
A5
E2
E6
F7
F2
F6
B3
B5
G1
G7
E1
E7
F1
F3
F5
A3
A5
E2
E6
F7
F2
F6
B3
B5
BT_UART_RX(A)
BT_UART_RX(B)
CLK_REQ(A)
I
O
O
I
Connected to baseband UART subsystem
Connected to BT UART subsystem of Wi-Link-6; drive strength = 8 mA
Connected to baseband SDIO controller; drive strength = 4 mA
Connected to SD/SDIO peripheral
CLK_REQ(B)
BT_UART_CTS(A)
AUDIO_IN(A)
I
Connected to baseband UART subsystem
I
Connected to baseband audio subsystem
AUDIO_IN(B)
O
I/O
I/O
I
Connected to Wi-Link-6 PCM subsystem; drive strength = 4 mA
Connected to baseband audio subsystem; drive strength = 4 mA
Connected to Wi-Link-6 PCM subsystem; drive strength = 4 mA
Connected to baseband UART subsystem
AUDIO_CLK(A)
AUDIO_CLK(B)
BT_EN(A)
BT_EN(B)
O
O
O
I
Connected to BT UART subsystem of Wi-Link-6; drive strength = 2 mA
Connected to BT UART subsystem of Wi-Link-6; drive strength = 4 mA
Connected to baseband UART subsystem; drive strength = 4 mA
Connected to BT UART subsystem of Wi-Link-6
BT_UART CTS(B)
BT_UART RTS(A)
BT_UART RTS(B)
AUDIO_F-SYN(A)
AUDIO_F-SYN(B)
I/O
I/O
Connected to baseband audio subsystem; drive strength = 4 mA
Connected to Wi-Link-6 PCM subsystem; drive strength = 4 mA
FUNCTION TABLE
CONTROL INPUTS
OPERATION
OE
AUD_DIR
H
X
All outputs are Hi-Z
AUDIO_CLK(A) to AUDIO_CLK(B) and
AUDIO_F-SYNC(A) to AUDIO_F-SYNC(B)
L
L
H
AUDIO_CLK(B) to AUDIO_CLK(A) and
AUDIO_F-SYNC(B) to AUDIO_F-SYNC(A)
L
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TWL1200
SCES786–JUNE 2009...................................................................................................................................................................................................... www.ti.com
LOGIC DIAGRAM
VCCA
VCCB
Control
Logic
OE
BT_EANBLE(A)
BT_EANBLE(B)
BT_UART_RX(A)
BT_UART_CTS(A)
BT_UART_TX(A)
BT_UART_RTS(A)
AUDIO_IN(A)
BT_UART_RX(B)
BT_UART_CTS(B)
BT_UART_TX(B)
BT_UART_RTS(B)
AUDIO_IN(B)
AUDIO_OUT(A)
SLOW_CLK(A)
AUDIO_OUT(B)
SLOW_CLK(B)
Audio
Control
AUD_DIR
AUDIO_CLK(A)
AUDIO_CLK(B)
AUDIO_FSYNC(A)
SDIO Bit
AUDIO_F_SYNC(B)
VCCA
VCCB
R1
(see Note A)
R2
(see Note A)
One-Shot
One-Shot
Translator
Gate Control
SDIO-CMD(A)
SDIO-CMD(B)
One-Shot
One-Shot
Translator
VCCA
VCCB
SDIO Bit
R1
(see Note A)
R2
(see Note A)
One-Shot
One-Shot
Translator
Gate Control
SDIO-DATA0(A)
SDIO-DATA0(B)
One-Shot
One-Shot
Translator
VCCA
VCCB
SDIO Bit
R1
(see Note A)
R2
(see Note A)
One-Shot
One-Shot
Translator
Gate Control
SDIO-DATA1(A)
SDIO-DATA1(B)
One-Shot
One-Shot
Translator
VCCA
VCCB
SDIO Bit
R1
(see Note A)
R2
(see Note A)
One-Shot
One-Shot
Translator
Gate Control
SDIO-DATA2(A)
SDIO-DATA2(B)
One-Shot
One-Shot
Translator
VCCA
VCCB
SDIO Bit
R1
(see Note A)
R2
(see Note A)
One-Shot
One-Shot
Translator
Gate Control
SDIO-DATA3(A)
SDIO-DATA3(B)
One-Shot
One-Shot
Translator
SDIO-CLK(A)
SDIO-CLK(B)
WLAN-ENABLE(A)
WLAN-IRQ(A)
WLAN-ENABLE(B)
WLAN-IRQ(B)
CLK-REQ(A)
CLK-REQ(B)
A. R1 and R2 resistor values are determined based upon the logic level applied to the A port or B port as follows:
R1 and R2 = 25 kΩ when a logic level low is applied to the A port or B port.
R1 and R2 = 4 kΩ when a logic level high is applied to the A port or B port.
R1 and R2 = 70 kΩ when the port is deselected (or in High-Z or 3-state).
B. OE controls all output buffers. When OE = high, all outputs are Hi-Z.
4
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www.ti.com ...................................................................................................................................................................................................... SCES786–JUNE 2009
TYPICAL APPLICATION BLOCK DIAGRAM
2.6 V
1.8 V
Wi-Link-6 (WL1271/3)
Baseband Processor
V
V
CCB
CCA
SDIO_DATA0(A)
SDIO_DATA1(A)
SDIO_DATA2(A)
SDIO_DATA3(A)
SDIO_CMD(A)
SDIO_DATA0(B)
SDIO_DATA1(B)
SDIO_DATA2(B)
SDIO_DATA3(B)
SDIO_CMD(B)
SD/SDIO
Peripheral
SDIO
Controller
SDIO_CLK(A)
SDIO_CLK(B)
WLAN_ENABLE(A)
WLAN_IRQ(A)
WLAN_ENABLE(B)
WLAN_IRQ(B)
CLK_REQ(A)
CLK_REQ(B)
BT_ENABLE(A)
BT_UART_RX(A)
BT_UART_CTS(A)
BT_UART_TX(A)
BT_UART_RTS(A)
AUDIO_IN(A)
BT_ENABLE(B)
BT_UART_RX(B)
BT_UART_CTS(B)
BT_UART_TX(B)
BT_UART_RTS(B)
AUDIO_IN(B)
TWL1200
BT UART
UART
AUDIO_CLK(A)
AUDIO_CLK(B)
AUDIO F-SYNK(B)
AUDIO_OUT(B)
SLOW_CLK(B)
AUDIO F-SYNK(A)
AUDIO_OUT(A)
PCM
Audio
SLOW_CLK(A)
AUD_DIR (see Note A)
OE (see Note B)
GND
A. AUD_DIR must be biased to determine audio direction (see Function Table for properly establishing the bias).
B. OE is an active-low pin that must be grounded to 0 V to enable operation of the TWL1200 device.
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TWL1200
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
4.6
UNIT
V
VCCA
VCCB
Supply voltage range
Supply voltage range
4.6
V
I/O ports (A port)
I/O ports (B port)
Control inputs
A port
4.6
VI
Input voltage range
4.6
V
4.6
4.6
Voltage range applied to any output in the high-impedance or power-off
state(2)
VO
VO
V
V
B port
4.6
A port
4.6
Voltage range applied to any output in the high or low state(2)
B port
4.6
IIK
IOK
IO
Input clamp current
VI < 0
–50
–50
±50
±100
150
mA
mA
mA
mA
°C
Output clamp current
VO < 0
Continuous output current
Continuous current through VCCA, VCCB, or GND
Storage temperature range
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
THERMAL IMPEDANCE RATINGS
UNIT
ZQC package
YFF package
171.6
TBD
θJA
Package thermal impedance(1)
°C/W
(1) The package thermal impedance is calculated in accordance with JESD 51-7.
6
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TWL1200
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RECOMMENDED OPERATING CONDITIONS(1)
VCCI
VCCO
MIN
1.1
MAX UNIT
VCCA
VCCB
Supply voltage
Supply voltage
3.6
3.6
V
V
1.1
Buffer type
VCCI × 0.65
VCCA × 0.65
VCCI – 0.2
3.6
VIH
VIH
High-level input voltage
High-level input voltage
1.1 V to 3.6 V
1.1 V to 3.6 V
1.1 V to 3.6 V
1.1 V to 3.6 V
V
V
OE and AUD_DIR
Switch type
3.6
VCCI
Buffer type and
Control Logic
0
VCCI × 0.35
VIL
Low-level input voltage
1.1 V to 3.6 V
1.1 V to 3.6 V
1.1 V to 3.6 V
1.1 V to 3.6 V
V
OE and AUD_DIR
Switch type
0
0
0
0
0
VCCA × 0.35
(2)
VIL
Low-level input voltage
Input voltage
0.15
3.6
VCCO
3.6
–0.5
–1
–2
–4
–8
0.5
1
V
V
VI
Active state
3-state
VO
Output voltage
V
1.1 V to 1.3 V
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
IOH
High-level output current
mA
1.1 V to 1.3 V
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
IOL
Low-level output current
2
mA
4
8
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
5
ns/V
°C
TA
–40
85
(1) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Note, the max VIL value is provided to ensure that a valid VOL is maintained. The VOL value is the VIL + the voltage-drop across the
pass-gate transistor.
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VCCA
1.1 V to 3.6 V
1.65 V
VCCB
1.1 V to 3.6 V
1.65 V
MIN
VCCO – 0.2
1.2
TYP(1) MAX UNIT
A port
(Buffer-type output,
8-mA drive)
IOH = –8 mA
IOH = –100 µA
IOH = –4 mA
2.5 V
2.5 V
1.97
VOH
V
1.1 V to 3.6 V
1.65 V
1.1 V to 3.6 V
1.65 V
VCCO – 0.2
1.2
A port
(Buffer-type output,
4-mA drive)
2.5 V
2.5 V
1.97
A port
1.65 V
1.65 V
1.5
VOH (Switch-type
outputs)
IOH = –20 µA
V
2.5 V
2.5 V
2.3
IOL = 100 µA
IOL = 8 mA
IOL = 100 µA
IOL = 4 mA
1.1 V to 3.6 V
1.65 V
1.1 V to 3.6 V
1.65 V
0.2
A port
(Buffer-type output,
8-mA drive)
0.45
2.5 V
2.5 V
0.55
V
VOL
1.1 V to 3.6 V
1.65 V
1.1 V to 3.6 V
1.65 V
0.2
A port
(Buffer-type output,
4-mA drive)
0.45
0.55
0.45
2.5 V
2.5 V
A port
VOL (Switch-type
outputs)
IOL = 220 µA, VIN = 0.15 V
IOL = 300 µA, VIN = 0.15 V
IOH = –100 µA
1.65 V
1.65 V
V
2.5 V
2.5 V
0.55
1.1 V to 3.6 V
1.65 V
1.1 V to 3.6 V
1.65 V
VCC0 – 0.2
1.2
B port
(Buffer-type output,
IOH = –8 mA
IOH = –100 µA
IOH = –4 mA
IOH = –100 µA
IOH = –2 mA
8-mA drive)
2.5 V
2.5 V
1.97
1.1 V to 3.6 V
1.65 V
1.1 V to 3.6 V
1.65 V
VCC0 – 0.2
1.2
B port
(Buffer-type output,
4-mA drive)
2.5 V
2.5 V
1.97
VOH
V
1.1 V to 3.6 V
1.65 V
1.1 V to 3.6 V
1.65 V
VCC0 – 0.2
1.2
B port
(Buffer-type output,
2-mA drive)
2.5 V
2.5 V
1.97
B port
1.65 V
1.65 V
1.5
(Switch-type
outputs)
IOH = –20 µA
2.5 V
2.5 V
2.3
IOL = 100 µA
IOL = 8 mA
IOL = 100 µA
IOL = 4 mA
IOL = 100 µA
IOL = 2 mA
1.1 V to 3.6 V
1.65 V
1.1 V to 3.6 V
1.65 V
0.2
0.45
0.55
0.2
B port
(Buffer-type output,
8-mA drive)
2.5 V
2.5 V
1.1 V to 3.6 V
1.65 V
1.1 V to 3.6 V
1.65 V
B port
(Buffer-type output,
4-mA drive)
0.45
2.5 V
2.5 V
0.55
V
VOL
1.1 V to 3.6 V
1.65 V
1.1 V to 3.6 V
1.65 V
0.2
0.45
0.55
0.45
B port
(Buffer-type output,
2-mA drive)
2.5 V
2.5 V
B port
(Switch-type
outputs)
IOL = 220 µA, VIN = 0.15 V
IOL = 300 µA, VIN = 0.15 V
VI = VCCA or GND
1.65 V
1.65 V
2.5 V
2.5 V
0.55
II
1.1 V to 3.6 V
1.1 V to 3.6 V
3.6 V
1.1 V to 3.6 V
1.1 V to 3.6 V
0 V
±1 µA
15
Switch-type I/O are open and all
other inputs are biased at either
VCC or GND
ICCA
14 µA
–12
0 V
3.6 V
(1) All typical values are at TA = 25°C.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
1.1 V to 3.6 V
3.6 V
VCCB
1.1 V to 3.6 V
0 V
MIN
TYP(1) MAX UNIT
15
Switch-type I/O are open and all
other inputs are biased at either
VCC or GND
ICCB
–12 µA
14
0 V
3.6 V
ICCA + ICCB
Auto-Dir (SDIO
VI = VCCI or GND, IO = 0
VI = VCCI
1.1 V to 3.6 V
1.1 V to 3.6 V
30 µA
5.5
pF
lines)
Cio
Bi-Dir buffer
AUD_DIR / OE
Buffer
VI = VCCX or GND
VI = VCCA or GND
VI = VCCX or GND
VI = VCCX or GND
VI = VCCX or GND
VI = VCCX or GND
4.5
4
Ci
pF
4
2-mA buffer
4-mA buffer
8-mA buffer
5
Co
5
6
pF
OUTPUT DRIVE STRENGTH
2 mA
4 mA
8 mA
WLAN_EN(B)
SLOW_CLK(B)
BT_EN(B)
AUDIO_OUT(A)
WLAN_IRQ(A)
SDIO_CLK(B)
BT_UART_TX(A)
BT_UART_RX(B)
CLK_REQ(A)
AUDIO_IN(B)
AUDIO_CLK(A)
BT_UART CTS(B)
BT_UART RTS(A)
AUDIO_F-SYNC(A)
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TIMING REQUIREMENTS
VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
UNIT
MIN
MAX
60
Push-pull driving
SDIO_CMD
Mbps
Open-drain driving
1
Data rate
SDIO_CLK
50 MHz
Push-pull driving
SDIO_DATAx
60 Mbps
Push-pull driving
17
1
ns
µs
ns
ns
SDIO_CMD
Open-drain driving
tW
Pulse duration
SDIO_CLK
10
17
Push-pull driving
SDIO_DATAx
TIMING REQUIREMENTS
VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
UNIT
MIN
MAX
Push-pull driving
60
1
SDIO_CMD
Open-drain driving
Data rate
Mbps
SDIO_CLK
50 MHz
Push-pull driving
SDIO_DATAx
60 Mbps
Push-pull driving
SDIO_CMD
17
1
ns
µs
ns
ns
Open-drain driving
tW
Pulse duration
SDIO_CLK
10
17
Push-pull driving
SDIO_DATAx
10
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SWITCHING CHARACTERISTICS
VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
Push-pull driving
UNIT
MIN
MAX
7
7
SDIO_CMD(A)
SDIO_CMD(B)
SDIO_CMD(B)
SDIO_CMD(A)
Open-drain driving (H-to-L)
Open-drain driving (L-to-H)
Push-pull driving
1.1
30
510
7
Open-drain driving (H-to-L)
Open-drain driving (L-to-H)
Push-pull driving
1
30
1
7.5
515
6.5
7
tpd
ns
SDIO_CLK(A)
SDIO_DATAx(A)
SDIO_DATAx(B)
Buffered input
Buffered input
Buffered input
SDIO_CLK(B)
SDIO_DATAx(B)
1
Push-pull driving
SDIO_DATAx(A)
1
7
2-mA drive strength output
4-mA drive strength output
8-mA drive strength output
2-mA drive strength output
4-mA drive strength output
8-mA drive strength output
Switch-type output
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Open-drain driving
Push-pull driving
Push-pull driving
Open-drain driving
1
7.6
7
1
1
6.5
16
19
18
1
ns
µs
ns
µs
ns
ten
OE
OE
2-mA drive strength output
4-mA drive strength output
8-mA drive strength output
Switch-type outputs
17
16.5
16
1
tdis
1
15
1
5
SDIO_CMD(A) rise time
trA
420
4.7
9.7
420
6
SDIO_DATAx(A) rise time
SDIO_CMD(B) rise time
1
15
0.5
1
trB
ns
ns
ns
SDIO_CLK(B) rise time
Push-pull driving
SDIO_DATAx(B) rise time
9.7
8.3
8.3
8.3
9.9
10.9
5.3
9.9
0.4
0.4
1.3
60
1
Push-pull driving
Open-drain driving
Push-pull driving
Push-pull driving
Open-drain driving
0.7
1.6
1
SDIO_CMD(A) fall time
SDIO_DATAx(A) fall time
SDIO_CMD(B) fall time
tfA
1
1.6
0.5
1
tfB
SDIO_CLK(B) fall time
SDIO_DATAx(B) fall time
SDIO Ch-A to Ch-B skew
SDIO Ch-B to Ch-A skew
SDIO channel-to-clock skew
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Open-drain driving
tsk(O)
ns
SDIO_CMD
Mbps
Max data rate
SDIO_CLK
50 MHz
60 Mbps
Push-pull driving
SDIO_DATAx
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SWITCHING CHARACTERISTICS
VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
Push-pull driving
UNIT
MIN
MAX
7
7
SDIO_CMD(A)
SDIO_CMD(B)
SDIO_CMD(B)
SDIO_CMD(A)
Open-drain driving (H-to-L)
Open-drain driving (L-to-H)
Push-pull driving
1.1
30
510
7
Open-drain driving (H-to-L)
Open-drain driving (L-to-H)
Push-pull driving
1
30
1
7.5
515
6.5
7
tpd
ns
SDIO_CLK(A)
SDIO_DATAx(A)
SDIO_DATAx(B)
Buffered input
Buffered input
Buffered -nput
SDIO_CLK(B)
SDIO_DATAx(B)
1
Push-pull driving
SDIO_DATAx(A)
1
7
2-mA drive strength output
4-mA drive strength output
8-mA drive strength output
2-mA drive strength output
4-mA drive strength output
8-mA drive strength output
Switch-type output
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Open-drain driving
Push-pull driving
Push-pull driving
Open-drain driving
1
7.6
7
1
1
6.5
16
19
ns
µs
ns
µs
ns
ten
OE
OE
19
1
2-mA drive strength output
4-mA drive strength output
8-mA drive strength output
Switch-type output
17
16
tdis
16
1
1
15
1
4.25
420
4.25
9.5
420
5.9
9.6
8.2
8.2
8.2
9.2
10.8
5.2
9.8
0.4
0.4
1.3
60
SDIO_CMD(A) rise time
trA
SDIO_DATAx(A) rise time
SDIO_CMD(B) rise time
1
15
0.5
1
trB
ns
ns
ns
SDIO_CLK(B) rise time
Push-pull driving
SDIO_DATAx(B) rise time
Push-pull driving
Open-drain driving
Push-pull driving
Push-pull driving
Open-drain driving
0.7
1.6
1
SDIO_CMD(A) fall time
SDIO_DATAx(A) fall time
SDIO_CMD(B) fall time
tfA
1
1.6
0.5
1
tfB
SDIO_CLK(B) fall time
SDIO_DATAx(B) fall time
SDIO Ch-A to Ch-B skew
SDIO Ch-B to Ch-A skew
SDIO Channel-to-Clock skew
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Push-pull driving
Open-drain driving
tsk(O)
ns
SDIO_CMD
Mbps
1
Max data rate
SDIO_CLK
50 MHz
60 Mbps
Push-pull driving
SDIO_DATAx
12
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OPERATING CHARACTERISTICS
TA = 25°C
VCCA = VCCB
= 1.8 V
VCCA = VCCB
= 2.5 V
PARAMETER
TEST CONDITIONS
UNIT
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
18.3
18.25
0.8
0.1
0.6
8.8
0.1
0.1
0.6
7.1
0.1
0.1
0.6
7.6
0.1
0.1
0.6
8.8
0.1
0.1
0.6
8.2
0.1
0.1
20.3
19.52
0.8
Enabled
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
DATAx and CMD
pF
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
0.1
0.9
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
10.1
0.1
Clock
pF
pF
pF
pF
pF
0.1
1.0
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
7.9
2-mA buffer
4-mA buffer
8-mA buffer
4-mA I/O
0.1
0.1
1.0
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
8.6
0.1
0.1
1.0
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
10.1
0.1
0.1
0.95
9.1
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
0.1
0.1
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TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.25
0.24
0.23
0.22
0.21
0.20
0.19
0.18
0.17
0.16
0.15
0.28
0.27
0.26
0.25
0.24
0.23
0.22
0.21
0.20
0.19
0.18
0.17
0.16
0.15
Switch Type
Switch Type
VCCA = VCCB = 2.6 V
IN = 0.15 V
VCCA = VCCB = 1.8 V
VIN = 0.15 V
V
TA = 85°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = -40°C
TA = -40°C
0
20 40 60 80 100 120 140 160 180 200 220
OL (µA)
0
30 60 90 120 150 180 210 240 270 300
I
IOL (µA)
Figure 1.
Figure 2.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
2-mA Buffer Type
VCCA = VCCB = 1.8 V
IN = 0.0 V
2-mA Buffer Type
VCCA = VCCB = 2.6 V
VIN = 0.0 V
V
TA = 85°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = -40°C
TA = -40°C
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
IOL (mA)
IOL (mA)
Figure 3.
Figure 4.
14
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TYPICAL CHARACTERISTICS (continued)
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.15
0.14
0.13
0.12
0.11
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.15
0.14
0.13
0.12
0.11
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
4-mA Buffer Type
4-mA Buffer Type
V
V
CCA = VCCB = 2.6 V
IN = 0.0 V
VCCA = VCCB = 1.8 V
VIN = 0.0 V
TA = 85°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = -40°C
TA = -40°C
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
IOL (mA)
IOL (mA)
Figure 5.
Figure 6.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
8-mA Buffer Type
8-mA Buffer Type
VCCA = VCCB = 2.6 V
VIN = 0.0 V
V
V
CCA = VCCB = 1.8 V
IN = 0.0 V
TA = 85°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = -40°C
TA = -40°C
0.0 0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0
0.0 0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0
IOL (mA)
IOL (mA)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
1.81
1.80
1.79
1.78
1.77
1.76
1.75
1.74
1.73
1.72
1.71
1.70
2.61
2.60
2.59
2.58
2.57
2.56
2.55
2.54
2.53
2.52
2.51
2.50
Switch Type
Switch Type
VCCA = VCCB = 1.8 V
VIN = 1.8 V
VCCA = VCCB = 2.6 V
VIN = 2.6 V
TA = -40°C
TA = -40°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
-20 -18 -16 -14 -12 -10 -8
-6
-4
-2
0
-20 -18 -16 -14 -12 -10 -8
-6
-4
-2
0
IOH (µA)
IOH (µA)
Figure 9.
Figure 10.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.61
2.60
2.59
2.58
2.57
2.56
2.55
2.54
2.53
2.52
2.51
2.50
1.81
1.80
1.79
1.78
1.77
1.76
1.75
1.74
1.73
1.72
1.71
1.70
1.69
1.68
2-mA Buffer Type
2-mA Buffer Type
VCCA = VCCB = 2.6 V
VCCA = VCCB = 1.8 V
VIN = 1.8 V
V
IN = 2.6 V
TA = -40°C
TA = -40°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
IOH (mA)
IOH (mA)
Figure 11.
Figure 12.
16
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TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.61
2.60
2.59
2.58
2.57
2.56
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
1.81
1.80 4-mA Buffer Type
1.79 VCCA = VCCB = 1.8 V
4-mA Buffer Type
V
V
CCA = VCCB = 2.6 V
IN = 2.6 V
VIN = 1.8 V
1.78
1.77
1.76
1.75
1.74
1.73
1.72
1.71
1.70
1.69
1.68
1.67
1.66
1.65
1.64
1.63
TA = -40°C
TA = -40°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
-4.0 -3.6 -3.2 -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0
-4.0 -3.6 -3.2 -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0
IOH (mA)
IOH (mA)
Figure 13.
Figure 14.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.61
1.81
8-mA Buffer Type
8-mA Buffer Type
VCCA = VCCB = 1.8 V
VIN = 1.8 V
1.79
1.77
1.75
1.73
1.71
1.69
1.67
1.65
1.63
1.61
1.59
1.57
1.55
V
V
CCA = VCCB = 2.6 V
IN = 2.6 V
2.59
2.57
2.55
2.53
2.51
2.49
2.47
2.45
2.43
2.41
TA = -40°C
TA = -40°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
-8.0 -7.2 -6.4 -5.6 -4.8 -4.0 -3.2 -2.4 -1.6 -0.8 0.0
-8.0 -7.2 -6.4 -5.6 -4.8 -4.0 -3.2 -2.4 -1.6 -0.8 0.0
IOH (mA)
IOH (mA)
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY TIME (HIGH TO LOW)
PROPAGATION DELAY TIME (LOW TO HIGH)
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Switch Type
A = -40°C
Switch Type
T
TA = -40°C
VCCA = VCCB = 1.8 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.6 V
VCCA = VCCB = 2.6 V
0
10
20
30
40
50
60
0
10
20
30
40
50
60
CL (pF)
CL (pF)
Figure 17.
Figure 18.
PROPAGATION DELAY TIME (HIGH TO LOW)
PROPAGATION DELAY TIME (LOW TO HIGH)
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Switch Type
A = 25°C
Switch Type
T
TA = 25°C
VCCA = VCCB = 1.8 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.6 V
VCCA = VCCB = 2.6 V
0
10
20
30
40
50
60
0
10
20
30
40
50
60
CL (pF)
CL (pF)
Figure 19.
Figure 20.
18
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TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY TIME (HIGH TO LOW)
PROPAGATION DELAY TIME (LOW TO HIGH)
vs
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Switch Type
TA = 85°C
Switch Type
TA = 85°C
VCCA = VCCB = 1.8 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.6 V
VCCA = VCCB = 2.6 V
0
10
20
30
40
50
60
0
10
20
30
40
50
60
CL (pF)
CL (pF)
Figure 21.
Figure 22.
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Typical Application Wiring for TWL1200 When Connecting to the WL1271
Table 1. WL1271+TWL1200 Interface
HOST
(MSM)
BALL
NO.
BALL
NO.
WL1271
COB
PIN NAME
TYPE
TYPE
PIN NAME
VCCA
C4
D4
B2
C2
C1
B1
A2
A1
D1
D2
E1
E2
G1
F1
G2
F2
F3
A3
B3
G3
G4
A4
B4
Power (3.0 V)
Power (3.0 V)
I/O ↔
I/O ↔
I/O ↔
I/O ↔
I/O ↔
I →
Power (1.8 V)
Power (1.8 V)
I/O ↔
I/O ↔
I/O ↔
I/O ↔
I/O ↔
O →
C5
D5
B6
C6
C7
B7
A6
A7
D6
D7
E7
E6
G7
F7
G6
F6
F5
A5
B5
G5
F4
D3
E3
E4
E5
VCCB
VCCB
VCCA
SDIO_DATA0(A)
SDIO_DATA1(A)
SDIO_DATA2(A)
SDIO_DATA3(A)
SDIO_CMD(A)
SDIO_CLK(A)
WLAN_EN(A)
WLAN_IRQ(A)
CLK_REQ(A)
BT_EN(A)
SDIO_DATA0(B)
SDIO_DATA1(B)
SDIO_DATA2(B)
SDIO_DATA3(B)
SDIO_CMD(B)
SDIO_CLK(B)
WLAN_EN(B)
WLAN_IRQ(B)
CLK_REQ(B)
BT_EN(B)
K4
J4
J3
J5
L3
M3
J2
I →
O →
O ←
I ←
G4
F5
O ←
I ←
I →
O →
G5
G7
E11
G8
G11
F6
BT_UART_RX(A)
BT_UART_CTS(A)
BT_UART_TX(A)
BT_UART_RTS(A)
AUDIO_IN(A)
AUDIO_CLK(A)
AUDIO_F-SYN(A)
AUDIO_OUT(A)
SLOW_CLK(A)
AUD_DIR
I →
TWL1200
O →
BT_UART_RX(B)
BT_UART_CTS(B)
BT_UART_TX(B)
BT_UART_RTS(B)
AUDIO_IN(B)
AUDIO_CLK(B)
AUDIO_F-SYN(B)
AUDIO_OUT(B)
SLOW_CLK(B)
GND
I →
O →
O ←
I ←
O ←
I ←
I →
I/O ↔
I/O ↔
I/O ↔
I ←
I/O ↔
I/O ↔
O ←
F8
H11
F7
I →
O →
K9
I →
GND
OE
active low
GND
GND
GND
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PARAMETER MEASUREMENT INFORMATION
2 × V
CCO
TEST
S1
S1
R
L
Open
GND
t
Open
pd
From Output
Under Test
t
t
/t
/t
2 × V
CCO
GND
PLZ PZL
PHZ PZH
C
L
R
L
(see Note A)
t
w
LOAD CIRCUIT FOR
BUFFER-TYPE OUTPUTS
V
CCI
V
CCI
/2
V
CCI
/2
Input
C
L
V
TP
R
L
V
CCO
0 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
15 pF
15 pF
15 pF
VOLTAGE WAVEFORMS
PULSE DURATION
V
CCA
Output
Control
(low-level
enabling)
V /2
CCA
V
CCA
/2
t
0 V
t
PZL
PLZ
V
V
CCO
Output
Waveform 1
V
CCI
V
/2
/2
CCO
Input
V
CCI
/2
V
CCI
/2
V
+ V
OL
TP
S1 at 2 × V
CCO
OL
0 V
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− V
TP
V
CCO
Output
V /2
CCO
V
CCO
/2
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
t
t
t
V
V
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
pd
PHL
is the V associated with the input port.
CC
CCI
is the V associated with the output port.
CCO
CC
Figure 23. Push-Pull Buffered Direction Control Load Circuit and Voltage Waveform
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PARAMETER MEASUREMENT INFORMATION (continued)
V
CCI
V
CCO
V
CCI
V
CCO
DUT
DUT
IN
IN
OUT
OUT
1 MW
1 MW
15 pF
15 pF
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
AN OPEN-DRAIN DRIVER
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
A PUSH-PULL DRIVER
From Output
Under Test
15 pF
1 MW
LOAD CIRCUIT FOR ENABLE/DISABLE TIME MEASUREMENT −
SWITCH-TYPE SDIOs
t
w
V
CCI
V
CCI
/2
V
CCI
/2
Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
OE
V
CCI
Input
Input
V
CCI
/2
V
CCI
/2
0 V
t
t
PLH
PHL
V
OH
0.9 y V
CCO
Output
Output
V /2
CCO
V
/2
CCO
0.1 y V
CCO
V
OL
t
en
t
dis
t
f
t
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
t
t
t
V
V
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
pd
PHL
is the V associated with the input port.
CC
CCI
is the V associated with the output port.
CCO
CC
J. All parameters and waveforms are not applicable to all devices.
Figure 24. Auto-Direction Control Load Circuit and Voltage Waveform
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APPLICATION CIRCUIT EXAMPLES
VCCB
VCCA
C
C
TWL1200
C4
D4
C5
D5
E1
E7
CLK_REQ(A)
CLK_REQ(B)
VCCA
VCCA
VCCB
VCCB
A1
A7
SDIO_CLK(A)
SDIO_CLK(B)
WLAN_SDIO30_CLK
WLAN_SDIO_CLK
F3
F5
BT_PCM30_DO
BT_PCM_DO
AUDIO_IN(A)
AUDIO_IN(B)
A2
A6
SDIO_CMD(A)
SDIO_CMD(B)
WLAN_SDIO30_CMD
WLAN_SDIO_CMD
A3
A5
BT_PCM30_CLK
BT_PCM_CLK
AUDIO_CLK(A)
AUDIO_CLK(B)
B2
C2
C1
B1
WLAN_SDIO30_D0
WLAN_SDIO30_D1
WLAN_SDIO30_D2
WLAN_SDIO30_D3
SDIO_DATA0(A)
SDIO_DATA1(A)
SDIO_DATA2(A)
SDIO_DATA3(A)
B3
B5
BT_PCM30_SYNC
BT_PCM_SYNC
AUDIO_F-SYN(A)
AUDIO_F-SYN(B)
B6
C6
C7
B7
A4
AUD_DIR
SDIO_DATA0(B)
SDIO_DATA1(B)
SDIO_DATA2(B)
SDIO_DATA3(B)
WLAN_SDIO_D0
WLAN_SDIO_D1
WLAN_SDIO_D2
WLAN_SDIO_D3
G3
G5
BT_PCM30_DI
BT_PCM_DI
AUDIO_OUT(A)
AUDIO_OUT(B)
E2
E6
G4
F4
BT_EN(A)
BT_EN(B)
BT_EN30
BT_EN
SLOW_CLK(A)
SLOW_CLK(B)
CLK32_COMBO
CLK32_COMBO18
F1
F7
D1
D6
BT_UART_CTS(A)
BT_UART_CTS(B)
BT_UART30_RTS
BT_UART_RTS
WLAN_EN(A)
WLAN_EN(B)
WLAN_EN30
WLAN_EN
BT_IRQ30
BT_UART30_CTS
BT_UART_CTS
D2
D7
F2
F6
WLAN_IRQ(A)
WLAN_IRQ(B)
WLAN_IRQ30
WLAN_IRQ
BT_UART_RTS(A)
BT_UART_RTS(B)
G1
G7
BT_UART30_TXD
BT_UART_TXD
BT_UART_RX(A)
BT_UART_RX(B)
D3
E3
E4
E5
G2
G6
GND
GND
GND
GND
BT_UART30_RXD
BT_UART_RXD
BT_UART_TX(A)
BT_UART_TX(B)
B4
OE
R
Figure 25. Application Circuit Example, OE Connection With Audio_CLK and Audio_F-SYNC Channels
Established From B Side to A Side
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VCCB
VCCA
C
C
TWL1200
C4
D4
C5
D5
E1
E7
CLK_REQ(A)
CLK_REQ(B)
VCCA
VCCA
VCCB
VCCB
A1
A7
SDIO_CLK(A)
SDIO_CLK(B)
WLAN_SDIO30_CLK
WLAN_SDIO_CLK
F3
F5
BT_PCM30_DO
BT_PCM_DO
AUDIO_IN(A)
AUDIO_IN(B)
A2
A6
SDIO_CMD(A)
SDIO_CMD(B)
WLAN_SDIO30_CMD
WLAN_SDIO_CMD
A3
A5
BT_PCM30_CLK
BT_PCM_CLK
AUDIO_CLK(A)
AUDIO_CLK(B)
B2
C2
C1
B1
WLAN_SDIO30_D0
WLAN_SDIO30_D1
WLAN_SDIO30_D2
WLAN_SDIO30_D3
SDIO_DATA0(A)
SDIO_DATA1(A)
SDIO_DATA2(A)
SDIO_DATA3(A)
VCCA
B3
B5
BT_PCM30_SYNC
BT_PCM_SYNC
AUDIO_F-SYN(A)
AUDIO_F-SYN(B)
R
B6
C6
C7
B7
A4
AUD_DIR
SDIO_DATA0(B)
SDIO_DATA1(B)
SDIO_DATA2(B)
SDIO_DATA3(B)
WLAN_SDIO_D0
WLAN_SDIO_D1
WLAN_SDIO_D2
WLAN_SDIO_D3
G3
G5
R
BT_PCM30_DI
BT_PCM_DI
AUDIO_OUT(A)
AUDIO_OUT(B)
E2
E6
G4
F4
BT_EN(A)
BT_EN(B)
BT_EN30
BT_EN
SLOW_CLK(A)
SLOW_CLK(B)
CLK32_COMBO
CLK32_COMBO18
F1
F7
D1
D6
BT_UART_CTS(A)
BT_UART_CTS(B)
BT_UART30_RTS
BT_UART_RTS
WLAN_EN(A)
WLAN_EN(B)
WLAN_EN30
WLAN_EN
D2
D7
F2
F6
WLAN_IRQ(A)
WLAN_IRQ(B)
WLAN_IRQ30
WLAN_IRQ
BT_UART30_CTS
BT_UART_CTS
BT_UART_RTS(A)
BT_UART_RTS(B)
G1
G7
BT_UART30_TXD
BT_UART_TXD
BT_UART_RX(A)
BT_UART_RX(B)
D3
E3
E4
E5
G2
G6
GND
GND
GND
GND
BT_UART30_RXD
BT_UART_RXD
BT_UART_TX(A)
BT_UART_TX(B)
B4
BT_WLAN_LEVEL_EN
VCCB
OE
R
Figure 26. Application Circuit Example, With Voltage Divider for AUD_DIR Connection
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PRINCIPLES OF OPERATION
Applications
The TWL1200 device has been designed to bridge the digital-switching compatibility gap between two voltage
nodes to successfully interface logic threshold levels between a host processor and the Texas Instruments
Wi-Link-6 WLAN/BT/FM products. It is intended to be used in a point-to-point topology when interfacing these
devices that may or may not be operating at different interface voltages.
Architecture
The BT/UART and PCM/Audio subsystem interfaces consist of a fully-buffered voltage translator design that has
its output transistors to source and sink current optimized for drive strength.
The SDIO lines comprise a semi-buffered auto-direction-sensing based translator architecture (see Figure 27)
that does not require a direction-control signal to control the direction of data flow of the A to B ports (or from B
to A ports).
VCCA
VCCB
One-Shot
One-Shot
R1
T1
R2
Translator
T2
SDIO-DATAx(A)
SDIO-DATAx(B)
Bias
N1
One-Shot
T3
Translator
One-Shot
T4
Figure 27. Architecture of an SDIO Switch-Type Cell
Each of these bidirectional SDIO channels independently determines the direction of data flow without a
direction-control signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is
how this auto-direction feature is realized.
The following two key circuits are employed to facilitate the "switch-type" voltage translation function:
1. Integrated pullup resistors to provide dc-bias and drive capabilities
2. An N-channel pass-gate transistor topology (with a high RON of ~300 Ω) that ties the A-port to the B-port
3. Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B
ports
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For bidirectional voltage translation, pullup resistors are included on the device for dc current sourcing capability.
The VGATE gate bias of the N-channel pass transistor is set at a level that optimizes the switch characteristics for
maximum data rate as well as minimal static supply leakage. Data can flow in either direction without guidance
from a control signal.
The edge-rate acceleration circuitry speeds up the output slew rate by monitoring the input edge for transitions,
helping maintain the data rate through the device.
During a low-to-high signal rising-edge, the O.S. circuits turn on the PMOS transistors (T1, T3) and its associated
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever
occurs first. This edge-rate acceleration provides high ac drive by bypassing the internal pullup resistors during
the low-to-high transition to speed up the rising-edge signal.
During a high-to-low signal falling-edge, the O.S. circuits turn on the NMOS transistors (T2, T4) and its associated
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever
occurs first.
To minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to
turn-off before applying a signal in the opposite direction. The worst-case duration is equal to the minimum
pulse-width number provided in the Timing Requirements section of this data sheet.
Once the O.S. is triggered and switched off, both the A and B ports must go to the same state (i.e. both High or
both Low) for the one-shot to trigger again. In a DC state, the output drivers maintain a Low state through the
pass transistor. The output drivers maintain a High through the "smart pullup resistors" that dynamically change
value based on whether a Low or a High is being passed through the SDIO lines, as follows:
•
•
•
RPU1 and RPU2 values are 25 kΩ when the output is driving a low
RPU1 and RPU2 values are 4 kΩ when the output is driving a high
RPU1 and RPU2 values are 70 kΩ when the device is disabled via the OE pin or by pulling the either VCCA or
VCCB to 0 V.
The reason for using these "smart" pullup resistors is to allow the TWL1200 to realize a lower static power
consumption (when the I/Os are low), support lower VOL values for the same size pass-gate transistor, and
improved simultaneous switching performance.
Input Driver Requirements
The continuous dc-current "sinking" capability is determined by the external system-level driver interfaced to the
SDIO pins. Since the high bandwidth of these bidirectional SDIO circuits necessitates the need for a port to
quickly change from an input to an output (and vice-vera), they have a modest dc-current "sourcing" capability of
hundreds of micro-Amps, as determined by the smart pullup resistor values.
The fall time (tfA, tfB) of a signal depends on the edge rate and output impedance of the external device driving
the SDIO I/Os, as well as the capacitive loading on these lines.
Similarly, the tpd and max data rates also depend on the output impedance of the external driver. The values for
tfA, tfB, tpd, and maximum data rates in the data sheet assume that the output impedance of the external driver is
less than 50 Ω.
Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC
,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TWL1200 SDIO output sees, so it is recommended that this lumped-load capacitance be
considered and kept below 75 pF to avoid O.S. retriggering, bus contention, output signal oscillations, or other
adverse system-level affects.
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TWL1200ZQCR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQC
48
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TWL1200ZQCR
BGA MI
CROSTA
R JUNI
OR
ZQC
48
2500
330.0
12.4
4.3
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jun-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
340.5 338.1 20.6
TWL1200ZQCR
BGA MICROSTAR
JUNIOR
ZQC
48
2500
Pack Materials-Page 2
IMPORTANT NOTICE
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Amplifiers
Applications
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Automotive
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Medical
Military
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Security
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Logic
Power Mgmt
Microcontrollers
RFID
Telephony
Video & Imaging
Wireless
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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相关型号：
TWL2214CAPFBR
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48, PLASTIC, TQFP-48, Power Management Circuit
TI
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