TVP3010-85MGA_技术文档

TVP3010C, TVP3010M

Data Manual

Video Interface Palette

SLAS082A

October 1997

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any

semiconductor product or service without notice, and advises its customers to obtain the latest

version of relevant information to verify, before placing orders, that the information being relied

on is current.

TI warrantsperformanceofitssemiconductorproductsandrelatedsoftwaretothespecifications

applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality

control techniques are utilized to the extent TI deems necessary to support this warranty.

Specific testing of all parameters of each device is not necessarily performed, except those

mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death,

personal injury, or severe property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES

OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer.

Use of TI products in such applications requires the written approval of an appropriate TI officer.

Questions concerning potential risk applications should be directed to TI through a local SC

sales office.

In order to minimize risks associated with the customer’s applications, adequate design and

operating safeguards should be provided by the customer to minimize inherent or procedural

hazards.

TI assumes no liability for applications assistance, customer product design, software

performance, or infringement of patents or services described herein. Nor does TI warrant or

represent that any license, either express or implied, is granted under any patent right, copyright,

mask work right, or other intellectual property right of TI covering or relating to any combination,

machine, or process in which such semiconductor products or services might be or are used.

Contents

Section

Title

Page

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1 Features (TVP3010C and TVP3010M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7

1.5 Terminal Functions (TVP3010C and TVP3010M) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7

2

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.1 MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.2 Color Palette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

2.2.1

2.2.2

2.2.3

2.2.4

Writing to Color-Palette RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Reading From Color-Palette RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Palette Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

Read Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

2.3 Clock Selection and Output-Clock (SCLK, RCLK, and VCLK) Generation . . . . . 2–5

2.3.1

2.3.2

RCLK, SCLK, VCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Frame-Buffer Clocking: Self-Clocked or Externally Clocked . . . . . . . . . 2–8

2.4 Multiplexing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

2.4.1

2.4.2

2.4.3

2.4.4

2.4.5

2.4.6

Little-Endian and Big-Endian Data Format . . . . . . . . . . . . . . . . . . . . . . . 2–12

VGA Pass-Through Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

Pseudo-Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

Direct-Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

True-Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Multiplex Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

2.5 On-Chip Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

2.5.1

2.5.2

2.5.3

2.5.4

2.5.5

Cursor RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Two-Color 64 × 64 Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

64 × 64 Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Crosshair Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

Dual-Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

2.6 Auxiliary Window, Port Select, and Color-Key Switching . . . . . . . . . . . . . . . . . . . . 2–27

2.6.1

2.6.2

Windowing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

Color-Key-Switching Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

2.7 Overscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

2.8 Horizontal Zooming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

2.9 Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

2.9.1

2.9.2

2.9.3

16-Bit CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Sense-Comparator Output and Test Register . . . . . . . . . . . . . . . . . . . . . 2–33

Identification Code (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

2.10 MUXOUT [SENSE]Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

iii

Section

Title

Page

2.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

2.11.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

2.11.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

2.12 Frame-Buffer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

2.13 Analog-Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

2.14 Video Control: Horizontal Sync, Vertical Sync, and Blank . . . . . . . . . . . . . . . . . . . 2–37

2.15 Split Shift Register Transfer VRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

2.16 Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

2.16.1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

2.16.2 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

2.16.3 Cursor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–40

2.16.4 Cursor Position X and Y Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

2.16.5 Sprite Origin X and Y Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

2.16.6 Window Start X and Y Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43

2.16.7 Window Stop X and Y Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–44

2.16.8 Cursor Color 0, 1 RGB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45

2.16.9 Cursor-RAM Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

2.16.10 Cursor RAM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

2.16.11 AuxiliaryControl Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47

2.16.12 Color-Key-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

2.16.13 Color-Key (Red, Green, Blue, Overlay) Low and High Registers . . . . 2–49

2.16.14 Overscan Color RGB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50

2.16.15 CRC LSB and MSB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51

2.16.16 CRC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51

3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . 3–1

3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.3 Electrical Characteristics for TVP3010C Over Recommended Ranges of

Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.4 Electrical Characteristics for TVP3010M Over Recommended Ranges of

Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . 3–3

3.5 Operating Characteristics (TVP3010C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

3.6 Operating Characteristics (TVP3010M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

3.7 Timing Requirements (TVP3010C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

3.8 Timing Requirements (TVP3010M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

3.9 Switching Characteristics for TVP3010C Over Recommended Ranges of

Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . 3–8

3.10 Switching Characteristics for TVP3010M Over Recommended Ranges of

Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . 3–10

3.11 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11

iv

Section

Title

Page

Appendix A

Appendix B

Appendix C

Appendix D

Appendix E

Printed Circuit Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . A–1

RCLK Frequency < VCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

Little-Endian and Big-Endian Data Formats . . . . . . . . . . . . . . . . . . . . . . . C–1

Examples: Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E–1

List of Illustrations

Figure

Title

Page

2–1

2–2

Dot Clock/VCLK/RCLK/SCLK Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = VCLK Frequency) . . . . . . . . . . . . . . . . 2–8

SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency) . . . . . . . . . . . . . . . . 2–9

SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = 4 x VCLK Frequency) . . . . . . . . . . . . 2–10

SCLK/VCLK Control Timing

2–3

2–4

2–5

(SSRT Enabled, RCLK/SCLK Frequency = 4 x VCLK Frequency) . . . . . . . . . . . . 2–10

CursorRAM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

Common Sprite-Origin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

Dual-Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

One Possible Custom-Cursor Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

2–6

2–7

2–8

2–9

2–10 VGA in the Auxiliary Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

2–11 Multiple VGA Windows Using Port Select (PSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30

2–12 Overscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

2–13 Equivalent Circuit of the Current Output (IOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

2–14 Composite Video Output (With 0 IRE, 8-Bit Output) . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

2–15 Composite Video Output (With 7.5 IRE, 8-Bit Output) . . . . . . . . . . . . . . . . . . . . . . . 2–36

2–16 Split Shift Register Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37

3–1

3–2

3–3

MPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11

Video Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12

SFLAG Timing (When SSRT Function is Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

v

List of Tables

Table

Title

Page

2–1

2–2

2–3

2–4

2–5

2–6

2–7

2–8

2–9

Direct Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Indirect Register Map (Extended Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Allocation of Palette-Page Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Input-Clock-Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

Output-Clock-Selection Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Multiplex Mode and Bus-Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Pseudo-Color Mode Pixel-Latching Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Direct-Color Mode Pixel-Latching Sequence (Little Endian) . . . . . . . . . . . . . . . . . . 2–19

Direct-Color Mode Pixel-Latching Sequence (Big Endian) . . . . . . . . . . . . . . . . . . . 2–20

2–10 True-Color Mode Pixel-Latching Sequence (Little Endian) . . . . . . . . . . . . . . . . . . . 2–21

2–11 True-Color Mode Pixel-Latching Sequence (Big Endian) . . . . . . . . . . . . . . . . . . . . 2–22

2–12 Two-Color 64 × 64 Cursor-RAM Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

2–13 Crosshair-Cursor Color Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

2–14 Cursor-Intersection Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

2–15 Windowing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28

2–16 Zoom Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32

2–17 Sense-Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34

2–18 K1 and K2 Values Defined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

2–19 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–38

2–20 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

2–21 Cursor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–40

2–22 Cursor Position X (LSB) and X (MSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

2–23 Sprite Origin X and Y Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

2–24 Window Start X and Y Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43

2–25 Window Stop X and Y Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–44

2–26 Cursor-Color RGB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45

2–27 Cursor RAM Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

2–28 Cursor RAM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

2–29 Auxiliary-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47

2–30 Color-Key Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

2–31 Color-Key Low and High Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–49

2–32 Overscan-Color RGB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50

2–33 CRC MSB and LSB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51

2–34 CRC Control Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–51

vi

1 Introduction

The TVP3010C and the TVP3010M palettes are commercial and military versions, respectively, of an

advanced Video Interface Palette (VIP) from Texas Instruments implemented in the EPIC 0.8-micron

CMOS process. Differences between the two versions are outlined in separate tables. In both versions,

maximum flexibility is provided by the pixel multiplexing scheme. The scheme accommodates 64-, 32-, 16-,

8-, and 4-bit pixel buses without any circuit modification. This enables the system to be easily reconfigured

forvaryingamountsofavailablevideoRAM. Thedevicesupportsselectionoflittle-orbig-endiandataformat

for the pixel-bus/frame-buffer interface. Data can be split into 1, 2, 4, or 8 bit-planes for pseudo-color mode

or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct-color modes, an 8-bit

overlay plane is available. The 16-bit direct-color and true-color modes can be configured to IBM XGA

(5, 6, 5), TARGA (5, 5, 5, 1), or (6, 6, 4) as another existing format. An additional 12-bit mode (4, 4, 4, 4)

is supported with 4 bits for each color and overlay. An on-chip, IBM XGA-compatible hardware cursor is

incorporated so that further increases in graphics-system performance are possible. Both devices are

software compatible with the INMOS IMSG176/8 and Brooktree Bt476/8 color palettes.

An internal-frequency doubler is incorporated, allowing convenient and cost-effective clock-source

alternatives to be utilized. An auxiliary windowing function and a pixel-port select function are provided so

that overlay or VGA graphics can be displayed on top of direct color inside or outside a specified auxiliary

window. Color-keyed switching of direct color and overlay is also supported.

Clocking is provided through one of five TTL inputs, CLK0–CLK4, and is software selectable. Additionally,

CLK1/CLK2 and CLK3/CLK4 can be selected as differential ECL clock sources. The video, shift-clock, and

reference-clock outputs provide a software-selected divide ratio of the chosen clock input. The reference

clock can optionally be provided as an output on CLK3, and a data-latch clock can optionally be input on

CLK4.

The TVP3010C and the TVP3010M have three 256

8 color look-up tables with triple 8-bit video

digital-to-analog converters (DACs) capable of directly driving a doubly-terminated 75-Ω line. The lookup

tables are designed with a dual-ported RAM architecture that enables ultra-high speed operation. Sync

generation is incorporated on the green output channel. Horizontal sync and vertical sync are fed through

the device and optionally inverted to indicate screen resolution to the monitor. A palette-page register

provides the additional bits of palette address when 1, 2, or 4 bit-planes are used. This allows the screen

colors to be changed with only one microprocessor-interface unit (MPU) write cycle.

Each device features a separate VGA bus that allows data from the feature connector of most

VGA-supported personal computers to be fed directly into the palette without the need for external data

multiplexing. This allows a replacement graphics board to remain downwards compatible by utilizing the

existing graphics circuitry often located on the motherboard.

Both the TVP3010 VIP and the TVP3010M VIP are highly system integrated. Either device can be

connected to the serial port of a VRAM device without external buffer logic and each device can be

connected to many graphics engines directly. The split shift register transfer function, which is supported

by VRAM, is also supported by the TVP3010C and TVP3010M.

The system-integration concept is carried to manufacturing testing and field diagnosis levels. To support

these testing and diagnostic levels, several highly-integrated test functions have been designed to enable

simplified testing of the palette, the graphics board, and the graphics system.

EPIC is a trademark of Texas Instruments Incorporated.

XGA is a registered trademark of International Business Machines Corporation.

TARGA is a registered trademark of Truevision Incorporated.

INMOS is a trademark of INMOS International Limited.

Brooktree is a trademark of Brooktree Corporation.

1–1

The TVP3010C and TVP3010M are 32-bit devices and both are pin compatible with the TLC3407X VIP,

allowing convenient performance upgrades when using devices in the TI Video Interface Palette family.

NOTE:

The TVP3010C and TVP3010M include circuits that are patented as well as circuit

designs that have patents pending.

1–2

1.1 Features (TVP3010C and TVP 3010M)

•

Second-Generation Video Interface Palette

•

Supports System Resolutions of:

–

1600 × 1280 × 1, 2, 4, 8, 16 Bits/Pixel @ 60-Hz Refresh Rate

1280 × 1024 × 1, 2, 4, 8, 16 Bits/Pixel @ 60-Hz and 72-Hz Refresh Rate

1024 × 768 × 1, 2, 4, 8, 16, 24 Bits/Pixel @ 60-Hz and 72-Hz Refresh Rate

And Lower Resolutions

•

Direct-Color Modes:

–

24-Bit/Pixel With 8-Bit Overlay

16-Bit/Pixel (5, 6, 5) XGA Configuration

16-Bit/Pixel (6, 6, 4) Configuration

15-Bit/Pixel With 1-Bit Overlay (5, 5, 5, 1) TARGA Configuration

12-Bit/Pixel With 4-Bit Overlay (4, 4, 4, 4)

True-Color Modes:

–

24-Bit/Pixel With Gamma Correction

16-Bit/Pixel (5, 6, 5) XGA Configuration With Gamma Correction

16-Bit/Pixel (6, 6, 4) Configuration With Gamma Correction

15-Bit/Pixel (5, 5, 5) TARGA Configuration With Gamma Correction

12-Bit/Pixel (4, 4, 4) With Gamma Correction

•

RCLK/SCLK/LCLK Data Latching Mechanism to Allow Flexible Control of VRAM Timing

Direct Interfacing to Video RAM

Support for Split Shift Register Transfers

Supports 64-Bit-Wide Pixel Bus

On-Chip Hardware Cursor:

–

64 × 64 × 2 Cursor (XGA Functionally Compatible)

Full-Window Crosshair

Dual-Cursor Mode

•

85-,110-,135-, and 170-MHz Versions

Supports Overscan for Creation of Custom Screen Borders

Versatile Pixel Bus Interface to Support Little- and Big-Endian Data Formats

Windowed-Overlay and VGA Capability

Color-Keyed Switching of Direct Color and Overlay

On-Chip Clock Selection

Internal Frequency Doubler

Triple 8-Bit D/A Converters

Analog Output Comparators

Triple 256 × 8 Color-Palette RAMs

RS-343A Compatible Outputs

Direct VGA Pass-Through Capability

Palette-Page Register

Horizontal Zooming Capability

Software Downward Compatible With IMSG176/8 and Bt476/8

Directly to Graphics Processors

EPIC 0.8-µm CMOS Process

1–3

1.2 Functional Block Diagram

The following functional block diagram applies to both the TVP3010C and TVP3010M.

REF

FS ADJUST

V

ref

1.235 V

24

16

8 – 8 – 8

6 – 6 – 4

5 – 6 – 5

5 – 5 – 5

4 – 4 – 4

12 - 24

Stuffing

Logic

Direct-Color

Pipeline Delay

16

15

12

True-Color

Multiplexer

32 32

24 24

24

Input

Latch

P(0 – 31)

COMP

IOR

32

256 × 8

Red

RAM

Pseudo-

Color

MUX

1:1

2:1

4:1

8:1

16:1

32:1

32

8

2

DAC

Read

Mask

Page

Reg

8

256 × 8

Green

RAM

4

8

Input

Latch

VGA(0 – 7)

8

256 × 8

Blue

RAM

1 × 24

Cursor

Color 0

1 × 24

Cursor

Color 1

8

Output

MUX

8

DAC

IOG

IOB

8

24

64 × 64

Cursor

RAM

and

Control

24

Frequency

Doubler

Color-Key

Switch

24

8

1 × 24

Overscan

D(0 – 7)

RS(0 – 2)

RD

8

3

MPU

Registers

and

Control

Logic

Test Function

and

Sense Comparator

2

Clock Select

and

Control

MUXOUT [SENSE]

WR

Auxiliary Window

and

Port Select

HSYNCOUT

VSYNCOUT

Video-Signal

Control

2

1–4

1.3 Terminal Assignments

84-PIN PLCC PACKAGE

11 10 9

8

7

6

5

4

3

2

1 84 83 82 81 80 79 78 77 76 75

P17

P16

P15

P14

P13

P12

P11

12

13

14

15

16

17

18

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

CLK3[RCLK]

CLK3[LCLK]

VGA7

VGA6

VGA5

VGA4

VGA3

P10 19

P9 20

VGA2

VGA1

21

22

23

24

25

26

27

28

29

30

31

32

P8

P7

VGA0

8/6[OVS]

MUXOUT [SENSE]

SFLAG

P6

P5

P4

VGABL

SYSBL

P3

P2

VSYNC

HSYNC

P1

P0

AV

DD

WR

RD

RS0

GND

AV

DD

GND

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

1–5

1.3 Terminal Assignments (continued)

84-PIN GA PACKAGE (TOP VIEW)

HSYNC-

OUT

FS

ADJUST

RS0

WR

D0

D1

D3

D2

D5

D4

D7

D6

AV

IOR

IOG

IOB

REF

12

11

DD

VSYNC-

OUT

RS3

[PSEL]

RS2

GND

COMP AV

DV

DD

P0

RD

RS1

GND

HSYNC

10

P2

P4

P6

P1

P3

P5

VSYNC SYSBL

VGABL SFLAG

9

8

7

8/6

[OVS]

MUXOUT

[SENSE]

P8

P9

P7

VGA1

VGA3

VGA5

VGA0

VGA2

VGA4

VGA6

VGA7

6

5

4

P10

P12

P15

P16

P11

P13

P14

(ESD symbol or alignment

dot on top)

CLK3

[LCLK]

P17

P19

CLK2

3

2

1

P22

P24

P27

P29

P31

GND

CLK0

CLK1

CLK3

[RCLK]

P18

A

P20

B

P21

C

P23

D

P25

E

P26

F

P28

G

P30

H

AV

J

SCLK VCLK

DD

K

L

M

1–6

1.4 Ordering Information

TVP3010 XXX – X – XX

Pixel Clock Frequency Indicator

Must contain three letters:

–85:

85-MHz pixel clock

–110: 110-MHz pixel clock

–135: 135-MHz pixel cock

–170: 170-MHz pixel clock

Military Extension M

Commercial Extension C

Package

Must contain two Letters:

FN: square plastic J-leaded chip carrier

GA: 84-pin (12 x 12) ceramic pin-grid array

1.5 Terminal Functions (TVP3010C and TVP3010M)

TERMINAL

I/O

DESCRIPTION

Analog power. All AV terminals must be connected.

NAME

NO. (FN)

55, 57

77

NO. (GA)

J1, L11, G12

K2

AV

DD

CLK0

I

Dot clock 0 input. CLK0 can be selected to drive the dot

clock at frequencies up to 140 MHz. When VGA mode is

(TTL

compatible) active, the default clock source is CLK0. The maximum

frequency in VGA mode is 85 MHz.

CLK1, CLK2

75, 76

L2, K3

I

Dual-mode dot clock input. These inputs are essentially

(TTL/ECL ECL-compatible inputs, but two TTL clocks may be used

compatible) on the CLK1 and CLK2 if so selected in the input clock

select register. These inputs may be selected as the dot

clock up to the device limit while in the ECL mode or up to

140 MHz in the TTL mode.

CLK3[RCLK]

74

M1

I/O

Dot clock 3 TTL input or reference clock output. When

configured as CLK3, this terminal is similar to CLK0 and

can be selected to drive the dot clock at frequencies up to

140MHz. WhenconfiguredasRCLK, thisterminaloutputs

the reference clock signal, which is similar to the SCLK

signal but not gated off during blanking. This signal can be

used for pixel-port timing reference or other system

synchronization.TheterminaldefaultstoCLK3afterreset.

CLK3[LCLK]

73

52

L3

I

Dotclock4TTLinputorpixel-portlatchclock. CLK3[LCLK]

can be configured to drive dot clock frequencies up to 140

MHz, or it can be configured as a latch-clock input to latch

pixel-port input data. It defaults to CLK4 after reset, and

LCLK is internally connected to RCLK to latch pixel-port

data.

COMP

K11

Compensation. COMP provides compensation for the

internal reference amplifier. A 0.1-µF ceramic capacitor is

requiredbetweenCOMPandAV . TheCOMPcapacitor

DD

must be as close to the device as possible to avoid noise

pick up.

NOTE 1: All unused inputs should be tied to a logic level and not be allowed to float.

1–7

1.5 Terminal Functions (TVP3010C and TVP3010M) Continued

TERMINAL

I/O

DESCRIPTION

terminalsmustbeconnected

NAME

NO. (FN)

NO. (GA)

DV

45, 81

M11

Digitalpower. AllDV

together.

DD

D(0–7)

36–43

51

B12, C12,

D11, D12,

E11, E12,

F11, F12

I/O

(TTL

MPU interface data bus. Data terminals are used to

transfer data in and out of the register map and

compatible) palette/overlay RAM.

FS ADJUST

L12

I

Full-scale adjustment. A resistor connected between

FS ADJUST and ground controls the full-scale range

of the DACs.

GND

44, 54,

56, 80

J2, L10,

K10, G11

Ground. All GND terminals must be connected. The

GNDs are connected internally.

HSYNCOUT

46

48, 49, 50

63

H12

O

(TTL

Horizontal sync output after pipeline delay. For

system mode the horizontal-sync output can be

compatible) programmed, but for the VGA mode the output

carries the same polarity as the input.

IOR, IOG, IOB

J12, J11,

K12

O

Analog current outputs. These outputs can drive a

37.5-Ω load directly (doubly terminated 75-Ω line),

thus eliminating the requirement for any external

buffering.

MUXOUT [SENSE]

M7

O

(TTL

Multiplexer output control or DAC comparator output

signal. When MUXOUT is configured as a multi-

compatible) plexer output control, it is software programmable

through the configuration register. When the

multiplexer control register is set to VGA mode, this

output terminal and corresponding configuration

register bit are set low to indicate to external devices

that the VGA pass-through mode is being used.

Alternatively, SENSE can be configured as the DAC

comparator output. In this case, the SENSE is low

when one or more of the DAC output analog levels is

above the internal comparator reference of 350 mV

50 mV.

P(0–31)

1–29,

82–84

A10, B9, A9,

B8, A8, B7,

I

Pixel input port. The port can be used in various

modes as shown in the multiplexer control register.

(TTL

A7, B6, A6, compatible) All the unused terminals need to be tied to GND.

A5, B5, A4,

B4, A3, A2,

B3, B2, C3,

A1, C2, B1,

C1, D2, D1,

E2, E1, F1,

F2, G1, G2,

H1, H2

NOTE 1: All unused inputs should be tied to a logic level and not be allowed to float.

1–8

1.5 Terminal Functions (TVP3010C and TVP3010M) Continued

TERMINAL

I/O

DESCRIPTION

NAME

REF

NO. (FN)

NO. (GA)

53

M12

Voltage reference for DACs. An internal voltage reference

of nominally 1.235 V is provided, which requires an

external 0.1-µF ceramic capacitor between REF and

analog GND. However, the internal reference voltage can

be overdriven by an externally supplied reference voltage.

A typical connection is shown in Appendix A.

RD

31

B10

I

Read strobe inputs When cleared to 0, RD initiates a

read from the register map. Reads are performed

(TTL

compatible) asynchronously and are initiated on the low-going edge of

RD (see Figure 3–1).

RS(0–2)

32–34

35

A12, C10,

B11

I

Register-select inputs. The RS terminals specify the

location in the register map that is to be accessed (see

(TTL

compatible) Table 2–1).

RS3 [PSEL]

C11

I

Register-selectinputorport-selectinput. Whenconfigured

as the RS3 input, this terminal has no effect. When

(TTL

compatible) configured as the port-select input, RS3 [PSEL] allows the

creation of VGA or overlay windows in a direct-color

background on a pixel-by-pixel basis.

SCLK

79

62

K1

O

(TTL

Shift clock output. SCLK is selected as a division of the dot

clock input. The output signals are gated off during

compatible) blanking, although SCLK is still used internally to

synchronize with the activation of Blank.

SFLAG

M8

I

Split shift register transfer flag. The TVP3010 detects a

low-to-high transition on SFLAG during blanking

(TTL

a

compatible) sequenceandimmediatelygeneratesanSCLKpulse.This

early SCLK pulse replaces the first SCLK pulse in the

normal sequence.

SYSBL

60

M9

I

System blank input. SYSBL is active (low).

(TTL

compatible)

HSYNC,

VSYNC

58, 59

M10, L9

I

Horizontal and vertical sync inputs. These signals

generate the sync level on the green current output. They

(TTL

compatible) are active (low) inputs, but the HSYNCOUT and

VSYNCOUT outputs can be programmed through the

general control register.

VCLK

78

61

L1

L8

O

(TTL

compatible)

Video clock output. VCLK is the user-programmable

output for synchronization to the graphics processor.

VGABL

VGA(0–7)

I

VGA blank input. VGABL is active (low).

(TTL

capability)

65–72

M6, L6, M5,

L5, M4, L4,

M3, M2

I

VGA pass-through bus. These buses can be selected as

the pixel bus for VGA mode, but it does not allow for any

(TTL

capability) multiplexing.

NOTE 1: All unused inputs should be tied to a logic level and not be allowed to float.

1–9

1.5 Terminal Functions (TVP3010C and TVP3010M) Continued

TERMINAL

I/O

DESCRIPTION

NAME

NO. (FN)

NO. (GA)

VSYNCOUT

47

H11

O

(TTL

Vertical sync output after pipeline delay. For system

mode, the output can be programmed, but for the

capability) VGA mode the output carries the same polarity as

the input.

WR

30

64

A11

L7

I

Writestrobeinput. AlowonWRinitiatesawritetothe

register map. As with RD, write transfers are

(TTL

capability) asynchronous and initiated on the low-going edge of

WR, (see Figure 3–1).

8/6 [OVS]

I

DAC resolution selection or overscan input. The 8/6

terminal selects the data-bus width (8 or 6 bits) for

(TTL

capability) the DAC and is essentially provided in order to

maintain compatibility with the IMSG176. When 8/6

[OVS] is high, 8-bit bus transfers are used with D7

the MSB and D0 the LSB. For 6-bit bus operation,

while the color palette still has the 8-bit information,

D5 shifts to the bit 7 position with D0 shifted to the bit

2 position and the 2 LSBs are filled with zeros at the

output multiplexer to DAC. The palette-holding

register zeroes the two MSBs when it is read in the

6-bit mode. The terminal can also be configured to

function as the overscan input facilitating the

creation of custom screen borders. This terminal

defaults to 8/6 after reset.

NOTE 1: All unused inputs should be tied to a logic level and not be allowed to float.

1–10

2 Detailed Description

The TVP3010C and TVP3010M VIPs are identical in their operation. Both the TVP3010C and TVP3010M

are 32-bit devices; both devices are terminal compatible with the TLC34076 and each device offers

advanced features. To facilitate the enhanced functionality, some terminals have dual functions. The

dual-function terminals are controlled by the configuration register discussed in subsection 2.16.1. At reset,

all pins default to the TLC34076 terminal functions.

2.1 MPU Interface

The microprocessor unit (MPU) interface is controlled using read and write strobes (RD, WR), three

register-select terminals [RS(0–2)], and the 8/6-select terminal. The 8/6 pin selects between an 8- or

6-bit-wide data path to the color-palette RAM and is provided in order to maintain compatibility with the

IMSG176. Since the 8/6 [OVS] pin is a dual-function pin, 2 bits are provided in the configuration register to

control this function. Configuration-register bit 1 determines whether the 8/6 [OVS] pin operates as 8/6 or

OVS. If configuration register bit 1 is cleared to 0 (default), then 8/6 operation is controlled by the pin. With

8/6 held low, data on the lowest 6 bits of the data bus are internally shifted up by 2 bits to occupy the upper

6 bits at the output multiplexer and the bottom 2 bits are then cleared to 0. This operation is carried out in

order to utilize the maximum range of the DACs.

The direct register map is shown in Table 2–1. Extended registers can be accessed through the index

register. The index register map is shown in Table 2–2. In general, the index register must first be loaded

withthetargetaddressvalue. Successivereadsorwritesfromandtothedataregisterthenaccessthetarget

location. The MPU interface operates asynchronously, with data transfers being synchronized by internal

logic.

NOTE:

RS3 is a do not care for register addressing but is used as the PSEL input (see

Section 2.6).

Table 2–1. Direct Register Map

RS2

0

RS1

0

RS0

0

REGISTER ADDRESSED BY MPU

Palette Address Register – Write Mode

Color Palette Holding Register

Pixel Read Mask

R/W

DEFAULT (HEX)

XX

FF

XX

0

1

0

1

0

1

Palette Address Register – Read Mode

Reserved

1

0

1

0

1

Reserved

1

0

Index Register

R/W

1

Data Register

2–1

Table 2–2. Indirect Register Map (Extended Registers)

INDEX REGISTER

(HEX)

DEFAULT

(HEX)

REGISTER ADDRESSED

BY INDEX REGISTER

R/W

00

01

R/W

00

1F

00

Cursor Position X LSB

Cursor Position X MSB

Cursor Position Y LSB

Cursor Position Y MSB

Sprite Origin X

02

03

04

05

Sprite Origin Y

06

Cursor Control Register

Reserved

07

08

W

XX

Cursor RAM Address LSB

Cursor RAM Address MSB

Cursor RAM Data

09

0A

0B

0C–0F

10

R/W

Reserved

Reserved-Undefined

Window Start X LSB

Window Start X MSB

Window Stop X LSB

Window Stop X MSB

Window Start Y LSB

Window Start Y MSB

Window Stop Y LSB

Window Stop Y MSB

Multiplexer Control Register 1

Multiplexer Control Register 2

Input-Clock Selection Register

Output-Clock Selection Register

Palette Page Register

General Control Register

Configuration Register

Reserved-Undefined

Overscan Color Red

Overscan Color Green

R/W

XX

80

11

12

13

14

15

16

17

18

19

98

1A

1B

1C

1D

1E

1F

20

00

3E

00

20

00

R/W

XX

21

NOTE 1: Reservedregistersshouldbeavoided;otherwise, circuitbehaviorcoulddeviate

from that specified. Reserved-undefined registers are nonexistent locations on

the register map.

2–2

Table 2–2. Indirect Register Map (Extended Registers) (Continued)

INDEX REGISTER

(HEX)

DEFAULT

(HEX)

REGISTER ADDRESSED

BY INDEX REGISTER

R/W

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

FF

R/W

XX

09

Overscan Color Blue

Cursor Color 0, Red

Cursor Color 0, Green

Cursor Color 0, Blue

Cursor Color 1, Red

Cursor Color 1, Green

Cursor Color 1, Blue

Auxiliary-Control Register

Reserved

R/W

XX

10

Color-Key OL/VGA Low

Color-Key OL/VGA High

Color-Key Red Low

Color-Key Red High

Color-Key Green Low

Color-Key Green High

Color-Key Blue Low

Color-Key Blue High

Color-Key Control Register

Reserved-Undefined

Sense-Test Register

Test-Data Register

CRC LSB

R/W

R

00

XX

10

R

CRC MSB

W

R

CRC Control Register

ID Register

W

XX

Reset Register

NOTE 1: Reservedregisters should be avoided; otherwise, circuit behavior could deviate

from that specified. Reserved-undefined registers are nonexistent locations on

the register map.

2–3

2.2 Color Palette

The color palette is addressed by an internal 8-bit address register for reading/writing data from/to the RAM.

This register is automatically incremented following a RAM transfer, allowing the entire palette to be

read/written with only one access of the address register. When the address register increments beyond

the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM

are asynchronous to SCLK, VCLK, and dot clock but performed within one dot clock. Therefore, they do not

cause any noticeable disturbance on the display.

The color RAM is 24 bits wide for each location and 8 bits wide for each color. Since the MPU access is

8 bits wide, the color data stored in the palette is 8 bits even when the 6-bit mode is chosen

(8/6 = 0). If the 6-bit mode is chosen, the 2 MSBs of color data in the palette have the values previously

written. However, if they are read back in the 6-bit mode, the 2 MSBs are 0s to be compatible with IMSG176

and Bt176. The output multiplexer shifts the six LSB to the six MSB positions and fills the 2 LSBs with 0s

after the color palette. The multiplexer then feeds the data to the DAC. The test register and the CRC

calculation both take data after the output multiplexer, enabling total system verification. The color-palette

access is described in the following two sections, and it is fully compatible with IMSG176/8 and Bt476/8.

2.2.1

Writing to Color-Palette RAM

Toloadthecolorpalette, theMPUmustfirstwritetotheaddressregister(writemode)withtheaddresswhere

the modification is to start. This is then followed by three successive writes to the palette-holding register

with 8 bits of red, green, and blue data. After the blue write cycle, the three bytes of color data are

concatenated into a 24-bit word that is then written to the RAM location specified by the address register.

The address register then increments to the next location, which the MPU may modify by simply writing

another sequence of red, green, and blue data. A block of color values in consecutive locations may be

written to by writing the start address and performing continuous red, green, and blue write cycles until the

entire block has been written.

2.2.2

Reading From Color-Palette RAM

Reading from the palette is performed by writing to the address register (read mode) with the location to be

read. This then initiates a transfer from the palette RAM into the holding register, followed by an increment

of the address register. Three successive MPU reads from the holding register produce red, green, and blue

color data (6 or 8 bits depending on the 8/6 mode) for the specified location. Following the blue read-cycle,

the contents of the color-palette RAM at the address specified by the address register are copied into the

holding register and the address register is again incremented. As with writing to the palette, a block of color

values in consecutive locations may be read by writing the start address and performing continuous red,

green, and blue read-cycles until the entire block has been read. Since the color-palette RAM is dual ported,

the RAM may be read during active display without disturbing the video.

2.2.3

Palette Page Register

The palette page register appears as an 8-bit register on the extended register map (see Section 2.1). Its

purpose is to provide high-speed color changing by removing the need for palette reloading. When using

1, 2, or 4 bit-planes, the additional planes are provided from the page register. When using four bit-planes,

the pixel inputs specify the lower 4 bits of the palette address with the upper 4 bits specified from the page

register. This gives the user the capability of selecting from 16 palette pages with only one-chip access, thus

allowing all the screen colors to be changed at the line frequency. A bit-to-bit correspondence is used;

therefore, in the above configuration, page-register bits 7 through 4 map onto palette-address bits 7 through

4, respectively. This is illustrated in Table 2–3.

2–4

NOTE:

The additional bits from the page register are inserted after the read mask.

The palette page register specifies the additional bit-planes for the overlay field in

direct-color modes with less than 8 bits per pixel overlay.

Table 2–3. Allocation of Palette Page Register Bits

NUMBER OF BIT PLANES

MSB

PALETTE-ADDRESS BITS

LSB

M

†

M

8

4

2

1

M

‡

P7

P6

P5

P4

M

P7

P3

P2

M

P1

M

†

‡

M = bit from pixel port

Pn = n bit from page register

2.2.4

Read Masking

The read-mask register is an 8-bit register used to enable or disable a bit-plane from addressing the

color-palette RAM in the pseudo-color modes. Each palette address bit is logically ANDed with the

corresponding bit from the read mask register before going to the palette page register and addressing the

palette RAM.

In order to provide maximum flexibility to control palette data, the read mask operation is performed before

the addition of the page register bits. Therefore, care must be taken in those modes that have less than 8

bits per pixel of pseudo-color or overlay data. Be aware of the palette page register settings in these modes.

2.3 Clock Selection and Output-Clock (SCLK, RCLK, and VCLK) Generation

The TVP3010C and the TVP3010M VIP provide a maximum of five clock inputs. CLK0 is dedicated as a

TTL input. The other four clock inputs can be selected as either two differential ECL input or two extra TTL

inputs. The TTL inputs can be used for video rates up to 140 MHz. The dual-mode clock input (ECL/TTL)

is primarily an ECL input but can be used as TTL-compatible inputs if the input-clock selection register is

so programmed. The clock source used at power up is CLK0; an alternative source can be selected by

software during normal operation. This chosen clock input can be used unmodified as the dot clock

(representing pixel rate to the monitor). Alternatively, when the input-clock selection register is programmed

tousetheinternalfrequency-doubler, thechosenclocksourceisusedasareferenceformultiplication. Each

device also allows for user programming of RCLK, SCLK and VCLK outputs (reference, shift and video

clocks) by using the output-clock selection register. The input-clock and output-clock selection registers are

located in the indirect register map (see Table 2–2).

The ECL inputs can be used as differential or single-ended inputs. When CLK1 or CLK3 is used as a

single-ended ECL input, CLK2 or CLK4 needs to be externally terminated to set the input common-mode

signal level. This can be done with a simple resistor divider, as is the case with fully differential ECL. Care

needs to be taken when choosing the resistor values to ensure that the dc level on CLK2 or CLK4 is in the

middle of the CLK1 or CLK3 ECL-input signal range.

2.3.1

RCLK, SCLK, VCLK

Both VIP devices provide a user-programmable reference clock (RCLK), a shift clock (SCLK), and video

(VCLK) clock outputs that can be set as divisions of the dot clock. RCLK is a continuously-running reference

clock and is not disabled during the Blank signal. RCLK can be selected as divisions of 1, 2, 4, 8, 16, 32 or

64 of the

2–5

dot clock (see Table 2–4). It is provided as a clock reference and is typically connected back to the LCLK

inputtolatchpixel-portdata. Sincepixel-portdataislatchedontherisingedgeofLCLK, theRCLKfrequency

must be set as a function of the desired multiplexing ratio (that depends on the pixel-bus width and number

of bit-planes, see Section 2.4).

Table 2–4. Output-Clock Selection Register Format

OUTPUT-CLOCK SELECTION-REGISTER BITS (see Note 2)

FUNCTION (see Notes 2, 3, 4, and 5)

6

5

0

1

x

1

4

0

1

0

1

x

1

3

0

1

0

1

0

1

0

1

x

1

2

x

0

1

x

0

1

0

1

0

x

0

1

0

1

0

1

0

1

VCLK/1 output ratio

VCLK/2 output ratio

VCLK/4 output ration

VCLK/8 output ratio

VCLK/16 output ratio

VCLK/32 output ratio

VCLK/64 output ratio

VCLK output held at logic 1

†

RCLK/1 output ratio (see Notes 2 and 5)

RCLK/2 output ratio (see Notes 2 and 5)

RCLK/4 output ratio (see Notes 2 and 5)

RCLK/8 output ratio (see Notes 2 and 5)

RCLK/16 output ratio (see Notes 2 and 5)

RCLK/32 output ratio (see Notes 2 and 5)

RCLK/64 output ratio (see Notes 2 and 5)

†

0

x

RCLK/64, SCLK output held at logic 0

RCLK, SCLK outputs held at logic 0

Clock counter reset (6)

†

These lines indicate the reset conditions as required for VGA pass-through.

NOTES: 2. Register bit 6 enables (1) and disables (default = 0) the SCLK output buffer. Register bit 7 is a don’t

care bit.

3. When the clocks are selected from one mode to the other, a minimum of 30 ns is needed before

the new clocks are stabilized and running.

4. When the output-clock-selection register is written with 3F (hex), the clock counter is reset,

RCLK = SCLK = 0, and VCLK = 1.

5. SCLK is the same as RCLK except that it is disabled during blank. When the RCLK divide ratio is

chosen, this sets the SCLK ratio as well.

SCLK is the same as RCLK but disabled during the Blank active period. SCLK is designed to be used as

the shift clock to interface directly with the VRAM. If SCLK is not used, the output can be switched off and

held low to protect against VRAM lockup due to invalid SCLK frequencies. The detailed SCLK control timing

is discussed in subsection 2.3.2.

VCLK is designed to be used as the timing reference by the graphics processor or other custom-designed

control logic to generate the graphics system control signals (SYSBL, HSYNC, and VSYNC). VCLK can be

selected as divisions of 1, 2, 4, 8, 16, 32, or 64 of the dot clock and can also be held at high (see Table 2–4).

The default setup is VCLK held at high since it is not used in VGA pass-through mode. Since these control

signals are sampled by VCLK, VCLK must be enabled for these to function properly.

Even though RCLK/SCLK and VCLK can be selected independently, there is still a relationship between

the two as discussed below. Many system considerations have been carefully covered in their design,

leaving maximum freedom to the user.

2–6

Internally, RCLK, SCLK, and VCLK are generated from a common clock counter that is counted at the rising

edge of the dot clock. Therefore, when VCLK is enabled, it is naturally in phase with RCLK and SCLK as

shown in Figure 2–1.

Normally, the video-control signal inputs HSYNC, VSYNC, and SYSBL are latched on the falling edge of

VCLKwheninanon-VGAmode. WhentheconfigurationregisterisprogrammedforoppositeVCLKpolarity,

these video-control signals are latched on the rising edge of VCLK.

The internal clock counter is initialized any time the output-clock selection register is written with 3F (hex).

This provides a simple mechanism to synchronize multiple palettes or system devices by providing a known

phase relationship for the various system clocks. It is left up to the user to provide some means of disabling

the dot-clock input to the part while this reset is occurring if multiple parts are to be synchronized.

The reset default divide ratio for RCLK is 64:1 with SCLK held low and VCLK held at high. When choosing

certain video timing parameters, exercise caution if the selected RCLK frequency is less than the selected

VCLK frequency (see Appendix B for a more detailed discussion).

Dot Clock

VCLK

(dot clock/4 as an example)

RCLK = SCLK

(dot clock/2 as an example)

Figure 2–1. Dot Clock/VCLK/RCLK/SCLK Relationship

The input-clock-selection register selects the desired input-clock source. Table 2–5 details how to program

the various options.

Table 2–5. Input-Clock Selection Register

INPUT-CLOCK-SELECT REGISTER

FUNCTION (see Note 7)

(HEX) (see Note 6)

†

00

01

02

03

04

06

07

10

11

12

13

14

16

17

Select CLK0 as TTL-clock source

Select CLK1 as TTL-clock source

Select CLK2 as TTL-clock source

Select CLK3 as TTL-clock source

Select CLK4 as TTL-clock source

Select CLK3/CLK4 as ECL-clock source up to 140 MHz

Select CLK1/CLK2 as ECL-clock source up to device limit

Select CLK0 as doubled TTL-clock source

Select CLK1 as doubled TTL-clock source

Select CLK2 as doubled TTL-clock source

Select CLK3 as doubled TTL-clock source

Select CLK4 as doubled TTL-clock source

Select CLK3/CLK4 as doubled ECL-clock source

Select CLK1/CLK2 as doubled ECL-clock source

†

CLK0 is chosen at reset as required for VGA pass-through.

NOTES: 6. Register bits 3 and 7 are don’t-care bits.

7. Register bits 5 and 6 are reserved.

8. Whentheclocksareselectedfromoneinputclocksourcetoanother, aminimumof30nsisneededbefore

the new clocks are stabilized and running.

2–7

The output-clock-selection register is used to program the desired divided-down frequencies for the

reference/shift and video clocks.

2.3.2

Frame-Buffer Clocking: Self-Clocked or Externally Clocked

The TVP3010C and the TVP3010M have two pixel-data latching modes, allowing for flexibility in the

frame-buffer interface timing. For the pixel port P(0–31), data is always latched on the rising edge of LCLK.

If auxiliary-control register (ACR) bit 3 is set to 1 (default), the internal circuitry is configured for self-clocked

mode. In this mode, the RCLK or SCLK output of the palette must be used as the timing reference to present

data to the pixel port P(0–31). In self-clocked mode, RCLK can be directly tied back to LCLK or LCLK can

be a delayed version of RCLK within the timing requirements of the VIP. The self-clocked mode of

frame-buffer latching is similar to the operation of the TLC3407X video-interface palette devices.

The VIP internal Blank signal is generated from either VGABL or SYSBL, depending on whether the VGA

port is enabled (multiplexer control register 2 (MCR2) bit 7 = 1) or disabled (MCR2 bit 7 = 0). The rising edge

of CLK0 latches VGABL when the VGA port is enabled. The falling edge of VCLK is used to sample and

latch the SYSBL input when the VGA port is disabled. When the internal Blank signal becomes active, SCLK

is disabled as soon as possible. For example, if SCLK is high when the sampled SYSBL goes low, SCLK

is allowed to complete the clock cycle and return to the low state. SCLK then is held low until the sampled

SYSBL signal goes back high. At this time, SCLK is enabled to clock the first pixel data valid from VRAM.

The VIP video-blanking circuitry is designed with sufficient pipeline delay to allow the internal sampled

SYSBL and VGABL signals to align with the pipelined RGB data to the video DACs. The logic described

previously works in situations where the SCLK period is shorter than, equal to, or longer than the VCLK

period.

When in the self-clocked mode, the SCLK control timing is designed to interface directly with the external

VRAM. The shift register in the system VRAM is supposed to be updated during the blank active period.

WhentheSYSBLinputissampledhighbythefallingedgeofVCLK, theVRAMshiftclock(SCLK)isrestarted

to clock the VRAM and enable the first group of pixel data to appear on the pixel bus as well as at the

TVP3010 pixel input port. The second SCLK causes the VRAM shift register to shift out the second group

of data. At the same time, LCLK latches the first group of pixel data into the VIP (see Figure 2–2 for a detailed

timing-diagram).

VCLK

In Phase

SYSBL

at Input Terminal

Latch Last Group

of Pixel Data

Latch First Group of Pixel Data

Latch Last Group

of Pixel Data

LD

Internal Delayed

LCLK = RCLK

Blank

(internal signal

before dot-clock

pipeline delay)

1st

2nd

3rd

4th

5th

Group Group Group Group Group

Pixel Data

at Input Terminal

6th

Group

Last Group of Pixel Data

SCLK

Figure 2–2. SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = VCLK Frequency)

The RCLK/SCLK phase relationship is designed so that timing specifications are satisfied for the case

where SCLK is driving a typical 2-MB VRAM load and RCLK is connected to LCLK. If an external buffer is

2–8

required on SCLK so that it can drive a larger load, a similar buffer can be placed on RCLK to match the

signal delay before connecting to LCLK. However, the delay from LCLK to RCLK cannot exceed one RCLK

period –7 ns, (see the timing-parameter specifications for more details).

When the VRAM split shift register operation is performed (see Figure 2–3 and Figure 2–4), the SCLK timing

is adjusted to work with the SFLAG input. Basically, the split shift register operation inserts an SCLK during

the blank period. This causes the first group of pixel data to appear at the pixel port during blank and allows

the first group of data to be displayed as soon as the palette comes out of blank. Figures 2–3 and 2–5 show

the case when the SSRT (split shift register transfer) function is enabled. When a rising edge occurs on the

SFLAG input, one SCLK with a minimum 15-ns pulse duration is generated after the specified delay. Since

this is designed to meet VRAM timing requirements, the SSRT-generated SCLK replaces the first SCLK in

the regular shift register transfer case as described above (see Section 2.15 for a detailed explanation of

the SSRT function).

VCLK

In Phase

SYSBL

at Input Terminal

SFLAG Input

Latch Last Group

of Pixel Data

Latch First Group of Pixel Data

Latch Last Group

of Pixel Data

LD

Internal Delayed

LCLK = RCLK

Blank

(internal signal

before dot-clock

pipeline delay)

Pixel Data

at Input Terminal

Last

Group

1st Group of

Pixel Data

2nd

3rd

4th

5th

6th

Group

Group Group Group Group

SCLK Between Split Shift-Register and Regular Shift-Register Transfer

SCLK

Figure 2–3. SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency)

2–9

VCLK

In Phase

SYSBL

at Input Terminal

Latch Last Group

of Pixel Data

LD

Internal Delayed

LCLK = RCLK

Latch first Group of Pixel Data

Blank

(internal signal

before dot-clock

pipeline delay)

Pixel Data

at Input Terminal

1st

2nd

3rd

4th

5th

6th

7th

Group

Last Group of Pixel Data

Group Group Group Group Group Group

SCLK

Figure 2–4. SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)

VCLK

In Phase

SYSBL

at Input Terminal

SFLAG Input

Latch Last Group

of Pixel Data

Latch Second Group

of Pixel Data

LD

Internal Delayed

LCLK = RCLK

Latch First Group of Pixel Data

Blank

(internal signal

before dot-clock

pipeline delay)

Pixel Data

at Input Terminal

5th

Group

2nd

3rd

4th

6th

Group

7th

Group

Last

Group

First Group of Pixel Data

Group Group Group

SCLK Between Split Shift-Register Transfer and Regular Shift-Register Transfer

SCLK

Figure 2–5. SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)

2–10

Externally clocked timing can be chosen for the pixel bus P(10–31) by clearing auxiliary control register bit 3

to 0. In externally clocked mode, the RCLK or SCLK output of the palette is not used as the timing reference

to present data to the pixel bus. Instead, pixel data is presented to the palette with a synchronous clock and

all palette timing is referenced to this clock. In this mode, the external clock should be connected to LCLK

and the selected clock input. (When the VGA port is enabled, the CLK0 input is selected independent of the

input-clock selection register.)

The externally clocked frame-buffer interface mode is intended for applications where windowed or

pixel-by-pixel switching between the VGA port and the pixel port is desired in non-VRAM-based graphics

systems. In such applications, the VGA port is enabled (multiplexer control register bit 7 set to 1) and the

appropriate direct-color mode is set in the multiplexer control register. The auxiliary-window, port-select,

and/or color-key switching functions are then configured and enabled to perform the desired switching. By

setting the frame-buffer interface to the externally clocked mode, the pixel port and VGA port timing and

pipeline delay are made the same. Also, since the VGA port is enabled, all video-control signal timing is

referenced to CLK0, utilizing the VGABL, HSYNC, and VSYNC inputs.

The externally clocked frame-buffer interface timing can also be used in non-VGA switching applications,

utilizing only the pixel port or only the VGA port. In either case, it is recommended that VGA video-control

signals be used (i.e., VGABL, HSYNC, VSYNC). In this way, all pixel data and video-control signals are

referenced to CLK0 and video blank and sync are aligned with pixel data.

NOTE:

When the pixel port is used in externally clocked mode (ACR3 = 0), RCLK must be

set to VCLK/1 (DOT/1) in the output-clock selection register and a 1:1 multiplexing

mode must be selected in the multiplexer control registers (see Table 2–6). The

external clock should be connected to the LCLK input as well as the selected clock

input. When the VGA port is also enabled (MCRB7 = 1), CLK0 is selected as the

input clock independent of the input-clock selection-register setting.

VGA switching can only be performed using a 1:1 multiplexing mode.

Overlay switching can only be performed using a 1:1 multiplexing mode when the

pixel port is set for externally clocked mode. When the pixel port is self-clocked, any

of the multiplex ratios may be used (see subsection 2.4.6).

When VGA switching is to be performed using externally clocked mode

(ACR3 = 0), the full VGA port frequency of 85 MHz may be utilized provided that

the VGA port and the pixel port are both synchronized to the CLK0 input clock.

If VGA switching is to be performed using self-clocked mode (ACR3 = 1), the

maximum pixel rate cannot exceed 50 MHz. This is because of internal delay from

the CLK0 input to the RCLK output. For external clocked timing, the LCLK input

needs to be enabled on terminal 73 (TVP3010C) or terminal L3 (TVP3010M) by

programming the configuration register bit 5 to 1.

VGA-data pipeline delay is adjusted within each VIP depending on whether self-

or externally clocked frame-buffer interface timing is used (see subsection 2.3.2 ).

If the VIP is programmed for self-clocked timing, three additional dot-clock pipeline

delays are inserted into the internal VGA-data path and into the internal blanking

signal. The additional pipeline delay accounts for the difference between VGABL

or SYSBL and the pixel-data inputs P(0–31) when used in the self- and externally

clocked modes. This is so the VGA and pixel-port data remain synchronous in time

when doing auxiliary window, port select, or color-keyed switching (see Section

2.6). When externally clocked timing is used, the VGA port and the pixel port are

already synchronous since both data and blanking are presented to the palette

during the same CLK0 clock cycle.

2–11

2.4 Multiplexing Scheme

Both the TVP3010C and TVP3010M palettes offer a highly versatile multiplexing scheme as illustrated in

Tables 2–6 through 2–11. The multiplexing scheme allows the pixel bus to be programmed to 1, 2, 4, 8, 12,

16, 24, or 32 bits/pixel with pixel-bus widths ranging from 1 bit to 32 bits. The use of on-chip multiplexing

allows graphics systems to be designed that can support multiple-pixel depths and resolutions with no

hardware modification. It also allows the system to be configured to the amount of RAM available. For

example, when only 256K bytes of memory are available, an 800 × 600 mode with four bit-planes (4 bits

perpixel)couldbeimplementedusingan8-bit-widepixelbus. Ifatalaterdateanother256Kbytesareadded

to another 8 bits of the pixel bus, the user has the option of using eight bit-planes at the same resolution or

four bit-planes at a 1024 × 768 resolution. When a further 512K bytes are added to the remaining 16 bits

of the pixel bus, the user has the option of eight bit-planes at 1024 × 768 or four bit-planes at 1280 × 1024.

Each VIP can also be configured for direct-color or true-color operation. All of the above can be achieved

without any board-level hardware modification and without any increase in the speed of the pixel bus.

Multiplexing of the pixel bus is controlled by and programmed through multiplexer control registers 1 and

2. For details of the multiplexer control register settings for each mode of operation, (see subsections 2.4.2

through 2.4.6).

2.4.1

Little-Endian and Big-Endian Data Format

The pixel bus on both the TVP3010C and TVP3010M supports both little-endian and big-endian data

formats for all pseudo-color, direct-color, and true-color modes of operation. The data-format select is

controlled by general control register-bit 3 (see subsection 2.16.2). When general control register (GCR)

bit 3 is cleared to 0 (default), then the format is set to little endian. When GCR bit 3 is set to 1, then the format

is set to big endian.

In a big-endian design, the external VRAM data-bus bits must be connected in reverse order to the VIP pixel

bus; i.e., D31 connected to P0, D0 connected to P31, etc. This ensures that the least-significant channel

always provides the first pixel to be displayed in the pseudo-color or true-color multiplexing modes. The

difference between little- and big-endian data formats and how they affect the pixel-bus operation is

discussed in detail in Appendix C.

2.4.2

VGA Pass-Through Mode

The TVP3010C and TVP3010M feature VGA pass-through mode.The VGA pass-through mode is used to

emulate the VGA modes of most personal computers. The advantage of this mode is that it can take data

presented on the feature connector of most VGA-compatible PC systems into the device on a separate bus,

thus requiring no external multiplexing. This feature is particularly useful in systems where the existing

graphics circuitry is on the motherboard. In this instance, it enables a drop-in graphics card to be

implemented that maintains compatibility with all existing software. This is accomplished by using the

on-board VGA circuitry but routing the emerging bit-plane data through the VIP. VGA pass-through is the

default mode at power up or reset.

Since this mode is designed with the feature connector philosophy, all data latching and control timing is

referenced to CLK0. When the VGA port is enabled (MCR2 bit 7 = 1), CLK0 is selected as the input clock

source independent of the input-clock-selection register. The VGA port always operates as in the externally

clocked mode of the pixel port P(0–31); it receives the VGA data [VGA(0–7)] and the VGA blank (VGABL),

both of which are referenced to an external clock (CLK0). CLK0 also latches the VGABL, HSYNC, and

VSYNC video-controlsignalswhenintheVGApass-throughmode. ExternalsignalsonLCLKhavenoeffect

on the VGA port since LCLK only latches data on the pixel port P(0–31).

VGA data pipeline delay is adjusted within the VIP depending on whether self- or externally clocked

frame-buffer interface timing is used (see subsection 2.3.2). When either device is programmed for

self-clocked timing, additional dot-clock pipeline delay is inserted into the internal VGA data path; this

permits the VGA and pixel-port data to remain synchronous when doing auxiliary window, port select, or

color-keyed switching (see Section 2.6). The additional VGA-pipeline delay accounts for the dot-

clock-to-RCLK pipeline delay within the palette.

2–12

2.4.3

Pseudo-Color Mode

In pseudo-color mode (sometimes called color indexing), the TVP3010C and TVP3010M pixel-bus inputs

are used to address the palette-RAM LUT (color-lookup table). The data in each RAM location is comprised

of 24 bits (8 bits for each of the red, green, and blue color DACs). The pseudo-color mode is further grouped

into 4 submodes, depending on the data bits per pixel. In each submode, a pixel bus width of 4, 8, 16, or

32 bits may be used. Data should always be presented on the least significant bits of the pixel bus; i.e., when

16 bits are used, the pixel data must be presented on P(15–0), 8 bits on P(7–0), and 4 bits on P(3–0) (see

subsection 2.4.6 for more details).

Submode1 uses a single bit-plane to address the color palette. The pixel port bit is fed into bit 0 of the palette

address, with the 7 high-order address bits defined by the palette page register (see subsection 2.2.3). This

mode has uses in high-resolution monochrome applications such as desktop publishing. This mode allows

the maximum amount of multiplexing with 32:1 ratio, thus giving a pixel bus rate of only 4 MHz at a screen

resolution of 1280 × 1024. Although only a single bit is used, alteration of the palette page register at the

line frequency allows 256 different colors to be displayed on each screen with two colors for each line.

Submode 2 uses two bit-planes to address the color palette. The 2 bits are fed into the low-order address

bits of the palette with the six high-order address bits being defined by the palette page register (see

subsection 2.2.3). This mode allows a maximum multiplex ratio of 16:1 on the pixel bus and is essentially

a four-color alternative to submode 1.

Submode 3 uses four bit-planes to address the color palette. The 4 bits are fed into the low-order address

bits of the palette with the four high-order address bits being defined by the palette page register (see

subsection 2.2.3). This mode provides 16 pages of 16 colors and can be used at multiplex ratios of /1 to /8.

Submode 4 uses 8 bit-planes to address the color palette. Since all 8 bits of palette address are specified

fromthepixelport, thepageregisterisnotused. Thismodeallowsdotclock-to-LCLKratiosof1:1(8-bitbus),

2:1 (16-bit bus), or 4:1 (32-bit bus). Therefore, in a 32-bit configuration, a 1024 × 768 pixel screen can be

implemented with an external data rate of only 16 MHz.

NOTE:

When externally clocked frame-buffer timing is used (ACR3 = 0, see subsection

2.3.2), only multiplex ratios of 1:1 can be used (see subsection 2.4.6).

The auxiliary-window, port-select, and color-key switching functions must be

disabled and set for palette graphics when in the pseudo-color mode. This is the

default condition at reset (see Section 2.6).

2.4.4

Direct-Color Mode

When either VIP is operated in direct-color mode, 24, 16, 15, or 12 bits of data can be transferred directly

to the RGB DACs but with the same amount of pipeline delay as the overlay data and the control signals

(Blank and Syncs). Depending on which direct-color mode is selected, overlay is provided by utilizing the

remaining bits of the pixel bus to address the palette RAM. This results in a 24-bit RAM output that is then

used as overlay information to the DACs. The overlay capability is designed to work with the

auxiliary-window, port-select, and color-key switching functions to provide overlay in specific windows or

on a pixel-by-pixel basis on the direct-color display as discussed in Section 2.6 (see subsection 2.4.6 for

more details on selecting the direct-color modes).

The default condition after reset is for the auxiliary-window and port-select functions to be disabled

(ACR1 = ACR2 = 0). The color-key comparisons, which are controlled by the color-key control (CKC)

register bits 0–3, are also disabled (CKC0 = CKC1 = CKC2 = CKC3 = 0). Also, since multiplexer control

register 2 bit 7 = 1 and ACR0 = CKC4 = 1 at reset, the default is for VGA pass-through. This is because

multiplexer control register 2 bit 7 enables the VGA port and the switching functions (switch = color key =

1, see Section 2.6) are disabled and set for palette graphics as opposed to direct-color palette bypass.

Submode 1 is the 24-bit direct-color mode that uses 8 bits to represent each color and 8 bits for overlay. In

this mode, there are basically two different configurations: the 32-bit data is grouped either as overlay, red,

green, blue, or blue, green, red, overlay.

2–13

Submode 2 is the XGA-compatible (5–6–5) 16-bit color mode supporting 5 bits of red, 6 bits of green, and

5 bits of blue data. Both VIPs support multiplex ratios for this mode of 1:1 and 2:1. With 2:1 multiplexing,

the TVP3010 can display 1024x768 direct color using 45-MHz VRAM without any glue logic. Overlay is not

available in this mode.

Submode3 is the TARGA-compatible (5–5–5) mode that uses 15 bits for color and 1 bit for overlay. It allows

5 bits for each of red, green, and blue data. The TVP3010C and the TVP3010M support 1:1 and 2:1

multiplexing ratios in this mode.

Submode 4 is (6–6–4) configuration. It provides 6 bits of red, 6 bits of green, and 4 bits of blue. Both VIPs

also support 1:1 and 2:1 multiplexing in this mode. Overlay is not available in this mode.

Submode 5 is (4–4–4–4) configuration. It provides 12 bits of direct color and 4 bits of overlay. It allows 4

bits for each of red, green, and blue data. The TVP3010C and the TVP3010M support 1:1 and 2:1

multiplexing ratios in this mode (see NOTE in subsection 2.4.5).

2.4.5

True-Color Mode

In true-color mode, the palette RAM is partitioned into three independent 256-word × 8-bit memory blocks

thatcanbeindividuallyaddressedbyeachcolorfieldofthetrue-colordata. Theindependentmemoryblocks

provide data for a single DAC output. With this architecture, gamma correction for each color is possible.

Since the palette is used in true-color mode, there is no memory space to be used for the overlay function.

All of the true-color submodes are the same as direct color except that overlay is not available. (see

Tables 2–6 through 2–11 for more details on mode selection and see NOTE below).

NOTE:

Since less than 8 bits are defined for each color in the various 12- or 16-bit direct-

or true-color modes, the data bits for the individual colors are internally shifted to

the MSB locations and the remaining LSB locations for each color are set 0 before

8-bit data is sent to the DACs.

Since the overlay information goes through the pseudo-color data path, it is subject

to read masking and the palette page register. This is especially important for those

direct-color modes that have less than eight bits of overlay information. The overlay

information in these modes justifies to the LSB bit positions, and the remaining

MSB positions are filled with the corresponding palette page data before

addressing the palette RAM.

In order to display true color (gamma corrected through the palette), either the

auxiliary windowing or the color-key switching function must be set for palette

graphics. For direct color, both functions must be set for direct color.

In order to use the overlay capability of the direct-color modes, the color-key

switchingorport-selectfunctionmustbeconfiguredandenabled. Overlayportdata

in a window is also available by enabling the auxiliary window function. If either the

auxiliary windowing or the color-key switching functions point to palette graphics,

palette graphics are always displayed (not direct color).

When in the 24-bit direct-color or true-color modes, the data input works only in the

8-bit mode. In other words, when only 6 bits are used, the two LSB inputs for each

color need to be tied to GND. However, the palette, which is used by the overlay

input, is still governed by 8/6, and the output multiplexer selects 8 bits or 6 bits of

data accordingly. The 8/6 is also valid in the other 16-bit modes.

The definitions of direct color (palette bypass) and true color are consistent with the

IBM XGA terminology.

2–14

Table 2–6. Multiplex Mode and Bus-Width Selection

DATA

BITS

PER

PIXEL

(see

Note 9)

MULTI-

MULTIPLEX- MULTIPLEX-

CONTROL CONTROL

REGISTER 1 REGISTER 2

OVERLAY

BITS

TABLE

REFERENCE

(see

PIXEL-

BUS

WIDTH

PLEX

RATIO

(see

SUB-

MODE

PER

(HEX)

PIXEL

Note 11)

Note 10)

VGA

80

98

00

01

02

03

08

09

0A

0B

10

11

12

13

19

1A

1B

8

1

2

4

8

4

1

4

NA

v1

s1

8

s2

1

2

16

32

4

16

32

2

s3

s4

s6

8

4

s7

16

32

4

8

s8

Pseudo

Color

16

1

s9

s11

s12

s13

s14

s16

s17

s18

8

2

3

4

16

32

8

4

8

1

16

32

2

4

NOTES: 9. Data bits per pixel is the number of bits of pixel-port information used as color data for each displayed pixel,

often referred to as the number of bit-planes.

10. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each

LCLK (load clock) pulse. For example, with a 32-bit pixel-bus width and eight bit-planes, each bus load

consists of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from

RCLK. Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The

RCLK divide ratio is not automatically set by mode selection but must be programmed in the output-clock

selection register by the user.

11. This column is a reference to Tables 2–7 through 2–11, where the actual manipulation of pixel information

and pixel latching sequences are illustrated for each of the multiplexing modes.

12. It is recommended that all unused input terminals be connected to ground to conserve power.

13. Multiplexer control register 2 bit 7 enables (1) and disables (0) the VGA port. When auxiliary-window or

port-select switching is to be done involving the VGA port, this bit needs to be set to 1 as well as

programming for the correct direct-color mode. For example, when auxiliary windowing is to be done with

direct-color submode 1 (32-bit pixel bus) and VGA, instead of programming 1B (hex), multiplexer control

register 2 should be programmed to 9B (hex). When only VGA pass-through is desired, the values should

be programmed for VGA mode as indicated in Table 2–6. When only VGA pass-through is desired, the

values should be programmed as indicated in Table 2–6 for VGA mode.

2–15

Table 2–6. Multiplex Mode and Bus-Width Selection (Continued)

DATA

BITS

PER

PIXEL

(see

Note 9)

MULTI-

MULTIPLEX- MULTIPLEX-

CONTROL CONTROL

REGISTER 1 REGISTER 2

OVERLAY

BITS

TABLE

REFERENCE

(see

PIXEL-

BUS

WIDTH

PLEX

RATIO

(see

SUB-

MODE

PER

(HEX)

PIXEL

Note 11)

Note 10)

06

07

05

1B

02

24

16

32

16

1

8

d1

d3

d5

1

24-bit

NA

2

(5–6–5)

XGA

05

04

03

01

03

02

03

02

03

12

13

16

15

16

12

32

16

32

16

32

16

32

2

1

2

1

2

1

2

NA

1

d6

d8

3

(5–5–5)

TARGA

Direct

1

d9

NA

4

d11

d12

d14

d15

4

16-bit

(6–6–4)

5

12-bit

(4–4–4)

4

NOTES: 9. Data bits per pixel is the number of bits of pixel-port information used as color data for each displayed pixel,

often referred to as the number of bit-planes.

10. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each

LCLK (load clock) pulse. For example, with a 32-bit pixel-bus width and eight bit-planes, each bus load

consists of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from

RCLK. Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The

RCLK divide ratio is not automatically set by mode selection but must be programmed in the output-clock

selection register by the user.

11. This column is a reference to Tables 2–8 through 2–11, where the actual manipulation of pixel information