TUSB9261IPAPQ1 [TI]
汽车类第二代超高速 USB 3.0 至串行 ATA 桥接器 | PAP | 64 | -40 to 85;
| 型号： | TUSB9261IPAPQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类第二代超高速 USB 3.0 至串行 ATA 桥接器 | PAP | 64 | -40 to 85 时钟 数据传输 驱动 外围集成电路 驱动器 |
| 文件： | 总26页 (文件大小：1576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TUSB9261-Q1
www.ti.com
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
USB 3.0 TO SATA BRIDGE
Check for Samples: TUSB9261-Q1
1
FEATURES
•
Qualified for Automotive Applications
•
Integrated ARM Cortex M3 Core
•
AEC-Q100 Qualified with the Following
Exceptions:
–
–
–
–
Customizable Application Code Loaded
From EEPROM Via SPI Interface
–
Device CDM ESD Classification Level C3
Two Additional SPI Port Chip Selects for
Peripheral Connection
•
•
Ideal for bridging Serial ATA (SATA) Devices,
Such as Hard Disk Drives (HDD), Solid State
Drives (SSD), or Optical Drives (OD) to
Universal Serial Bus (USB)
Up to 5 GPIOs for End-User Configuration
via HID
Serial Communications Interface for Debug
(UART)
USB Interface
–
Integrated Transceiver Supports SS/HS/FS
Signaling
•
General Features
–
Integrated Spread Spectrum Clock
–
Best in Class Adaptive Equalizer
Generation Enables Operation from a
Single Low Cost Crystal or Clock Oscillator
–
Allows for Greater Jitter Tolerance in the
Receiver
–
Supports 20, 25, 30 or 40 MHz
–
USB Class Support
–
–
JTAG Interface for IEEE1149.1 and
IEEE1149.6 Boundary Scan
–
USB Attached SCSI Protocol (UASP) for
HDD and SSD
Available in a Fully RoHS Compliant
Package (PAP)
–
USB Mass Storage Class Bulk-Only
Transport (BOT) Including Support for
Error Conditions Per the 13 Cases
(Defined in the BOT Specification)
APPLICATIONS
•
•
•
•
Automotive
–
–
USB Bootability Support
External HDD/SSD
External DVD
USB Human Interface Device (HID)
–
Supports Firmware Update Via USB Using a
TI Provided Application
HDD-Based Portable Media Player
•
SATA Interface
TUSB9261-Q1
HDD
(Media Drive)
–
Serial ATA Specification Revision 2.6
Supporting gen1 and gen2 Data Rates
Console
Embedded
Host
–
–
Supports hot plug
Convenience Port
TUSB8041-Q1
Console
Supports Mass-Storage Devices
Compatible with the ATA/ATAPI-8
Specification
Convenience Port
Console
SD Reader
USB 2.0 Connection
USB 3.0 Connection
USB 3.0 Hub
USB 3.0 Port
USB 2.0 Device
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2014, Texas Instruments Incorporated
TUSB9261-Q1
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
www.ti.com
DESCRIPTION
The TUSB9261-Q1 is an ARM cortex M3 microcontroller based Universal Serial Bus (USB) 3.0 to Serial ATA
(SATA) bridge. It provides the necessary hardware and firmware to implement a USB Attached SCSI Protocol
(UASP) compliant mass storage device suitable for bridging SATA compatible hard disk drives (HDD) and solid
state disk drives (SSD) to a USB 3.0 bus. The firmware also implements the mass storage class bulk-only
transport (BOT) for bridging optical drives and other compatible SATA devices to the USB bus. In addition to
UASP and BOT support,a USB human interface device (HID) interfaces is supported for control of the general
purpose input/ouput (GPIO). The SATA interface supports gen1 (1.5-Gbps) and gen2 (3.0-Gbps) for cable
lengths up to 2 meters.
The device is available in a 64-pin HTQFP package and is designed for operation over the industrial temperature
range of -40°C to 85°C.
ROM
GRSTz
Power
and
TCK
TMS
TDO
TDI
TRST
ARM
Cortex M3
VDD3.3
VDD1.1
JTAG
Reset
Distribution
RAM
64 kB
Data Path
RAM
80 kB
USB 3.0
Device
Controller
XI
Clock
Generation
X0
SATA
AHCI
Watchdog
Timer
Timer
SATA II
PHY
USB SS
PHY
USB HS/FS
PHY
SCI
(UART)
GPIO
PWM
SPI
Figure 1. TUSB9261-Q1 Block Diagram
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
2
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
www.ti.com
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
PIN ASSIGNMENTS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
VDD
FREQSEL1
FREQSEL0
JTAG_TRSTZ
JTAG_TMS
JTAG_TDO
JTAG_TDI
USB_VBUS
VDD33
XI
VSSOSC
XO
VDD
JTAG_TCK
VDD33
SATA_TXM
SATA_TXP
VSS
Thermal Pad
SPI_CS2/GPIO11
SPI_CS1/GPIO10
SPI_CS0
SATA_RXM
SATA_RXP
VDD
SPI_DATA_IN
VDD
VDDA33
VDD
SPI_DATA_OUT
SPI_SCLK
VSS
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 2. TUSB9261-Q1 Pin Diagram
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
www.ti.com
Table 1. I/O Definitions
I/O TYPE
DESCRIPTION
Input
I
O
Output
I/O
PU
PD
PWR
Input - Output
Internal pull-up resistor
Internal pull-down resistor
Power signal
Table 2. Clock and Reset Signals
TERMINAL
I/O
DESCRIPTION
PIN
NO.
NAME
GRSTz
I
Global power reset. This reset brings all of the TUSB9261-Q1 internal registers to their default
states. When GRSTz is asserted, the device is completely nonfunctional.
4
PU
Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately
be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor
is required between X1 and XO.
XI
52
I
Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an
external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback
resistor is required between X1 and XO.
XO
54
O
Frequency select. These terminals indicate the oscillator input frequency and are used to
configure the correct PLL multiplier. The field encoding is as follows:
FREQSEL[1]
FREQSEL[0]
INPUT CLOCK FREQUENCY
I
0
0
1
1
0
1
0
1
20 MHz
25 MHz
30 MHz
40 MHz
FREQSEL[1:0]
31, 30
PU
Table 3. SATA Interface Signals(1)
TERMINAL
NAME
SATA_TXP
I/O
DESCRIPTION
PIN
NO.
57
56
60
59
O
O
I
Serial ATA transmitter differential pair (positive)
Serial ATA transmitter differential pair (negative)
Serial ATA receiver differential pair (positive)
Serial ATA receiver differential pair (negative)
SATA_TXM
SATA_RXP
SATA_RXM
I
(1) Note that the default firmware and reference design for the TUSB9261-Q1 have the SATA TXP/TXM swapped for ease of routing in the
reference design. If you plan to use the TI default firmware please review the reference design in the TUSB9261 DEMO User’s Guide
(SLLU139) for proper SATA connection.
4
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
www.ti.com
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
Table 4. USB Interface Signals
TERMINAL
NAME
I/O
DESCRIPTION
PIN
NO.
USB_SSTXP
USB_SSTXM
USB_SSRXP
USB_SSRXM
USB_DP
43
42
46
45
36
35
O
O
I
SuperSpeed USB transmitter differential pair (positive)
SuperSpeed USB transmitter differential pair (negative)
SuperSpeed USB receiver differential pair (positive)
SuperSpeed USB receiver differential pair (negative)
USB High-speed differential transceiver (positive)
USB High-speed differential transceiver (negative)
I
I/O
I/O
USB_DM
USB Upstream port power monitor. The USB_VBUS input is a 1.2V I/O cell and requires a voltage
divider to prevent damage to the input. The signal USB_VBUS must be connected to VBUS
through a 90.9 kΩ ±1% resistor, and to signal ground through a 10 kΩ ±1% resistor. This allows
the input to detect VBUS present from a minimum of 4V and sustain a maximum VBUS voltage up
to 10V (applied to the voltage divider).
USB_VBUS
50
I
USB_R1
38
39
O
I
Precision resistor reference. A 10-kΩ ±1% resistor should be connected between R1 and R1RTN.
USB_R1RTN
Precision resistor reference return
Table 5. Serial Peripheral Interface (SPI) Signals
TERMINAL
NAME
SPI_SCLK
I/O
DESCRIPTION
PIN
NO.
O
PU
17
18
20
21
SPI clock
O
PU
SPI_DATA_OUT
SPI_DATA_IN
SPI_CS0
SPI master data out
SPI master data in
I
PU
O
PU
Primary SPI chip select for Flash RAM
SPI_CS2/
GPIO11
I/O
PU
SPI chip select for additional peripherals. When not used for SPI chip select this pin may be used
as general purpose I/O. SeeTable 8 for firmware configuration defaults.
23
22
SPI_CS1/
GPIO10
I/O
PU
SPI chip select for additional peripherals. When not used for SPI chip select this pin may be used
as general purpose I/O. SeeTable 8 for firmware configuration defaults.
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
www.ti.com
Table 6. JTAG, GPIO, and PWM Signals
TERMINAL
NAME
I/O
DESCRIPTION
PIN
NO.
I
JTAG_TCK
25
26
27
28
29
6
JTAG test clock
PD
I
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTz
GPIO9/UART_TX
GPIO8/UART_RX
GPIO7
JTAG test data in
JTAG test data out
JTAG test mode select
JTAG test reset
PU
O
PD
I
PU
I
PD
I/O
PU
GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a
UART channel. SeeTable 8 for firmware configuration defaults.
I/O
PU
GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART
channel. SeeTable 8 for firmware configuration defaults.
5
I/O
PD
16
15
14
13
11
10
9
I/O
PD
GPIO6
I/O
PD
GPIO5
I/O
PD
GPIO4
Configurable as general purpose input/outputs. SeeTable 8 for firmware configuration defaults.
I/O
PD
GPIO3
I/O
PD
GPIO2
I/O
PD
GPIO1
I/O
PD
GPIO0
8
O
PWM0
2
PD(1)
Pulse Width Modulation (PWM) which can be used to drive status LED's. SeeTable 8 for firmware
configuration defaults.
O
PWM1
3
PD(1)
(1) PWM pull down resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down
resistors are enabled by default.
6
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
www.ti.com
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
Table 7. Power and Ground Signals
TERMINAL
NAME
I/O
DESCRIPTION
PIN
NO.
1, 12,
19, 32,
33, 41,
47, 49,
55, 61,
63
VDD
PWR 1.1-V power rail
7, 24,
51
VDD33
PWR 3.3-V power rail
34, 40,
48, 62
VDDA33
PWR 3.3-V analog power rail
Oscillator ground. If using a crystal, this should not be connected to PCB ground plane. If
PWR using an oscillator, this should be connected to PCB ground. See the Clock Source
Requirements section for more details.
VSSOSC
53
37, 44, 58,
64
VSS
VSS
PWR Ground
65
PWR Ground - Thermal Pad
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VDD
Steady-state supply voltage
Steady-state supply voltage
–0.3 to 1.4
V
VDD33/
VDDA33
–0.3 to 3.8
V
USB 2.0 DP/DM
–0.3 to 3.8
–0.3 to 3.8
–0.3 to 3.8
–0.3 to 1.98
–0.3 to 3.8
–0.3 to 1.2
-65 to 150
-40 t o 105
2
SuperSpeed USB TXP/M and RXP/M
SATA TXP/M and RXP/M
XI/XO
VIO
V
3.3V Tolerant I/O
VUSB_VBUS Voltage at USB_VBUS pad
V
TSTG
TJ
Storage temperature range
°C
°C
kV
Operating junction temperature range
Human-body model (HBM) AEC-Q100 Classification Level H2
Corner pins
750
ESD rating
AEQ-Q100 Classification Level C4B
AEQ-Q100 Classification Level C3
Charged-device model
(CDM)
Non-corner pins
except USB_R1
500
450
V
USB_R1
THERMAL INFORMATION
TUSB9261-Q1
THERMAL METRIC(1)
PAP
64 PINS
30.2
11
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
θJCtop
θJB
Junction-to-board thermal resistance(4)
6.1
°C/W
ψJT
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
.04
ψJB
6.1
θJCbot
0.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
1.045
3
NOM
1.1
MAX
1.155
3.6
UNIT
VDD
Digital 1.1 supply voltage
Digital 3.3 supply voltage
Analog 3.3 supply voltage
V
V
V
VDD33
VDDA33
3.3
3
3.3
3.6
8
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
www.ti.com
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX
VDD33
VDD33
VDD33
1.8
UNIT
USB 2.0 DM/DP
SuperSpeed USB TXM/P and RXM/P
0
VIO
SATA TXM/P and RXM/P
XI/XO
0
V
0
3.3V Tolerant I/O
0
VDD33
1.155
85
VUSB_VBUS Voltage at USB_VBUS PAD
0
V
TA
TJ
Operating free-air temperature range
Operating junction temperature range
-40
-40
°C
°C
105
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
www.ti.com
DC ELECTRICAL CHARACTERISTICS FOR 3.3-V DIGITAL I/O
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRIVER
TR
Rise time
5 pF
5 pF
1.5
ns
ns
mA
mA
V
TF
Fall time
1.53
IOL
Low-level output current
High-level output current
Low-level output voltage
High-level output voltage
Output voltage
VDD33 = 3.3 V, TJ = 25°C
VDD33 = 3.3 V, TJ = 25°C
IOL = 2 mA
6
IOH
–6
VOL
0.4
VOH
IOL = –2 mA
2.4
0
V
VO
VDD33
V
RECEIVER
VI
Input voltage
0
0
VDD33
0.8
V
V
VIL
VIH
Vhys
tT
Low-level input voltage
High-level input voltage
Input hysteresis
2
V
200
mV
ns
µA
pF
Input transition time (TR and TF)
Input current
10
5
II
VI = 0 V to VDD33
CI
Input capacitance
VDD33 = 3.3 V, TJ = 25°C
0.384
SuperSpeed USB POWER CONSUMPTION
POWER RAIL
TYPICAL ACTIVE CURRENT (mA)(1)
TYPICAL SUSPEND CURRENT (mA)(2)
VDD11
VDD33(3)
291
65
153
28
(1) Transferring data via SS USB to a SSD SATA Gen II device. No SATA power management, U0 only.
(2) SATA Gen II SSD attached no active transfer. No SATA power management, U3 only.
(3) All 3.3-V power rails connected together.
HIGH SPEED USB POWER CONSUMPTION
POWER RAIL
TYPICAL ACTIVE CURRENT (mA)(1)
TYPICAL SUSPEND CURRENT (mA)(2)
VDD11
VDD33(3)
172
56
153
28
(1) Transferring data via HS USB to a SSD SATA Gen II device. No SATA power management.
(2) SATA Gen II SSD attached no active transfer. No SATA power management.
(3) All 3.3-V power rails connected together.
10
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
www.ti.com
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
OPERATION
General Functionality
The TUSB9261-Q1 ROM contains boot code that executes after a global reset which performs the initial
configuration required to load a firmware image from an attached SPI flash memory to local RAM. In the absence
of an attached SPI flash memory or a valid image in the SPI flash memory, the firmware will idle and wait for a
connection from a USB host through its HID interface which is also configured from the boot code. The latter can
be accomplished using a custom application or driver to load the firmware from a file resident on the host
system.
Once the firmware is loaded it configures the SATA advanced host controller interface host bus adapter (AHCI)
and the USB device controller. In addition, the configuration of the AHCI includes a port reset which initiates an
out of band (OOB) TX sequence from the AHCI link layer to determine if a device is connected, and if so
negotiate the connection speed with the device (3.0 Gbps or 1.5 Gbps). Following speed negotiation, the
firmware queries the attached device for capabilities and configures the device as appropriate for its interface
and supported capabilities, for example a HDD that supports native command queuing (NCQ). If no SATA device
is connected, the firmware will configure the USB interface as a removable media device which supports SATA
hot plug events.
The configuration of the USB device controller includes creation of the descriptors, configuration of the device
endpoints for support of UASP and USB mass storage class bulk-only transport, allocation of memory for the
transmit request blocks (TRBs), and creation of the TRBs necessary to transmit and receive packet data over the
USB. In addition, the firmware provides any other custom configuration required for application specific
implementation, for example a HID interface for user initiated backup.
After USB device controller configuration is complete, the firmware connects the device to the USB bus when
VBUS is detected. According to the USB 3.0 specification, the TUSB9261-Q1 will initially try to connect at
SuperSpeed USB, if successful it will enter U0; otherwise, after the training time out it will enable the DP pull up
and connect as a USB 2.0 high-speed or full-speed device depending on the speed supported by host or hub
port.
When connected, the firmware presents the BOT interface as the primary interface and the UASP interface as
the secondary interface. If the host stack is UASP aware, it can enable the UASP interface using a
SET_INTERFACE request for alternate interface 1.
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
www.ti.com
Firmware Support
Default firmware support is provided for the following:
•
•
•
SuperSpeed USB and USB 2.0 High-Speed and Full-Speed
USB Attached SCSI Protocol (UASP) for Hard Disk Drives (HDD) and Solid State Drives (SSD)
USB Mass Storage Class (MSC) Bulk-Only Transport (BOT) for HDD, SSD, and Optical Drives
–
Including the 13 Error Cases
•
•
USB Mass Storage Specification for Bootability
USB Device Class Definition for Human Interface Devices (HID)
–
Firmware Update and Custom Functionality (e.g. One-Touch Backup)
•
•
Serial ATA Advanced Host Controller Interface (AHCI)
General Purpose Input/Output (GPIO)
–
LED Control and Custom Functions (e.g. One-Touch Backup Control)
Pulse Width Modulation (PWM)
LED Dimming Control
Serial Peripheral Interface (SPI)
Firmware storage and storing Custom Device Descriptors
Serial Communications Interface (SCI)
Debug Output Only
•
•
•
–
–
–
GPIO/PWM LED Designations
The default firmware provided by TI drives the GPIO and PWM outputs as listed in the table below.
Table 8. GPIO/PWM LED Designations
GPIO0
Undefined. Defaults to input with integrated pull-down. Controllable as output via HID.
00: U3 state or default
Output indicating USB3 power state (U0-U3), if U1/U2
01: U2 state
10: U1 state
11: U0 state
is enabled. Otherwise, defaults to an input with pull-
down and may be driven low or high as an output via
HID.
GPIO1/GPIO5
GPIO2
GPIO3
GPIO4
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
PWM0
PWM1
Output indicating HS/FS suspend when connected as USB 2.0. High indicates the USB 2.0 HS/FS bus is suspended.
Input with integrated pull-down for momentary push button input to signal remote wake.
Input to identify bus or self-powered status. Input should be high to indicate self-powered.
Undefined. Defaults to input with pull-down. Controllable as output via HID.
Output indicating SuperSpeed USB connection status. High indicates a SuperSpeed USB connection.
UART Rx
UART Tx
Undefined. Defaults to input with integrated pull-up. Controllable as output via HID.
Input with integrated pull-up to indicate a power fault condition. Low indicates a power fault.
Output indicating disk activity.
Output indicating software heartbeat.
The LED’s on the TUSB9261 Product Development Kit (PDK) board are connected as in the table above. Please
see the TUSB9261 PDK Guide for more information on GPIO LED connection and usage. This EVM is available
for purchase, contact TI for ordering information.
12
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
www.ti.com
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
Power Up and Reset Sequence
The TUSB9261-Q1 does not have specific power sequencing requirements with respect to the core power
(VDD), I/O power (VDD33), or analog power (VDDA33) for reliability reasons. The core power (VDD) or IO power
(VDD33) may be powered up for an indefinite period of time while others are not powered up if all of these
constraints are met:
•
•
All maximum ratings and recommended operating conditions are observed.
All warnings about exposure to maximum rated and recommended conditions are observed, particularly
junction temperature. These apply to power transitions as well as normal operation.
•
•
Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the
device.
Bus contention while VDD33 is powered down may violate the absolute maximum ratings.
A supply bus is powered up when the voltage is within the recommended operating range. It is powered down
when it is below that range, either stable or in transition.
A minimum reset duration of 1 ms is required. This is defined as the time when the power supplies are in the
recommended operating range to the de-assertion of GRSTz. If a passive reset circuit is used to provide GRSTz
it is recommended that core power (VDD) be ramped prior to or at the same time as I/O power (VDD33). If this is
not practical it is recommended to use a power good output from the core voltage regulator or voltage
supervisory circuit to ensure a good reset input. The recommended duration of the GRSTz input is greater than 2
ms but less than 100 ms.
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
www.ti.com
CLOCK CONNECTIONS
Clock Source Requirements
The TUSB9261-Q1 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a
crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a crystal is
used, the connection needs to follow the guidelines below.
Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as
possible and away from any switching leads. It is also recommended to minimize the capacitance be-tween XI
and XO. This can be accomplished by connecting the VSSOSC lead to the two external capaci-tors CL1 and
CL2 and shielding them with the clean ground lines. The VSSOSC should not be connected to PCB ground
when using a crystal.
Load capacitance (Cload) of the crystal varying with the crystal vendors is the total capacitance value of the entire
oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2 in Figure 3.
The trace length between the decoupling capacitors and the corresponding power pins on the TUSB9261 needs
to be minimized. It is also recommended that the trace length from the capacitor pad to the power or ground
plane be minimized.
CL1
XI
VSSOSC
Crystal
XO
CL2
Figure 3. Typical Crystal Connections
Clock Source Selection Guide
Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the trans-mit eye
and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing system performance.
Additionally, a particularly jittery reference clock may interfere with PLL lock detection mechanism, forcing the
Lock Detector to issue an Unlock signal. A good quality, low jitter reference clock is required to achieve
compliance with supported USB3.0 standards. For example, USB3.0 specification requires the random jitter (RJ)
component of either RX or TX to be 2.42 ps (random phase jitter calculated after applying jitter transfer function -
JTF). As the PLL typically has a number of additional jitter components, the Reference Clock jitter must be
considerably below the overall jitter budget.
14
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
www.ti.com
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
Oscillator
XI should be tied to the 1.8-V clock source and XO should be left floating.
VSSOSC should be connected to the PCB ground plane.
A 20-, 25-, 30- or 40-MHz clock can be used.
Table 9. Oscillator Specification
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
pF
V
CXI
XI input capacitance
Low-level input voltage
High-level input voltage
Frequency tolerance
Duty cycle
TJ = 25°C
0.414
VIL
0.7
VIH
1.05
–50
45
V
Ttosc_i
Tduty
TR/TF
RJ
Operational temperature
50
55
6
ppm
%
50
Rise/Fall time
20% - 80 %
ns
Reference clock RJ
Reference clock TJ
Reference clock jitter
JTF (1 sigma)(1) (2)
JTF (total p-p)(2) (3)
(absolute p-p)(4)
0.8
25
50
ps
TJ
ps
Tp-p
ps
(1) Sigma value assuming Gaussian distribution
(2) After application of JTF
(3) Calculated as 14.1 x RJ + DJ
(4) Absolute phase jitter (p-p)
Crystal
A parallel, 20-pF load capacitor should be used if a crystal source is used.
VSSOSC should not be connected to the PCB ground plane.
A 20-, 25-, 30- or 40-MHz crystal can be used.
Table 10. Crystal Specification
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
MHz
Ω
Oscillation mode
Fundamental
20
25
fO
Oscillation frequency
30
40
20 MHz and 25 MHz
30 MHz
50
ESR
Equivalent series resistance
40
40 MHz
30
Ttosc_i
Frequency tolerance
Frequency stability
Load capacitance
Operational temperature
1 year aging
±50
±50
ppm
ppm
pF
CL
12
20
24
4.5
0.8
Crystal and board stray
capacitance
CSHUNT
pF
Drive level (max)
mW
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links :TUSB9261-Q1
TUSB9261-Q1
SLLSEE2A –JANUARY 2014–REVISED JANUARY 2014
www.ti.com
REVISION HISTORY
Changes from Original (January 2014) to Revision A
Page
•
Deleted ORDERING INFORMATION table .......................................................................................................................... 2
16
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links :TUSB9261-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TUSB9261IPAPQ1
TUSB9261IPAPRQ1
ACTIVE
ACTIVE
HTQFP
HTQFP
PAP
PAP
64
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
TUSB9261IQ1
TUSB9261IQ1
1000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
OTHER QUALIFIED VERSIONS OF TUSB9261-Q1 :
Catalog: TUSB9261
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB9261IPAPRQ1
HTQFP
PAP
64
1000
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PAP 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
TUSB9261IPAPRQ1
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
TUSB9261IPAPQ1
PAP
HTQFP
64
160
8 X 20
150
322.6 135.9 7620 15.2
13.1
13
Pack Materials-Page 3
GENERIC PACKAGE VIEW
PAP 64
10 x 10, 0.5 mm pitch
HTQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226442/A
www.ti.com
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
TUSONIX 4300系列焊接型EMI/RFI滤波器
4300系列焊接型EMI/RFI滤波器 工作电压：70VDC，50VDC，150VDC，300VDC 工作电流：5A 容值范围：5PF~50000PF 容值误差：GMV，±20% 插入损耗：5~35 dB@10MHZ 4300系列焊接型EMI/RFI滤波器的主要特点： 小型化高性能C型滤波器 玻璃顶部密封可以提供最好的密封效果 镀金管脚可以提供卓越的传导与连接性能 小的封装和宽范围的电性能 适合多种微波应用 本信息网址：http://www.wellking.com/default/NewProductShow.asp?ID=115
TOSHIBA
TUSONIX 79系列带滤波功能的标准连接滤波片
79系列带滤波功能的标准连接滤波片 分单排和双排两种 每排最多可安装10个滤波器 装配板材料：合金铜,表面镀锡 装配板厚度： 0.7mm 滤波器管脚材料：合金铜，表面镀金 滤波器管脚直径：0.64mm 滤波器额定电流：5A 滤波器管脚形式：两端都是直的/一端弯曲90度/两端都弯曲90度 当一个系统中需要多个EMI滤波器时，采用79系列带滤波功能的标准连接滤波片是一种有效，经济的方法，对于大于50MHz的高频应用， 滤波器装配板比表面贴装滤波器更有效；对于5MHz以上的信号有很好的屏蔽作用。这些提前就装配好滤波器的产品经过100%的测试， 可以有效的减小安装EMI滤波器所需要花费的精力。 本信息网址：http://www.wellking.com/default/NewProductShow.asp?ID=388
ETC
©2020 ICPDF网 联系我们和版权申明