TUSB217AI [TI]
TUSB217A USB 2.0 High-Speed Signal Conditioner With DCP and CDP Controllers;
| 型号： | TUSB217AI |
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TEXAS INSTRUMENTS |
| 描述： | TUSB217A USB 2.0 High-Speed Signal Conditioner With DCP and CDP Controllers CD |
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TUSB217A
SLLSFK5 – JUNE 2021
TUSB217A USB 2.0 High-Speed Signal Conditioner With DCP and CDP Controllers
1 Features
3 Description
•
•
Wide supply voltage range: 2.3 - 6.5 V
Ultra-low USB disconnect and shutdown power
consumption
Provides USB 2.0 high-speed signal conditioning
Compatible with USB 2.0, OTG 2.0 and BC 1.2
Support for low-speed, full-speed, high-speed
signaling
Integrated BC 1.2 Charging Downstream
Port (CDP) and Dedicated Charging Port
(DCP) controllers that dynamically changes per
DCP/CDP pin
The TUSB217A is a third-generation USB 2.0 high-
speed signal conditioner designed to compensate
both AC loss (due to capacitive load) and DC loss
(due to resistive loss) in the transmission channel.
•
•
•
The TUSB217A leverages a patented design to
speed-up transition edges of USB 2.0 high-speed
signal with an edge booster and increases static
levels with a DC boost function. In addition, the
TUSB217A includes a pre-equalization function to
improve the receiver sensitivity and compensate the
inter-symbol interference (ISI) jitter in application
with longer cable length. USB low-speed and full-
speed signal characteristics are unaffected by the
TUSB217A.
•
•
•
Host/Device agnostic
Supports up to 5-m cable length
– Four selectable signal boost (edge boost along
with DC boost) settings via external pull-down
resistor values
– Three selectable RX equalization settings via
pull-up-or-down to compensate ISI jitter for
high-loss applications
Supports up to 10-m cable length with two
TUSB217A devices
Scalable solution - devices can be daisy chained
for high loss applications
The TUSB217A improves signal quality without
altering packet timing or adding propagation delay or
latency.
The TUSB217A helps a system to pass the USB 2.0
high-speed near end eye compliance with a cable as
long as 5 meters.
•
•
•
The TUSB217A is compatible with the USB On-The-
Go (OTG) and battery charging (BC 1.2) protocols.
The Integrated BC 1.2 battery charging controller can
be enabled via a control pin.
RWB is pin compatible with TUSB211/212/214/216
2 Applications
•
•
•
•
•
•
Laptop, desktop/docking stations
Portable electronics
Tablets
Cell phones
Televisions
Device Information
PART
NUMBER
OP TEMP (TA)
°C
BODY SIZE
(NOM)
PACKAGE
X2QFN
(12RWB)
1.60 mm x 1.60
mm
TUSB217A
TUSB217AI
2.3 œ 6.5V
0 to 70
Active cable, cable extenders, backplane
X2QFN
(12RWB)
1.60 mm x 1.60
mm
-40 to 85
VCC
USB
Host
USB
Cable
D2
D1
Connector
GND
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB217A
SLLSFK5 – JUNE 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................7
7.6 Switching Characteristics ...........................................8
7.7 Timing Requirements .................................................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................10
8.5 TUSB217A Registers................................................11
9 Application and Implementation..................................15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................24
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Receiving Notification of Documentation Updates..26
12.2 Support Resources................................................. 26
12.3 Trademarks.............................................................26
12.4 Electrostatic Discharge Caution..............................26
12.5 Glossary..................................................................26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 26
13.1 Package Option Addendum....................................30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
June 2021
*
Initial Release
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5 Device Comparison
TUSB211
TUSB212
3.3
TUSB214
3.3
TUSB216I
TUSB217A
Supply (V)
DC Boost
3.3
2.3 to 6.5
2.3 to 6.5
3 levels
3 levels
Tandem with AC
Boost
Tandem with AC
Boost
RX pre-equalization
for ISI compensation
3 levels
3 levels
Charging
Always ON
Pin Controlled
Always ON.
Downstream Port
(CDP) controller
Dynamically selected
by DCP/CDP pin
Dedicated Charging
Port (DCP) controller
Always ON.
Dynamically selected
by DCP/CDP pin
Cable length
2/1 - 28AWG
4/2 - 28AWG
4/2 - 28AWG
6/3 - 28AWG (10
- 24AWG with one
redriver on each end) redriver on each end)
6/3 - 28AWG (10
- 24AWG with one
compensation for
near-end high-speed
eye mask Compliance
(pre-channel before
redriver/post-channel
after redriver) (meter -
gauge)
Cable length
5/3 - 28AWG
8/6 - 28AWG
8/6 - 28AWG
10/8 - 26AWG (10
- 28AWG with one
redriver on each end) redriver on each end)
10/8 - 26AWG (10
- 28AWG with one
compensation for far-
end high-speed eye
mask Compliance
(pre-channel before
redriver/post-channel
after redriver) (meter -
gauge)
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6 Pin Configuration and Functions
D1P D1M
VCC
3
4
12
SDA
2
1
11 DCP/CDP
10 GND
SCL/CD
RSTZ 5
7
8
BOOST 6
9 RX_SEN/ENA_HS
Not to scale
Figure 6-1. TUSB217A RWB 12-Pin X2QFN Top View
Table 6-1. Pin Functions
PIN (RWB)
NAME
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NO. (RWB)
USB High-speed boost select via external pull down resistor.
Both edge boost and DC boost are controlled by a single pin in non-
I2C mode. In I2C mode edge boost and DC boost can be individually
controlled.
Sampled upon power up. Does not recognize real time adjustments.
Auto selects BOOST LEVEL = 3 when left floating.
BOOST
6
I
I
N/A
DCP or CDP mode selection. Low=DCP and High=CDP
TUSB217ARWB BC1.2 controller is always enabled.
DCP/CDP
11
500 kΩ PU
In I2C mode:
Reserved for TI test purpose.
In non-I2C mode:
At reset: 3-level input signal RX_SEN. USB High-speed RX
Equalization Setting to Compensate ISI Jitter
H (pin is pulled high) – high RX equalization (high loss channel)
M (pin is left floating) – medium RX equalization (medium loss
channel)
L (pin is pulled low) – low RX equalization (low loss channel)
After reset: Output signal ENA_HS. Flag indicating that channel is in
High-speed mode. Asserted upon:
RX_SEN(2)/ENA_HS
9
I/O
N/A
1. Detection of USB-IF High-speed test fixture from an unconnected
state followed by transmission of USB TEST_PACKET pattern.
2. Squelch detection following USB reset with a successful HS
handshake [HS handshake is declared to be successful after single
chirp J chirp K pair where each chirp is within 18 μs – 128 μs].
D2P
D2M
GND
D1M
D1P
7
8
I/O
I/O
P
N/A
N/A
N/A
N/A
N/A
USB High-speed positive port.
USB High-speed negative port.
Ground
10
1
I/O
I/O
USB High-speed negative port..
USB High-speed positive port.
2
I2C Mode:
500 kΩ PU
1.8 MΩ PD
Bidirectional I2C data pin [7-bit I2C slave address = 0x2C].
In non I2C mode:
Reserved for TI test purpose.
SDA(1)
VCC
3
I/O
P
12
N/A
Supply power
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Table 6-1. Pin Functions (continued)
PIN (RWB)
NAME
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NO. (RWB)
Device disable/enable.
Low – Device is at reset and in shutdown, and
High - Normal operation.
Recommend 0.1-µF external capacitor to GND to ensure clean
power on reset if not driven. If the pin is driven, it must be held low
until the supply voltage for the device reaches within specifications.
500 kΩ PU
1.8 MΩ PD
RSTN
5
I
In I2C mode:
I2C clock pin [I2C address = 0x2C].
Non I2C mode:
When RSTN asserted there is
a 500 kΩ PD
SCL(1)/CD
4
I/O
After reset: Output CD. Flag indicating that a USB device is attached
(connection detected). Asserted from an unconnected state upon
detection of DP or DM pull-up resistor. De-asserted upon detection of
disconnect.
(1) Pull-up resistors for SDA and SCL pins in I2C mode should be RPull-up (depending on I2C bus voltage). If both SDA and SCL are pulled
up at power-up the device enters into I2C mode.
(2) Pull-down and pull-up resistors for RX_SEN pin must follow RRXSEN1 and RRXSEN2 resistor recommendations in non I2C mode.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
-0.3
-0.3
–65
MAX
7
UNIT
V
Supply voltage range
VCC
Voltage range USB data
Voltage range on BOOST pin
Voltage range other pins
Storage temperature, Tstg
DxP, DxM
5.5
V
BOOST
1.98
5.5
V
RX_SEN, DCP/CDP,SDA,SCL, RSTN
V
150
125
°C
°C
Maximum junction temperature, TJ (max)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per
Charged-device model (CDM), per
V(ESD)
Electrostatic discharge
V
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.3
1.62
0
NOM
MAX
UNIT
V
VCC
Supply voltage
5
6.5
3.6
VI2C_BUS
DxP, DxM
BOOST
DIGITAL
RX_SEN
I2C Bus Voltage
V
Voltage range USB data
3.6
V
Voltage range BOOST pin
Voltage range other pins (SCL, SDA, RSTN, DCP/CDP)
Voltage range RX_SEN pin
0
1.98
3.6
V
0
V
0
5.0
V
7.4 Thermal Information
RWB (X2QFN)
12 PINS
137.4
62
THERMAL METRIC (1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
67.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.9
ψJB
67.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
POWER
USB channel = HS mode. 480 Mbps
traffic. VCC supply stable, with Boost =
Max
IACTIVE_HS
High Speed Active Current
22
36
mA
USB channel = HS mode, no traffic.
VCC supply stable, Boost = Max
IIDLE_HS
IHS_SUPSPEND
IFS
High Speed Idle Current
High Speed Suspend Current
Full-Speed Current
22
0.75
0.75
36
1.4
1.4
mA
mA
mA
USB channel = HS Suspend mode.
VCC supply stable
USB channel = FS mode, 12 Mbps traffic,
Vcc supply stable
Host side application. No device
attachment.
IDISCONN
ISHUTDN
Disconnect Power
Shutdown Power
0.80
60
1.4
mA
µA
RSTN driven low, VCC supply stable
115
CONTROL PIN LEAKAGE
Pin failsafe leakage current for
SDA, RSTN
ILKG_FS
ILKG_FS
ILKG_FS
VCC = 0 V, pin at VIH, max
VCC = 0 V, pin at VIH, max
VCC = 0 V, pin at VIH, max
10
6
15
15
70
µA
µA
nA
Pin failsafe leakage current for
RX_SEN
Pin failsafe leakage current for
SCL
INPUT RSTN
VIH
High level input voltage
Low-level input voltage
High level input current
Low level input current
1.5
0
3.6
0.5
V
V
VIL
IIH
VIH = 3.6 V, RPU enabled
VIL = 0V, RPU enabled
±15
±20
µA
µA
IIL
INPUT DIGITAL
High level input voltage (DCP/
CDP)
VIH
VIL
1.5
0
3.6
0.5
V
V
Low-level input voltage (DCP/
CDP)
IIL
Low level input current
High level input current
VIL = 0V
±20
±15
µA
µA
IIH
VIH = 3.6 V
INPUT RX_SEN (3-level input, for mid level leave pin floating)
Maximum High level input
VIH(Max)
voltage
VCC = 2.3V to 6.5V
5.0
V
VCC > 4.5V
3.3
75
V
%
V
Minimum High level input voltage
VIH(Min)
VCC = 2.3V to 4.5V (% of VCC)
VCC > 4.5V
0.75
15
Low level input voltage
VIL
VCC = 2.3V to 4.5V (% of VCC)
%
INPUT BOOST
External pulldown resistor for
BOOST Level 0
RBOOST_LVL0
160
2
Ω
External pulldown resistor for
BOOST Level 1
RBOOST_LVL1
RBOOST_LVL2
1.5
3.4
1.8
3.6
kΩ
kΩ
External pulldown resistor for
BOOST Level 2
3.96
External pulldown resistor for
BOOST Level 3 to remove upper
limit for resistor value, can be left
open
RBOOST_LVL3
7.5
kΩ
OUTPUTS CD, ENA_HS
High level output voltage for CD
and ENA_HS
VOH
VOH
IO = –50 µA, VCC >= 3.0V
2.5
1.7
V
V
High level output voltage for CD IO = –25 µA, VCC = 2.3V
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Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
High level output voltage for
ENA_HS
VOH
VOL
IO = –25 µA, VCC = 2.3V
1.8
V
Low level output voltage for CD
and ENA_HS
IO = 50 µA
0.3
V
I2C
CI2C_BUS
IOL
I2C Bus Capacitance
4
150
pF
I2C open drain output current
VOL = 0.4V
1.5
mA
2.3V<= VCC<= 4.3V, VI2C_BUS
1.8V +/-10%
=
=
VIL
VIL
VIH
RPull-up =1.6kΩ to 2.5kΩ, % of VI2C_BUS
RPull-up =2.8kΩ to 7kΩ, % of VI2C_BUS
RPull-up =1.6kΩ to 2.5kΩ, % of VI2C_BUS
RPull-up =2.8kΩ to 7kΩ, % of VI2C_BUS
25
25
%
%
%
VI2C_BUS = 3.3V +/-10%
2.3V<= VCC<= 4.3V, VI2C_BUS
1.8V +/-10%
80
VIH
VI2C_BUS = 3.3V +/-10%
VI2C_BUS = 1.8V +/-10%
VI2C_BUS = 3.3V +/-10%
75
1.6
2.8
%
kΩ
kΩ
kHz
RPull-up
2
2.5
7
RPull-up
4.7
SCL Frequency
DxP, DxM
100
Measured with VNA at 240 MHz,
VCC supply stable, Redriver off
CIO_DXX
Capacitance to GND
2.5
pF
(1) All typical values are at VCC = 5 V, and TA = 25°C.
7.6 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
DxP, DxM USB Signals
USB channel = HS mode. 480 Mbps
traffic. VCC supply stable
FBR_DXX
tR/F_DXX
Bit Rate
Rise/Fall time
480
Mbps
ps
100
(1) All typical values are at VCC = 5 V, and TA = 25°C.
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7.7 Timing Requirements
MIN
NOM
MAX
UNIT
POWER UP TIMING
Minimum width to detect a valid RSTN signal assert when the pin is actively
driven low
TRSTN_PW
TSTABLE
TREADY
100
300
µs
µs
µs
VCC must be stable before RSTN de-assertion
Maximum time needed for the device to be ready after RSTN is de-
asserted.
500
100
TRAMP
VCC ramp time
VCC ramp time
ms
ms
TRAMP
0.2
I2C (STD)
Stop setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz
STD
tSUSTO
tHDSTA
tSUSTA
tSUDAT
tHDDAT
4
4
µs
µs
µs
ns
µs
Start hold time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns), 100kHz
STD
Start setup time, SCL (Tr=600ns-1000ns), SDA (Tf=6.5ns-106.5ns),
100kHz STD
4.7
250
5
Data input or False start/stop, setup time, SCL (Tr=600ns-1000ns), SDA
(Tf=6.5ns-106.5ns), 100kHz STD
Data input or False start/stop, hold time, SCL (Tr=600ns-1000ns), SDA
(Tf=6.5ns-106.5ns), 100kHz STD
tBUF
tLOW
tHIGH
tF
Bus free time between START and STOP conditions
Low period of the I2C clock
4.7
4.7
4
µs
µs
µs
ns
ns
High period of the I2C clock
Fall time of both SDA and SCL signals
Rise time of both SDA and SCL signals
300
tR
1000
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8 Detailed Description
8.1 Overview
The TUSB217A is a USB High-Speed (HS) signal conditioner designed to compensate for ISI signal loss in a
transmission channel. TUSB217A has a patented design for USB Low Speed (LS) and Full Speed (FS) signals.
It does not alter the signal characteristics. HS signals are compensated. The design is compatible with USB
On-The-Go (OTG) and Battery Charging (BC) specifications.
Programmable signal gain through an external resistor permits fine tuning device performance to optimize
signals. This helps pass USB HS electrical compliance tests at the connector. Additional RX sensitivity, tuned by
external pull-up resistor and pull-down resistor, allows to overcome attenuation in cables. The TUSB217A allows
application in series to cover longer distances, or high loss transmission paths. A maximum of 4 devices can be
daisy-chained.
8.2 Functional Block Diagram
Low and Full
Speed Bypass
D2P
D1P
USB
TRANSCEIVER
High Speed
Compensation
ESD
PROTECTION
USB
CONNECTOR
D1M
D2M
CD
OPTIONAL
PLD
ENA_HS
Status flags
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8.3 Feature Description
8.3.1 High-speed Boost
The high-speed booster (combination of edge boost and DC boost) improves the eye width for USB2.0 high-
speed signals. It is direction independent and by that is compatible to OTG systems. The BOOST pin is
configuring the booster strength with different values of pull down resistors to set 4 levels of boosts, alternatively
the boost level can be set via I2C register according to Section 8.4.6. Internal circuitry of the signal conditioner
reduces possible overshoot.
8.3.2 RX Sensitivity
The RX_SEN pin is a tri-level pin. It is used to set the equalization gain of the device according to system
channel inter-symbol interference (ISI) loss. RX equalization can be increased to compensate for the higher ISI
loss of the channel for example due to a long cable.
8.4 Device Functional Modes
8.4.1 Low-speed (LS) Mode
TUSB217A automatically detects a LS connection and does not enable signal compensation. CD pin is asserted
high but ENA_HS will be low.
8.4.2 Full-speed (FS) Mode
TUSB217A automatically detects a FS connection and does not enable signal compensation. CD pin is asserted
high but ENA_HS will be low
8.4.3 High-speed (HS) Mode
TUSB217A automatically detects a HS connection and will enable signal compensation as determined by the
configuration of the RX_SEN pin and the external pull down resistance on its BOOST pin.
CD pin and ENA_HS pin are asserted high when high-speed boost is active.
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8.4.4 High-speed Downstream Port Electrical Compliance Test Mode
TUSB217A will detect HS compliance test fixture and enter downstream port high-speed eye diagram test mode.
CD pin will be low and ENA_HS pin is asserted high when TUSB217A is in HS eye compliance test mode.
If RSTN pin is asserted low and de-asserted high while TUSB217A is operating in HS functional mode,
TUSB217A may transition to HS eye compliance test mode and CD asserts low and ENA_HS remains high.
When this occurs signal compensation is enabled.
8.4.5 Shutdown Mode
TUSB217A can be disabled when its RSTN pin is asserted low. DP, DM traces are continuous through the
device in shutdown mode. The USB channel is still fully operational, but there is neither signal compensation,
nor any indication from the CD pin as to the status of the channel.
Table 8-1. CD and ENA_HS Pins in Different Modes
MODE
CD
ENA_HS
LOW
Low-speed
Full-speed
HIGH
HIGH
HIGH
LOW
LOW
LOW
High-speed
HIGH
HIGH
LOW
High-speed downstream port electrical test
Shutdown
8.4.6 I2C Mode
TUSB217A supports 100 KHz I2C for device configuration, status read back and test purposes. For detail
electrical and functional specifications refer to I2C Bus Specification 2.1, 2001 – STANDARD MODE. This
controller is enabled after SCL and SDA pins are sampled high shortly after return from shutdown. In this
mode, the CSR can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is advised to set
CFG_ACTIVE bit before changing values. This halts the FSM, and reset it after all changes are made. This
ensure proper startup into high-speed mode.
8.4.7 BC 1.2 Battery Charging Controller
Battery charging controller feature is always enabled in TUSB217ARWB and supports both CDP charging
downstream port functionality and DCP dedicated charging port functionality depending on DCP/CDP pin. When
DCP/CDP pin is high the BC 1.2 controller supports CDP mode and when DCP/CDP pin is low BC 1.2 controller
supports DCP mode. DCP/CDP pin can be dynamically controlled. When host or hub is disabled DCP/CDP pin
can be set low to support DCP mode and when host or hub is enabled DCP/CDP pin can be set to high to
support CDP. Downstream VBUS should be toggled after the DCP/CDP pin change so BC 1.2 handshake starts
over to indicate charging mode change.
DCP/CDP pin has an internal pull up resistor. When DCP/CDP pin is left unconnected the BC 1.2 controller will
be in CDP mode.
Table 8-2. TUSB217ARWB Battery Charging Controller Modes
Pin 11 (DCP/CDP)
CDP
DCP
YES
NO
Low
NO
High
YES
8.5 TUSB217A Registers
Table 8-3 lists the memory-mapped registers for the TUSB217A registers. All register offset addresses not listed
in Table 8-3 should be considered as reserved locations and the register contents should not be modified.
Table 8-3. TUSB217A Registers
Offset
0x1
Acronym
Register Name
Section
Go
EDGE_BOOST
CONFIGURATION
This register is setting EDGE BOOST level.
This register is selecting device mode.
0x3
Go
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Table 8-3. TUSB217A Registers (continued)
Offset
0xE
Acronym
Register Name
Section
DC_BOOST
RX_SEN
This register is setting DC BOOST level.
This register is setting RX Sensitivity level.
Go
Go
0x25
Complex bit access types are encoded to fit into small table cells. Table 8-4 shows the codes that are used for
access types in this section.
Table 8-4. TUSB217A Access Type Codes
Access Type
Read Type
RH
Code
Description
H
R
Set or cleared by hardware
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
8.5.1 EDGE_BOOST Register (Offset = 0x1) [reset = X]
EDGE_BOOST is shown in Figure 8-1 and described in Table 8-5.
Return to Summary Table.
This register is setting EDGE BOOST level.
Figure 8-1. EDGE_BOOST Register
7
6
5
4
3
2
1
0
ACB_LVL
RH/W-X
RESERVED
RH/W-X
Table 8-5. EDGE_BOOST Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
ACB_LVL
RH/W
X
XXXXb (sampled at startup from BOOST pin)
0000b to 1111b range
0x0 = BOOST PIN LEVEL 0 (lowest edge boost setting)
0x3 = BOOST PIN LEVEL 1
0x6 = BOOST PIN LEVEL 2
0xA = BOOST PIN LEVEL 3
0xF = (highest edge boost setting)
3-0
RESERVED
RH/W
X
These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these
reserved bits and rewrite with the same values
8.5.2 CONFIGURATION Register (Offset = 0x3) [reset = X]
CONFIGURATION is shown in Figure 8-2 and described in Table 8-6.
Return to Summary Table.
This register is selecting device mode.
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Figure 8-2. CONFIGURATION Register
7
6
5
4
3
2
1
0
RESERVED
RH/W-X
CFG_ACTIVE
RH/W-0x1
Table 8-6. CONFIGURATION Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
RH/W
X
These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these
reserved bits and rewrite with the same values
0
CFG_ACTIVE
RH/W
0x1
Configuration mode
After reset, if I2C mode is true (SCL and SDA are both pulled high)
set the bit to get into configuration mode and clear to return to
normal mode.
0x0 = NORMAL MODE
0x1 = CONFIGURATION MODE
8.5.3 DC_BOOST Register (Offset = 0xE) [reset = X]
DC_BOOST is shown in Figure 8-3 and described in Table 8-7.
Return to Summary Table.
This register is setting DC BOOST level.
Figure 8-3. DC_BOOST Register
7
6
5
4
3
2
1
0
RESERVED
RH/W-X
DCB_LVL
RH/W-X
Table 8-7. DC_BOOST Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
RH/W
X
These bits are reserved bits and set by hardware at reset.
When this register is modified the software should first read these
reserved bits and rewrite with the same values
3-0
DCB_LVL
RH/W
X
XXXXb (sampled at startup from BOOST pin)
0000b to 1111b range
0x0 = BOOST PIN LEVEL 0 (lowest dc boost setting)
0x2 = BOOST PIN LEVEL 1 and 2
0x6 = BOOST PIN LEVEL 3
0xF = (highest dc boost setting)
8.5.4 RX_SEN Register (Offset = 0x25) [reset = X]
RX_SEN is shown in Figure 8-4 and described in Table 8-8.
Return to Summary Table.
This register is setting RX Sensitivity level.
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Figure 8-4. RX_SEN Register
7
6
5
4
3
2
1
0
RX_SEN
RH/W-X
Table 8-8. RX_SEN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RX_SEN
RH/W
X
XXXXb (sampled at startup from RX_SEN pin)
00000000b to 11111111b range
0x0 = RX_SEN LEVEL LOW
0x33 = RX_SEN LEVEL MID
0x66 = RX_SEN LEVEL HIGH
0xFF = (highest setting)
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The purpose of the TUSB217A is to re-store the signal integrity of a USB High-speed channel up to the USB
connector. The loss in signal quality stems from reduced channel bandwidth due to high loss PCB trace and
other components that contribute a capacitive load. This can cause the channel to fail the USB near end eye
mask. Proper use of the TUSB217A can help to pass this eye mask.
A secondary purpose is to use the CD pin of the TUSB217A to control other blocks on the customer platform, if
so desired.
9.2 Typical Application
A typical application for TUSB217A with dynamic mode change between DCP and CDP is shown in Figure 9-1.
BC 1.2 controller mode will be based on host/hub active state in this application. When host/hub is not active the
controller will be in DCP mode and when the host/hub is active the controller will be in CDP mode. Downstream
VBUS needs to be toggled by the power controller to change advertisement and for portable device to re-detect
the BC 1.2 controller charging mode. In this setup, D2P and D2M face the USB connector while D1P and D1M
face the USB host. The orientation may be reversed [that is, D2 faces transceiver and D1 faces connector]
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RBOOST
100 nF
BOOST
RSTZ
Connect
D1P and D2P
D1P
D2P
CON_D2P
CON_D2N
USB_D1P
USB_D1N
USB
Host or Hub
D2M
D1M
Connect
D1M and D2M
DCP/
CDP
VCC
VBUS
Downstream VBUS needs to
be toggled to change charging
sement
Supply
+3.3V or +5 V
VBUS Supplymode adver
GND
Ferrite Bead
100 @100MHz
Vcc
+5 V
1uF
(op onal)
100 nF
VCC
IN
A
B
Y
SN74AHC1G86
TPS2024
OUT
22 μF 0.1 μF
RRXSEN2
EN
RX_SEN/ENA_HS
VBUS TOGGLE
CIRCUIT
Upstream VBUS (5V+/-10%)
indica ng Host/Hub State
RRXSEN1
ꢀꢁ μF
Upstream VBUS Low -> DCP
Upstream VBUS High -> CDP
10 k
-1%
V-
–
22 k
+3.3V
TLV1701
+
5 k
+/-1%
75 k +/-
V+
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Figure 9-1. TUSB217A : A Reference Schematic (Design Example with DCP/CDP dynamic switching).
Downstream VBUS needs to be toggled if upstream VBUS state changes for BC 1.2 controller to change
DCP/CDP advertisement.
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9.2.1 Design Requirements
TUSB217A requires a valid reset signal as described in the power supply recommendations section. The
capacitor at RSTN pin is not required if a micro controller drives the RSTN pin according to recommendations.
For this design example, use the parameters shown in Table 9-1, Table 9-2 and Table 9-3
Table 9-1. Design Parameters for 5-V Supply With High Loss System
PARAMETER
VALUE(1)
5 V ±10%
No
VCC
I2C support required in system (Yes/No)
RBOOST
0-Ω
BOOST Level
0
Boost Level 1:
RBOOST = 1.8 kΩ
Edge and DC Boost
1.8 kΩ ±1%
3.6 kΩ ± 1%
1
2
3
Do Not Install (DNI)
RRXSEN2
RRXSEN1
RX_SEN Level
Low
High RX
Sensitivity Level:
RRXSEN1 = 37.5
kΩ
22 kΩ - 40 kΩ (27 kΩ typical)
Do Not Install (DNI)
Do Not Install (DNI)
Do Not Install (DNI)
RX Sensitivity
Medium
RRXSEN2 = 12.5
kΩ
37.5 kΩ(2)
12.5 kΩ
High
(1) These parameters are starting values for a high loss system. Further tuning might be required based on specific host and/or device as
well as cable length and loss profile. These settings are not specific to a 5V supply system could be applicable to 3.3V supply system
as well.
(2) This resistor is needed for a 5V supply to divide the voltage down so the RX_SEN pin voltage does not exceed 5.0V
Table 9-2. Design Parameters for 3.3-V Supply With Low to Medium Loss System
PARAMETER
VALUE(1)
3.3 V ±10%
No
VCC
I2C support required in system (Yes/No)
RBOOST
0-Ω
BOOST Level
0
Boost Level 0:
RBOOST = 0-Ω
Edge and DC Boost
1.8 kΩ ±1%
3.6 kΩ ±1%
1
2
3
Do Not Install (DNI)
RRXSEN2
RRXSEN1
RX_SEN Level
Low
Medium RX
Sensitivity Level:
RRXSEN1 = DNI
RRXSEN2 = DNI
22 kΩ - 40 kΩ (27 kΩ typical)
Do Not Install (DNI)
Do Not Install (DNI)
Do Not Install (DNI)
22 kΩ - 40 kΩ (27 kΩ typical)
RX Sensitivity
Medium
High
Do Not Install (DNI)
(1) These parameters are starting values for a low to medium loss system. Further tuning might be required based on specific host and/or
device as well as cable length and loss profile. These settings are not specific to a 3.3V supply system could be applicable to 5V
supply system as well.
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Table 9-3. Design Parameters for 2.3-V to 4.3-V VBAT Supply With Low to Medium Loss System
PARAMETER
VALUE(1)
VCC
2.3 V to 4.3V
No
I2C support required in system (Yes/No)
RBOOST
0-Ω
BOOST Level
0
Boost Level 0:
RBOOST = 0-Ω
Edge and DC Boost
1.8 kΩ ±1%
3.6 kΩ ±1%
1
2
3
Do Not Install (DNI)
RRXSEN2
RRXSEN1
RX_SEN Level
Low
Medium RX
Sensitivity Level:
RRXSEN1 = DNI
RRXSEN2 = DNI
22 kΩ - 40 kΩ (27 kΩ typical)
Do Not Install (DNI)
37.5 kΩ(2)
Do Not Install (DNI)
Do Not Install (DNI)
12.5 kΩ
RX Sensitivity
Medium
High
(1) These parameters are starting values for a low to medium loss system. Further tuning might be required based on specific host and/or
device as well as cable length and loss profile. These settings are not specific to a 2.3V-4.3V supply system could be applicable to 5V
supply system as well.
(2) This resistor is needed for a VBAT supply (2.3V - 4.3V) to divide the voltage down so the RX_SEN pin voltage does not exceed 5.0V
9.2.2 Detailed Design Procedure
The ideal BOOST setting is dependent upon the signal chain loss characteristics of the target platform. The
recommendation is to start with BOOST level 0, and then increment to BOOST level 1, and so on. Same applies
to the RX sensitivity setting where it is recommended to plan for the required pads or connections to change
boost settings, but to start with RX sensitivity level Low.
In order for the TUSB217A to recognize any change to the BOOST setting, the RSTN pin must be toggled. This
is because the BOOST pin is latched on power up and the pin is ignored thereafter.
Note
The TUSB217A compensates for extra attenuation in the signal path according to the configuration of
the RX_SEN pin. This maximum recommended voltage for this pin is 5 V when selecting the highest
RX sensitivity level.
Placement of the device is also dependent on the application goal. Table 9-4 summarizes our recommendations.
Table 9-4. Platform Placement Guideline
PLATFORM GOAL
Pass USB Near End Mask at the receptacle
Pass USB Far End Eye Mask at the plug
SUGGESTED TUSB217A PLACEMENT
Close to measurement point (connector)
Close to USB PHY
Cascade multiple TUSB217As to improve device enumeration
Midway between each USB interconnect
Table 9-5. Table of Recommended Settings
BOOST and RX_SEN settings (1)for channel loss
Pre-channel cable length (Between USB
PHY and TUSB217A)
BOOST
RX_SEN
0-3 meter
2-5 meter
Level 0
Level 1
Medium or High
Medium or High
Post-channel cable length (Between
TUSB217A and inter-connect)
BOOST
RX_SEN
0-2 meter
1-4 meter
Level 0
Level 1
Medium or High
Medium or High
(1) These parameters are starting values for different cable lengths. Further tuning might be required based on specific host and/or device
as well as cable length and loss profile.
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9.2.2.1 Test Procedure to Construct USB High-speed Eye Diagram
Note
USB-IF certification tests for High-speed eye masks require the mandated use of the USB-IF
developed test fixtures. These test fixtures do not require the use of oscilloscope probes. Instead
they use SMA cables. More information can be found at the USB-IF Compliance Updates Page. It is
located under the Electrical Specifications section, ID 86 dated March 2013.
The following procedure must be followed before using any oscilloscope compliance software to construct a USB
High-speed Eye Mask:
9.2.2.1.1 For a Host Side Application
1. Configure the TUSB217A to the desired BOOST setting
2. Power on (or toggle the RSTN pin if already powered on) the TUSB217A
3. Using SMA cables, connect the oscilloscope and the USB-IF host-side test fixture to the TUSB217A
4. Enable the host to transmit USB TEST_PACKET
5. Execute the oscilloscope USB compliance software.
6. Repeat the above steps in order to re-test TUSB217A with a different BOOST setting (must reset to change)
9.2.2.1.2 For a Device Side Application
1. Configure the TUSB217A to the desired BOOST setting
2. Power on (or toggle the RSTN pin if already powered on) the TUSB217A
3. Connect a USB host, the USB-IF device-side test fixture, and USB device to the TUSB217A. Ensure that the
USB-IF device test fixture is configured to the ‘INIT’ position
4. Allow the host to enumerate the device
5. Enable the device to transmit USB TEST_PACKET
6. Using SMA cables, connect the oscilloscope to the USB-IF device-side test fixture and ensure that the
device-side test fixture is configured to the ‘TEST’ position.
7. Execute the oscilloscope USB compliance software.
8. Repeat the above steps in order to re-test TUSB217A with a different BOOST setting (must reset to change)
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9.2.3 Application Curves
Redriver-EVM
Various
cable
lengths
Figure 9-2. Near End Eye Measurement Set-Up With Pre-Channel Cable
Figure 9-3. 2 Meter Pre-Channel Without
TUSB217A
Figure 9-4. 2 Meter Pre-Channel With TUSB217A
BOOST=1 RX_SEN=MED
Figure 9-5. 2 Meter Pre-Channel With TUSB217A
BOOST=0 RX_SEN=HIGH
Figure 9-6. 3 Meter Pre-Channel Without
TUSB217A
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Figure 9-7. 3 Meter Pre-Channel With TUSB217A
Figure 9-8. 5 Meter Without TUSB217A
BOOST=0 RX_SEN=HIGH
Figure 9-9. 5 Meter Pre-Channel With TUSB217A
BOOST=1 RX_SEN=MED
Figure 9-10. 5 Meter Pre-Channel With TUSB217A
BOOST=2 RX_SEN=MED
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Redriver-EVM
Various
cable
lengths
Figure 9-11. Near End Eye Measurement Set-Up With Post-Channel Cable
Figure 9-12. 6 Inches Post Channel Without
Figure 9-13. 6 Inches Post-Channel With
TUSB217A BOOST=0 RX_SEN=HIGH
TUSB217A
Figure 9-14. 1 Meter Post-Channel Without
TUSB217A
Figure 9-15. 1 Meter Post-Channel With TUSB217A
BOOST=0 RX_SEN=MED
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Figure 9-16. 1 Meter Post-Channel With TUSB217A
BOOST=0 RX_SEN=HIGH
Figure 9-17. 2 Meter Post-Channel Without
TUSB217A
Figure 9-18. 2 Meter Post-Channel With TUSB217A Figure 9-19. 2 Meter Post-Channel With TUSB217A
BOOST=1 RX_SEN=MED
BOOST=1 RX_SEN=HIGH
Figure 9-20. 4 Meter Post-Channel Without
TUSB217A
Figure 9-21. 4 Meter Post-Channel With TUSB217A
BOOST=2 RX_SEN=MED
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10 Power Supply Recommendations
On power up, the interaction of the RSTN pin and power on ramp could result in digital circuits not being set
correctly. The device should not be enabled until the power on ramp has settled to minimum recommended
supply voltage or higher to ensure a correct power on reset of the digital circuitry. If RSTN cannot be held low by
microcontroller or other circuitry until the power on ramp has settled, then an external capacitor from the RSTN
pin to GND is required to hold the device in the low power reset state.
The RC time constant should be larger than five times of the power on ramp time (0 to VCC). With a typical
internal pullup resistance of 500 kΩ, the recommended minimum external capacitance is calculated as:
[Ramp Time x 5] ÷ [500 kΩ]
(1)
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11 Layout
11.1 Layout Guidelines
Although the land pattern has matched trace width to pad width, optimal impedance control is based on the
user's own PCB stack-up. The recommendation is to maintain 90 Ω differential routing underneath the device.
11.2 Layout Example
Figure 11-1. Layout Example
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RWB0012A
X2QFN - 0.4 mm max height
SCALE 6.500
PLASTIC QUAD FLATPACK - NO LEAD
1.65
1.55
B
A
PIN 1 INDEX AREA
1.65
1.55
C
0.4 MAX
SEATING PLANE
0.05 C
2X 1.2
SYMM
(0.13)
TYP
0.05
0.00
6X 0.4
3
6
2
1
7
8
SYMM
2X
0.4
0.4
0.2
8X
12
9
0.25
0.15
12X
0.6
4X
0.4
0.07
0.05
C B A
C
4221631/B 07/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
RWB0012A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.3)
6X (0.4)
9
12
4X (0.7)
2X (0.4)
1
8
SYMM
(1.5)
7
2
8X (0.5)
3
6
SYMM
(R0.05) TYP
12X (0.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221631/B 07/2017
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RWB0012A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.3)
6X (0.4)
12
9
4X (0.67)
1
2
8
SYMM
(1.5)
2X (0.4)
7
8X
METAL
8X (0.5)
3
6
(R0.05) TYP
SYMM
12X (0.2)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PADS 1,2,7 & 8
96% PRINTED SOLDER COVERAGE BY AREA
SCALE:50X
4221631/B 07/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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13.1 Package Option Addendum
Packaging Information
Orderable Device
Status(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan(2) Lead/Ball
Finish(6)
MSL Peak Op Temp
Temp(3)
(°C)
Device
Marking(4) (5)
TUSB217ARWBR
PREVIEW
X2QFN
X2QFN
X2QFN
X2QFN
RWB
RWB
RWB
RWB
12
3000
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260 0 to 70
C-1 YEAR
7A
Green
(RoHS
& no Sb/Br)
TUSB217ARWBT
TUSB217AIRWBR
TUSB217AIRWBT
PREVIEW
PREVIEW
PREVIEW
12
12
12
250
Level-2-260 0 to 70
C-1 YEAR
7A
7A
7A
Green
(RoHS
& no Sb/Br)
3000
250
Level-2-260 -40 to 85
C-1 YEAR
Green
(RoHS
& no Sb/Br)
Level-2-260 -40 to 85
C-1 YEAR
Green
(RoHS
& no Sb/Br)
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