TSC2013QRSARQ1 [TI]
1.2V 至 3.6V、12 位、毫微功耗、4 线触摸屏控制器 | RSA | 16 | -40 to 125;
| 型号： | TSC2013QRSARQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.2V 至 3.6V、12 位、毫微功耗、4 线触摸屏控制器 | RSA | 16 | -40 to 125 控制器 |
| 文件： | 总70页 (文件大小：1517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TSC2013-Q1
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
TSC2013-Q1 具有 I2C 接口的 12 位、毫微功耗 4 线
双触摸屏控制器
1 特性
2 应用
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
•
•
•
•
•
汽车信息娱乐显示屏
汽车导航系统
工业用户界面
–
–
器件温度 1 级：-40°C 至 125°C 的
医疗设备
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
2
消费类便携电子产品
–
器件充电器件模型 (CDM) ESD 分类等级 C4B
3 说明
•
•
•
4 线制触摸屏界面
比例换算
TSC2013-Q1 器件是一款超低功耗双触摸屏控制器，
设计用于搭配汽车信息娱乐和导航系统中的功耗敏感型
低成本触摸显示屏使用。 其具有完整的超低功耗 12
位模数转换 (ADC) 电阻式触摸屏转换器，包括驱动器
和测量触摸压力的控制逻辑。
1.6V 至 3.6V 单电源：
–
–
I/OVDD 1.2V 至 3.6V
SNSVDD：1.6V 至 3.6V
•
•
•
•
通过预处理减少总线活动
高速 I2C 兼容接口
TSC2013-Q1 器件可通过标准四线制界面实现捏拉缩
放和旋转功能。 针对所有三种定义模式（标准、快速
与高速），该器件均支持 I2C 串行总线与数据传输协
议。 可轻松对 10 或 12 位范围内的 ADC 进行编程，
以实现对系统和用户体验的自定义。
屏幕触摸内部检测
基于寄存器可编程:
–
–
–
10 位或 12 位分辨率
采样速率
系统时序
器件信息(1)
•
•
•
触摸压力测量
自动断电控制
低功耗：
部件号
TSC2013-Q1
封装
PVQFN (16)
TSSOP (16)
封装尺寸（标称值）
4.00mm x 4.00mm
4.40mm × 5.00mm
–
–
–
1.8V，50SSPS 时为 430μA
1.6V，50SSPS 时为 320μA
1.6V，8.2kSPS（设备采样率） 时为 58μA
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
方框图
PENIRQ
SNSVDD/
VREF
PINTDAV
DAV
X+
SCL
Touch Screen
Driver
Interface
X±
SAR
ADC
SDA
AD0
2
MUX
Y+
I C Serial
Interface and
Control
Y±
AD1
AUX
Internal
Clock
RESET
SNSGND
R
(SENSE)
AGND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSC89
TSC2013-Q1
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configurations and Functions....................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 23
7.5 Programming........................................................... 29
7.6 Register Maps......................................................... 41
Application and Implementation ........................ 51
8.1 Application Information............................................ 51
8.2 Typical Application ................................................. 52
Power Supply Recommendations...................... 60
8
9
6.6 Timing Requirements — I2C Standard Mode (ƒ(SCL)
=
10 Layout................................................................... 60
10.1 Layout Guidelines ................................................. 60
10.2 Layout Example .................................................... 61
11 器件和文档支持 ..................................................... 61
11.1 商标....................................................................... 61
11.2 静电放电警告......................................................... 61
11.3 术语表 ................................................................... 61
12 机械封装和可订购信息 .......................................... 61
100 kHz) .................................................................... 7
6.7 Timing Requirements — I2C Fast Mode (ƒ(SCL) = 400
kHz) ........................................................................... 7
6.8 Timing Requirements — I2C High-Speed Mode
(ƒ(SCL) = 1.7 MHz)...................................................... 8
6.9 Timing Requirements — I2C High-Speed Mode
(ƒ(SCL) = 3.4 MHz) ..................................................... 8
6.10 Typical Characteristics.......................................... 10
4 修订历史记录
Changes from Original (June 2014) to Revision A
Page
•
•
发布了完整版数据表 ............................................................................................................................................................... 1
已更改 已将器件状态从产品预览更改为生产数据 ................................................................................................................... 1
2
Copyright © 2014, Texas Instruments Incorporated
TSC2013-Q1
www.ti.com.cn
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
5 Pin Configurations and Functions
16-Pin VQFN With Thermal Pad
RSA Package
16-Pin TSSOP
PW Package
Top View
Top View
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD0
SDA
SNSGND
Y–
SCL
X–
AD1
Y+
PINTDAV
RESET
DGND
I/OVDD
X+
13
14
15
16
8
7
6
AUX
X–
Y–
SNSVDD/VREF
AGND
I/OVDD
DGND
RESET
SNSGND
AD0
AUX
5
Pin Functions
PIN
I/O
ADC
DESCRIPTION
NAME
RSA
16
3
PW
1
AD0
I
D
D
I2C bus TSC address input bit 0
I2C bus TSC address input bit 1
AD1
4
I
AGND
AUX
9
10
9
—
—
—
A
Analog, digital, and ESD ground(1)
8
Auxiliary channel
No internal connection. Connect this pin to analog ground for mechanical
stability.
DGND
6
7
4
7
8
5
—
I
—
—
D
I/OVDD
Digital interface voltage
Interrupt output. Data available or the pen-detect interrupt (PENIRQ),
depending on setting. Pin polarity is active-low.
PINTDAV
O
RESET
SDA
5
6
I
I/O
I
D
D
D
—
—
A
External hardware reset input (active-low).
1
2
Serial data I/O
SCL
2
3
Serial clock
SNSGND
15
10
11
13
12
14
16
11
12
14
13
15
—
I
Sensor driver return
SNSVDD/VREF
Power supply for sensor drivers and other analog blocks
X+
X–
Y+
Y–
—
—
—
—
X+ channel
X– channel
Y+ channel
Y– channel
A
A
A
(1) For optimized system IEC ESD performance, contact Texas Instruments for schematic and layout reviews and suggestions.
Copyright © 2014, Texas Instruments Incorporated
3
TSC2013-Q1
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range (unless otherwise noted).
MIN
–0.4
–0.4
–0.3
–0.3
–0.3
–2.4
–0.3
–0.3
MAX
UNIT
V
Analog input X+, Y+, AUX to SNSGND
Analog input X–, Y– to SNSGND
SNSVDD + 0.1
SNSVDD + 0.1
V
SNSVDD to SNSGND
5
V
Voltage
SNSVDD to AGND
5
V
I/OVDD to AGND
SNSVDD to I/OVDD
5
V
0.3
V
Digital input voltage to AGND
Digital output voltage to AGND
Power dissipation
I/OVDD + 0.3
I/OVDD + 0.3
V
V
(TJmax – TA) / RθJA
Operating free-air temperature range, TA
Junction temperature, TJmax
–40
125
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
–65
MAX
150
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per AEC Q100-002(1)
Corner pins (RSA: 1, 4, 5,
–2000
2000
V(ESD)
Electrostatic discharge
8, 9, 12, 13, and 16;
PW: 1, 8, 9, and 16)
–750
750
V
Charged device model (CDM),
per AEC Q100-011
Other pins
–500
–15
500
15
IEC contact discharge(2)
IEC air discharge(2)
X+, X–, Y+, Y–
X+, X–, Y+, Y–
kV
kV
–25
25
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Test method based on IEC standard 61000-4-2. Contact Texas Instruments for test details.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
NOM
3.3
MAX
UNIT
Input voltage SNSVDD/VR
Input voltage I/OVDD
3.6
3.6
V
V
1.2
3.3
6.4 Thermal Information
RSA
PW
THERMAL METRIC(1)
UNIT
16 PINS
33.7
36.7
10.5
0.6
16 PINS
100.9
36.1
45.7
2.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
10.5
2.5
45.1
—
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
版权 © 2014, Texas Instruments Incorporated
TSC2013-Q1
www.ti.com.cn
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
6.5 Electrical Characteristics
At TA = –40°C to 125°C, V(SNSVDD/VREF) = 1.6 V to 3.6 V, and V(I/OVDD)(1) = 1.2 V to V(SNSVDD/VREF), unless otherwise noted.
PARAMETER
AUXILIARY ANALOG INPUT
Input voltage
TEST CONDITIONS
MIN
TYP
MAX
Vref
1
UNIT
0
V
Input capacitance
12
2
pF
μA
μA
Input leakage current
No ADC conversion
–1
Full-scale average input current
V(SNSVDD/VREF) = 1.6 V, continuous AUX, ƒ(ADC) = 2 MHz
ADC
Resolution
Programmable: 10 or 12 bits
12
Bits
Bits
No missing codes
Integral linearity
Differential linearity
Offset error
12-bit resolution
11
12-bit resolution mode, ƒ(ADC) = 2 MHz
12-bit resolution mode, fADC = 2MHz
V(SNSVDD/VREF) = 1.6 V, 12-bit mode, ƒ(ADC) = 2 MHz, filter off
V(SNSVDD/VREF) = 1.6 V, 12-bit mode, ƒ(ADC) = 2 MHz, filter off
–3 –0.5 to 0.5
3
4
LSB(2)
LSB
LSB
LSB
–2 –0.5 to 0.5
0.2
2
Gain error
Data format
Straight binary
REFERENCE INPUT
Vref range
1.6
V(SNSVDD/VREF)
V
SNSVDD/VREF input-current drain
Input impedance
TOUCH SENSORS
X+ 50-kΩ pullup resistor, R(IRQ)
Y+, X+
Y–, X–
Switch drivers drive current
INTERNAL OSCILLATOR
Continuous AUX mode, V(SNSVDD/VREF) = 1.6 V, ƒ(ADC) = 2 MHz
No ADC conversion
5
μA
MΩ
> 100
52
7
kΩ
Ω
TA = 25°C, V(SNSVDD/VREF) = 1.6 V
TA = 25°C, V(SNSVDD/VREF) = 1.6 V
100-ms duration
Switch on-resistance
5
Ω
50
mA
V(SNSVDD/VREF) = 1.6 V, TA = 25°C
V(SNSVDD/VREF) = 3 V, TA = 25°C
V(SNSVDD/VREF) = 1.6 V
3.3
3.7
3.8
4.3
MHz
MHz
%/°C
%/°C
ƒ(OSC)
Clock frequency
Frequency drift
–0.008
–0.021
V(SNSVDD/VREF) = 3 V
DIGITAL INPUT/OUTPUT
Logic family
CMOS
0.7 ×
V(I/OVDD)
VIH
Input-voltage logic-level high
1.2 V ≤ V(I/OVDD) < 3 V
1.2 V ≤ V(I/OVDD) < 3 V
3.6
V
VIL
Input-voltage logic-level low
–0.3
–1
0.2 × V(I/OVDD)
V
IIL, IIH
CI
Input-current logic-level low and high
Input-capacitance logic level
1
μA
pF
10
V(I/OVDD)
– 0.2
VOH
Output-voltage logic-level high
IOH = 100 μA
V(I/OVDD)
V
VOL
Ilkg
Output-voltage logic-level low
Leakage-current logic level
Output-capacitance logic level
IOL = –3.2 mA
SDA
0
0.2
1
V
–1
μA
pF
CO
SDA
10
POWER-SUPPLY REQUIREMENTS
Power-supply voltage
SNSVDD
1.6
1.2
3
V
V
I/OVDD(1)
V(SNSVDD/VREF)
(1) I/OVDD must be ≤ SNSVDD.
(2) LSB means least-significant bit. With SNSVDD/VREF= 2.5 V, one LSB is 610 μV.
版权 © 2014, Texas Instruments Incorporated
5
TSC2013-Q1
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
www.ti.com.cn
Electrical Characteristics (接下页)
(1)
At TA = –40°C to 125°C, V(SNSVDD/VREF) = 1.6 V to 3.6 V, and V(I/OVDD) = 1.2 V to V(SNSVDD/VREF), unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C, filter off, M = W = 1, C[3:0] = (1, 0,
0, 0), RM = 1, CL[1:0] = (0, 1), cont AUX
mode, ƒ(ADC) = 2 MHz, without reading data
register
V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V
420
570
μA
TA = 25°C, filter on, M = 15, W = 7, PSM = 1,
C[3:0] = (0, 0, 0, 0), RM = 1, CL[1:0] = (0, 1),
BTD[2:0] = (1, 0, 1), 50 SSPS, MAVEX =
MAVEY = MAVEZ = 1, ƒ(ADC) = 2 MHz, sensor
drivers supply included(5)
V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V
V(SNSVDD/VREF) = V(I/OVDD) = 3 V
V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V
V(SNSVDD/VREF) = V(I/OVDD) = 3 V
200
400
180
370
μA
μA
μA
μA
TA = 25°C, filter off, M = W = 1, PSM = 1,
C[3:0] = (0, 0, 0, 0), RM = 1, CL[1:0] = (0, 1),
BTD[2:0] = (1, 0, 1), 50 SSPS, MAVEX =
MAVEY = MAVEZ = 1, ƒ(ADC) = 2 MHz, sensor
drivers supply included(5)
V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V,
approximately 28 kSPS effective
rate
190
370
355
655
36.2
64.9
μA
μA
μA
μA
μA
μA
Quiescent supply
current(3)(4)
TA = 25°C, filter off, M = W = 1, C[3:0] = (0, 1,
0, 1), RM = 1, CL[1:0] = (0, 1), non-cont AUX
mode, ƒ(ADC) = 2 MHz, high-speed mode
V(SNSVDD/VREF) = V(I/OVDD) = 3 V,
approximately 28.4 kSPS
effective rate
V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V,
approximately 10.5 kSPS
effective rate
TA = 25°C, filter on, M = 7, W = 3, C[3:0] = (0,
1, 0, 1), RM = 1, CL[1:0] = (0, 1), MAVEAUX
= 1, non-cont AUX mode, ƒ(ADC) = 2 MHz,
high-speed mode, full speed
V(SNSVDD/VREF) = V(I/OVDD) = 3 V,
approximately 10.9 kSPS
effective rate
V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V,
approximately 1.17 kSPS
effective rate
TA = 25°C, filter on, M = 7, W = 3, C[3:0] = (0,
1, 0, 1), RM = 1, CL[1:0] = (0, 1), MAVEAUX
= 1, non-cont AUX mode, ƒ(ADC) = 2 MHz,
high-speed mode, reduced speed (8.2-kSPS
equivalent rate)
V(SNSVDD/VREF) = V(I/OVDD) = 3 V,
approximately 1.17 kSPS
effective rate
TA = 25°C, not addressed, SCL = SDA = 1, RESET = 1,
PINTDAV = 1, V(SNSVDD/VREF) = I/OVDD = Vref = 1.6 V
Power-down supply current
0.04
0.04
0.8
0.8
μA
μA
TA = 25°C, not addressed, SCL = SDA = 1, RESET = 1,
PINTDAV = 1, V(SNSVDD/VREF) = V(I/OVDD) = Vref = 1.6 V
Digital power-down supply current
(3) Supply current from SNSVDD.
(4) For detailed information on test condition parameter and bit settings, see the section.
(5) Touch sensor modeled by 2 kΩ for X– plane and Y– plane, and 1 kΩ for Z-plane (touch resistance).
6
版权 © 2014, Texas Instruments Incorporated
TSC2013-Q1
www.ti.com.cn
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
6.6 Timing Requirements — I2C Standard Mode (ƒ(SCL) = 100 kHz)
All specifications typical at –40°C to 125°C, V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V to 3 V, unless otherwise noted.
MIN
MAX
UNIT
μs
t(WL_RESET) Reset low time(1)
See 图 1 and 图 37
10
ƒ(SCL)
t(BUF)
SCL clock frequency
100
kHz
Bus free time between a STOP and START
condition
4.7
μs
th(STA)
t(LOW)
t(HIGH)
tsu(STA)
th(DAT)
tsu(DAT)
tr
Hold time for (repeated) START condition
Low period of SCL clock
4
4.7
4
μs
μs
μs
μs
μs
ns
ns
ns
μs
pF
See 图 1
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
4.7
0
3.45
Data setup time
250
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Capacitive load for each bus line
1000
300
C(b) = total bus capacitance
See 图 1
tf
tsu(STO)
C(b)
See 图 1
4
C(b) = total capacitance of one bus line in pF
400
N/A
Pulse duration of spikes that must be
suppressed by the input filter
td(SP)
N/A
ns
(1)
V(SNSVDD/VREF) ≥ 1.6 V
6.7 Timing Requirements — I2C Fast Mode (ƒ(SCL) = 400 kHz)
All specifications typical at –40°C to 125°C, V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V to 3 V, unless otherwise noted.
MIN
MAX
UNIT
μs
t(WL_RESET) Reset low time(1)
See 图 1 and 图 37
10
ƒ(SCL)
t(BUF)
SCL clock frequency
400
kHz
Bus free time between a STOP and START
condition
1.3
μs
th(STA)
t(LOW)
t(HIGH)
tsu(STA)
th(DAT)
tsu(DAT)
tr
Hold time for (repeated) START condition
Low period of SCL clock
0.6
μs
μs
μs
μs
μs
ns
ns
ns
μs
pF
1.3
See 图 1
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
0.6
0.6
0
100
0.9
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals(2)
Setup time for STOP condition
Capacitive load for each bus line
20 + 0.1 × C(b)
20 + 0.1 × C(b)
0.6
300
300
C(b) = total bus capacitance
See 图 1
tf
tsu(STO)
C(b)
See 图 1
C(b) = total capacitance of one bus line in pF
400
50
Pulse duration of spikes that must be
suppressed by the input filter
td(SP)
0
ns
(1)
V(SNSVDD/VREF) ≥ 1.6 V
(2) C(b) = the total capacitance of one bus line in pF. If using both fast-mode and Hs-mode devices, one may use faster fall times according
to the Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 3.4 MHz) section. Note that the TSC2013-Q1 device is an Hs-mode
device and follows the table requirements listed in the Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 3.4 MHz) section.
版权 © 2014, Texas Instruments Incorporated
7
TSC2013-Q1
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
www.ti.com.cn
6.8 Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 1.7 MHz)
All specifications typical at –40°C to 125°C, V(SNSVDD/VREF) = V(I/OVDD) = to 3 V, unless otherwise noted.
MIN
MAX
UNIT
μs
t(WL_RESET) Reset low time(1)
See 图 2 and 图 37
10
ƒ(SCL)
th(STA)
t(LOW)
t(HIGH)
tsu(STA)
th(DAT)
tsu(DAT)
tr(CL)
SCL clock frequency
1.7
MHz
ns
Hold time of (repeated) START condition
Low period of SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
160
320
120
160
0
ns
ns
See 图 2
ns
150
ns
Data setup time
10
20
20
20
1
ns
Rise time of SCL signal
Rise time of SDA signal
Fall time of SCL signal
80
160
80
ns
tr(DA)
ns
tf(CL)
C(b) = total bus capacitance(2)
图 2
ns
tf(DA)
Fall time of SDA signal
160
ns
Rise time of SCL signal after a repeated START
condition and after an acknowledge bit
tr(CL1)
20
160
ns
tsu(STO)
C(b)
Setup time for STOP condition
Capacitive load for each bus line
See 图 2
160
ns
C(b) = total capacitance of one bus line in pF
400
10
pF
Pulse duration of spikes that must be
suppressed by the input filter
td(SP)
0
ns
(1)
V(SNSVDD/VREF) ≥ 1.6 V
(2) For capacitive bus loads between 100 pF and 400 pF, interpolate the rise-time and fall-time values linearly.
6.9 Timing Requirements — I2C High-Speed Mode (ƒ(SCL) = 3.4 MHz)
All specifications typical at –40°C to 125°C, V(SNSVDD/VREF) = V(I/OVDD) = 1.6 V(1) to 3 V, unless otherwise noted.
MIN
MAX
UNIT
μs
t(WL_RESET) Reset low time(2)
See 图 2 and 图 37
10
ƒ(SCL)
th(STA)
t(LOW)
t(HIGH)
tsu(STA)
th(DAT)
tsu(DAT)
tr(CL)
SCL clock frequency
3.4
MHz
ns
Hold time for (repeated) START condition
Low period of SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
160
160
60
160
0
ns
ns
See 图 2
ns
70
ns
Data setup time
10
10
10
10
1
ns
Rise time of SCL signal
Rise time of SDA signal
Fall time of SCL signal
40
80
40
80
ns
tr(DA)
ns
tf(CL)
C(b) = total bus capacitance(3)
See 图 2
ns
tf(DA)
Fall time of SDA signal
ns
Rise time of SCL signal after a repeated START
condition and after an acknowledge bit
tr(CL1)
10
80
ns
tsu(STO)
C(b)
Setup time for STOP condition
Capacitive load for each bus line
See 图 2
160
ns
C(b) = total capacitance of one bus line in pF
100
10
pF
Pulse duration of spikes that must be
suppressed by the input filter
td(SP)
0
ns
(1) Because of the low supply voltage of 1.2 V and the wide temperature range of –40°C to 125°C, the I2C system devices may not reach
the maximum specification of I2C high-speed mode, and ƒ(SCL) may not reach 3.4 MHz.
(2)
V(SNSVDD/VREF) ≥ 1.6 V
(3) Capacitive load from 10 pF to 100 pF.
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S
Sr
P
S
SDA
tsu(STA)
tsu(DAT)
t(BUF)
th(STA)
th(DAT)
t(LOW)
tsu(STO)
SCL
th(STA)
t(HIGH)
tr
tf
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
= Resistor Pull Up
图 1. Detailed I/O Timing for Standard and Fast Modes
Sr
Sr
P
tf(DA)
tr(DA)
SDA
th(DAT)
tsu(STO)
tsu(STA)
th(STA)
tsu(DAT)
SCL
tf(CL)
(1)
(1)
tr(CL1)
tr(CL)
t(LOW)
tr(CL1)
t(HIGH)
t(HIGH)
t(LOW)
= Current Source Pull Up
= Resistor Pull Up
Sr = Repeated START Condition
P = STOP Condition
(1) The First rising edge of the SCL signal after Sr and after each acknowledge bit.
图 2. Detailed I/O Timing for High-Speed Mode
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6.10 Typical Characteristics
At TA = –40°C to 125°C, SNSVDD/VREF = 1.6 V to 3 V, I/OVDD = 1.2 V to SNSVDD/VREF, ƒ(ADC) = ƒ(OSC) / 2, high-speed
mode (ƒ(SCL) = 3.4 MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
1.5
1
1.5
1
V(SNSVDD) = 1.2 V
(SNSVDD) = 1.6 V
V(SNSVDD) = 3 V
V(I/OVDD) = 1.2 V
(I/OVDD) = 1.6 V
V(I/OVDD) = 3 V
V
V
0.5
0
0.5
0
–0.5
–1
–0.5
–1
–1.5
–1.5
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
图 3. Change in Offset vs Temperature
图 4. Change in Gain vs Temperature
450
400
350
300
250
200
150
100
50
0.6
0.5
0.4
0.3
0.2
0.1
0
ƒ(ADC) = 1 MHZ
ƒ(SAMPLE) = 23 kHz
ƒ(ADC) = 2 MHZ
ƒ(SAMPLE) = 28 kHz
V(SNSVDD) = 1.6 V
V(SNSVDD) = 3 V
-40
-20
0
20
40
60
80
100
1.2
1.6
2.0
2.4
2.8
3.2
3.6
Temperature (°C)
Supply Voltage (V)
M = 1
W = 1 (See 表 1)
AUX non-continuous mode
ƒ(SAMPLE) = 28 kHz
TA = 25° C
图 5. SNSVDD Supply Current vs Temperature
图 6. SNSVDD Supply Current vs SNSVDD Supply Voltage
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1400
M = 5, W = 7
M = 1, W = 1
V(SNSVDD) = 1.6 V
1200
1000
800
600
400
200
0
V(SNSVDD) = 3 V
1.2
1.6
2.0
2.4
2.8
3.2
3.6
-40
-20
0
20
40
60
80
100
Supply Voltage (V)
Temperature (°C)
t(PVS), t(PRE), t(SNS) = default values
TSC-initiated mode scan X, Y, and Z at 50SSPS
Touch sensor modeled by: 2 kΩ for X-plane and Y-plane and 1 kΩ
for Z (touch resistance, See 图 14)
图 7. Supply Current vs Supply Voltage, TA = 25° C
图 8. Power-Down Supply Current vs Temperature
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Typical Characteristics (接下页)
At TA = –40°C to 125°C, SNSVDD/VREF = 1.6 V to 3 V, I/OVDD = 1.2 V to SNSVDD/VREF, ƒ(ADC) = ƒ(OSC) / 2, high-speed
mode (ƒ(SCL) = 3.4 MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
100
80
60
40
20
0
45
40
35
30
25
20
15
10
5
V(I/OVDD) = 1.2 V
(I/OVDD) = 1.6 V
V(I/OVDD) = 3 V
V
SNSVDD
0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
–40
–20
0
20
40
60
80
100
Supply Voltage (V)
Temperature (°C)
TA = 25°C
I/OVDD = SNSVDD/VREF
图 9. Power-Down Supply Current vs Supply Voltage
图 10. I/OVDD Supply Current vs Temperature
60
10
8
50
40
30
20
10
0
6
4
2
V(SNSVDD) = 1.6 V
V(SNSVDD) = 3 V
0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
-40
-20
0
20
40
60
80
100
Voltage (V)
Temperature (°C)
IOVDD = SNSVDD/VREF
ƒ(SAMPLE) = 28 kHz
IOVDD = SNSVDD/VREF
AUX continuous mode
图 11. I/OVDD Supply Current vs I/OVDD Supply Voltage
图 12. Reference Input Current vs Temperature
14
12
10
8
6
4
2
0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
Voltage (V)
IOVDD = SNSVDD/VREF
TA = 25°C
AUX continuous mode
图 13. Reference Input Current vs SNSVDD Supply Voltage
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7 Detailed Description
7.1 Overview
The TSC2013-Q1 device is an analog interface circuit for a human-interface touch-screen device. A register-
based architecture eases integration with microprocessor-based systems through a standard I2C bus. Registers
and onboard state machines control all peripheral functions. The TSC2013-Q1 features include:
•
•
•
Very low-power touch-screen controller
Very small onboard footprint
Flexible preprocessing which relieves the host from tedious routine tasks and saves resources for more
critical tasks
•
•
•
•
•
Ability to work on very low supply voltage
Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required
Enhanced ESD protection
Panel-current sensing
Miniature device, yet complete; requires no external supporting components
注
Although the TSC2013-Q1 device can use an external reference, the SNSVDD/VREF pin
can also be used as the reference.
The TSC2013-Q1 device consists of the following blocks (see the Functional Block Diagram section):
•
•
•
•
•
Touch-screen interface
Auxiliary input (AUX)
Acquisition-activity preprocessing
Internal conversion clock
I2C interface
Communication with the TSC2013-Q1 device is through an I2C serial interface. The TSC2013-Q1 device is an
I2C slave device. Therefore, data shifts into or out of the TSC2013-Q1 device under the control of the host
microprocessor, which also provides the serial data clock.
Writing to different registers in the TSC2013-Q1 device controls the TSC2013-Q1 device and device functions.
The use of a simple command protocol (compatible with I2C) addresses these registers. This protocol can be an
I2C write-address followed by multiple control bytes, or multiple combinations of control and data bytes for writing
into different registers (two bytes each). To read from registers, write an I2C read-address to the TSC2013-Q1
device, followed by one or multiple sequential reads from the registers.
The host writes the address of the register to be read in control byte 0 with the register address and read-bit (as
described in the previous paragraph). The register address serves as a pointer to the register map where the first
read starts. This designated register address is static and a write to a register address does not need to occur
again unless a new register address has overwritten it or after a TSC2013-Q1 reset (by a software reset or by
the RESET pin).
The touch-measurement result goes into the TSC2013-Q1 registers, from which the host may read it at any time.
This preprocessing frees up the host in order to allocate resources to more-critical tasks. Two optional signals
are also available from the TSC2013-Q1 device to indicate that data are available for the host to read. The
PINTDAV pin is a programmable interrupt or status output pin. With the PINTDAV pin programmed as a DAV
output, the pin indicates that an ADC conversion has completed and that data are available. With the PINTDAV
pin programmed as a PENIRQ output, the pin indicates the detection of a touch on the touch screen. The status
register of the TSC2013-Q1 device provides an extended status reading, including the state of the DAV and
PENIRQ outputs, without the cost of any dedicated pin. See 图 14 for a typical application of the TSC2013-Q1
device.
To detect two touches, add an external R(SENSE) resistor as shown in 图 14. The value of R(SENSE) depends on the
touch-panel resistance. The ratio between the lowest touch-panel resistance and R(SENSE) should be
approximately 4.5.
12
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Overview (接下页)
1.6 VDC
1 µF
0.1 µF
1.6 VDC
AGND
Host
1.2 kΩ
1.2 kΩ
Processor
PINTDAV
RESET
SDA
GPIO
GPIO
SDA
SCL
X+
Y+
TSC2013-Q1
X–
Y–
SCL
Touch
Screen
(PINTDAV is optional;
software implementation
polling of the Status register is
possible)
AGND
R(SENSE)
47 Ω
图 14. Typical Circuit Configuration
7.2 Functional Block Diagram
PENIRQ
SNSVDD/
VREF
PINTDAV
DAV
X+
SCL
Touch Screen
Driver
Interface
X±
SAR
ADC
SDA
AD0
2
MUX
Y+
I C Serial
Interface and
Control
Y±
AD1
AUX
Internal
Clock
RESET
SNSGND
R
(SENSE)
AGND
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7.3 Feature Description
7.3.1 Touch-Screen Operation
A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in
resistance at a given point on the matrix where an input (stylus, pen, or finger) touches the screen. The change
in the resistance ratio marks the location on the touch screen.
The TSC2013-Q1 device supports resistive 4-wire configurations as shown in 图 15. The circuit determines
location in two coordinate-pair dimensions, although addition of a third dimension for measuring pressure is
possible.
7.3.2 4-Wire Touch Screen Measurements
图 15 shows construction of a typical four-wire touch screen. The screen consists of two transparent resistive
layers separated by insulating spacers.
Conductive Bar
Transparent Conductor (ITO)
Bottom Side
Y+
X+
Silver
Transparent
Conductor (ITO)
Top Side
Ink
X-
Y-
Insulating Material (Glass)
ITO = Indium Tin Oxide
图 15. Four-Wire Touch Screen Construction
The four-wire touch-screen panel works by applying a voltage across the vertical or horizontal resistive network.
To determine a touch location, the TSC2013-Q1 device provides a set of eight data measurements (X1, X2, IX,
Y1, Y2, IY, Z1, and Z2). 图 17 through 图 19 show the internal ADC configurations. Taking an X1 measurement
involves activating the X+ and X– drivers and digitizing the voltage at Y+. The R(SENSE) resistor must be
connected as shown in 图 14. The SNSGND and AUX pins connect to one end of R(SENSE), and the other end
connects to the AGND pin.
The TSC2013-Q1 device can also measure touch pressure (Z). To determine a pen or finger touch,
determination of the pressure of the touch is required. Generally, having very high performance for this test is not
necessary. Therefore, TI recommends 10-bit resolution mode. Several different ways of performing this
measurement are available. The TSC2013-Q1 device supports two methods. The first method requires knowing
the X-plate resistance, the measurement of X1, and two additional cross-panel measurements (Z2 and Z1) of the
touch screen (see 图 16). 公式 1 calculates the touch resistance (R(TOUCH)).
X1
Z2
Z1
§
·
R(TOUCH) RX(PLATE)
u
u
ꢀ1
¸
¨
©
4096
¹
(1)
The second method requires knowing both the X-plate and Y-plate resistance, and the measurement of X1, Y1,
and Z1. 公式 2 also calculates the touch resistance.
RX(PLATE)
4096
Z1
Y1
§
·
§
·
R(TOUCH)
ꢀ1 ꢀRY(PLATE) u 1ꢀ
¸ ¨
¨
©
¸
¹
4096
4096
¹
©
(2)
14
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Feature Description (接下页)
Measure X1
X+
Y+
Touch
X1-Position
X–
Y–
Measure Z1-Position
Y+
X+
Touch
Z1-Position
X–
Y–
Y+
X+
Touch
Z2-Position
X–
Y–
Measure Z2-Position
图 16. Pressure Measurement
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Feature Description (接下页)
X1 Measurement
X2 Measurement
X+
X+
+REF
+REF
Y+
Y-
+IN
+IN
Converter
Converter
-IN
-IN
-REF
-REF
X–
X–
X+, X– drivers are On
X+, X– drivers are On
IX Measurement
VREF
+REF
AUX
+IN
Converter
-IN
-REF
AGND
X+, X– drivers are On
图 17. X-Coordinate Differential-Triplet Measurement (X1, X2, IX)
16
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Feature Description (接下页)
Y1 Measurement
Y2 Measurement
Y+
Y+
+REF
+REF
X+
X-
+IN
+IN
Converter
Converter
-IN
-IN
-REF
-REF
Y-
Y-
Y+, Y– drivers are On
Y+, Y– drivers are On
IY Measurement
VREF
+REF
AUX
+IN
Converter
-IN
-REF
AGND
Y+, Y– drivers are On
图 18. Y-Coordinate-Differential-Triplet Measurement (Y1, Y2, IY)
Z1 Measurement
Z2 Measurement
Y+
Y+
+REF
+REF
X+
Y-
+IN
+IN
Converter
Converter
-IN
-IN
-REF
-REF
X–
X–
X–, Y+ drivers are On
X–, Y+ drivers are On
图 19. Z-Measurement (Z1, Z2)
When touching or pressing the touch panel with the drivers to the panel turned on, the voltage across the touch
panel often overshoots and then slowly settles down (decays) to a stable DC value. This effect is a result of
mechanical bouncing caused by vibration of the top-layer sheet of the touch panel when pressing the panel.
Without accounting for this settling time, the converted value is in error. Therefore, introducing a delay between
the time the driver for a particular measurement is turned on and the time a measurement is made is necessary.
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Feature Description (接下页)
In some applications, external capacitors may be required across the touch screen for filtering noise picked up by
the touch screen (such as noise generated by the LCD panel or back-light circuitry). The value of these
capacitors provides a low-pass filter to reduce noise, but causes an additional settling-time requirement when the
panel is touched.
The TSC2013-Q1 device offers several solutions to this problem. A programmable delay time is available that
sets the delay between turning the drivers on and making a conversion. The TSC2013-Q1 device uses this
delay, referred to as the panel voltage-stabilization time, in some of the device modes. In other modes,
commands can cause the TSC2013-Q1 device to turn on the drivers only without performing a conversion.
Issuing the command to perform a conversion occurs after allowing sufficient stabilization time.
The TSC2013-Q1 touch-screen interface can measure different data sets. Determination of these measurements
is possible under three different modes of the ADC:
•
•
TSMode1: conversion controlled by the TSC2013-Q1 device and initiated by the touchscreen controller (TSC)
TSMode2: conversion controlled by the TSC2013-Q1 device and initiated by the host responding to the
PENIRQ signal
•
TSMode3: conversion completely controlled by the host processor
7.3.3 Analog-to-Digital Converter
图 20 shows the analog inputs of the TSC2013-Q1 device. A multipexer provides the analog inputs (X, Y, and Z
touch panel coordinates and auxiliary inputs) to the successive-approximation register (SAR) analog-to-digital
converter (ADC). The basis of ADC architecture is capacitive redistribution architecture, which inherently includes
a sample-and-hold function.
SNSVDD/VREF
PINTDAV
SNSVDD
Level Shift
(1)
R(IRQ)
50 kΩ
Preprocessing
Data
Pen Touch
Available
Zone
Control
Logic
Detect
MAV
SNSVDD
C3-C0
X+
X–
SNSVDD
Y+
Y–
+REF
+IN
Converter
–REF
–IN
SNSGND
AUX
AGND
R(SENSE)
(1) Untrimmed resistor; see the typical value in the table.
图 20. Simplified Diagram of the Analog Input Section
18
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Feature Description (接下页)
A unique configuration of low on-resistance switches allows an unselected ADC input channel to provide power
and an accompanying pin to provide ground for driving the touch panel. By maintaining a differential input to the
converter and a differential reference input architecture, negating errors caused by the on-resistance of the driver
switches is possible.
Two ADC-control registers control the ADC. Several modes of operation are possible, depending on the bits set
in the control registers. Programming of channel selection, scan operation, preprocessing, resolution, and
conversion rate is through these registers. The following sections outline these modes for each type of analog
input. The appropriate result register stores the conversion results.
7.3.3.1 Data Format
The TSC2013-Q1 output data are in straight binary format as shown in 图 21. 图 21 shows the ideal output code
for the given input voltage and does not include the effects of offset, gain, or noise.
(1)
VFS = Full-Scale Voltage = Vref
1 LSB = Vref(1) / 4096
1 LSB
11...111
11...110
11...101
00...010
00...001
00...000
0 V
FS - 1 LSB
Input Voltage(2) (V)
(1) Reference voltage at converter: +REF – (–REF). See 图 20.
(2) Input voltage at converter, after multiplexer: +IN – (–IN). See 图 20.
图 21. Ideal Input Voltages and Output Codes
7.3.3.2 Reference
The TSC2013-Q1 device uses an external voltage reference applied to the SNSVDD/VREF pin. Using the
SNSVDD/VREF pin as the reference voltage is possible because the upper reference voltage range is the same
as the supply-voltage range.
7.3.3.3 Variable Resolution
The TSC2013-Q1 device provides either 10-bit or 12-bit resolution for the ADC. Lower resolution is often
practical for measuring slow-changing signals such as touch pressure. Performing the conversions at lower
resolution reduces the amount of time required for the ADC to complete the conversion process which also
lowers power consumption.
7.3.3.4 Conversion Clock and Conversion Time
The TSC2013-Q1 device contains an internal clock (oscillator) that drives the internal state machines that
perform the many functions of the part. This clock is divided down to provide a conversion clock for the ADC.
The setting for the division ratio of this clock is in the ADC control register (see Configuration Register 0 (address
= 0) [reset = 4000h for read; 0000h for write]). The ability to change the conversion clock rate allows the user to
select the optimal values for resolution, speed, and power dissipation. Using the 4-MHz (oscillator) clock directly
as the ADC clock (when the CL[1:0] bit is set to 0) limits the ADC resolution to 10 bits. Using higher resolutions
at this speed does not result in more accurate conversions. Twelve-bit resolution requires that the CL bits 1 and
0 are set to 0 and 1, or 1 and 0 (respectively).
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Feature Description (接下页)
Regardless of the conversion clock speed, the internal clock runs nominally at 3.8 MHz at a 3-V supply
(SNSVDD) and slows down to 3.6 MHz at a 1.6-V supply. The conversion time of the TSC2013-Q1 device
depends on several functions. The conversion clock speed plays an important role in the time required for a
conversion to complete. However, proper sampling of the signal requires a certain number of internal clock
cycles. Moreover, additional times (such as the panel voltage-stabilization time), can add significantly to the time
it takes to perform a conversion. Conversion time can vary depending on the mode of use of TSC2013-Q1
device. This data sheet makes use of internal and conversion clock cycles throughout as the units used to
describe the amount of time that many functions take. Take these times into account when considering the total
system design.
7.3.3.5 Touch Detect
The PINTDAV pin can be programmed to generate an interrupt to the host. 图 22 shows an example for a typical
screen-touch situation. While in the power-down mode, the Y– driver is on and connects to GND. The internal
pen-touch signal depends on whether or not the X+ input is low. A touch on the panel pulls the X+ input to
ground through the touch screen and sets the internal pen-touch output to low because of the detection on the
current path through the panel to ground, which initiates an interrupt to the processor. During the measurement
cycles for X and Y-position, the device disconnects the X+ input, which eliminates any leakage current from the
pullup resistor flowing through the touch screen, thus causing no errors.
Analog V
Plane
DD
PINTDAV
SNSVDD
SNSVDD
Level
Shifter
(1)
R
(IRQ)
50 kꢀ
Y+
Pen
Data Available from ADC
Touch
Control
Logic
Connected
when a touch
is applied to
the screen
X+
High when
the X+ or Y+
driver is on.
Sense
Y±
DGND
High when the X+ or Y+
driver is on or when any
sensor connection or short
circuit tests are activated.
ON
SNSGND
(SENSE)
R
Vias go to the system analog ground plane.
AGND
(1) Untrimmed resistor; see the typical value in the table.
图 22. Example of a Pen-Touch Induced Interrupt via the PINTDAV Pin
20
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TSC2013-Q1
www.ti.com.cn
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
Feature Description (接下页)
In modes where the TSC2013-Q1 device must detect whether or not a touch remains on the screen (for
example, when doing a pen-touch-initiated X, Y, and Z conversion), the TSC2013-Q1 device must reset the
drivers to connect the R(IRQ) resistor again. Because of the high value of this pullup resistor, any capacitance on
the touch screen inputs causes a long delay time, and may prevent the detection from occurring correctly. To
prevent this possible delay, the TSC2013-Q1 device has a circuit that allows prechargingd any screen
capacitance, so that the pullup resistor must not be the only source for the charging current. The setting for the
time allowed for this precharge, as well as the time needed to sense if the screen touch remains, is in the
configuration register.
This configuration underscores the need to use the minimum possible capacitor values on the touch-screen
inputs. Capacitors can be used to reduce noise, but capacitors with too large a value increase the required
precharge and sense times, as well as the panel voltage-stabilization time.
7.3.3.6 Preprocessing
The TSC2013-Q1 device offers an array of powerful preprocessing operations that reduce unnecessary traffic on
the bus and reduce the host processor loading. This reduction is especially critical for the serial interface
because of the slow bus speed and the high CPU bandwidth required for I2C communication.
All data-acquisition tasks are looking for specific data that meet certain criteria. Many of these tasks fall into a
predefined range, while other tasks may be looking for a value in a noisy environment. If the host processor is to
retrieve all these data for processing, the limited bus bandwidth quickly saturates, along with the host processor
processing capability. In any case, reserving the host processor for more critical tasks rather than routine work is
always necessary.
The preprocessing unit consists of two main functions which result in the combined MAV (median and averaging-
value) filter: the median value filter (MVF) and the averaging-value filter (AVF).
7.3.3.6.1 Preprocessing—Median Value Filter and Averaging Value Filter
The first preprocessing function, a combined MAV filter, can operate independently as a median value filter
(MVF), an averaging value filter (AVF), and a combined filter (MAV filter).
If the acquired signal source is noisy because of the digital switching circuit, evaluating the data without noise
may be necessary. In this case, the median value filter (MVF) operation helps to discard noise. The first action is
sorting the array of N converted results. The return value is either the middle (median value) of an array of M
converted results, or the average value of a window size of W of converted results:
N
= the total number of converted results used by the MAV filter
= the median value filter size programmed
M
W
= the averaging window size programmed
If M is equal to 1, then N is equal to W. A special case is W equal to 1, which indicates a bypassed MAV filter.
Otherwise, if W is greater than 1, averaging is the only function performed on these converted results. In either
case, the return value is the averaged value of window size W of converted results.
If M is greater than 1 and W is equal to 1, then N is equal to M, meaning the only operating filter is the median
value filter. The return value is the middle position converted result from the array of M converted results.
If M is greater than 1 and W is greater than 1, then N is equal to M. In this case, W is less than M. The return
value is the averaged value of middle portion W of converted results out of the array of M converted results.
Because the value of W is an odd number in this case, the calculation of the averaging value counts the middle-
position converted result twice (averaging a total of W + 1 converted results).
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www.ti.com.cn
Feature Description (接下页)
表 1. Median Value Filter-Size Selection
MEDIAN VALUE FILTER
M =
POSSIBLE AVERAGING WINDOW SIZE
W =
M1
0
M0
0
1
3
1, 4, 8, 16
1
0
1
1
0
7
1, 3
1
1
15
1, 3, 7
表 2. Averaging Value Filter-Size Selection
AVERAGING VALUE FILTER SIZE SELECTION
W =
W1
0
W0
0
M = 1 (Averaging Only)
M > 1
1
4
1
0
1
3
7
1
0
8
1
1
16
Reserved
The device uses the default MVF setting (median value filter with averaging bypassed) for any invalid MAV filter
configuration. For example, if M1, M0, W1, and W0 equals 1, 0, 1, and 0 (respectively), the MAV filter will
perform as if it were configured for 1, 0, 0, 0, median filter only with filter size of 7, and no averaging. The only
exception is when M is greater than 1 and when W1 and W0 equal 1. Avoid using this reserved setting.
表 3. Combined MAV Filter Setting
M
W
INTERPRETATION
Bypass both MAF and AVF
Bypass MVF only
N =
W
OUTPUT
= 1
= 1
> 1
= 1
> 1
= 1
The converted result
W
Average of W converted results
Median of M converted results
Bypass AVF only
M
Average of middle W of M converted results with the median
counted twice
> 1
> 1
M > W
M
The MAV filter is available for all analog inputs including the touch-screen inputs and the AUX measurement.
Averaging output
from window W
W
M = 1
N
N Acquired
Data
N measurements input
into temporary array
Sort by
descending order
Median value
from array M
N
M > 1 and W = 1
N
N
M
M
Averaging output
from window W
W
M > 1 and W > 1
图 23. MAV Filter Operation
22
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TSC2013-Q1
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ZHCSCV1A –JUNE 2014–REVISED JULY 2014
7.4 Device Functional Modes
7.4.1 Conversion Controlled by TSC2013-Q1 and Initiated by TSC2013-Q1 (TSMode 1)
In TSMode 1, before a pen-touch detection is possible, the TSC2013-Q1 device must be programmed with the
PSM bit set to 1 and one of two scan modes:
1. X-triplet, Y-triplet, Z-scan (converter function select bits C[3:0] = control byte 1 D[6:3] = 0000)
2. IX-IY scan (converter function select bits C[3:0] = control byte 1 D[6:3] = 0001).
See 表 7 for more information on the converter function-select bits.
On touching the touch panel, the internal pen-touch signal activates, lowering the PINTDAV output if
programmed as PENIRQ. The TSC2013-Q1 device then executes the preprogrammed scan function without a
host intervention.
7.4.1.1 IX-IY Scan
The TSC2013-Q1 device starts up the internal clock. The device then turns on the Y-drivers, and after a
programmed panel voltage-stabilization time, the device powers up the ADC and converts the IY coordinate.
With preprocessing selected, several conversions can occur. When data preprocessing is complete, a temporary
register stores the IY coordinate result.
If the screen touch remains at this time, the device enables the X-drivers and the process repeats but measures
the IX coordinate instead, storing the result in a temporary register.
图 24 shows a flowchart for this process. The time required to go through this process depends on the selected
resolution, internal conversion clock rate, panel voltage-stabilization time, precharge and sense times, and the
selection status of preprocessing. Use 公式 3 to calculate the time required to achieve a complete X and Y
coordinate (sample set) reading.
§
·
§
¨
©
·
ª
º
»
ª
«
º
»
ª
«
º
»
W(OH1)
Wd(OH1)
¦
¦
W(PPRO)
1
(OSC)
(ADC)
¨
¸
¸
¹
t(COORDINATE)
ꢂ 2 u t(PVS) ꢂ t(PRE) ꢂ t(SNS)
ꢂ
ꢂ 2 u N u B ꢂ 2 u
ꢂ tc(OH)
u
ꢂ
¨
¸
¸
¹
«
ꢀ
ꢁ
¨
¦
¦
¦
¦
«
¬
»
¼
«
¬
»
¼
«
¬
»
¼
(OSC)
(OSC)
(OSC)
(OSC)
©
where
•
•
t(COORDINATE) = time to complete IX and IY coordinate reading
N = number of measurements for MAV filter input, as given in 表 3 as N
(For no MAV: M1 = M0 = W1 = W0 = 0)
•
•
•
•
•
t(PVS) = panel voltage stabilization time, as listed in 表 11
t(PRE) = precharge time, as listed in 表 11
t(SNS) = sense time, as listed in 表 11
B = number of bits of resolution
ƒ(OSC) = TSC onboard OSC clock frequency. See the Electrical Characteristics section for supply frequency
(SNSVDD)
•
•
•
•
•
ƒ(ADC) = ADC clock frequency, as listed in 表 11
t(OH1) = overhead time number 1 = 2.5 internal clock cycles
td(OH1) = total overhead time for t(PVS), t(PRE), and t(SNS) = 10 internal clock cycles
tc(OH) = total overhead time for A-to-D conversion = 3 internal clock cycles
t(PPRO) = preprocessor preprocessing time as listed in 表 4
(3)
表 4. Preprocessing Delay
t(PPRO)
=
M =
1
W =
FOR B = 12 BIT
FOR B = 10 BIT
1, 4, 8, 16
2
2
3, 7
7
1
3
1
3
7
28
31
31
34
38
24
27
29
32
36
15
15
15
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www.ti.com.cn
Programmed for
Self-Control
(PSM = 1)
IX-IY Scan Mode
(Control Byte1
D[6:3] = 0001)
TSC
Not Addressed
Reading Reading
IX-Data IY-Data
Register Register
t(COORDINATE)
Sample, Conversion, and
Preprocessing for
IY Coordinate
Sample, Conversion, and
Preprocessing for
IX Coordinate
Sample, Conversion, and
Preprocessing for
IY Coordinate
Detecting
Touch
Detecting
Touch
Detecting
Touch
Detecting Touch
PINTDAV Programmed:
Touch is Detected
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Detected
As PENIRQ and DAV,
CFR2, D[15:14] = 00
图 24. Example of an IX and IY Touch-Screen Scan Using TSMode 1
7.4.1.2 X-Triplet, Y-Triplet, Z-Scan
The TSC2013-Q1 device starts up the internal clock. The device then turns on the Y-drivers, and after a
programmed panel voltage-stabilization time, powers up the ADC and converts the Y-triplet. With preprocessing
selected, several conversions can occur. When data preprocessing is complete, temporary registers store the Y-
triplet results.
If the screen touch remains at this time, the device enables the X-drivers and the process repeats but measures
the X-triplet instead, storing the result in temporary registers.
The process continues in the same way, but measures the Z1 and Z2 values instead, storing the results in
temporary registers. When the complete sample set of data (X1, X2, IX, Y1, Y2, IY, Z1, and Z2) are available,
the device loads the data in the X1, X2, IX, Y1, Y2, IY, Z1, and Z2 registers. 图 25 shows this process. This
process time depends on the previously described settings. Use 公式 4 to calculate the time for a complete X1,
X2, IX, Y1, Y2, IY, Z1, and Z2 coordinate reading.
§
·
§
¨
©
·
ª
º
»
ª
«
º
»
ª
«
º
»
W(OH2)
Wd(OH1)
¦
¦
W(PPRO)
1
(OSC)
(ADC)
¨
¸
¸
¹
t(COORDINATE)
ꢂ 3 u t(PVS) ꢂ t(PRE) ꢂ t(SNS)
ꢂ
ꢂ 8 u N u B ꢂ 2 u
ꢂ tc(OH)
u
ꢂ
¨
¸
¸
¹
«
ꢀ
ꢁ
¨
¦
¦
¦
¦
«
¬
»
¼
«
¬
»
¼
«
¬
»
¼
(OSC)
(OSC)
(OSC)
(OSC)
©
where
•
t(OH2) = overhead time number 2 = 3.5 internal clock cycles
(4)
Programmed for
Self-Control
(PSM = 1)
TSC
Not Addressed
Reading
X1, X2, IX, Y1, Y2, IY, Z1, Z2
Register
X1, X2, IX, Y1, Y2, IY, Z1, Z2
Scan Mode
(Control Byte1
D[6:3] = 0000)
t(COORDINATE)
Sample, Conversion,
and Preprocessing for
Z1 Coordinate and Z2 Coordinate
Sample, Conversion,
and Preprocessing for
Y-Triplet
Sample, Conversion,
and Preprocessing for
X-Triplet
Sample, Conversion,
and Preprocessing for
Y-Triplet
Detecting
Touch
Detecting
Touch
Detecting
Touch
Detecting
Touch
Detecting
Touch
PINTDAV Programmed:
Touch is Detected
Touch is Detected
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Detected
As PENIRQ and DAV,
CFR2, D[15:14] = 00
图 25. Example of an X-Triplet and Y-Triplet Coordinate Touch-Screen Scan Using TSMode 1
24
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TSC2013-Q1
www.ti.com.cn
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
7.4.2 Conversion Controlled by TSC2013-Q1 and Initiated by Host (TSMode 2)
In TSMode 2, the TSC2013-Q1 device detects when a touch of the touch panel occurs and causes the internal
pen-touch signal to activate, which lowers the PINTDAV output if programmed as PENIRQ. The host recognizes
the interrupt request and then writes to the ADC control register to select one of the following two Touch-Screen
Scan functions:
1. X-triplet, Y-triplet, Z-scan (converter function select bits C[3:0] = control byte 1 D[6:3] = 0000); or
2. IX-IY scan (converter function select bits C[3:0] = control byte 1 D[6:3] = 0001).
See 表 7 for more information on the converter function-select bits.
The conversion process then proceeds as shown in 图 26. See the IX-IY Scan and X-Triplet, Y-Triplet, Z-Scan
sections for additional details.
The main difference between this mode and the previous mode is that the host, not the TSC2013-Q1 device,
decides when the touch-screen scan begins.
Use 公式 3 to calculate the time required to convert both IX and IY under host control (not including the time
required to send the command over the I2C bus):
TSC
Not
Addressed
Programmed
for
Host-
Controlled
Mode
(PSM = 0)
TSC
Not Addressed
TSC
Not Addressed
Programmed
for
IX-IY
Reading Reading
IX-Data IY-Data
Register Register
Scan Mode
t(COORDINATE)
Waiting for Host to
Write Into
Control Byte 1 D[6:3]
Sample, Conversion,
and Preprocessing for
IY Coordinate
Sample, Conversion,
and Preprocessing for
IX Coordinate
Sample, Conversion,
and Preprocessing for
IY Coordinate
Detecting
Touch
Detecting
Touch
Detecting
Touch
Detecting
Touch
PINTDAV Programmed:
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
Touch is Detected
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Still Here
As PENIRQ and DAV,
CFR2, D[15:14] = 00
图 26. Example of an IX and IY Touch-Screen Scan Using TSMode 2
版权 © 2014, Texas Instruments Incorporated
25
TSC2013-Q1
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
www.ti.com.cn
7.4.3 Conversion Controlled by Host (TSMode 3)
In TSMode 3, the TSC2013-Q1 device detects a touch of the touch panel and causes the internal pen-touch
signal to be active, which lowers the PINTDAV output if programmed as PENIRQ. The host recognizes the
interrupt request. Instead of starting a sequence in the TSC2013-Q1 device, which then reads each coordinate in
turn, the host must now control all aspects of the conversion. Generally, on receiving the interrupt request, the
host turns on the X drivers.
注
With the drivers turned off, the device detects this condition and turns the driver on before
the scan starts. This situation is why the event of turn on drivers is shown as optional in
图 27 and 图 29.
After waiting for the settling time, the host then addresses the TSC2013-Q1 device again, this time requesting an
X-coordinate conversion.
The process then repeats for the Y and Z coordinates. 图 27 and 图 29 show this process. 图 27 shows two
consecutive scans on IX and IY. 图 29 shows a single Z scan.
Use 公式 5 to calculate the time required to convert any single X-triplet or Y-triplet under host control (not
including the time required to send the command over the I2C bus):
§
·
§
¨
©
·
ª
º
»
ª
«
º
»
ª
«
º
»
W(OH1)
Wd(OH2)
¦
¦
W(PPRO)
1
(OSC)
¨
¸
¸
¹
t(COORDINATE)
ꢂ t(PRE) ꢂ t(SNS)
ꢂ
ꢂ 3N u B ꢂ 2 u
ꢂ tc(OH)
u
ꢂ
¨
¸
¸
¹
«
ꢀ
ꢁ
¨
¦
¦
¦
¦
«
¬
»
¼
«
¬
»
¼
«
¬
»
¼
(OSC)
(OSC)
(ADC)
(OSC)
(OSC)
©
where
•
td(OH2) = total overhead time for t(PRE) and t(SNS) = 6 internal clock cycles
(5)
Programmed for:
Turn On
X+ and
Programmed for:
Turn On
Y+ and
TSC
Not
Addressed
TSC
Not
Addressed
TSC
Not
Addressed
TSC
Not
Addressed
Programmed
for Host-
Controlled
Mode
(PSM = 0)
Reading
X1, X2,
IX
Reading
Y-Data
Register
Y-Triplet
X-Triplet
X-
Y-
Mode
Mode
(1)
(1)
Register
Drivers
Drivers
t(COORDINATE)
t(COORDINATE)
Sample, Conversion,
and Preprocessing
for X-Triplet
Sample, Conversion,
and Preprocessing
for Y-Triplet
Waiting for Host to
Write Into Control
Byte 1 D[6:3]
Detecting
Touch
Waiting for Host to Write Into
Control Byte 1 D[6:3]
Detecting Waiting for Host to Write Into
Detecting
Touch
Control Byte 1 D[6:3]
Touch
Touch is Detected
PINTDAV Programmed:
Touch is Detected
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
As PENIRQ and DAV,
CFR2, D[15:14] = 00
(1) Optional. If not turned on, it will be turned on by the scan mode, when detected.
图 27. Example of X-Triplet and Y-Triplet Touch-Screen Scan
(Without Panel Stabilization Time) Using TSMode 3
26
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TSC2013-Q1
www.ti.com.cn
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
Use 公式 6 to calculate the time required to convert any single X-triplet or Y-triplet under host control (not
including the time required to send the command over the I2C bus):
§
·
§
¨
©
·
ª
«
º
»
ª
«
º
»
ª
«
º
»
W(OH1)
Wd(OH2)
¦
¦
W(PPRO)
1
(OSC)
¨
¨
©
¸
¸
¹
t(COORDINATE)
ꢂ t
ꢂ t(PRE) ꢂ t(SNS)
ꢂ
ꢂ 3N u
B ꢂ 2 u
ꢂ tc(OH)
u
ꢂ
¨
¸
¸
¹
ꢀ
ꢁ
(PVS)
¦
¦
¦
¦
«
¬
»
¼
«
¬
»
¼
«
¬
»
¼
(OSC)
(OSC)
(ADC)
(OSC)
(OSC)
(6)
TSC
Not Addressed
TSC
Not Addressed
TSC
Not Addressed
Reading
X1 , X2 , IX
Programmed
for
Programmed for
Host-Controlled
Mode
X-Triplet
Scan Mode
Data
Register
(PSM = 0)
t(COORDINATE)
Detecting
Touch
Detecting
Touch
Waiting for Host to Write
Into Control Byte 1 D[6:3]
Sample, Conversion, and
Preprocessing for X-Triplet
Waiting for Host to Write
Into Control Byte 1 D[6:3]
PINTDAV Programmed:
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Still Here
As PENIRQ and DAV,
CFR2, D[15:14] = 00
图 28. Example of a Single X-Triplet Touch-Screen Scan
(With Panel Stabilization Time) Using TSMode 3
版权 © 2014, Texas Instruments Incorporated
27
TSC2013-Q1
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
www.ti.com.cn
Use 公式 7 to calculate the time required to convert any Z1 and Z2 coordinate under host control (not including
the time required to send the command over the I2C bus):
§
·
§
¨
©
·
ª
«
º
»
ª
«
º
»
ª
«
º
»
W(OH2)
Wd(OH2)
¦
¦
W(PPRO)
1
(OSC)
¨
¨
©
¸
¸
¹
t(COORDINATE)
ꢂ t(PRE) ꢂ t(SNS)
ꢂ
ꢂ N u
B ꢂ 2 u
ꢂ tc(OH)
u
ꢂ
¨
¸
¸
¹
ꢀ
ꢁ
¦
¦
¦
¦
«
¬
»
¼
«
¬
»
¼
«
¬
»
¼
(OSC)
(OSC)
(ADC)
(OSC)
(OSC)
(7)
Programmed for:
Turn On
TSC
Not
Addressed
Programmed
for
Host-Controlled
Mode
(PSM = 0)
TSC
Not Addressed
TSC
Not Addressed
Reading Reading
Z1-Data Z2-Data
Register Register
Y+
and
Z
Scan
Mode
X-
Drivers(1)
t(COORDINATE)
Sample, Conversion, Sample, Conversion,
Detecting
Touch
Detecting
Touch
Waiting for Host to Write
Into Control Byte 1 D[6:3]
Waiting for Host to Write
Into Control Byte 1 D[6:3]
and Preprocessing
for Z1 Coordinate
and Preprocessing
for Z2 Coordinate
PINTDAV Programmed:
Touch is Detected
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
As PENIRQ and DAV,
CFR2D[15:14] = 00
(1) Optional. If not turned on, it will be turned on by the scan mode, when detected.
图 29. Example of Z1 and Z2 Coordinate Touch-Screen Scan
(Without Panel Stabilization Time) Using TSMode 3
If the drivers do not turn on prior to programming the touch-screen scan mode, include the panel stabilization
time. In this case, use 公式 8 to calculate the time required to convert any single X or Y under host control (not
including the time required to send the command over the I2C bus):
§
·
§
¨
©
·
ª
º
»
ª
«
º
»
ª
«
º
»
W(OH2)
Wd(OH2)
¦
¦
W(PPRO)
1
(OSC)
(ADC)
¨
¸
¸
¹
t(COORDINATE)
ꢂ t(PVS) ꢂ t(PRE) ꢂ t(SNS)
ꢂ
ꢂN u B ꢂ 2 u
ꢂ tc(OH)
u
ꢂ
¨
¸
¸
¹
«
ꢀ
ꢁ
¨
¦
¦
¦
¦
«
¬
»
¼
«
¬
»
¼
«
¬
»
¼
(OSC)
(OSC)
(OSC)
(OSC)
©
(8)
TSC
TSC
Not Addressed
TSC
Not Addressed
Programmed
Programmed for
Host-Controlled
Mode
Reading Reading
Z1-Data Z2-Data
Register Register
Not Addressed
for
Z1-Z2
Scan Mode
(PSM = 0)
t(COORDINATE)
Detecting
Touch
Detecting
Touch
Waiting for Host to Write Sample, Conversion, and
Into Control Byte 1 D[6:3] Preprocessing for Z1, Z2 Coordinates
Waiting for Host to Write
Into Control Byte 1 D[6:3]
PINTDAV Programmed:
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Still Here
As PENIRQ and DAV,
CFR2D[15:14] = 00
图 30. Example of a Z1 and Z2 Coordinate Touch-Screen Scan
(With Panel Stabilization Time) Using TSMode 3
28
版权 © 2014, Texas Instruments Incorporated
TSC2013-Q1
www.ti.com.cn
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
7.5 Programming
7.5.1 I2C Interface
The TSC2013-Q1 device supports the I2C serial bus and data transmission protocol in all three defined modes:
standard, fast, and high-speed. A device that sends data onto the bus has the definition of a transmitter, and a
device receiving data that of a receiver. The device that controls the message is a master. Devices controlled by
the master are slaves. A master device that generates the serial clock (SCL), controls bus access, and generates
the START and STOP conditions must control the bus The TSC2013-Q1 device operates as a slave on the I2C
bus. Connections to the bus are through the open-drain I/O lines, SDA and SCL.
The following bus protocol has been defined (see 图 31):
•
•
A device can initiate data transfer only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as control signals.
Accordingly, definitions for the following bus conditions follow:
Bus Not Busy Both data and clock lines remain high.
Start Data Transfer A change in the state of the data line, from high to low, while the clock is high, defines a
start condition.
Stop Data Transfer A change in the state of the data line, from low to high, while the clock line is high, defines
the stop condition.
Data Valid The state of the data line represents valid data, when, after a start condition, the data line is stable
for the duration of the high period of the clock signal. One clock pulse occurs per bit of data.
Each data transfer begins with a start condition and terminates with a stop condition. The
number of data bytes transferred between start and stop conditions, which the master device
determines, is not limited. The information transfers byte-wise, and the receiver
acknowledges each byte with a ninth bit.
The I2C bus specifications define a standard mode (100-kHz clock rate), a fast mode (400-
kHz clock rate), and a high-speed mode (3.4-MHz clock rate). The TSC2013-Q1 device
works in all three modes.
Acknowledge Each receiving device, when addressed, must generate an acknowledge after the reception of
each byte. The master device must generate an extra clock pulse for association with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is stable low during the high period of the
acknowledge clock pulse. Of course, the timing must take into account setup and hold times.
A master must signal an end-of-data to the slave by not generating an acknowledge bit on
the last byte that clocks out of the slave. In this case, the slave must leave the data line high
to enable the master to generate the stop condition.
图 31 shows the data-transfer process on the I2C bus. Depending on the state of the R/W bit, two types of data
transfer are possible:
1. Data transfer from a master transmitter to a slave receiver.
The first byte transmitted by the master is the slave address. A number of data bytes occurs next. The slave
returns an acknowledge bit after the slave address and each received byte.
2. Data transfer from a slave transmitter to a master receiver.
The master transmits the first byte, the slave address. The slave then returns an acknowledge bit. Next, the
slave transmits a number of data bytes to the master. The master returns an acknowledge bit after all
received bytes other than the last byte. At the end of the last received byte, the master returns a not-
acknowledge.
The master device generates all of the serial clock pulses and the start and stop conditions. A transfer ends with
a stop condition or a repeated start condition. Because a repeated start condition is also the beginning of the
next serial transfer, the bus is not released.
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Programming (接下页)
The TSC2013-Q1 device can operate in the following two modes:
1. Slave receiver mode
Reception of serial data and clock is through SDA and SCL. After the reception of each byte, the receiver
transmits an acknowledge bit. Start and stop conditions designate the beginning and end of a serial transfer.
Hardware performs address recognition after reception of the slave address and direction bit.
2. Slave transmitter mode
Reception and handling of the first byte (the slave address) is the same as in the slave receiver mode.
However, in this mode the direction bit indicates a reversal of the transfer direction. Serial data transmission
on SDA by the TSC2013-Q1 device occurs during input of the serial clock on SCL. Start and stop conditions
designate the beginning and end of a serial transfer.
7.5.1.1 I2C Fast or Standard Mode (F-S Mode)
In I2C fast or standard (F-S) mode, serial data transfer must meet the timing shown in the timing requirement
tables in the Specifications section.
In the serial transfer format of F-S mode, the master signals the beginning of a transmission to a slave with a
start condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has
finished communicating with the slave, the master issues a stop condition (P), which is a low-to-high transition on
SDA while SCL is high, as shown in 图 31. The bus is free for another transmission after the occurrence of a
stop. 图 31 shows the complete F-S mode transfer on the I2C, two-wire serial interface. Transmission of the
address byte, control byte, and data byte is between the start and stop conditions. The SDA state can only
change while SCL is low, except for the start and stop conditions. Data transmission is in 8-bit words. Nine clock
cycles are necessary to transfer the data into or out of the device (8-bit word plus acknowledge bit).
P
or
Sr
S
SDA
MSB
Slave Address
R/W
Direction Bit
Acknowledgement
Signal from Receiver
Acknowledgement
Signal from Receiver
1
2
6
7
8
9
1
2
3-8
8
9
SCL
ACK
ACK
Repeated If More Bytes Are Transferred
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
= Resistor Pull Up
图 31. Complete Fast or Standard-Mode Transfer
30
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Programming (接下页)
7.5.1.2 I2C High-Speed Mode (Hs Mode)
Serial data transfer format in high-speed (Hs) mode meets the fast or standard (F-S) mode I2C bus specification.
Hs mode can only commence after the following conditions (all of which are in F-S mode) exist:
1. Start condition (S)
2. 8-bit master code (0000 1xxx)
3. Not-acknowledge bit (N)
图 32 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for
triggering Hs mode. Do not use these codes for slave addressing or any other purpose. The master code
indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the
Hs mode specification. Because no device can acknowledge the master code, a not-acknowledge bit (N) follows
the master code.
After the not-acknowledge bit (N) and SCL achieve a high level, the master switches to Hs-mode and enables (at
time t(H); shown in 图 32) the current-source pullup circuit for SCL. Because other devices can delay the serial
transfer before t(H) by stretching the LOW period of SCL, the master enables the current-source pullup circuit
when all devices have released SCL and SCL has reached a high level, thus speeding up the last part of the rise
time of the SCL.
The master then sends a repeated start condition (Sr) followed by a 7-bit slave address with an R/W bit address,
and receives an acknowledge bit (A) from the selected slave. After a repeated start (Sr) condition and after each
acknowledge bit (A) or not-acknowledge bit (N), the master disables the current-source pullup circuit. This
disabling enables other devices to delay the serial transfer by stretching the low period of SCL. The master re-
enables the current-source pullup circuit again when all devices have released, and SCL reaches a high level,
which speeds up the last part of the SCL signal rise time.
Data transfer continues in Hs mode after the next repeated start (Sr), and only switches back to F-S mode after a
stop condition (P). To reduce the overhead of the master code, the master can link to a number of Hs mode
transfers, separated by repeated start conditions (Sr).
8-Bit Master Code 00001xxx
N
tH
S
SDA
SCL
1
2 to 5
6
7
8
9
Fast or Standard Mode
R/W
A
n x (8-Bit DATA
+
A/N)
7-Bit Slave Address
Sr
Sr P
SDA
SCL
1
6
7
8
9
1
2 to 5
6
7
8
9
2 to 5
If P then
Fast or Standard Mode
High-Speed Mode
If Sr (dashed lines
then High-Speed Mode
)
A = Acknowledge (SDA LOW)
= Current-Source Pull Up
= Resistor Pull Up
tH
N = Not Acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
tFS
Sr = Repeated START Condition
图 32. Complete High-Speed Mode Transfer
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Programming (接下页)
7.5.2 Digital Interface
7.5.2.1 Address Byte
The TSC2013-Q1 device has a 7-bit slave address word. The factory presets the first five bits (MSBs) of the
slave address to comply with the I2C standard for ADCs; the setting is always 1 0010. The logic state of the
address input pins (AD1 through AD0) determines the two LSBs of the device address to activate
communication. Therefore, one bus can accommodate a maximum of four devices with the same preset code at
one time.
The device only reads the AD1 through AD0 address inputs during a power-up of the device, and the pin
connections should be to a digital supply (I/OVDD) or digital ground (DGND). The TSC2013-Q1 latches the slave
address on the falling edge of SCL after reception of the R/W bit by the slave.
The last bit of the address byte (R/W) defines the operation to be performed. Setting the bit to 1 selects a read
operation. Setting the bit to 0 selects a write operation. Following the start condition, the TSC2013-Q1 device
monitors the SDA bus, checking the transmitted device-type identifier. On receiving the 1 0010 code, the
appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
表 5. I2C Slave Address Byte
MSB
D7
LSB
D0
D6
D5
D4
D3
D2
D1
1
0
0
1
0
AD1
AD0
R/W
R/W (D0)
1: I2C master read from TSC (I2C read addressing).
0: I2C master write to TSC (I2C write addressing).
I2C Write-Addressing Byte
A = Acknowledge (SDA LOW)
S = START Condition
From Master to Slave
From Slave to Master
S/Sr
1
0
0
1
0
AD1 AD0
0
A
START or
Repeated START
ACK
Sr = Repeated START Condition
I2C Read-Addressing Byte
S/Sr
1
0
0
1
0
AD1 AD0
1
A
START or
Repeated START
ACK
图 33. I2C Bus Addressing (Slave-Address Byte Format)
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7.5.3 Control Byte
表 6. Control Byte Format: Start a Conversion and Mode Setting, D7 = 1
MSB
D7
LSB
D0
D6
C3
D5
D4
D3
D2
D1
1
C2
C1
C0
RM
SWRST
STS
(Control Byte 1)
Control Byte ID (D7)
C[3:0] (D6:D3)
RM (D2)
1: Control Byte 1 (start conversion and channel select and conversion-related
configuration).
0: Control Byte 0 (read/write data registers and non-conversion-related controls).
Converter function select bits
These bits select the input for conversion, and the converter function to be executed.
表 7 lists the possible converter functions.
Resolution select
If RM = 1, the conversion-result resolution is 12-bit; otherwise, the resolution is 10-bit.
This bit is the same RM bit shown in CFR0.
0: 10-bit
1: 12-bit
SWRST (D1)
STS (D0)
Software reset. This bit is self-clearing.
1: Reset all register values to default
Stop bit for all converter functions. This bit is self-clearing.
On writing a 1 to this register, this bit aborts the converter function currently running in
the TSC2013-Q1. An automatic write of 0 to this register occurs when the abort has
completed. Setting this bit to 1 can only stop converter functions; it does not reset any
data, status, or configuration registers. This bit is the same STS bit shown in CFR0, but
reading can only be through the CFR0 register.
Write 0: Normal operation
Write 1: Stop converter functions and power down
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表 7. Converter Function Select
C3 C2 C1 C0 FUNCTION
Touch-Screen Scan function: X triplet, Y triplet, Z1, and Z2 coordinates converted and the results returned to X1, X2,
IX, Y1, Y2, IY, Z1, and Z2 data registers. Scan continues until either lifting of the pen or sending of a stop bit.
0
0
0
0
0
0
0
1
Touch-Screen Scan function: IX and IY coordinates converted and the results returned to IX and IY data registers.
Scan continues until either lifting of the pen or sending of a stop bit.
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Touch screen function: X triplet converted and the results returned to X1, X2, IX data register.
Touch screen function: Y triplet converted and the results returned to Y1, Y2, IY data register.
Touch screen function: Z1 and Z2 coordinates converted and the results returned to Z1 and Z2 data registers.
Auxiliary input converted and the results returned to the AUX data register.
Touch screen function: IX converted and result returned to IX data register.
Touch screen function: IY converted and result returned to IY data register.
Auxiliary input conversion occurs continuously and the results returned to the AUX data register.
RESERVED
RESERVED
RESERVED(1)
RESERVED
X+, X– drivers activated
Y+, Y– drivers activated
Y+, X– drivers activated
(1) Any condition caused by this command can be cleared by setting the STS bit to 1.
表 8. Control Byte Format: Start a Conversion and Mode Setting D7 = 0
MSB
D7
LSB
D0
D6
D5
D4
D3
D2
D1
0
Reserved
(Write 0)
A3
A2
A1
A0
PND0
R/W
(Control Byte 0)
Control byte ID (D7)
1: Control byte 1—start conversion, channel select, and conversion-related
configuration
0: Control byte 0—read/write data registers and non-conversion-related controls
Register address bits as detailed in 表 9
A[3:0] (D6:D3)
RESERVED (D2)
PND0 (D1)
Set a 0 in this bit for normal operation
Power-not-down control
1: ADC biasing circuitry is always on between conversions but shuts down after the
converter function stops
0: ADC biasing circuitry shuts down either between conversions or after the converter
function stops. Example power savings for the following condition is approximately 5%:
AUX conversion, continuous mode, median filter = 15, averaging filter = 7, ƒ(ADC) = 2
MHz.
R/W (D0)
TSC internal-register data-flow control
1: Set the starting address of the TSC internal registers for a register read (see 图 34)
0: Write to TSC internal registers
34
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7.5.3.1 Touch-Screen Scan Function for XYZ or XY
These scan functions (C3–C0 = 0000 or 0001) can collaborate with the PSM bit that defines the control mode of
converter functions. With the PSM bit set to 1, TI recommends issuing these scan-function select commands
before detection of a pen touch in order to allow the TSC2013-Q1 device to initiate and control the scan
processes immediately after detection of the screen touched. Without issuing these functions before detection of
a pen touch, the TSC2013-Q1 waits for the host to write these functions before starting a scan process. If PSM
stays as 1 after a TSC-initiated scan function is complete, the host is not required to write these function-select
bits again for each of the following pen touches after the detected touch. In the host-controlled converter function
mode (PSM = 0), the host must send these functions select bits repeatedly for each scan function after a
detected pen touch.
注
The update of the data registers may occur while a host reading is in progress. Using the
sequential read cycle (see 图 35) prevents the TSC from updating registers while a host
reading is in progress. To ensure a correct reading of the XYZ or XY coordinates, use the
sequential read cycle to read the coordinates after the scan.
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表 9. Internal Register Map
REGISTER ADDRESS
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
REGISTER CONTENT
READ/WRITE
X1 measurement result
R
R
R
R
R
R
R
R
R
R
X2 measurement result
Y1 measurement result
Y2 measurement result
IX measurement result
IY measurement result
Z1 measurement result
Z2 measurement result
Status
AUX measurement result
RESERVED
RESERVED
CFR0
R/W
R/W
R/W
R
CFR1
CFR2
Converter function select status
R/W is the register read and write control. A 1 indicates that the value of the internal register address bits A3–A0
is stored internally as the starting address for a register read (see 图 34). The content of the addressed register
is sent to SDA by using I2C read addressing (see 图 35 and 图 36). A0 indicates that the data following control
byte 0 on SDA are written into the internal register addressed by bits A3–A0 (see 图 34).
7.5.4 Start a Write Cycle
A write cycle begins when the master issues the slave address to the TSC2013-Q1 device. The slave address
consists of seven address bits and a write bit (R/W = 0; see 表 6).On receipt of the eighth bit, if the address
matches the AD1 through AD0 address input pin setting, the TSC2013-Q1 device issues an acknowledge bit by
pulling SDA low for one additional clock cycle (ACK = 0); see 图 33.
When the master receives the acknowledge bit from the TSC2013-Q1 device, the master writes the input control
byte to the slave (see 表 6). After the control byte is received by the slave, the slave issues another acknowledge
bit by pulling SDA low for one clock cycle (ACK = 0). The master then ends the write cycle by issuing a STOP or
repeated START condition; see 图 34.
36
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Write Cycle
7
1
0
8
S
I2C Slave Address
A
Control Byte 1
A
P
I2C Write-
Addressing Byte
STOP(1)
1
C3 C2 C1 C0 RM
START
ACK
Converter Function Select
7
1
8
8
8
Data Byte 1/2
Data Byte 2/2
S
I2C Slave Address
0
A
Control Byte 0
A
P
A
A
(HIGH Byte)
(LOW Byte)
I2C Write-
Addressing Byte
STOP(1)
0
ACK
A3 A2 A1 A0
0
START
TSC Internal Register Address for Write Data
7
1
8
S
I2C Slave Address
0
A
Control Byte 0
A
P
I2C Write-
Addressing Byte
STOP(1)
0
ACK
A3 A2 A1 A0
1
START
TSC Internal Register Starting Address mh(2)
(M + N × 3) × 8
7
1
S
I2C Slave Address
0
A
A
A
A
P
I2C Write-
Addressing Byte
Mixed M (Control Byte 1 or Control Byte 0 with Read Bit)
Plus N (Control Byte 0 with Data Bytes), Separated by TSC ACKs
START
STOP(1)
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
From Master to Slave
From Slave to Master
P = STOP Condition
Sr = Repeated START Condition
(1) In order to start the next sequence, a stop condition must be followed by a start condition. If no stop is used, then a
repeated start (Sr) must be used. Also note that if a stop condition is issued in high-speed mode, the mode reverts to
the previous mode which is either fast or standard mode.
(2) mh is a hexadecimal number.
图 34. Write Cycle
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7.5.5 Register Access
Data access begins with the master issuing a START (or repeated START) condition followed by the 7-bit
address and a read bit (R/W = 1; see 表 6). On receipt of the eighth bit has been received and an address
match, the slave issues an acknowledge by pulling SDA low for one clock cycle (ACK = 0). The first byte of serial
data then follows. After the slave has sent the first byte, it then releases the SDA line for the master to issue an
acknowledge (ACK = 0). The slave issues the second byte of serial data on receiving the acknowledgment from
the master (D7–D0), followed by a not-acknowledge bit (ACK = 1) from the master to indicate receipt of the last
data byte has been received. The master then issues a STOP condition (P) or repeated START (Sr), which ends
the read cycle, as shown in 图 35 and 图 36. If the master issues a not-acknowledge (ACK = 1) after receipt of
the first data byte, the master must then issue a stop condition (P) to reset the registers. If the master is not
ready to receive the second data byte, it should issue the acknowledge (ACK = 0), or the master should stretch
the clock. On restart of the clock, the master can receive the second byte of data.
Read Cycle: Sequential, from Register Address mh(2) to (m + n)h(3)
8
8
7
1
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
S
I2C Slave Address
A
A
A
A
START I2C Read-Addressing Byte
Register (Address = mh) Content
8
8
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
A
Register (Address = (m + 1)h) Content
8
8
NACK
N
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
A
P
STOP(1)
Register (Address = (m + n)h) Content
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
From Master to Slave
From Slave to Master
P = STOP Condition
Sr = Repeated START Condition
(1) In order to start the next sequence, a Stop condition must be followed by a start condition. If no stop is used, then a
repeated start must be used. Also note that if a stop condition is issued in high-speed mode, the mode reverts to the
previous mode which is either fast or standard mode.
(2) mh is a hexadecimal number.
(3) If (m+n)h is greater than Fh, then (m + n)h is modulo 16.
图 35. Sequential Read Cycle
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Read Cycle: Repeated, Register Address mh(2)
8
8
NACK
N
7
1
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
S
I2C Slave Address
A
A
A
A
P
START I2C Read-Addressing Byte
Register (Address = mh) Content
STOP(1)
8
8
NACK
7
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
S
I2C Slave Address
1
A
N
P
START I2C Read-Addressing Byte
Register (Address = mh) Content
STOP(1)
8
8
NACK
7
I2C Slave Address
START I2C Read-Addressing Byte
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
S
1
A
N
P
STOP(1)
Register (Address = mh) Content
Or...
8
8
NACK
7
1
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
Sr
I2C Slave Address
A
A
A
A
N
I2C Read-Addressing Byte
Register (Address = mh) Content
Repeated
START
8
8
NACK
N
7
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
Sr
I2C Slave Address
1
A
I2C Read-Addressing Byte
Register (Address = mh) Content
Repeated
START
8
8
NACK
N
7
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
Sr
I2C Slave Address
1
A
P
I2C Read-Addressing Byte
Register (Address = mh) Content
STOP(1)
Repeated
START
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
From Master to Slave
From Slave to Master
P = STOP Condition
Sr = Repeated START Condition
(1) In order to start the next sequence, a Stop condition must be followed by a start condition. If no stop is used, then a
repeated start must be used. Also note that if a stop condition is issued in high-speed mode, the mode reverts to the
previous mode which is either fast or standard mode.
(2) mh is a hexadecimal number.
图 36. Repeated Read Cycle
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7.5.6 Communication Protocol
All control of the TSC2013-Q1 is through registers. Reading and writing to these registers are accomplished by
the use of Control Byte 0, which includes a 4-bit address plus one read-write TSC register-control bit. The data
registers defined in 表 9 are all 16-bit, right-adjusted.
注
Except for some configuration registers and the status register that are full 16-bit registers,
the rest of the value registers are 12-bit (or 10-bit) data preceded by four (or six) zeros.
See the Configuration and Status Registers section for the register field descriptions.
7.5.7 Register Reset
The TSC2013-Q1 device can be reset in one of three ways. First, at power-on, a power-good signal generates a
prolonged reset pulse internally to all registers.
Second, an external pin, RESET, is available to perform a system reset or allow other peripherals (such as a
display) to reset the device if the pulse meets the timing requirement (at least 10 μs in duration). Any RESET
pulse less than 5 μs is rejected. To accommodate the timing drift between devices because of process variation,
a RESET pulse duration between 5 μs and 10 μs falls into the gray area that is unrecognized, giving an
undetermined result; avoid this situation. See 图 37 for details. A good reset pulse must be low for at least 10 μs.
An internal spike filter is available to reject spikes up to 20 ns wide.
tr
tr
t(WL_RESET) < 5 µs
t(WL_RESET) ³ 10 µs
RESET
State
Normal Operation
Resetting
Initial Condition
NOTE: See the timing requirement tables in the Specifications section for more information.
图 37. External Reset Timing
Third, a software reset is activated by writing a 1 to CB1.1 (bit 1 of control byte 1). Note that this reset is not self-
clearing, so the user must write a 0 to remove the software reset.
A reset clears all registers and loads default values. A power-on reset and external (hardware) reset take
precedence over a software reset. If the user does not clear a software reset, either a power-on reset or an
external (hardware) reset clears it.
40
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7.6 Register Maps
The TSC2013-Q1 device has several 16-bit registers that allow control of the device, as well as providing a location to store results from the TSC2013-Q1
device until read out by the host microprocessor. 表 10 shows the memory map.
表 10. Register Content and Reset Values(1)
RESET
A3-A0
(HEX)
REGISTER
NAME
VALUE
(HEX)
D15
0
D14
0
D13
0
D12
0
D11
R11
R11
R11
R11
R11
R11
R11
R11
D10
R10
R10
R10
R10
R10
R10
R10
R10
D9
R9
R9
R9
R9
R9
R9
R9
R9
D8
R8
R8
R8
R8
R8
R8
R8
R8
D7
R7
R7
R7
R7
R7
R7
R7
R7
D6
R6
R6
R6
R6
R6
R6
R6
R6
D5
R5
R5
R5
R5
R5
R5
R5
R5
D4
R4
R4
R4
R4
R4
R4
R4
R4
D3
R3
R3
R3
R3
R3
R3
R3
R3
D2
R2
R2
R2
R2
R2
R2
R2
R2
D1
R1
R1
R1
R1
R1
R1
R1
R1
D0
R0
R0
R0
R0
R0
R0
R0
R0
0
1
2
3
4
5
6
7
X1
X2
Y1
Y2
IX
0000
0000
0000
0000
0000
0000
0000
0000
0
0
0
0
0
0
0
0
0
0
0
0
T(2)
T(2)
0
0
0
0
IY
0
0
0
Z1
Z2
0
0
0
0
0
0
0
DAVZ DAVZ DAVA
RESE
T
8
Status
DAVX
DAVY
0
0
0
0
0
0
0
PDST
0
0
0004
1
2
UX
R11
0
9
A
B
C
D
AUX
0
0
0
0
0
0
R10
0
R9
0
R8
0
R7
0
R6
0
R5
0
R4
0
R3
0
R2
0
R1
0
R0
0
0000
0000
0000
4000
0000
RSVD
RSVD
CFR0
CFR1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PSM
0
STS
0
RM
0
CL1
0
CL0
0
PV2
0
PV1
0
PV0
0
PR2
0
PR1
0
PR0
0
SN2
0
SN1
0
SN0
BTD2
DTW
BTD1
LSM
BTD0
MAVE
X TRIPLET
MAVE
Y TRIPLET
MAVE
Z
MAVE
AUX
E
F
CFR2
CFN
PINTS1
CFN15
PINTS0
M1
M0
0
W1
0
W0
0
0
0
0
0
0
0
0
0000
0000
CFN14 CFN13
CFN8 CFN7
R6
R5
R4
R3
R2
R1
R0
(1) For all combination bits, do not use the pattern marked as RSVD (reserved). The default pattern is read back after reset.
(2) Use of the D15 bit only occurs during a single IX or single IY conversion command.
T = 0: No touch detected during conversion
T = 1: Touch detected during conversion
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7.6.1 Configuration and Status Registers
7.6.1.1 Configuration Register 0
7.6.1.1.1 Configuration Register 0 (address = 0) [reset = 4000h for read; 0000h for write]
图 38. Configuration Register 0
D15
PSM
D14
STS
R/W-
D13
RM
D12
D11
D10
D2
D9
D8
CL[1:0]
R/W-
PV[2:0]
R/W-
R/W-Reset
R/W-
D7
D6
D5
D4
D3
D1
D0
PR[2:0]
R/W-
SN[2:0]
R/W-
DTW
R/W-
LSM
R/W-
表 11. Configuration Register 0 Field Descriptions
Bit
Field
Type
Reset
Description
D15
PSM
R/W
0
Pen status or control mode. This bit is the MSB.
Reading this bit allows the host to determine if a touch of the screen has
occurred. Writing to this bit selects the mode used to control the flow of
converter functions that are either initiated and/or controlled by host or under
control of the TSC2013-Q1 responding to a pen touch. When reading, the PSM
bit indicates if the pen is down or not. When writing to this register, this bit
determines if the TSC2013-Q1 or the host controls the converter functions. The
default state is the host-controlled converter function mode (0). The other state
(1) is the TSC-initiated scan function mode that must only collaborate with
C3–C0 = 0000 or 0001 in order to allow the TSC2013-Q1 to initiate and control
the scan function for XYZ or XY when a on detection of a pen touch.
0 (R): No screen touch detected
1 (R): Screen touch detected
0 (W): Converter functions initiated and/or controlled by host
1 (W): Converter functions initiated and controlled by the TSC2013-
Q1
D14
STS
R/W
1 for R
0 for W
ADC status
When reading, this bit indicates if the converter is busy or not busy. Continuous
scans or conversions can be stopped by writing a 1 to this bit, immediately
aborting the running converter function (even if the pen is still down) and
causing the ADC to power down. The default state for write is 0 (normal
operation), and the default state for read is 1 (converter is not busy). Note that
the same bit can be written through Control Byte 1 (bit 0). This bit is self-
clearing.
0 (R): Converter is busy
1 (R): Converter is not busy
0 (W): Normal operation
1 (W): Stop converter function and power down
D13
RM
R/W
0
Resolution control
This bit specifies the ADC resolution. See for a description of these bits. This bit
is the same whether reading or writing, and defaults to 0. Note that one cn write
the same bit through Control Byte 1.
0: 10-bit resolution. Default after power up and reset
1: 12-bit resolution
42
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表 11. Configuration Register 0 Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
D12-D11 CL[1:0]
R/W
0
Conversion-clock control
These two bits specify CL bits that specify the clock rate that the ADC uses to
perform conversion.
CL1 = 0, CL0 = 0: ƒ(ADC) = ƒ(OSC) / 1, referred to as the 4-MHz ADC clock
rate, 10-bit resolution only
CL1 = 0, CL0 = 1: ƒ(ADC) = ƒ(OSC) / 2, referred to as the 2-MHz ADC clock
rate
CL1 = 1, CL0 = 0: ƒ(ADC) = ƒ(OSC) / 4, referred to as the 1-MHz ADC clock
rate
CL1 = 1, CL0 = 1: ƒ(ADC) = ƒ(OSC) / 4, referred to as the 1-MHz ADC clock
rate
D10-D8 PV[2:0]
R/W
0
Panel-voltage stabilization-time control
These bits specify a delay time from the moment of touch-screen drivers
enabling to the time of voltage sampling and the start of a conversion. These
bits allow the user to adjust the appropriate settling time for the touch panel and
external capacitances. See for settings of these bits. The default state is 000,
indicating a 0-μs stabilization time (t(PVS)). These bits are the same whether
reading or writing.
PV2 = 0, PV1 = 0, PV0 = 0: 0 μs
PV2 = 0, PV1 = 0, PV0 = 1: 100 μs
PV2 = 0, PV1 = 1, PV0 = 0: 500 μs
PV2 = 0, PV1 = 1, PV0 = 1: 1 ms
PV2 = 1, PV1 = 0, PV0 = 0: 5 ms
PV2 = 1, PV1 = 0, PV0 = 1: 10 ms
PV2 = 1, PV1 = 1, PV0 = 0: 50 ms
PV2 = 1, PV1 = 1, PV0 = 1: 100 ms
D7-D5
PR[2:0]
R/W
0
Precharge time selection
These bits set the amount of time allowed for precharging any pin capacitance
on the touch screen prior to sensing whether a pen touch is in progress. The
following lists the precharge time (t(PRE)
PR2 = 0, PR1 = 0, PR0 = 0: 20 μs
PR2 = 0, PR1 = 0, PR0 = 1: 84 μs
)
PR2 = 0, PR1 = 1, PR0 = 0: 276 μs
PR2 = 0, PR1 = 1, PR0 = 1: 340 μs
PR2 = 1, PR1 = 0, PR0 = 0: 1.044 ms
PR2 = 1, PR1 = 0, PR0 = 1: 1.108 ms
PR2 = 1, PR1 = 1, PR0 = 0: 1.3 ms
PR2 = 1, PR1 = 1, PR0 = 1: 1.364 ms
D4-D2
SN[2:0]
R/W
0
Sense-time selection
These bits set the amount of time the TSC2013-Q1 device waits after converting
a coordinate to sense whether a screen touched is in progress.
SNS2 = 0, SNS1 = 0, SNS0 = 0: 32 μs
SNS2 = 0, SNS1 = 0, SNS0 = 1: 96 μs
SNS2 = 0, SNS1 = 1, SNS0 = 0: 544 μs
SNS2 = 0, SNS1 = 1, SNS0 = 1: 608 μs
SNS2 = 1, SNS1 = 0, SNS0 = 0: 2.08 ms
SNS2 = 1, SNS1 = 0, SNS0 = 1: 2.144 ms
SNS2 = 1, SNS1 = 1, SNS0 = 0: 2.592 ms
SNS2 = 1, SNS1 = 1, SNS0 = 1: 2.656 ms
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表 11. Configuration Register 0 Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
D1
DTW
R/W
0
Detection of pen touch in wait (patent pending)
Writing a 1 to this bit enables pen-touch detection in the background while
waiting for the host to issue the converter function in host-initiated and -
controlled modes. This background detection allows the TSC2013-Q1 to pull
PINTDAV high to indicate no pen touch detected while waiting for the host to
issue the converter function. If the host polls a high state at PINTDAV before the
transmission of the convert function, the host can abort the issuance of the
convert function and stay in the polling PINTDAV mode until the detection of the
next pen touch.
D0
LSM
R/W
0
Longer sampling mode. This bit is the LSB.
With this bit set to 1, an extra 500 ns of sampling time is added to the normal
sampling cycles of each conversion. This additional time is represented as
approximately two internal oscillator clock cycles.
44
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7.6.1.2 Configuration Register 1 (address = Dh) [reset = 0000h]
Configuration register 1 (CFR1) defines the connection test-bit modes configuration and batch-delay selection.
图 39. Configuration Register 1
D15
D7
D14
D6
D13
D12
D4
D11
D3
D10
D2
D9
D8
D0
RESERVED
W-0
D5
RESERVED
W-0
D1
BTD[2:0]
R/W-0
表 12. Configuration Register 1 Field Descriptions
Bit
D15-D3 RESERVED
D2-D0 BTD[2:0]
Field
Type
W
Reset
Description
0
0
R/W
Batch time-delay mode
These are the selection bits that specify the delay before the triggering of a
sample or conversion scan cycle. When it is set, Batch time-delay mode uses a
set of timers to trigger
a sequence of sample-and-conversion events
automatically. The mode works for both TSC-initiated scans (XYZ or XY) and
host-initiated scans (XYZ or XY).
Configure a TSC-initiated scan (XYZ or XY) by setting the PSM bit in CFR0 to 1
and C[3:0] in control byte 1 to 0000 or 0001. In the case of a TSC-initiated scan
(XYZ or XY), the sequence begins with the TSC responding to a pen touch.
After the first processed sample set completes during the batch delay, the scan
enters a wait mode until the end of the batch delay. If detection of a pen touch
persists at that moment, the scan continues to process the next sample set,
along with a resumption of the batch delay. The selected batch delay during the
time of the detected pen touch regulates the throughput of the processed
sample sets (shown in as sample sets per second, or SSPS). One can
configure a TSC-initiated scan (XYZ or XY) by setting the PSM bit in CFR0 to 1
and C[3:0] in control byte 1 to 0000 or 0001. Note that the throughput of the
processed sample set also depends on the settings of stabilization, precharge,
and sense times, and the total number of samples to be processed per
coordinates. If the accrual time of these factors exceeds the batch delay time,
the accrual time dominates. Batch delay time starts when the pen touch initiates
the scan function that converts coordinates.
One can configure a host-initiated scan (XYZ or XY) by setting the PSM bit in
CFR0 to 0 and C[3:0] in control byte 1 to 0000 or 0001. For the host-initiated
scan (XYZ or XY), the host must set TSC internal register C[3:0] in control byte
1 to 0000 or 0001 initially after a pen-touch detection; see . After engagement of
the scan (XYZ or XY), the selected batch-delay timer regulates the throughput
of the processed sample sets, as long as the initial detected touch is
uninterrupted.
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表 12. Configuration Register 1 Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
Throughput for TSC-initiated or host-initiated scan, XYZ OR XY:
BTD2 = 0, BTD1 = 0, BTD0 = 0, td = 0: Normal operation throughput
depends on settings
BTD2 = 0, BTD1 = 0, BTD0 = 1, td = 1: 1000 SSPS
BTD2 = 0, BTD1 = 1, BTD0 = 0, td = 2: 500 SSPS
BTD2 = 0, BTD1 = 1, BTD0 = 1, td = 4: 250 SSPS
BTD2 = 1, BTD1 = 0, BTD0 = 0, td = 10: 100 SSPS
BTD2 = 1, BTD1 = 0, BTD0 = 1, td = 20: 50 SSPS
BTD2 = 1, BTD1 = 1, BTD0 = 0, td = 40: 25 SSPS
BTD2 = 1, BTD1 = 1, BTD0 = 1, td = 100: 10 SSPS
For example, if stabilization time, precharge time, and sense time are selected
as 100 μs, 84 μs, and 96 μs, respectively, and the batch delay time is 2 ms,
then the scan function enters wait mode after the first processed sample set
until the 2 ms of batch-delay time expires. When the scan function starts to
process the second sample set (if a touch is still present on the screen), the
batch delay restarts at 2 ms (in this example). This procedure remains regulated
by 2 ms until the pen touch is undetected or a stop bit or any reset form stops
the scan function.
46
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ZHCSCV1A –JUNE 2014–REVISED JULY 2014
7.6.1.3 Configuration Register 2 (address = Eh) [reset = 0000h]
Configuration register 2 (CFR2) defines the preprocessor configuration.
图 40. Configuration Register 2
D15
D14
D13
D5
D12
D11
D10
D2
D9
D1
D8
PINTS1
R/W-0
PINTS0
R/W-0
M[1:0]
W[1:0]
RESERVED
W-0
R/W-00
R/W-00
D7
D6
D4
D3
D0
RESERVED
W-0
RESERVED
MAVE
X TRIPLET
MAVE
Y TRIPLET
MAVE
Z
MAVE
AUX
W-0
R/W-0000
R/W-0000
R/W-0000
R/W-0000
表 13. Configuration Register 2 Field Descriptions
Bit
Field
PINTS1
Type
Reset
Description
D15
R/W
0
This bit controls the output format of the PINTDAV pin. With this
bit set to 0, the output format is the AND-form of internal signals
of PENIRQ and DAV). With this bit set to 1, PINTDAV outputs
PENIRQ only.
PINTDAV PIN OUTPUT =
0: AND combination of PENIRQ (active-low) and DAV (active-
high).
0: Data available, DAV (active-low).
1: Interrupt, PENIRQ (active-low) generated by pen-touch.
1: Data available, DAV (active-low).
D14
PINTS0
R/W
0
This bit selects the output on the PINTDAV pin. With this bit set
to 0, the output format of PINTDAV depends on the selection
made on the PINTS1 bit. With this bit set to 1, PINTDAV outputs
the internal signal of DAV.
PINTDAV PIN OUTPUT =
0: AND combination of PENIRQ (active-low) and DAV (active-
high).
1: Data available, DAV (active-low).
0: Interrupt, PENIRQ (active-low) generated by pen-touch.
1: Data available, DAV (active-low).
D13-D12 M[1:0]
R/W
R/W
00
00
Preprocessing MAV filter control
Note that when the MAV filter is processing data, the STS bit
and the corresponding DAV bits in the status register indicate
that the converter is busy until all conversions necessary for the
preprocessing are complete. The default state for these bits is
0000, which bypasses the preprocessor. These bits are the
same whether reading or writing.
D11-D10 W[1:0]
Preprocessing MAV filter control
Note that when the MAV filter is processing data, the STS bit
and the corresponding DAV bits in the status register indicate
that the converter is busy until all conversions necessary for the
preprocessing are complete. The default state for these bits is
0000, which bypasses the preprocessor. These bits are the
same whether reading or writing.
D9-D5
D4-D1
RESERVED
W
0
MAVE
R/W
0000
MAV-filter function-enable bit
When any bit is set to 1, the MAV filter setup is applied to the
corresponding measurement.
D0
RESERVED
W
0
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7.6.1.4 Converter-Function Select Register (address = Fh) [reset = 0000h]
The converter-function select (CFN) register reflects the converter function select status.
图 41. Converter-Function Select Register
D15
D7
D14
CFN[15:13]
R-0
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
CFN[8:0]
R-0
RESERVED
R-0
D6
D0
CFN[8:0]
R-0
表 14. Converter-Function Select Register Field Descriptions
Bit
Field
Type
Reset
Description
D15-D13 CFN[15:13]
R
0
Touch-screen driver status
These bits represent the current status of the turned-on touch-
screen drivers. The device sets CFN13 to 1 with both X+ and X–
drivers turned on, CFN14 to 1 with both Y+ and Y– drivers
turned on, and CFN15 to 1 with Y+ and X– drivers turned on.
Otherwise, the device sets these bits to 0. The device resets
these bits to 000b whenever the converter function is complete,
stopped by the STS bit, or reset (by a hardware reset from the
RESET pin or a software reset from SWRST bit in control byte
1).
D12-D9 RESERVED
D8-D0 CFN[8:0]
R
R
0
0
Converter function-select status.
These bits represent the converter function currently running,
which is set in bits C3–C0 of control byte 1. When the CFNx bit
shows 1, where x is the decimal value of converter function-
select bits C3–C0, it is an indication that the converter function
set in bits C3–C0 is running. For example, when CFN2 shows 1,
it indicates the converter function set in bits C3-C0 (0010) is
running. Reset of the CFNx bits to 0000h occurs whenever the
converter function is complete, stopped by STS bit, or reset (by
the hardware reset from the RESET pin or the software reset
from SWRST bit in Control Byte 1). However, if the TSC sets the
PSM bit in the CFR0 register to 1 to initiate the scan-function
mode, reset of the CFN0 or CFN1 does not occur when the
corresponding converter function is complete, because there is
no pen touch. This event allows the TSC2013-Q1 to initiate the
scan process (corresponding to CFN0 or CFN1 set to 1)
immediately on detection of the next pen touch.
48
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ZHCSCV1A –JUNE 2014–REVISED JULY 2014
7.6.1.5 Status Register (address = 8h) [reset = 0004h]
The Status Register provides information about the TSC2013-Q1 status.
图 42. Status Register
D15
D14
D13
D12
D11
D10
D9
D8
D0
DAV
Due
X TRIPLET
DAV
Due
Y TRIPLET
DAV
Due
Z1
DAV
Due
Z2
DAV
Due
AUX
RESERVED
R-0
D5
R-0
D1
D7
D6
D4
D3
D2
RESET
Flag
RESERVED
R-0
PDST
RESERVED
R-0
R-0
R-1
表 15. Status Register Field Descriptions
Bit
Field
Type
Reset
Description
D15-D11 DAV
R
0
Data available bits
These five bits mirror the operation of the internal signals of
DAV. On storing any processed data in data registers, the DAV
bit (D15 to D11) corresponding to the data type is set to 1. The
bIt stays at 1 until the registers updated to the host has read out
the processed data. If the user submits a single IX or single IY
conversion command, bit D15 or D14 (respectively) shows data
availability. In this case, only data register IX or IY receives an
update.
0: No new processed data are available.
1: Processed data are available. This bit remains at 1 until
the host has read out all updated registers.
D10-D8 RESERVED
R
R
0
0
D7
RESET
Interpretation of the RESET flag bits:
0: Device was reset since the last status poll (hardware or
software reset).
1: Device reset has not occurred since the last status poll.
D6-D3
D2
RESERVED
PDST
R
R
0
1
Power-down status
This bit reflects the setting of the PND0 bit in Control Byte 0.
When this bit shows 0, it indicates ADC bias circuitry power is
still on after each conversion and before the next sampling;
otherwise, it indicates ADC bias circuitry power is down after
each conversion and before the next sampling. However, power
is down between conversion sets. Because this status bit is in
synchrony with the internal clock, it does not reflect the setting of
the PND0 bit until detection of a pen touch is detected or
initiation of a converter function.
D1-D0
RESERVED
R
0
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7.6.2 Data Registers
The data registers of the TSC2013-Q1 hold data results from conversions. All of these registers default to 0000h
on reset.
7.6.2.1 X1, X2, IX, Y1, Y2, IY, Z1, Z2, and AUX registers (offset = see 表 10) [reset = see 表 10]
The results of all ADC conversions are placed in the appropriate data registers, as described in 表 9. The data
format of the result word (R) of these registers is right-justified, as shown in .
图 43. X1, X2, IX, Y1, Y2, IY, Z1, Z2, and AUX Registers
D15
D14
D13
D12
D11
R11(1)
R-0
D10
R10(1)
R-0
D9
R9
D8
R8
RESERVED
R-0
R-0
R-0
D7
R7
D6
R6
D5
R5
D4
R4
D3
R3
D2
R2
D1
R1
D0
R0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
(1) R11 and R10 are 0 in 10-bit mode.
表 16. X1, X2, IX, Y1, Y2, IY, Z1, Z2, and AUX Register Field Descriptions
Bit
Field
Type
Reset
Description
D15-D12 RESERVED
R
0
Use of the D15 bit only occurs during a single IX or single IY
conversion command (see 表 10).
T = 0: No touch detected during conversion
T = 1: Touch detected during conversion
D11-D0 R[11:0]
R
0
12-bit data
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8 Application and Implementation
8.1 Application Information
8.1.1 Auxiliary Measurement
The TSC2013-Q1 device can measure the voltage from the auxiliary input (AUX). Applications for the AUX can
include external temperature sensing, ambient light monitoring for controlling backlighting, or sensing the current
drawn from batteries. Two converter functions can be used for the measurement of the AUX:
1. Non-continuous AUX measurement as shown in 图 44 (converter function select bits C[3:0] = control byte 1
D[6:3] = 0101)
2. Continuous AUX measurement as shown in 图 45 (converter function select bits C[3:0] = control byte 1
D[6:3] = 1000)
See 表 7 for more information on the converter function select bits.
Use 公式 9 to calculate the time required to make a non-continuous auxiliary measurement.
§
·
§
· §
¸ ¨
¹ ©
·
W(OH3)
¦
¦
W(PPRO)
1
(OSC)
(ADC)
t(COORDINATE)
ꢂN u B ꢂ 2 u
ꢂ tc(OH)
u
ꢂ
¨
¸
¸
¹
¨
¨
©
¸ ¨
¸
¸
¹
ꢀ
ꢁ
¨
¦
¦
¦
(OSC)
(OSC)
(OSC)
©
where
•
t(OH3) = overhead time number 3 = 3.5 internal clock cycles.
(9)
TSC
Not Addressed
TSC
Not Addressed
TSC
Not Addressed
Reading
AUX-Data
Register
Programmed for
Non-Continuous
AUX Measurement
t(COORDINATE)
No Touch
Detected
Sample, Conversion, and
Averaging for AUX Measurement
No Touch
Detected
Host Write to
Control Byte 1 D[6:3]
Waiting for Host to
Read AUX Data
As DAV
图 44. Non-Touch Screen, Non-Continuous AUX Measurement
Use 公式 9 to calculate the time required to make a continuous auxiliary measurement.
TSC
Not
Addressed
TSC
Not Addressed
TSC
Not Addressed
TSC
Not Addressed
Programmed for
Continuous
Reading
AUX-Data
Register
Reading
AUX-Data
Register
AUX Measurement
t(COORDINATE)
t(COORDINATE)
t(COORDINATE)
Sample, Conversion,
and Averaging for
AUX Measurement
Sample, Conversion,
and Averaging for
AUX Measurement
Sample, Conversion,
and Averaging for
AUX Measurement
No Touch
Detected
Host to Write to
Control Byte 1 D[6:3]
As DAV
图 45. Non-Touch Screen, Continuous AUX Measurement
8.1.2 Single IX or Single IY Measurement
图 46 shows the sequence for a single IX or single IY measurement.
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Application Information (接下页)
TSC
Not Addressed
TSC
Not Addressed
TSC
Not Addressed
Reading
IX or IY Data
Register
Single IX or
Single IY Measurement
t(COORDINATE)
No Touch
Detected
Sample, Conversion, and
Averaging for IX or IY Measurement
No Touch
Detected
Host Write to
Control Byte 1 D[6:3]
Waiting for Host to
Read IX or IY Data
As DAV
图 46. Touch Screen, Single IX or IY Measurement
8.2 Typical Application
1.6 VDC
1 µF
0.1 µF
1.6 VDC
AGND
Host
1.2 kΩ
1.2 kΩ
Processor
PINTDAV
RESET
SDA
GPIO
GPIO
SDA
SCL
X+
Y+
TSC2013-Q1
X–
Y–
SCL
Touch
Screen
(PINTDAV is optional;
software implementation
polling of the Status register is
possible)
AGND
R(SENSE)
47 Ω
图 47. Typical Application Diagram
8.2.1 Design Requirements
The system-level requirements for this design include:
•
•
•
Normal 4-wire resistive touch screen with low activation force (from center area down to 0.1 to 0.3 N) to
enable smooth dual-touch operation.
The R(SENSE) resistor value is the lowest panel resistance (X or Y layer) which is approximately 4.5. This
resistor value provides the best dynamic range for dual-touch separation.
To achieve the best possible SNR, select the highest operating voltage of the TSC2013-Q1 device that is
compatible with the system.
8.2.2 Detailed Design Procedure
Resistive dual touch using TSC2013-Q1 device is based on the principle of measuring resistance changes
between X and Y panel. The resistive touch screen has two ITO layers which are located apart from each other.
When the user uses a single-finger touch, only a minor parallel connection occurs between these two layers.
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Typical Application (接下页)
During a dual-finger touch when the finger touches are located on different areas of the screen, parallel
connection is much higher which results in a reduction in panel resistance. Because the TSC2013-Q1 device
measures both X and Y-layer panel resistance, the finger touch distance can be easily calculated from the
resistance change. This calculation is achieved by using one external resistor the is connected internally in series
with the measured X-Y panel.
Use the following methods to enable the dual-touch function of the TSC2013-Q1 device:
•
•
•
Measure all four nodes and use those measurements to calculate center point of the finger touch.
Use the measurements of the four nodes to correctly place the touch positions to the correct quadrants.
Measure the two-layer panel resistance by using a single external resistor that is connected internally in
series with measured panel layer. A change in resistance is interpreted as a change in finger distance.
All calculations are performed by the host-side processor. The TSC2013-Q1 device provides only data.
The following sections describe the design procedure in detail.
8.2.2.1 Power-On-Reset and Reset Consideration
The TSC2013-Q1 device can be rest to the default working state in one of three ways. These resets are: power-
on reset (see the Power-On Reset section), hardware reset (see the Hardware Reset section), and software
reset (see the Software Reset section).
The requirements for ensuring a proper TSC2013-Q1 power-on reset (POR) are very stringent and can be very
hard to meet in many applications. To workaround this issue, users should apply a proper hardware or software
reset, instead of or in addition to the POR.
8.2.2.1.1 Power-On Reset
Based on design principles and extensive tests with TSC2013-Q1 device, the power of the device must meet a
specific on-off timing and sequence to ensure the POR is implemented during each TSC2013-Q1 power on. This
specific timing and sequence also ensures that a lockup is prevented.
During the device power on, the POR brings the TSC2013-Q1 device into a known default working state by
initializing the internal state machine, data and control registers, and the condition of the output pins. Without the
POR, the TSC2013-Q1 device can power on in a random state and can cause the PINTDAV pin to respond
incorrectly.
The TSC2013-Q1 POR circuit was designed to not consume power during normal operation. The power-down
current is kept as low as possible (0.8-µA maximum power-down supply current).
This POR circuit in TSC2013-Q1 device requires specific power-up and power-down ramps and sequences.
Figure 48 shows and Table 17 lists the recommended power-off times, on-ramp, and off-ramp specifications.
t
t
(SNSVDD_ON_ramp)
(SNSVDD_OFF_ramp)
SNSVDD
0 V
t
(SNSVDD_OFF)
Figure 48. POR Sequence
Table 17. Requested POR Timings
(1)
TEMPERATURE RANGE
–40°C to –21°C
MINIMAL t(SNSVDD_OFF_ramp)
MINIMAL t(SNSVDD_ON_ramp)
MINIMAL t(SNSVDD_OFF)
12 kV/s
2 kV/s
12 kV/s
12 kV/s
1.2 s
–20°C to 85°C
200 ms
(1) t(SNSVDD_OFF) time begins when the SNSVDD pin voltage reaches and stays at 0 V.
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8.2.2.1.2 Requesting a Minimal t(SNSVDD_OFF) Time
The POR circuit of the TSC2013-Q1 device contains a capacitor that is charged when the device powers up
which generates an internal reset signal. This capacitor is discharged after the TSC2013-Q1 supply is switched
off. The TSC2013-Q1 device is designed for low-power operation, therefore the POR requires time to charge and
discharge the capacitor, especially under cold temperatures (less than –20°C). If the SNSVDD off time is not
sufficient, the device can lock up. Only a power recycle can resolve this lockup condition.
8.2.2.1.3 Requesting a Minimal t(SNSVDD_OFF_ramp) and t(SNSVDD_ON_ramp) Ramp
To ensure proper initialization of the TSC2013-Q1 device, the device must reach a certain voltage before the
internal POR signal is released. If the power supply on the ramp is too slow the device can power up in a random
state which can cause a lock up.
The capacitor inside the POR circuit must be discharged through the SNSVDD pin. To support a proper
discharge when the TSC2013-Q1 supply is switched off, TI recommends to provide a low resistance path on the
SNSVDD pin.
8.2.2.1.4 Hardware Reset
The hardware reset pin, RESET, is available to perform a system reset which resets the device if the pulse width
meets the timing requirement (at least 10-µs wide and the SNSVDD/VREF or I/OVDD pin is greater than or equal
to 1.6 V). Any reset pulse less than 5 µs is rejected. To accommodate the timing drift between devices because
of process variation, a reset pulse width between 5 µs and 10 µs is not recognized and the result is
undetermined. This situation should be avoided. A good reset pulse must be low for at least 10 µs
(SNSVDD/VREF or I/OVDD pin is greater than or equal to 1.6 V). An internal spike filter rejects spikes up to 20
ns wide. See 图 37 for the hardware reset timing diagram.
8.2.2.1.5 Software Reset
During normal operation a software reset can be sent by the host processor to the device by setting the SWRST
bit (D1) to 1 in the control byte 1 (see 表 6).
8.2.2.2 Power Up Considerations
8.2.2.2.1 Power-Off Cycles During Normal Operation
The TSC2013-Q1 device is a low-power device and therefore switching the TSC2013-Q1 device off during
normal operation is not needed nor recommended.
Every power cycle (power on → power off → power on) must meet the requirements described in the Power-On
Reset section. If requirements cannot be met, TI recommends to issue a hardware reset after every power cycle.
8.2.2.2.2 Supply Glitches During Normal Operation
A TSC2013-Q1 SNSVDD or IOVDD power glitch during normal operation can cause a lockup condition.
Therefore ensure that the system is able to either recycle the power in the system following the requirements
described in the Power-On Reset section or issue a hardware reset as described in the Hardware Reset section.
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8.2.2.2.3 TSC2013-Q1 Digital Pins
In many applications, users use the same power supply for both the TSC2013-Q1 analog and digital supplies.
The SNSVDD supply is connected with the I/OVDD supply. Under such cases, the logic high status on the
TSC2013-Q1 digital pins before power-up become a concern when performing a proper POR.
Table 18 lists the digital I/O pins of the TSC2013-Q1 device.
Table 18. TSC2013-Q1 Digital Pin List
TSC2013-Q1 PINS
DESCRIPTION
PINTDAV
Digital Output. Data available or the pen-detect interrupt (PENIRQ), depending on setting. Pin polarity
is active-low.
RESET
SCL
SDA
A0
Digital input. External hardware reset input (active-low).
Open drain and collector. Serial clock
Open drain and collector. Serial data I/O
Digital input. I2C bus TSC address input bit 0
Digital input. I2C bus TSC address input bit 1
A1
Every TSC2013-Q1 pin is well protected against ESD strikes. The TSC2013-Q1 RESET, A0, and A1 pins have
the same protection as the SDA and SCL pins. This protection allows the RESET, A0, and A1 pins to be pulled
high before the device powers on without activating an internal ESD diode and without causing a power up of the
TSC2013-Q1.
The output pin, PINTDAV, is a digital output pin. The host processor must define the PINTDAV pin as an input to
the host processor without any pullup-pulldown feature. In some cases the default of the host processor is an
output with an enabled pullup-pulldown feature but the host-processor firmware changes this definition at a later
point to an input. If the TSC2013-Q1 device is not powered up, a power up can also occur through the ESD cells
as shown in by the red line in Figure 49. This power up is considered a false power up. A false power up cannot
ensure a proper power supply to the device or a proper POR.
In case the TSC2013-Q1 device is powered up, both the device and drive processor drive different levels on the
same line resulting in high power consumption.
The TSC2013-Q1 PINTDAV pin should be connected to the correct pin on the host processor to avoid bus
conflicts and illegal powering up of the TSC2013-Q1 device.
I/OVDD
PINTDAV
Digital Output
TSC2013-Q1
GND
Figure 49. Internal ESD Protection Diodes at the TSC2013-Q1 PINTDAV Pin
8.2.2.2.4 Suggested Hardware Reset During Power-On
The suggested sequence during power up is the following:
•
•
•
Keep RESET pin low
Wait for the supplies to settle
Wait for at least 10µs before releasing the RESET pin
Figure 50 shows the suggested waveform.
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SNSVDD
I/OVDD
> 10 µs
RESET
Figure 50. Suggested RESET Waveform During Power-On
8.2.2.3 Device Timing Setup and Use
The TSC2013-Q1 device is a register-based touch-screen controller (TSC). This section describes the setup and
use of the programable timings available in the TSC2013-Q1 device.
图 52 through 图 56 in the Application Curves were generated to show the principal. The TSC2013-Q1 X triplet
contains X1, X2, and IX conversions. The TSC2013-Q1 Y triplet contains Y1, Y2, and IY conversions. The
TSC2013-Q1 Z measurement contains Z1 and Z2 conversions.
8.2.2.3.1 Touch-Panel Driving Power
On a resistive touch-screen system, the driving current of the touch panel, provided by the TSC device through
the analog interface, has the highest impact on the power consumption in the touch screen system. This touch-
panel power consumption is decided by the resistance of the touch panel and the TSC power-supply (SNSVDD)
voltage. 图 51 shows this relationship. The touch screen is driven by the TSC from the SNSVDD supply and the
resistance of the panel determines the peak drive current.
图 51 only shows the ideal TSC driving condition where the internal resistance of the TSC is ignored because the
resistance is small (5 to 6 Ω) compared to the resistance of the touch panel (100s to 1000s Ω). Therefore the
actual power consumption should be a little less than that shown in 图 51.
A user can reduce power consumption in three ways:
•
•
•
Using touch screens with higher resistance
Using a low-power supply, SNSVDD, to the TSC
Reducing the driver on-time or the on-off ratio of the driver
Touch panels with higher resistance are likely to cause more noise and longer settling time which limits the
options for users.
The TSC20013-Q1 device is designed with a power supply, SNSVDD, range of 1.6 V to 3.6 V.
Reducing the driver on-time involves setting various touch-screen timings and delays. lists the relevant
parameters concerning these timings and delays. The following sections describe the functions and effects of
these timings and delays. See the Register Maps section for the timing settings of the configuration registers.
8.2.2.3.2 ADC Clock Effects
A TSC2013-Q1 device contains a nominal 4-MHz internal clock that is used to drive the state machines inside
the device which performs the many functions. This clock is divided down to provide a clock to run the SAR ADC
(analog-to-digital converter). If the 4-MHz clock is used directly (divided by 1), the ADC is limited to a 10-bit
resolution, then using higher resolutions at this speed does not result in accurate conversions. The 12-bit
resolution requires that the conversion clock run at either 2 MHz (divided by 2) or 1 MHz (divided by 4). The
division ratio for the ADC clock is set in the configuration register 0 (CFR0), by setting the CL1 and CL0 bits (see
表 6).
56
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The ability to change the conversion clock rate allows the user to select the optimal value for the ADC resolution,
speed, and power dissipation. Higher clock frequency results in faster touch-data converting speed and shorter
touch-driver on-time which usually result in lower SNSVDD power consumption. 图 52 and 图 53 show examples
of the ADC clock effect on the analog interface traffic (X+, X–, Y+, and Y– lines). In these figures, a TSC drives
the touch panel to acquire the X, Y, Z1, and Z2 coordinates and three samples-per-coordinate. 图 52 shows an
analog interface with the clock frequency set to 2 MHz. 图 53 shows an analog interface with the clock frequency
set to 1-MHz. In 图 52 and 图 53, other than the ADC clock frequency difference, all other settings are
completely identical with the following values: PVS equal to 0 µs, PR equal to 20 µs, and SN equal to 32 µs (see
the Panel Voltage Stabilization Time section for more information on these timers).
The ADC clock frequency determines the length of the TSC acquisition time and TSC driver on-time. The faster
the ADC clock, the shorter the driver on-time. For example, sampling 3 Y data with an ADC clock value of 2 MHz
(see 图 52) uses only about half of the time compared to sampling the data with an ADC clock value of 1 MHz
(see 图 53).
Use Equation 10 to calculate the analog power-supply current, I(SNSVDD)
.
§
·
V
§
·
SSPS u S u B
(SNSVDD)
I(SNSVDD) f V
ꢂ
u
¨
¨
©
¸
¸
¹
ꢀ
(SNSVDD) ꢁ
¨
¨
¸
¸
5
¦
(OSC)
©
¹
where
•
•
•
•
f(V(SNSVDD)) is a function of V(SNSVDD)
V(SNSVDD) is the SNSVDD voltage (in V)
R is the average resistance of the touch panel (in Ω)
SSPS is sample sets-per-second, which indicates how many sets of touch data is received by the host within a
second
•
•
•
S is the number of data in a set of samples
B is the TSC resolution, either 10 bit or 12 bit
ƒ(OSC) is ADC clock frequency, which can be 4, 2, or 1 MHz
(10)
Equation 10 includes two parts: the internal circuitry power consumption or f(V(SNSVDD)) and the current to drive
the external resistive-touch panel which is calculated using Equation 11.
§
·
V
§
·
SSPS u S u B
(SNSVDD)
I(TOUCHꢀPANEL)
u
¨
¨
©
¸
¸
¹
¨
¨
¸
¸
5
¦
(OSC)
©
¹
(11)
A concern for using the faster ADC clock is because of the settling time or transients of the analog interface. The
higher clock frequency can reduce the accuracy of the data in those cases where the TSC begins the data
acquisitions before the analog interface lines reach the stable voltages. Therefore, adding some delays on the
analog interface in order to wait for the interface to become stable before an ADC begins working might be
necessary. These delays can include the panel voltage-stabilization time, the precharge time of the pins, the
sense time (see the Panel Voltage Stabilization Time section), or a combination.
8.2.2.4 Panel Voltage Stabilization Time
The panel voltage-stabilization time, td(PVS), specifies a delay time from the moment the touch screen drivers are
enabled to the time the voltage is sampled and a conversion is started. These bits allow the user to adjust the
appropriate settling time for the touch panel based on the external capacitances at the analog interface lines.
图 54 shows examples where with td(PVS) is 0 µs (no PVS delay), 100 µs, and 500 µs. In the examples, the TSC
uses the sets of 4 × 3 = 12 data which are 3 X, 3 Y, 3 Z1, and 3 Z2. The TSC2013-Q1 device always performs
the Y coordinate first when it was set to X-Y or X-Y-Z scan mode. The sequence for receiving a set of samples in
图 54 is as follows:
1. The TSC adds driver power to Y+ (SNSVDD) and Y– (AGND), waits td(PVS) µs, and acquires 3 Y data
2. The TSC adds driver power to X+ (SNSVDD) and X– (AGND), waits td(PVS) µs, and acquires 3 X data
3. The TSC adds driver power to Y+ (SNSVDD) and X– (AGND), waits td(PVS) µs, and acquires 3 Z1 and 3 Z2
data
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The PVS delay consumes power because a driver is on during the PVS delay. Use Equation 12 to calculate the
power.
V
§
·
(SNSVDD)
P
u SSPS u t
u 3
d(PVS)
¨
¨
¸
¸
R
©
¹
where
•
3 indicates that the X, Y, and Z drivers are on
(12)
Based on Equation 10, use Equation 13 to calculate a complete expression of the analog power consumption for
X-Y-Z 3-dimension coordinates.
V
§
·
S u B
F
ª
º
(SNSVDD)
P f V
ꢂ
u SSPS u
ꢂ 3 u td(PVS)
ꢀ
(SNSVDD) ꢁ
¨
¨
¸
¸
«
¬
»
¼
R
©
¹
(13)
(14)
Use Equation 14 to calculate the power consumption for X-Y 2-dimension touch data.
V
§
·
S u B
F
ª
º
(SNSVDD)
P f V
ꢂ
u SSPS u
ꢂ 2 u td(PVS)
ꢀ
(SNSVDD) ꢁ
¨
¨
¸
¸
«
¬
»
¼
R
©
¹
where
•
2 indicates that the X and Y drivers are on
8.2.2.5 Precharge and Sense Time
Unlike the ADC clock frequency (bits CL1 to CL0) and panel voltage-stabilization time (bits PV2 to PV0), the
other two TSC timings in the CFR0 register (see 表 6) affect the bus shape and traffic speed but do not effect
power consumption of the analog interface.
As shown in 图 54, some added time or delays occur between samples of two coordinates such as after
sampling Y and before the X driver turns on. This added time or delay is the precharge time (bits PR2 to PR0)
and sense time (bits SN2 to SN0).
The precharge time sets the amount of time allowed for precharging any pin capacitance on the touch screen
during TSC ADC conversions as shown in 图 55.
The sense time sets the amount of delay for the TSC device to wait between two coordinates during TSC ADC
conversions as shown in 图 56.
If a pressure remains on the touch panel, the TSC devices can automatically and continuously acquire touch
data. As many as several-thousand SSPS of touch data can be driven on, sampled, converted, and processed.
For a typical application, however, users usually need only 100 to 500 SSPS of touch data because of the control
and response limits of a human. To save power, users often do not want the system to acquire any unnecessary
data.
The SSPS of a TSC can be reduced in several ways, including:
•
•
Using the batch delay to add waiting time between the sets of touch data
Inserting delays, such as PR and SN (but not PVS), to slow down the coordinate samples within a set
because PR and SN do not consume power
See 表 6 for the bit locations and for the selectable time ranges.
8.2.2.6 Single-Touch Operation
The TSC2013-Q1 device can also be used only for single-touch operation. By measuring all 4-wire nodes (X+,
X–, Y+, Y–) more-precise touch accuracy can be achieved compared to normal resistive TSCs.
TI advises to calculate the center point of the touch by using both node values. Equation 15 shows an example.
X = 0.5 × ([X+] – [X–]) + (X+)
(15)
This same calculation method is used on dual-touch middle-point calculation.
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8.2.3 Application Curves
18
16
14
12
10
8
Sample 3 Y
SNSVDD = 1.6 VDC
SNSVDD = 2.5 VDC
SNSVDD = 3 VDC
SNSVDD = 3.6 VDC
Sample 3 X
Sample 3 Z1 and Z2
X+
X–
Y+
6
4
2
0
Y–
200 400 600 800 1000 1200 1400 1600 1800 2000
Panel Resistance (Ω)
图 52. Analog Interface Under
图 51. Touch Panel Power Consumption
ADC Clock = 2 MHz
Sample 3 Y
Sample 3 X
Sample 3 Z1 and Z2
X+
X+
X–
Y+
Sample 3 Y
Sample 3 X
Sample 3 Z1 and Z2
X–
Y+
PV = 500 µs
PV = 100 µs
PV = 0 µs
Y–
Y–
图 54. Panel Voltage Stabilization 0 µs, 100 µs,
图 53. Analog Interface Under
and 500 µs
ADC Clock = 1 MHz
Precharge time
or PR
Sense time
or SN
X+
X+
X–
Y+
X–
Y+
Y–
Y–
图 55. Precharge Time on TSC Analog Interface Lines
图 56. Sense Time on TSC Analog Interface Lines
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9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 1.6 V and 3.6 V. Power to the
TSC2013-Q1 device should be clean and well-bypassed. Add a 0.1-μF ceramic bypass capacitor between
(SNSVDD and AGND) or (I/OVDD and AGND).
10 Layout
10.1 Layout Guidelines
The following layout suggestions should obtain optimum performance from the TSC2013-Q1 device. However,
many portable applications have conflicting requirements for power, cost, size, and weight. In general, most
portable devices have fairly clean power and grounds because most of the internal components are very low-
power. This situation would mean less bypassing for the converter power and less concern regarding grounding.
Still, each application is unique, so review the following suggestions carefully.
For optimum performance, take care with the physical layout of the TSC2013-Q1 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the power supply, reference, and ground connections,
and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any
single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can
easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital
logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout,
and the exact timing of the external event. The error can change if the external event changes in time with
respect to the SCL input.
With this in mind, power to the TSC2013-Q1 device should be clean and well-bypassed. Add a 0.1-μF ceramic
bypass capacitor between (SNSVDD and AGND) or (I/OVDD and AGND). The circuit also requires a 0.1-μF
decoupling capacitor between SNSVDD/VREF and AGND. Place these capacitors as close to the device as
possible. The circuit may also require a 1-μF to 10-μF capacitor if the impedance of the connection between
SNSVDD/VREF and the power supply is high. Short I/OVDD to the same supply plane as SNSVDD/VREF. Short
both SNSVDD/VREF and I/OVDD to the analog power-supply plane.
The ADC architecture offers no inherent rejection of noise or voltage variation in regards to using an external
reference input, which is of particular concern when the reference input is tied to the power supply for auxiliary
input. Any noise and ripple from the supply appears directly in the digital results. While high-frequency noise can
be filtered out by the built-in MAV filter, voltage variation as a result of line frequency (50 Hz or 60 Hz) can be
difficult to remove. Avoid any active trace going under the analog pins listed in the table without shielding them
by a ground or power plane.
Connect the AGND pin to a clean ground point. In many cases, this connection will be the analog ground. Avoid
connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power-supply entry or battery-connection point. The ideal layout
includes an analog ground plane dedicated to the converter and associated analog circuitry.
In the specific case of use with a resistive touch screen, take care with the connection between the converter and
the touch screen. Because resistive touch screens have fairly low resistance, the interconnection should be as
short and robust as possible. Loose connections can be a source of error when the contact resistance changes
with flexing or vibrations.
As indicated previously, noise can be a major source of error in touch-screen applications (for example,
applications that require a backlit LCD panel). This electromagnetic interference (EMI) noise can coupled through
the LCD panel to the touch screen and cause flickering of the converted ADC data. On can do several things to
reduce this error, such as using a touch screen with a bottom-side metal layer connected to ground, which
couples the majority of noise to ground. Another way to filter out this type of noise is by using the TSC2013-Q1
built-in MAV filter (see the section). Filtering capacitors, from Y+, Y–, X+, and X– to ground, can also help. Note,
however, that the use of these capacitors increases screen settling time and requires longer panel voltage
stabilization times, and also increases precharge and sense times for the PINTDAV circuitry of the TSC2013-Q1
device. The resistor value varies depending on the touch-screen sensor used. The internal 50-kΩ pullup resistor
(R(IRQ)) may be adequate for most sensors.
60
版权 © 2014, Texas Instruments Incorporated
TSC2013-Q1
www.ti.com.cn
ZHCSCV1A –JUNE 2014–REVISED JULY 2014
10.2 Layout Example
Bypass Capacitor
R(SENSE) Resistor
Ground Plane
2
1
2
1
1
2
1
2
1
1
1
1
2
1
1
12
11
10
9
2
1
2
3
4
1
2
1
2
1
2
17
2
1
1
2
1
1
2
图 57. TSC2013-Q1 Layout Example
11 器件和文档支持
11.1 商标
All trademarks are the property of their respective owners.
11.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 要获得这份数据表的浏览器版本，请查阅左侧导航栏。
版权 © 2014, Texas Instruments Incorporated
61
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TSC2013QPWRQ1
TSC2013QRSARQ1
ACTIVE
ACTIVE
TSSOP
QFN
PW
16
16
2000 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TS2013Q
RSA
NIPDAU
TSC
2013Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TSC2013QPWRQ1
TSC2013QRSARQ1
TSSOP
QFN
PW
16
16
2000
2500
330.0
330.0
12.4
12.4
6.9
5.6
1.6
8.0
8.0
12.0
12.0
Q1
Q2
RSA
4.25
4.25
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TSC2013QPWRQ1
TSC2013QRSARQ1
TSSOP
QFN
PW
16
16
2000
2500
350.0
346.0
350.0
346.0
43.0
33.0
RSA
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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