TS3A5017QRGYRQ1 [TI]

具有断电保护功能的汽车类 3.3V、4:1、2 通道模拟多路复用器 | RGY | 16 | -40 to 125;


型号：	TS3A5017QRGYRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有断电保护功能的汽车类 3.3V、4:1、2 通道模拟多路复用器 \| RGY \| 16 \| -40 to 125 复用器
文件：	总24页 (文件大小：773K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

适用于汽车的 TS3A5017-Q1 双通道 4:1 模拟开关转换器

1 特性

2 应用

•

符合面向汽车应用的 AEC-Q100 标准

•

采样和保持电路

信息娱乐音频和视频信号路由

远程信息处理控制单元

–

器件温度范围：–40°C 至 125°C，T_A

器件 HBM 分类等级：±1500V

器件 CDM 分类等级：±1000V

3 说明

•

支持关断保护，当 V_CC= 0V 时，I/O 引脚处于高阻

抗状态

TS3A5017-Q1 器件是一款双通道 4:1 多路复用器，其

设计工作电压为 2.3V 至 3.6V。该器件是一款双向器

件，可以处理数字和模拟信号。该器件的断电保护功能

可确保 V_CC= 0V 时信号路径为高阻抗，从而简化了电

源定序，并提高了系统可靠性。

•

低导通状态电阻

低电荷注入

1Ω 通态电阻匹配

0.25% 总谐波失真 (THD+N)

2.3V 至 3.6V 单电源运行

器件信息⁽¹⁾

锁断性能超过 100mA，符合 JESD 78 II 类规范的

要求

器件编号

封装

VQFN (16)

封装尺寸（标称值）

TS3A5017-Q1

4.00mm × 3.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

方框图

IN1

IN2

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCDS387

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 15

Application and Implementation ........................ 16

9.1 Application Information............................................ 16

9.2 Typical Application ................................................. 16

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics for 3.3-VSupply................. 5

6.6 Electrical Characteristics for 2.5-VSupply................. 6

6.7 Switching Characteristics for 3.3-VSupply................ 8

6.8 Switching Characteristics for 2.5-VSupply................ 8

6.9 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 11

Detailed Description ............................................ 15

8.1 Overview ................................................................. 15

8.2 Functional Block Diagram ....................................... 15

10 Power Supply Recommendations ..................... 17

11 Layout................................................................... 18

11.1 Layout Guidelines ................................................. 18

11.2 Layout Example .................................................... 18

12 器件和文档支持 ..................................................... 19

12.1 器件支持................................................................ 19

12.2 文档支持................................................................ 19

12.3 接收文档更新通知 ................................................. 20

12.4 社区资源................................................................ 20

12.5 商标....................................................................... 20

12.6 静电放电警告......................................................... 20

12.7 术语表 ................................................................... 20

13 机械、封装和可订购信息....................................... 20

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2018 年 10 月

最初发布版本

TS3A5017-Q1

www.ti.com.cn

ZHCSIY9 –OCTOBER 2018

5 Pin Configuration and Functions

RGY Package

16-Pin VQFN

(Top View)

IN2

1S4

1S3

1S2

1S1

2EN

IN1

Thermal

Pad

2S4

2S3

2S2

2S1

Not to scale

If exposed thermal pad is used, it must be connected as a secondary ground or left electrically open.

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

I/O

Common path for switch 1

Active-low enable for switch 1

Switch 1 channel 1

Switch 1 channel 2

Switch 1 channel 3

Switch 1 channel 4

Common path for switch 2

Active-low enable for switch 2

Switch 2 channel 1

Switch 2 channel 2

Switch 2 channel 3

Switch 2 channel 4

Ground

1EN

1S1

1S2

1S3

1S4

I/O

2EN

2S1

2S2

2S3

2S4

GND

IN1

I/O

–

Switch 1 input select

Switch 2 input select

Supply voltage

IN2

V+

–

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

(2)

MIN

–0.5

MAX

UNIT

V₊

V_S, V_DAnalog voltage^{(3) (4)}

Supply voltage⁽³⁾

4.6

I_SK

Analog port clamp current

V_S, V_D< 0

–50

I_DK

I_S, I_D

V_I

ON-state switch current

V_S, V_D= 0 to 7 V

V_I< 0

–128

–0.5

–50

128

4.6

Digital input voltage

I_IK

Digital input clamp current^{(3) (4)}

Continuous current through V₊

Continuous current through GND

Storage temperature

°C

I₊

100

I_GND

T_stg

–100

–65

150

(1) Stresses beyond those listed underAbsolute Maximum Ratings may cause permanent damage to thedevice. These are stress ratings

only, and functional operation of the device at these or any otherconditions beyond those indicated under Recommended

OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extendedperiods may affect device reliability.

(2) The algebraic convention, whereby the most negative value is aminimum and the most positive value is a maximum.

(3) All voltages are with respect to ground, unless otherwisespecified.

(4) The input and output voltage ratings may be exceeded if theinput and output clamp-current ratings are observed.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1500

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

3.6

UNIT

V_I/O

V+

V_I

Switch input/output voltage range

Supply voltage range

2.3

3.6

Control input voltage range

Operating Temperature Range

3.6

T_A

–40

125

°C

6.4 Thermal Information

TS3A5017-Q1

RGY (VQFN)

16 PINS

47.1

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

58.5

24.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

1.8

ψ_JB

24.0

(1) For more information about traditional and new thermalmetrics, see the IC Package ThermalMetrics application report .

TS3A5017-Q1

www.ti.com.cn

ZHCSIY9 –OCTOBER 2018

6.5 Electrical Characteristics for 3.3-VSupply

V₊= 2.7 V to 3.6 V, T_A= –40°C to125°C (unless otherwise noted)⁽¹⁾

PARAMETER

Analog Switch

V_D, V_S

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog signal range

V₊

T_A= 25°C

V₊= 3 V

ON-state

resistance

0 ≤ V_S≤ V₊,

I_D= –32 mA,

Switch ON,

see 图 12

r_on

Ω

T_A= Full

V₊= 3 V

T_A= 25°C

V₊= 3 V

ON-state

resistance match

between channels

V_S= 2.1 V,

I_D= –32 mA,

Switch ON,

see 图 12

Δr_on

T_A= Full

V₊= 3 V

T_A= 25°C

V₊= 3 V

ON-state

resistance flatness

0 ≤ V_S≤ V₊,

I_D= –32 mA,

Switch ON,

see 图 12

r_on(flat)

T_A= Full

V₊= 3 V

0.3

T_A= 25°C

V₊= 3.6 V

0.05

0.5

V_S= 1 V, V_D= 3 V,

V_S= 3 V, V_D= 1 V,

I_S(OFF)

T_A= Full

V₊= 3.6 V

–0.3

–10

–0.3

–20

Switch OFF,

see 图 13

OFF leakage

current

μA

T_A= 25°C

V₊= 0 V

V_S= 0 to 3.6 V,

V_D= 3.6 V to 0,

I_SPWR(OFF)

T_A= Full

V₊= 0 V

T_A= 25°C

V₊= 3.6 V

0.05

0.5

V_S= 1 V, V_D= 3 V,

V_S= 3 V, V_D= 1 V,

I_D(OFF)

T_A= Full

V₊= 3.6 V

Switch OFF,

see 图 13

OFF leakage

current

μA

T_A= 25°C

V₊= 0 V

V_D= 0 to 3.6 V,

V_S= 3.6 V to 0,

I_DPWR(OFF)

T_A= Full

V₊= 0 V

V_S= 1 V, V_D

Open,

V_S= 3 V, V_D

Open,

T_A= 25°C

V₊= 3.6 V

0.05

Switch ON,

see 图 14

I_S(ON)

ON leakage

current

μA

T_A= Full

V₊= 3.6 V

–0.3

0.3

V_D= 1 V, V_S

Open,

V_D= 3 V, V_S

Open,

T_A= 25°C

V₊= 3.6 V

0.05

Switch ON,

see 图 14

I_D(ON)

ON leakage

current

T_A= Full

V₊= 3.6 V

Digital Control Inputs (IN1, IN2, EN)⁽²⁾

V_IH

V_IL

Input logic high

Input logic low

T_A= Full

V₊

0.8

T_A= 25°C

V₊= 3.6 V

0.05

Input leakage

current

I_IH, I_IL

V_I= V₊or 0

μA

T_A= Full

V₊= 3.6 V

–1

V_GEN= 0, R_GEN= 0,

C_L= 0.1 nF,

T_A= 25°C

V₊= 3.3 V

Q_C

Charge injection

See 图 21

See 图 15

4.5

V_S= V₊or GND,

Switch OFF,

T_A= 25°C

V₊= 3.3 V

C_S(OFF)

C_D(OFF)

C_S(ON)

OFF capacitance

V_D= V₊or GND,

Switch OFF,

T_A= 25°C

V₊= 3.3 V

OFF capacitance

V_S= V₊or GND,

Switch ON,

T_A= 25°C

V₊= 3.3 V

ON capacitance

(1) The algebraic convention, whereby the most negative value is aminimum and the most positive value is a maximum

(2) All unused digital inputs of the device must be held atV₊or GND to ensure proper device operation. Refer to the TI applicationreport,

Implications of Slow or Floating CMOS Inputs, literaturenumber SCBA004.

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

Electrical Characteristics for 3.3-VSupply (continued)

V₊= 2.7 V to 3.6 V, T_A= –40°C to125°C (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_D= V₊or GND,

Switch ON,

T_A= 25°C

V₊= 3.3 V

C_D(ON)

C_I

See 图 15

ON capacitance

Digital input

capacitance

T_A= 25°C

V₊= 3.3 V

V_I= V₊or GND,

See 图 15

See 图 17

See 图 18

See 图 19

See 图 20

165

–69

–49

–69

–80

0.25

MHz

R_L= 50 Ω,

Switch ON,

T_A= 25°C

V₊= 3.3 V

Bandwidth

R_L= 50 Ω,

f = 1 MHz,

T_A= 25°C

V₊= 3.3 V

O_ISO

OFF isolation

Crosstalk

R_L= 50 Ω,

f = 10 MHz,

T_A= 25°C

V₊= 3.3 V

O_ISO

R_L= 50 Ω,

f = 1 MHz,

T_A= 25°C

V₊= 3.3 V

X_TALK

X_TALK(ADJ)

R_L= 50 Ω,

f = 1 MHz,

T_A= 25°C

V₊= 3.3 V

Crosstalk adjacent

Total harmonic

distortion

R_L= 600 Ω,

C_L= 50 pF,

f = 20 Hz to 20 kHz, T_A= 25°C

THD

see 图 22

V₊= 3.3 V

Supply

T_A= 25°C

V₊= 3.6 V

2.5

Positive supply

current

I₊

V_I= V₊or GND,

Switch ON or OFF

μA

T_A= Full

V₊= 3.6 V

6.6 Electrical Characteristics for 2.5-VSupply

V₊= 2.3 V to 2.7 V, T_A= –40°C to125°C (unless otherwise noted)⁽¹⁾

PARAMETER

Analog Switch

Analog signal

TEST CONDITIONS

MIN

TYP MAX UNIT

V_D, V_S

V₊

range

T_A= 25°C

V₊= 2.3 V

ON-state

resistance

0 ≤ V_S≤ V₊,

I_D= –24 mA,

Switch ON,

see 图 12

r_on

Ω

T_A= Full

V₊= 2.3 V

T_A= 25°C

V₊= 2.3 V

ON-state

V_S= 1.6 V,

I_D= –24 mA,

Switch ON,

see 图 12

Δr_on

Ω

resistance match

between channels

T_A= Full

V₊= 2.3 V

T_A= 25°C

V₊= 2.3 V

ON-state

resistance flatness I_D= –24 mA,

0 ≤ V_S≤ V₊,

Switch ON,

see 图 12

r_on(flat)

T_A= Full

0.3

V₊= 2.3 V

T_A= 25°C

V₊= 2.7 V

0.05

0.5

V_S= 0.5 V, V_D= 2.2 V,

V_S= 2.2 V, V_D= 0.5 V,

I_S(OFF)

T_A= Full

V₊= 2.7 V

–0.3

-15

Switch OFF,

see 图 13

OFF leakage

current

μA

T_A= 25°C

V₊= 0 V

V_S= 0 to 2.7 V,

V_D= 2.7 V to 0,

I_SPWR(OFF)

T_A= Full

V₊= 0 V

(1) The algebraic convention, whereby the most negative value is aminimum and the most positive value is a maximum

TS3A5017-Q1

www.ti.com.cn

ZHCSIY9 –OCTOBER 2018

Electrical Characteristics for 2.5-VSupply (continued)

V₊= 2.3 V to 2.7 V, T_A= –40°C to125°C (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

T_A= 25°C

V₊= 2.7 V

0.05

V_S= 0.5 V, V_D= 2.2 V,

V_S= 2.2 V, V_D= 0.5V,

I_D(OFF)

T_A= Full

V₊= 2.7 V

–0.3

0.3

μA

Switch OFF,

see 图 13

OFF leakage

current

T_A= 25°C

V₊= 0 V

0.5

V_D= 0 to 2.7 V,

V_S= 2.7 V to 0,

I_DPWR(OFF)

T_A= Full

V₊= 0 V

-20

–0.3

T_A= 25°C

V₊= 2.7 V

0.05

V_S= 0.5 V, V_D= Open,

V_S= 2.2 V, V_D= Open,

Switch ON,

see 图 14

I_S(ON)

ON leakage

current

μA

T_A= Full

V₊= 2.7 V

0.3

T_A= 25°C

V₊= 2.7 V

0.05

V_D= 0.5 V, V_S= Open,

V_D= 2.2 V, V_S= Open,

Switch ON,

see 图 14

I_D(ON)

ON leakage

current

μA

T_A= Full

V₊= 2.7 V

0.3

Logic Inputs (IN1, IN2, EN)⁽²⁾

V_IH

V_IL

Input logic high

Input logic low

T_A= Full

1.7

V₊

0.7

T_A= 25°C

V₊= 2.7 V

0.05

Input leakage

current

I_IH, I_IL

V_I= V₊or 0

μA

T_A= Full

V₊= 2.7 V

–1

V_GEN= 0, R_GEN= 0,

C_L= 0.1 nF,

T_A= Full

V₊= 2.5 V

Q_C

Charge injection

See 图 21

See 图 15

See 图 17

See 图 18

See 图 19

See 图 20

4.5

18.5

MHz

V_S= V₊or GND,

Switch OFF,

T_A= Full

V₊= 2.5 V

C_S(OFF)

C_D(OFF)

C_S(ON)

C_D(ON)

C_I

OFF capacitance

V_D= V₊or GND,

Switch OFF,

T_A= Full

V₊= 2.5 V

OFF capacitance

V_S= V₊or GND,

Switch ON,

T_A= Full

V₊= 2.5 V

ON capacitance

V_D= V₊or GND,

Switch ON,

T_A= Full

V₊= 2.5 V

ON capacitance

Digital input

capacitance

T_A= Full

V₊= 2.5 V

V_I= V₊or GND,

R_L= 50 Ω,

Switch ON,

T_A= Full

V₊= 2.5 V

Bandwidth

165

–69

–49

–69

–85

0.3

R_L= 50 Ω,

f = 1 MHz,

T_A= Full

V₊= 2.5 V

O_ISO

OFF isolation

Crosstalk

R_L= 50 Ω,

f = 10 MHz,

T_A= Full

V₊= 2.5 V

O_ISO

R_L= 50 Ω,

f = 1 MHz,

T_A= Full

V₊= 2.5 V

X_TALK

X_TALK(ADJ)

R_L= 50 Ω,

f = 1 MHz,

T_A= Full

V₊= 2.5 V

Crosstalk adjacent

Total harmonic

distortion

R_L= 600 Ω,

C_L= 50 pF,

f = 20 Hz to 20 kHz,

see 图 22

T_A= Full

V₊= 2.5 V

THD

Supply

(2) All unused digital inputs of the device must be held atV₊or GND to ensure proper device operation. Refer to the TI applicationreport,

Implications of Slow or Floating CMOS Inputs, literaturenumber SCBA004.

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

Electrical Characteristics for 2.5-VSupply (continued)

V₊= 2.3 V to 2.7 V, T_A= –40°C to125°C (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

T_A= Full

V₊= 2.7 V

2.5

Positive supply

current

I₊

V_I= V₊or GND,

Switch ON or OFF

μA

T_A= Full

V₊= 2.7 V

6.7 Switching Characteristics for 3.3-VSupply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_A= 25°C

V₊= 3.3 V

9.5

10.5

3.5

V_D= 2 V,

R_L= 300 Ω,

C_L= 35 pF,

see 图 16

t_ON

Turnon time⁽¹⁾

T_A= Full

V₊= 3 V to 3.6 V

T_A= 25°C

V₊= 3.3 V

1.5

V_D= 2 V,

R_L= 300 Ω,

C_L= 35 pF,

see 图 16

t_OFF

Turnoff time⁽¹⁾

T_A= Full

V₊= 3 V to 3.6 V

4.5

(1) Specified by design, not tested in production

6.8 Switching Characteristics for 2.5-VSupply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

T_A= 25°C

V₊= 2.5 V

V_COM= 2 V,

R_L= 300 Ω,

C_L= 35 pF,

see 图 16

t_ON

Turnon time⁽¹⁾

T_A= Full

V₊= 2.3 V to 2.7 V

T_A= 25°C

V₊= 2.5 V

4.5

V_COM=2 V,

R_L= 300 Ω,

C_L= 35 pF,

see 图 16

t_OFF

Turnoff time⁽¹⁾

T_A= Full

V₊= 2.3 V to 2.7 V

(1) Specified by design, not tested in production.

TS3A5017-Q1

www.ti.com.cn

ZHCSIY9 –OCTOBER 2018

6.9 Typical Characteristics

= 25°C

V = 2.5 V

85°C

25°C

V = 3.3 V

–40°C

0.0

0.5

1.0

1.5

2.0

(V)

COM

2.5

3.0

3.5

(V)

COM

图 1. r_onvs V_COM

图 2. r_onvs V_COM(V₊= 3.3 V)

NC(ON)

COM(ON)

NO(ON)

85°C

25°C

COM(OFF)

NC(OFF)

–40°C

NO(OFF)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

–40

COM

(V)

(°C)

图 3. r_onvs V_COM(V₊= 2.5 V)

图 4. Leakage Current vs Temperature (V₊= 3.6 V)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

= 3.3 V

= 2.5 V

OFF

2.0

2.5

3.0

(V)

3.5

4.0

0.0

0.5

1.0

1.5

2.0

(V)

2.5

3.0

3.5

COM

图 6. t_ONand t_OFFvs Supply Voltage

图 5. Charge Injection (Q_C) vs V_COM

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

Typical Characteristics (接下页)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

(V)

图 7. Logic-Level Threshold vs V₊

图 8. Bandwidth (Gain vs Frequency) (V₊= 3.3 V)

0.35

0.30

0.25

0.20

0.15

0.10

100

1000

10 K

100 K

Frequency (Hz)

图 10. Total Harmonic Distortion vs Frequency

图 9. OFF Isolation and Crosstalk vs Frequency

(V₊= 3.3 V)

(°C)

图 11. Power-Supply Current vs Temperature

(V₊= 3.6 V)

TS3A5017-Q1

www.ti.com.cn

ZHCSIY9 –OCTOBER 2018

7 Parameter Measurement Information

Channel ON

– V

or V

S2-S4

= V or V

IH IL

图 12. ON-State Resistance (r_on)

OFF-State Leakage Current

Channel OFF

V = V or V

or V

= 0 to V

S2-S4 +

and

= V to 0

图 13. OFF-State Leakage Current (I_D(OFF), I_S(OFF)

)

ON-State Leakage Current

Channel ON

V = V or V

图 14. ON-State Leakage Current (I_D(ON), I_S(ON)

)

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

Parameter Measurement Information (接下页)

= V to GND

BIAS

V = V or V

Capacitance is measured at S1,

S2-S4, D, and IN inputs during

ON and OFF conditions.

图 15. Capacitance (C_I, C_D(OFF), C_D(ON), C_S(OFF), C_S(ON)

)

35 pF

300 Ω

(C)

(B)

(A)

OFF

A. All

input

pulses

are

supplied

generators

having

the

following

characteristics:

PRR ≤ 10 MHz, Z_O= 50 Ω, t_r< 5 ns, t_f< 5 ns.

B. C_Lincludes probe and jig capacitance.

C. See Electrical Characteristics for V_D.

图 16. Turnon (t_ON) and Turnoff Time (t_OFF

)

Channel ON: S to D

V = V or GND

50 Ω

Network Analyzer Setup

Source Power = 0 dBm

(632-mV P-P at 50-Ω load)

50 Ω

DC Bias = 350 mV

图 17. Bandwidth (BW)

TS3A5017-Q1

www.ti.com.cn

ZHCSIY9 –OCTOBER 2018

Parameter Measurement Information (接下页)

Channel OFF: S to D

V = V or GND

50 Ω

Network Analyzer Setup

Source Power = 0 dBm

(632-mV P-P at 50-Ω load)

50 Ω

DC Bias = 350 mV

图 18. OFF Isolation (O_ISO

)

Channel ON: S to D

Channel OFF: S -S to D

50 Ω

V = V or GND

S2-S4

Network Analyzer Setup

Source Power = 0 dBm

(632-mV P-P at 50-Ω load)

50 Ω

DC Bias = 350 mV

图 19. Crosstalk (X_TALK

)

Channel ON: S to D

50 Ω

Network Analyzer Setup

Source Power = 0 dBm

(632-mV P-P at 50-Ω load)

50 Ω

DC Bias = 350 mV

图 20. Adjacent Crosstalk (X_TALK

)

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

Parameter Measurement Information (接下页)

ΔV

= 0 to V

= 0

GEN

= 0.1 nF

= C X ΔV

V = V or V

A. All

input

pulses

are

supplied

generators

having

the

following

characteristics:

PRR ≤ 10 MHz, Z_O= 50 Ω, t_r< 5 ns, t_f< 5 ns.

B. C_Lincludes probe and jig capacitance.

图 21. Charge Injection (Q_C)

10 µF

(A)

10 µF

600 Ω

A. C_Lincludes probe and jig capacitance.

图 22. Total Harmonic Distortion (THD)

TS3A5017-Q1

www.ti.com.cn

ZHCSIY9 –OCTOBER 2018

8 Detailed Description

8.1 Overview

The TS3A5017-Q1 is a dual Single-Pole-4-Throw (SP4T) solid-state analog switch. The TS3A5017-Q1, like all

analog switches, is bidirectional. Each D pin connects to its four respective S pins, with the switch connection

dependent on the status of EN, IN2, and IN1. See 表 1 for the switch configuration truth table.

8.2 Functional Block Diagram

IN1

IN2

图 23. Functional Block Diagram (Each Switch)

8.3 Feature Description

Isolation in powered-down mode allows signals to be present at the inputs while the switch is powered off without

causing damage to the device. The low ON-state resistance and low charge injection give the TS3A5017-Q1

better performance at higher speeds.

8.4 Device Functional Modes

表 1. Function Table

D TO S,

IN2

IN1

S TO D

D = S₁

D = S₂

D = S₃

D = S₄

OFF

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TS3A5017-Q1 can be used in a variety of customer systems. The TS3A5017-Q1 can be used anywhere

multiple analog or digital signals must be selected to pass across a single line.

9.2 Typical Application

3.3 V

V+

IN1

IN2

To/From

System

C or System

Logic

GND

图 24. System Schematic for TS3A5017-Q1

9.2.1 Design Requirements

In this particular application, V+ was 3.3 V, although V+ is allowed to be any voltage specified in Recommended

Operating Conditions. A decoupling capacitor is recommended on the V+ pin. See Power Supply

Recommendations for more details.

9.2.2 Detailed Design Procedure

In this application, EN, IN1, and IN2 are, by default, pulled low to GND. Choose these resistor sizes based on

the current driving strength of the GPIO, the desired power consumption, and the switching frequency (if

applicable). If the GPIO is open-drain, use pullup resistors instead.

TS3A5017-Q1

www.ti.com.cn

ZHCSIY9 –OCTOBER 2018

Typical Application (接下页)

9.2.3 Application Curve

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

OFF

–40

(°C)

图 25. t_ONand t_OFFvs Temperature (V₊= 3.3 V)

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

Recommended Operation Conditions.

Each V_CCterminal should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled V_CC, then a 0.01-μF or

0.022-μF capacitor is recommended for each V_CCbecause the V_CCpins will be tied together internally. For

devices with dual-supply pins operating at different voltages, for example V_CCand V_DD, a 0.1-µF bypass

capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject

different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor

should be installed as close to the power terminal as possible for best results.

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own

discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the

change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This

upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the

trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and the traces will turn

corners. 图 26 shows progressively better techniques of rounding corners. Only the last example maintains

constant trace width and minimizes reflections.

Unused switch I/Os, such as NO, NC, and COM, can be left floating or tied to GND. However, the IN1, IN2, and

EN pins must be driven high or low. Due to partial transistor turnon when control inputs are at threshold levels,

floating control inputs can cause increased I_CCor unknown switch selection states. See Implications of Slow or

Floating CMOS Inputs, SCBA004 for more details.

11.2 Layout Example

WORST

BETTER

BEST

1W min.

图 26. Trace Example

TS3A5017-Q1

www.ti.com.cn

ZHCSIY9 –OCTOBER 2018

12 器件和文档支持

12.1 器件支持

12.1.1 器件命名规则

表 2. 参数说明

符号

说明

V_COM

V_NC

COM 处的电压

NC 处的电压

NO 处的电压

V_NO

r_on

通道打开时 COM 和 NC 或 NO 端口之间的电阻

特定器件中通道间 r_on的差值

Δr_on

r_on(flat)

I_NC(OFF)

I_NC(ON)

I_NO(OFF)

I_NO(ON)

I_COM(OFF)

I_COM(ON)

V_IH

额定条件范围下，同一通道内 r_on最大值与最小值之间的差值

相应通道（NC 到 COM）处于关断状态时，在 NC 端口测得的泄漏电流

相应通道（NC 到 COM）处于导通状态且输出 (COM) 处于开路状态时，在 NC 端口测得的泄漏电流

相应通道（NO 到 COM）处于关断状态时，在 NO 端口测得的泄漏电流

相应通道（NO 到 COM）处于导通状态且输出 (COM) 处于开路状态时，在 NO 端口测得的泄漏电流

相应通道（COM 到 NC 或 NO）处于关断状态时，在 COM 端口测得的泄漏电流

相应通道（COM 到 NC 或 NO）处于导通状态且输出 (NC 或 NO) 处于开路状态时，在 COM 端口测得的泄漏电流

控制输入 (IN, EN) 逻辑高电平的最小输入电压

V_IL

控制输入 (IN, EN) 逻辑低电平的最大输入电压

V_I

控制输入 (IN, EN) 处的电压

I_IH、I_IL

控制输入 (IN, EN) 处测量的泄漏电流

开关开通时间。此参数是在特定条件范围下，开关开通时，通过数字控制 (IN) 信号和模拟输出 NC 或 NO）信号之间的传播

延迟测量得出。

t_ON

开关关断时间。此参数是在特定条件范围下，开关开通时，通过数字控制 (OFF) 信号和模拟输出（NC 或 NO）信号之间的

传播延迟测量得出。

t_OFF

电荷注入是测量从控制 (IN) 输入到模拟（NC 或 NO）输入产生的不需要的信号耦合的方法。电荷注入以库仑为单位，可通

Q_C

过测量开关控制输入产生的总感应电荷得出该值。电荷注入，Q_C= C_L× ΔV_COM，C_L是负载电容，ΔV_COM是模拟输出电压的

变化。

C_NC(OFF)

C_NC(ON)

C_NO(OFF)

C_NO(ON)

C_COM(OFF)

C_COM(ON)

C_I

相应通道（NC 到 COM）关闭时 NC 端口的电容

相应通道（NC 到 COM）开启时 NC 端口的电容

相应通道（NO 到 COM）关闭时 NC 端口的电容

相应通道（NO 到 COM）开启时 NC 端口的电容

相应通道（COM 到 NC）关闭时 COM 端口的电容

相应通道（COM 到 NC）开启时 COM 端口的电容

控制输入 (IN, EN) 电容

开关关断隔离用于衡量关断状态开关阻抗的大小。关断隔离以 dB 为单位，当相应通道（NC 到 COM）处于关断状态时，在

额定频率下测量得出。

O_ISO

串扰是测量从开启状态的通道到关断状态的通道（NC1 到 NO1）产生的不必要信号耦合的方法。相邻串扰是测量从一条开启

状态的通道到相邻开启状态的通道（NC1 到 NC2）产生的不必要信号耦合的方法。相邻串扰在额定频率下测量得出且以 dB

为单位。

X_TALK

THD

I₊

开关带宽。这是导通通道增益低于直流增益 -3dB 时的频率。

总谐波失真用于描述由模拟开关导致的信号失真。其定义为二次、三次和更高次谐波与基波绝对幅度之比的均方根 (RMS)

值。

静态电源电流，以及 V₊或 GND 的控制 (IN) 引脚

12.2 文档支持

12.2.1 相关文档

•

《慢速或浮点 CMOS 输入的影响》，SCBA004

TS3A5017-Q1

ZHCSIY9 –OCTOBER 2018

www.ti.com.cn

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

E2E is a trademark of Texas Instruments.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TS3A5017QRGYRQ1

ACTIVE

VQFN

RGY

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

5017Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

TS3A5017QRGYRQ1 [TI]

相关型号：

TS3A5017RGYR

TS3A5017RGYRG4

TS3A5017RSV

TS3A5017RSVR

TS3A5017RSVRG4

TS3A5017_10

TS3A5017_14

TS3A5018

TS3A5018D

TS3A5018DBQR

TS3A5018DBQRE4

TS3A5018DBQRG4