TS3A227EYFFR [TI]
具有 I2C 的 60mΩ、4.5V 自主音频附件检测和配置开关 | YFF | 16 | -40 to 85;
| 型号： | TS3A227EYFFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 的 60mΩ、4.5V 自主音频附件检测和配置开关 | YFF | 16 | -40 to 85 开关 |
| 文件： | 总61页 (文件大小：1637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
TS3A227E 车用音频附件检测和配置开关
1 特性
3 说明
1
•
•
•
电源电压范围为 2.5V 至 4.5V
TS3A227E 是一款音频附件自主检测和配置开关，用
于检测 3 孔或 4 孔音频附件并配置内部开关，以便进
行信号传输。
具有防反跳可调定时功能的附件插入/移除检测
附件配置检测：
–
–
–
立体声 3 孔耳机
TS3A227E 的内部接地 FET 具有 60mΩ 超低 RON，能
够最大限度地减少串扰影响。 接地 FET 也可用于传送
FM 信号，因此，可以使用附件的接地线作为移动音频
应用中的 FM 天线。
麦克风 (MIC) 连接 Sleeve 的 4 孔标准耳机
MIC 连接 Ring2 的 4 孔国际标准 (OMTP) 耳机
•
•
可对多达 4 个按键进行按压检测
超低接地场效应晶体管 (FET) 导通电阻 RON，仅为
60mΩ
利用内部隔离开关，TS3A227E 可以消除插入或移除
音频附件时可能产生的卡嗒/爆裂噪音。 此外，器件中
的耗尽型 FET 可防止器件未通电时出现悬空接地，并
防止将附件插入未通电系统时产生嗡嗡声。
•
•
断电后可消除噪声
隔离音频插孔的麦克风偏置电压 (MICBIAS)，消除
卡嗒/爆裂噪音
•
•
•
•
集成编解码器感测线路
手动 I2C 控制
当没有插入耳机时，低功耗睡眠模式可将部分内部电路
关断，以实现极低的静态电流和功耗。
调频 (FM) 传输能力
两种小型封装选项
TS3A227E 具有集成按键按压检测功能，最多可检测 4
个按键的按压和释放操作。
–
16 引脚芯片尺寸球状引脚栅格阵列 (DSBGA)
封装
手动 I2C 控制可控制防反跳设置和开关状态，从而使
TS3A227E 适应应用需求。
–
16 引脚四方扁平无引线 (QFN) 封装
器件信息(1)
2 应用范围
器件型号
TS3A227E
封装
QFN (16)
DSBGA (16)
封装尺寸（标称值）
3.50mm x 3.50mm
1.79mm × 1.79mm
•
•
•
•
移动电话
平板电脑
笔记本电脑和超级本
使用 3.5mm 音频接口的任意应用
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
4 简化电路原理图
BATTERY
TS3A227E
Audio Codec
R
G
L
Application
Processor
L
L
R G M
R M G
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SCDS358
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 18
9.3 Feature Description................................................. 19
9.4 Device Functional Modes........................................ 20
9.5 Register Maps ........................................................ 24
9.6 Register Field Descriptions ..................................... 24
10 Application and Implementation........................ 33
10.1 Application Information.......................................... 33
10.2 Typical Application ............................................... 33
11 Power Supply Recommendations ..................... 47
12 Layout................................................................... 48
12.1 Layout Guidelines ................................................. 48
12.2 Layout Example (QFN) ......................................... 48
12.3 Layout Example (DSBGA) .................................... 49
13 器件和文档支持 ..................................................... 50
13.1 商标....................................................................... 50
13.2 静电放电警告......................................................... 50
13.3 术语表 ................................................................... 50
14 机械封装和可订购信息 .......................................... 50
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 I2C Interface Timing Characteristics ......................... 8
7.7 Timing Diagrams....................................................... 9
7.8 Typical Characteristics............................................ 12
Parameter Measurement Information ................ 12
Detailed Description ............................................ 17
9.1 Overview ................................................................. 17
8
9
5 修订历史记录
Changes from Revision A (December 2014) to Revision B
Page
•
•
Added DSBGA package to the Thermal Information table. ................................................................................................... 5
Updated SWITCH RESISTANCE for the DSBGA package. ................................................................................................. 6
Changes from Original (July 2014) to Revision A
Page
•
最初发布的完整版文档。 ....................................................................................................................................................... 1
2
Copyright © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
6 Pin Configuration and Functions
DSBGA – YFF
Top View
QFN – RVA
Top View
4
3
2
1
SLEEVE_
SENSE
SLEEVE
GNDA
RING2
D
C
B
A
16 15 14 13
RING2_
SENSE
SCL
SDA
VDD
TIP
INT
GND
GND
GND
GND
SDA
VDD
1
2
3
4
12 RING2
11 GNDA
10 SLEEVE
DET_
TRIGGER
MICP
THERMALPAD
9
SCL
GND_
SENSE
MIC_
PRESENT
5
6
7
8
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
RVA
YFF
B1
A falling edge from high to low on this pin triggers accessory detection. This pin can be connected the
headset jack to allow automatic pull-down to ground after headset insertion to initialize detection.
DET_TRIGGER
GND
15
1, 2
11
5
I/O
A2, B2
D2
GND Primary ground connection for the TS3A227E. Must be connected to system ground.
Ground connection for the internal ground FETs of the TS3A227E. If FM is being supported connect this pin
to the FM matching network. If FM is not being support connect this pin to system ground.
GNDA
I/O
GND_SENSE
INT
A4
I/O
Ground sense line for the codec.
Open drain interrupt output from the TS3A227E to notify the host that an event has occurred. If I2C is not
used this pin must be grounded.
13
C2
GND
MIC_PRESENT
MICP
16
6
A1
B4
I/O
I/O
Open drain output to indicate to the host that a headset with a microphone is inserted..
Microphone signal connection to the codec. Microphone bias is applied to this pin.
Headset current return path if RING2 is ground for the headset. Connect to 3.5 mm jack RING2 connection
with low DC resistance trace.
RING2
12
7
D1
C4
O
Connected to the RING2 pin of the 3.5 mm jack. If RING2 pin on plug in is MIC signal, this is connected to
MICP. If not, this is connected to GND_SENSE and becomes the ground sensing feedback for the accessory
RING2_SENSE
GND
Clock from I2C bus. This can be connected to VDD if I2C is not used.
SCL
SDA
9
3
C3
B3
I
Bidirectional data from/to I2C bus. This can be connected to VDD if I2C is not used.
I/O
Headset current return path if SLEEVE is GND for headset. Connect to 3.5 mm jack SLEEVE connection with
low DC resistance trace.
SLEEVE
10
8
D3
D4
O
Connected to the SLEEVE pin of the 3.5 mm jack. If SLEEVE pin on plug in is MIC signal, this is connected to
MICP. If not, this is connected to GND_SENSE and becomes the ground sensing feedback for the accessory
SLEEVE_SENSE
THERMAL PAD
GND
The THERMAL PAD of the RVA – QFN package must be connected to any internal PCB ground plane using
multiple vias for best thermal performance.
GND
I/O
TIP
14
4
C1
A3
Connect to the TIP pin of the 3.5 mm jack.
VDD
PWR Power input to the TS3A227E. External de-coupling capacitors are required on this pin.
Copyright © 2014–2015, Texas Instruments Incorporated
3
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)(1)
MIN
MAX
5
UNIT
Input Voltage
VDD
–0.3
–0.3
–3.3
–2.2
–0.3
V
V
V
V
V
SDA, SCL, INT, MIC_PRESENT
VDD + 0.5
VDD + 0.5
VDD + 0.5
TIP
DET_TRIGGER
GND_SENSE, RING2, SLEEVE, RING2_SENSE, SLEEVE_SENSE,
MICP, GNDA
3.6(2) and VDD
0.5
+
ON-state switch
current
Combined continuous current through R2GNDFET and SLV GNDFET
Continuous current through R2DFET and SLV DFET
Continuous current through S1
500
50
mA
20
Continuous current through S2
20
Continuous current through S3PR
50
Continuous current through S3PS
50
Continuous current through S3GR
100
100
85
Continuous current through S3GS
Operating ambient temperature range
Tstg Storage temperature range
–40
–65
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This rating is exclusive and the voltage on the pins must not exceed either 3.6 and VDD. E.g. if VDD = 4.5 V the voltage on the pin must
not exceed 3.6 V and if VDD is = 2.5 V the voltage on the pin must not exceed 3.0 V.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), ESD stress voltagenew note #1 to the ESD
Ratings table and combined MIN MAX column to VALUE
Charged device model (CDM), ESD stress voltage(1) (3)
V
V
V
(1) (2)
V(ESD)
Electrostatic discharge
Contact discharge model (IEC) ESD stress voltage on TIP,
±8000
DET_TRIGGER, RING2_SENSE, SLEEVE_SENSE, RING2, SLEEVE(1)
(1) Electrostatic Discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
0
MAX
4.5
UNIT
VDD Power supply voltage range
SDA, SCL
V
V
V
VDD
VDD
VI
Digital input voltage range
DET_TRIGGER
–2.2
RING2_SENSE, SLEEVE_SENSE, RING2,
SLEEVE, GND_SENSE, MICP
0
3.3(1) and VDD
VIO
Input/output voltage range
V
TIP
–3
VDD
VDD
VO
Output voltage range
Input logic high
INT, MIC_PRESENT
SDA, SCL
0
V
V
1.2
VDD
VIH
DET_TRIGGER
SDA, SCL
0.65 × VDD
VDD
V
0
0
0.4
V
VIL
TA
Input logic low
DET_TRIGGER
0.4 × VDD
85
V
Operating ambient temperature
–40
°C
(1) This rating is exclusive and the voltage on the pins must not exceed either 3.3 and VDD. E.g. if VDD = 4.5 V the voltage on the pin must
not exceed 3.3 V and if VDD is = 2.5 V the voltage on the pin must not exceed 2.5 V.
7.4 Thermal Information
TS3A227E
RTE
TS3A227E
YFF
THERMAL METRIC(1)
UNIT
16 PINS
45.9
16 PINS
77.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
52.6
0.6
21.2
12.5
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
2.3
ψJB
21.2
12.5
RθJC(bot)
4.3
-
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014–2015, Texas Instruments Incorporated
5
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
7.5 Electrical Characteristics
Unless otherwise noted the specification applies over the VDD and ambient operating temperature range.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VDD Supply voltage
2.5
3.3
0.5
4.5
10
V
No accessory inserted. I2C bus inactive(1)
VDD = 2.5 V to 4.5 V
µA
Manual switch control = ’1’ , I2C bus inactive,(1)
VDD = 2.5 V to 4.5 V, Depletion FETs on
7
15
40
µA
µA
Manual switch control = ’1’ , I2C bus inactive,
VDD = 2.5 V to 4.5 V Depletion FETs off
20
3-pole accessory inserted.
I2C bus inactive(1), FM Support = ’0’
VDD = 2.5 V to 4.5 V
11
20
µA
IDD
Quiescent current
3-pole accessory inserted.
I2C bus inactive,(1) FM Support = ’1’
VDD = 2.5 V to 4.5 V
25
25
30
45
40
45
µA
µA
µA
4-pole Accessory inserted.
I2C bus inactive,(1) VDD = 2.5 V to 4.5 V
4-pole Accessory inserted.
KP detection enabled
I2C bus inactive,(1) VDD = 2.5 V to 4.5 V
No accessory inserted.
I2C bus inactive at 1.8 V,(3)
VDD = 2.5 V to 4.5 V
Quiescent current addition from using a
1.8 V I2C bus.(2)
IDD_1.8
1
8
µA
SWITCH RESISTANCE
RING2 GNDFET on resistance (DSBGA
40
60
40
60
85
95
85
95
Package)
RR2GNDFT
RING2 GNDFET on resistance (QFN
Package)
VDD = 3.3 V, VGND = 0V,
IGNDA = 75 mA
mΩ
SLEEVE GNDFET on resistance (DSBGA
Package)
RSLVGNDFT
SLEEVE GNDFET on resistance (QFN
Package)
RS3PS
RS3PR
RS3GS
RS3GR
S3PS on resistance
S3PR on resistance
S3GS on resistance
S3GR on resistance
VDD = 3.3 V,
VSLEEVE_SENSE/RING2_SENSE = 0 V to 2.7 V,
IMICP = ±10 mA
3
3
6.5
6.5
1
Ω
Ω
VDD = 3.3 V,
VSLEEVE_SENSE/RING2_SENSE = 0 V to 2.7 V,
IGND_SENSE = ±75 mA
0.5
0.5
1
RS1
Switch 1 on resistance
15
15
75
75
30
30
Ω
Ω
RS2
Switch 2 on resistance
VDD = 3.3 V, IGND = 10 mA
RR2DFET
RSLVDFET
RING2 depletion FET on resistance
SLEEVE depletion FET on resistance
150
150
SWITCH LEAKAGE CURRENT
RING2 pin off leakage
1
1
1
1
1
1
1
SLEEVE pin off leakage
RING2_SENSE pin off leakage
IOFF
VIN = 0 V to 3.3 V, VDD = 3.3 V
µA
µA
SLEEVE_SENSE pin off leakage
MICP pin off leakage
GND_SENSE pin off leakage
ION
S2PS, S3PR, S3GS, S3GR on leakage
VSLEEVE/RING2 = 0V, VDD = 3.3 V
(1) The I2C bus is inactive if both the SDA and SCL lines are tied to VDD
.
(2) If the I2C bus is operating at 1.8 V the IDD_1.8 current number will be in addition to the other current consumption numbers specified.
(3) The I2C bus is inactive if both the SDA and SCL lines are tied to 1.8 V.
6
Copyright © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
Electrical Characteristics (continued)
Unless otherwise noted the specification applies over the VDD and ambient operating temperature range.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWITCH TIMING
VDD = 2.5 V, 3.3 V, 4.5 V,
RL = 300 Ω, CL = 50 pF
VSLEEVE_SENSE/RING2_SENSE = 2.5 V (VDD = 2.5 V),
3.3 V (VDD = 3.3 V, VDD = 4.5 V)
Turn off time for S3PS, S3PR, S3GS,
S3GR
5
µs
VDD = 2.5 V, 3.3 V, 4.5 V
RPU = 1500 Ω, CL = 50 pF
VPU = 2.5 V (VDD = 2.5 V),
3.3 V (VDD = 3.3 V, VDD = 4.5 V)
Turn off time for S1, S2, RING2 GNDFET,
SLEEVE GNDFET
tOFF
5
500
1
µs
µs
µs
µs
µs
VDD = 2.5 V, 3.3 V, 4.5 V
RPU = 1500 Ω, CL = 50 pF
VPU = 2.5 V (VDD = 2.5 V),
3.3 V (VDD = 3.3 V, VDD = 4.5 V)
Turn off time for RING2 DFET and
SLEEVE DFET
VDD = 2.5 V, 3.3 V, 4.5 V
RL = 300 Ω, CL = 50 pF
VSLEEVE_SENSE/RING2_SENSE = 2.5 V (VDD = 2.5 V),
3.3 V (VDD = 3.3 V, VDD = 4.5 V)
Turn on time for S3PS, S3PR, S3GS,
S3GR
VDD = 2.5 V, 3.3 V, 4.5 V
RPU = 1500 Ω, CL = 50 pF
VPU = 2.5 V (VDD = 2.5 V),
3.3 V (VDD = 3.3 V, VDD = 4.5 V)
Turn on time for S1, S2, RING2 GNDFET,
SLEEVE GNDFET
tON
35
1
VDD = 2.5 V, 3.3 V, 4.5 V
RPU = 1500 Ω, CL = 50 pF
VPU = 2.5 V (VDD = 2.5 V),
3.3 V (VDD = 3.3 V, VDD = 4.5 V)
Turn on time for RING2 DFET and
SLEEVE DFET
DIGITAL I/O
MIC_PRESENT low level output voltage
INT low level output voltage
0
0
0.4
0.4
VDD = 3.3 V, IOL = 10 mA
VOL
V
V
SDA low level output voltage
VDD = 3.3 V, IOLMAX = 3 mA
SDA, SCL
0
0.4
1.2
VDD
VIH
Input logic high
Input logic low
VDD
x
0.65
DET_TRIGGER
VDD
SDA, SCL
0
0
0.4
VIL
DET_TRIGGER
VDD x 0.4
Internal DET_TRIGGER pull-up
resistance
RPU/DT
VDD = 3.3 V, I/DET_TRIGGER = 1 µA
0.5
1
1.85
MΩ
Copyright © 2014–2015, Texas Instruments Incorporated
7
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
Electrical Characteristics (continued)
Unless otherwise noted the specification applies over the VDD and ambient operating temperature range.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
VDD = 3.3 V ± 200 mVPP, f = 217 Hz, RL at
RING2= 50 Ω
PSR217
–95
–85
–70
–120
–110
–90
VDD = 3.3 V ± 200 mVPP, f = 1 kHz, RL at
RING2= 50 Ω
PSR1k
PSR20k
ISOS3
Power supply rejection
dB
dB
VDD = 3.3 V ± 200 mVPP, f = 20 kHz, RL at
RING2= 50 Ω
SLEEVE_SENSE or RING2_SENSE to
MICP Isolation
VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL = 50 Ω
–90
SLEEVE_SENSE to RING2_SENSE
Separation
SEPS3
BW
VIN = 200 mVPP, f = 20 Hz – 20 kHz, RL = 50 Ω
–75
150
dB
Bandwidth through GNDFETs
VIN = 60 mVPP, IBIAS = 10 mA
120
–90
MHz
VIN = 1.5 V + 200 mVPP, f = 20 Hz – 20 kHz,
RS = 600 Ω, RL = 600 Ω
THD200
0.003 %
MICP to RING2_SENSE or
SLEEVE_SENSE total harmonic
distortion
VIN = 1.5 V + 500 mVPP, f = 20 Hz – 20 kHz,
RS = 600 Ω, RL = 600 Ω
THD500
SNR
0.002%
–110
VIN = 1 VRMS, f = 20 Hz – 20 kHz,
RS = 600 Ω, RL = 600 Ω
MICP to RING2_SENSE or
SLEEVE_SENSE signal to noise ratio
dB
ms
ms
ms
Time between DET_TRIGGER transition from
high to low and INT transition from high to low.
Default 90 ms insertion debounce.
tDET
Detection sequence duration
Power up time Power-up time
Removal wait period
175
20
210
25
Time from VDD > 2.5 V till I2C communication is
ready
Tpower-up
Time between DET_TRIGGER transition from
low to high and RING2/SLEEVE DFETs turning
on
tREMOVAL
50
65
7.6 I2C Interface Timing Characteristics
Unless otherwise noted the specification applies over the VDD and ambient operating temperature range
STANDARD MODE
I2C BUS
FAST MODE I2C
BUS
UNIT
PARAMETER
MIN
0
MAX
MIN
MAX
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
100
0
0.6
1.3
400
kHz
µs
µs
ns
ns
ns
ns
ns
4
4.7
50
50
tsds
tsdh
ticr
I2C serial data setup time
I2C serial data hold time
I2C input rise time
250
0
100
0
1000
300
21
21
300
300
ticf
I2C input fall time
20 + 0.1
Cb
tocf
I2C output fall time; 10 pF to 400 pF bus
300
300
µs
tbuf
I2C bus free time between Stop and Start
I2C Start or repeater Start condition setup time
I2C Start or repeater Start condition hold time
I2C Stop condition setup time
4.7
4.7
4
1.3
0.6
0.6
0.6
0.3
µs
µs
µs
µs
µs
tsts
tsth
tsps
4
tvd(data)
Valid data time; SCL low to SDA output valid
3.45
3.45
400
0.9
0.9
Valid data time of ACK condition; ACK signal from SCL low to SDA
(out) low
tvd(ack)
Cb
0.3
0
µs
pF
I2C bus capacitive loading
0
400
8
Copyright © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
7.7 Timing Diagrams
Insertion
de-bounce time
(90 ms default)
Removal
Accessory detection time
wait time
DET_TRIGGER
INT
High
MIC_PRESENT
(A)
(B)
(C)
(D)
(E)
(F)
A. (This is the point that DET_TRIGGER has stopped glitching and is fully low. The de-bounce time of 90 ms starts from
the point that the pin is constantly below the VIL level. Any time the DET_TRIGGER pin cross the VIH level the de-
bounce timer will restart.
B. Point B is the end of the insertion de-bounce time and the beginning of accessory detection.
C. Detection has completed at this point. The switches will be routed before the INT pin is pulled low.
D. INT is cleared after the host reads the interrupt register.
E. The headset is removed here. The switch states will change immediately and INT will be pulled low.
F. After a 50 ms removal de-bounce timer the TS3A227E will go back into sleep mode if manual switch control is not
enabled
图 1. 3-Pole Accessory
版权 © 2014–2015, Texas Instruments Incorporated
9
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
Timing Diagrams (接下页)
Insertion
de-bounce time
(90 ms default)
Removal
wait time
Accessory detection time
DET_TRIGGER
INT
High
MIC_PRESENT
(A)
(B)
(C)
(D)
(E)
(F)
A. This is the point that DET_TRIGGER has stopped glitching and is fully low. The de-bounce time of 90 ms starts from
the point that the pin is constantly below the VIL level. Any time the DET_TRIGGER pin cross the VIH level the de-
bounce timer will restart.
B. Point B is the end of the insertion de-bounce time and the beginning of accessory detection.
C. Detection has completed at this point. The switches will be routed before the INT and MIC_PRESENT pins are pulled
low.
D. INT is cleared after the host reads the interrupt register.
E. The headset is removed here. The switch states will change immediately and INT will be pulled low. The
MIC_PRESENT pin will be released.
F. After a 50 ms removal de-bounce timer the TS3A227E will go back into sleep mode if manual switch control is not
enabled
图 2. 4-Pole Accessory
10
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
Timing Diagrams (接下页)
7.7.1 Removal
A removal event will interrupt any on-going process in the TS3A227E. The following diagram depicts how the
device “jumps” during a removal.
If the removal event occurs during the insertion de-bounce period the TS3A227E will jump to the (A) point of the
diagram depicted by the green arrow and line.
Any time after point (B) has been reached and the accessory is removed the device jumps to point (E), which
includes key press detection. Under Manual Switch Control the switch states will not change.
Insertion
de-bounce time
(90 ms default)
Removal
wait time
Accessory detection time
DET_TRIGGER
INT
High
MIC_PRESENT
(A)
(B)
(C)
(D)
(E)
(F)
图 3. Removal Timing During Insertion
版权 © 2014–2015, Texas Instruments Incorporated
11
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
7.8 Typical Characteristics
0.0035
0.003
0.0025
0.002
0.0015
0.001
0.0005
0
200 mVpp
500 mVpp
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
D001
图 4. S3PX THD
8 Parameter Measurement Information
Channel ON
RON = VSLEEVE/RING2 / IGNDA
VSLEEVE/RING2
IGNDA
R2/SLV GNDFET
图 5. RING2/SLEEVE GNDFET On Resistance Measurement
Channel ON
RON = VSLEEVE/RING2 / IGND
VSLEEVE/RING2
IGND
R2/SLV DFET
图 6. RING2/SLEEVE DFET On Resistance Measurement
12
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
Parameter Measurement Information (接下页)
Channel ON
RON = VMICP/GND_SENSE / IGND
VMICP/GND_SENSE
IGND
S1/S2
图 7. S1/S2 On Resistance Measurement
Channel ON
RON = VMICP/GND_SENSE / IRING2_SENSE/SLEEVE_SENSE
VMICP/GND_SENSE
S3PS/R
S3GS/R
IRING2_SENSE/SLEEVE_SENSE
图 8. S3PS, S3PR, S3GS, S3GR On Resistance Measurement
Channel OFF
VIN
VOUT
Switch
图 9. Switch Off Leakage Current
版权 © 2014–2015, Texas Instruments Incorporated
13
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
Parameter Measurement Information (接下页)
Channel ON
VOUT
ILeakage
Switch
图 10. Switch On Leakage Current
Channel ON
3.3 V 200 mVPP
VDD
Reference
Source
Signal
Test
Switch
50 Ω
Source Generator
图 11. Power Supply Rejection Ratio (PSRR)
Channel Off
Network Analyzer
50 Ω
VMICP/GND_SENSE
VSLEEVE_SENSE/RING2_SENSE
Source
Signal
50 Ω
Switch
50 Ω
图 12. Switch Off Isolation
14
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
Parameter Measurement Information (接下页)
Network Analyzer
50 Ω
VMICP
VSLEEVE_SENSE
VRING2_SENSE
Source
Signal
VGND_SENSE
50 Ω
Switches
50 Ω
50 Ω
图 13. Channel Separation
Audio Analyzer
600 Ω
VMICP
VSLEEVE_SENSE/RING2_SENSE
Source
Signal
Switch
600 Ω
图 14. Total Harmonic Distortion (THD) and SNR
版权 © 2014–2015, Texas Instruments Incorporated
15
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
Parameter Measurement Information (接下页)
VMICP/GND_SENSE
VTEST
RL
CL
SDA
Digital
Core
SCL
SCL
VTEST
VTEST
90
tON
%
10
%
tOFF
图 15. S3 tOFF/tON
VPU
RPU
VTEST
CL
SDA
SCL
Digital
Core
SCL
VTEST
VTEST
70
%
tOFF
30
%
tON
图 16. S1, S2, GNDFET and DFET tON/tOFF
16
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
9 Detailed Description
9.1 Overview
The TS3A227E is an autonomous audio accessory switch with adjustable de-bounce settings, ultra-low RON
ground FETs, depletion FETs and manual I2C control.
The detection sequence is initiated via the external DET_TRIGGER pin or via I2C command. The device
incorporates internal de-bounce timings that remove the need for external RC circuits, reducing cost and overall
PCB footprint. Additionally all switches of the TS3A227E and the internal de-bounce timings can be controlled
through I2C.
Before an insertion, TS3A227E isolates the MICBIAS voltage output from the audio jack to remove click/pop
noise that can be created during an insertion event. In addition the device also includes depletion FETs to
ground the accessory SLEEVE and RING2 pins when VDD is not powered. This removes the humming noise
that can be created when plugging an accessory into and unpowered system.
The TS3A227E detects the presence and configuration of the microphone in an attached headset upon insertion.
Upon detection of a microphone the TS3A227E automatically connects a system analog microphone pin (MICP)
to the appropriate audio jack connection. The device also automatically routes the device GNDA pin to the
headset ground. After a 4-pole headset insertion the host can enable the Key Press detection feature of the
TS3A227E.
The device also features an ultra-low power sleep mode to conserve battery life when an accessory is not
inserted.
For FM transmission the ground FETs of the device can be used as an FM transmission path by placing the FM
receiver and matching network on the GNDA pin. The FM support bit must be set to ‘1’ through I2C for FM
transmission to pass.
版权 © 2014–2015, Texas Instruments Incorporated
17
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
9.2 Functional Block Diagram
BATTERY
AUDIO
AMPLIFIER
VDD
TS3A227E
MIC_PRESENT
SCL
SDA
INTB
Digital interface
control
DIGITAL BASEBAND
EMI
TIP
FILTER
Detection
Circuitry
DET_TRIGGER
RING2_SENSE
EMI
FILTER
ESD Protection
SLEEVE_SENSE
MICP
MICROPHONE
AMPLIFIER
Mic Switch
Matrix
RING2
GND_SENSE
SLEEVE
GND Switch
Matrix
S1 and S2
Depletion FETs
GND
GNDA
FM
Receiver
18
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
9.3 Feature Description
9.3.1 Accessory Configuration Detection
There are currently two difference configurations for headsets with microphones as shown in 表 1. Many codecs
requires that the system designer make a tough decision via a hardware connection which headset they would
like to support. This is done by directly connecting the microphone bias and the ground connections to the sleeve
and ring2 pins of the audio jack. For the end user this leaves a headset standard as fully unsupported.
表 1. Two Difference Configurations for Headsets
PHYSICAL CONNECTOR
INTERNAL IMPEDANCE NETWORK
PIN NAME CONFIGURATION
Tip
Ring
Sleeve
Tip
Audio Left
L
R
G
Ring
Audio Right
TRS
16-2 kΩ
Sleeve
Ground
16-2 kΩ
3-pole TRS
600-4kΩ
Tip
Audio Left
Audio Right
Ground
Ring1
Ring2
L
R
G
M
Tip
Ring1
Ring2
Sleeve
Sleeve
Microphone
Standard
16-2 kΩ
16-2 kΩ
600-4kΩ
Tip
Audio Left
Audio Right
Microphone
Ring1
Ring2
4-pole TRRS
L
R
M
G
Sleeve
Ground
OMTP
16-2 kΩ
16-2 kΩ
The TS3A227E fills this system gap by detecting the presence and location of the microphone and automatically
routing the MICBIAS and ground lines to support each headset. This enhances the overall user experience by
allowing headsets from all manufacturers.
9.3.2 Optional Manual I2C Control
The TS3227E also features optional manual I2C control for enhanced system flexibility. This allows the system
designer to manually control the switches and de-bounce settings at their discretion enabling the TS3A227E to
adapt to unique use cases.
This is an optional feature that does not need to be used for the device to operate autonomously.
9.3.3 Adjustable De-bounce Timings
The TS3A227E features manual control of the insertion de-bounce timer with selectable values. The default
insertion de-bounce timer is 90 ms.
This eliminates the need for external RC components which reduces BOM cost, the PCB footprint of the external
RC components. Further information on how to select an appropriate de-bounce timer can be found in the
application and implementation section.
版权 © 2014–2015, Texas Instruments Incorporated
19
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
9.3.4 Key Press Detection
After a headset is inserted, the host can enable Key Press detection through the I2C registers. This will configure
the TS3A227E to detect up to 4 different keys and report when the key is pressed and released.
9.3.5 Click Pop Noise Reduction
During an accessory insertion and removal event the TS3A227E use special techniques to remove the click/pop
noise that can occur with a traditional implementation creating a better user experience.
9.3.6 Power off Noise Removal
In a system that intends to support both headset types, the end user can place the system into sleep mode and
leave a headset/speaker plugged into the audio jack. If the audio jack switch is turned off to conserve power in
the sleep mode this would typically mean the headset/speaker ground would not be connected because there is
no power to turn on the ground FETs. This creates an audible humming noise at the speaker/headset output that
can be discomforting to listen to.
By utilizing always on depletion FETs this issue can be removed and the headset/speaker can be connected to
ground even with the device unpowered.
9.3.7 Sleep Mode
The TS3A227E will automatically enter a low power sleep when no accessory is inserted and manual switch
control is not enabled. After an accessory is inserted the device will wake, run detection, and configure the
switches as necessary.
9.3.8 Codec Sense Line
In the complex systems of today, there is an increasing amount of ICs on any given board. The issue this creates
is that a codec can be far away from the audio jack and there is a potential difference between the grounding of
the codec and the grounding of the headset.
By incorporating a ground sense line into the TS3A227E the codec can compensate for this offset and create a
higher quality audio experience.
9.3.9 FM Support
FM can be picked up using the headset ground line and passed through the ground FETs of the TS3A227E. By
having a bandwidth of 200 MHz the full FM band can be passed through these FETs to a FM matching network
and the FM receiver.
9.4 Device Functional Modes
9.4.1 Sleep Mode
The device will realize a sleep mode of 1 µA if the following are true:
•
•
No accessory is inserted
Manual Switch Control = ‘0’
The TS3A227E will respond to I2C communication and insertion events while in sleep mode. The user can set
the de-bounce settings and device configuration as desired while in the sleep mode. If the user sets the Manual
Switch Control bit to ‘1’ the device will turn on all blocks and come out of sleep mode.
If there is no accessory inserted and the users exits manual switch control, the switches will revert to the no-
insertion state and all unnecessary blocks of the TS3A227E will turn off and enter the sleep mode.
20
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
Device Functional Modes (接下页)
9.4.2 Manual Switch Control
The TS3A227E supports manual switch control that can be utilized by setting Bit6 of the Device Settings 1
register to ‘1’.
Key operational characteristics of manual switch control are below.
1. Enabling the manual switch control does not disable automatic insertion and accessory type detection.
2. Manual Switch Control is blocked during accessory type detection which includes an automatic detection
sequence or a manual SW triggered detection sequence. Any changes to the switch control registers, or
setting the device to manual switch control will not update the switches until after the accessory type
detection has completed.
3. Manual Switch Control is also blocked during de-bounce periods.
4. Excluding items 2 and 3 above, immediately after the system enables manual switch control the switch states
will change to reflect the switch control registers. It is advised to set the desired state of the switches before
enabling manual switch control.
5. Turning off the depletion FETs of the device will result in increased power consumption as defined in the
electrical characteristics table.
6. Immediately upon setting Manual Switch Control = ‘0’ the device will automatically configure the switches to
the latest detection state. If an accessory is inserted but the TS3A227E has not run detection due to
Auto_Det_EN = ‘0’, the switch status will revert to the no insertion state.
7. The device cannot be in sleep mode and utilize manual switch control at the same time.
9.4.3 Manual Switch Control Use Cases
The table below captures what occurs after a 3-pole insertion with the Manual Switch Control, Auto DET Enable,
and DET Trigger bits set to the following before an insertion.
MANUAL
SWITCH
CONTROL
DOES TYPE
DETECTION
RUN
AUTO DET DET TRIGGER
SWITCH STATUS AFTER
INSERTION
DET TRIGGER (SW) AFTER
INSERTION
EN
(SW)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
no
No-insertion
0
0
0
0
0
0
0
0
yes
yes
yes
no
3-pole config
3-pole config
3-pole config
Switch control registers
Switch control registers
Switch control registers
Switch control registers
yes
yes
yes
The table below captures the switch and relevant register outputs for sequence 1.
EVENT
NO.
3-POLE
BIT
4-POLE
OMTP BIT
4-POLE
STANDARD BIT
EVENT DESCRIPTION
Device powers up
SWITCH STATUS
1
2
3
4
5
6
No-insertion
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
User sets Auto DET Enable = ‘0’
No-insertion
3-pole accessory is inserted
No-insertion
System sets Manual Switch Control = ‘1’
System sets switch control registers = 0xFF
System sets Manual Switch Control = ‘0’
System controlled
System controlled
No-insertion
版权 © 2014–2015, Texas Instruments Incorporated
21
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
In sequence 1 at event 3 the switch status does not change because the system set the Auto DET Enable = ‘0’.
When the accessory is inserted we will not run detection and not change the switches because of this.
At event 6 the system turns off manual switch control, the switch state reverts back to the No-insertion state
because the TS3A227E has not ran detection.
The table below captures the switch and relevant register outputs for sequence 2.
EVENT
NO.
SWITCH STATUS
AFTER EVENT
3-POLE
BIT
4-POLE
STANDARD BIT
4-POLE
OMTP BIT
EVENT DESCRIPTION
Device powers up
1
2
3
4
5
6
7
No-insertion
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
User sets Auto DET Enable = ‘0’
No-insertion
3-pole accessory is inserted
No-insertion
System sets Manual Switch Control = ‘1’
System sets switch control registers = 0xFF
System sets DET Trigger = ‘1’
System controlled
System controlled
System controlled
3-pole configuration
System sets Manual Switch Control = '0'
In sequence 2 at event 3 the switch status does not change because the system set the Auto DET Enable = ‘0’.
When the accessory is inserted we will not run detection and not change the switches because of this.
At event 6 the system turns triggers a manual type detection and the TS3A227E detects a 3-pole accessory. The
switch state will remain in the system controlled state.
At event 7 the system exits manual switch control. The switch status will then change back to the last detection
state. Because detection was ran at event 6 and a 3-pole was detected, the switch state will reflect that of the 3-
pole switch configuration.
22
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
9.4.4 FM Support Mode
FM support mode needs to be entered via I2C through the Device Settings register. This will turn off the
depletion switches when an accessory is inserted, eliminating the extra ground path. The ground line of the
headset/headphone is used for FM transmission. This signal must pass through the TS3A227E ground FETs as
shown in 图 17 where the red line indicates the transmission path.
TS3A227E
S3PR
RING2_SENSE
MICP
S3PS
S3GS
S3GR
Audio Jack
SLEEVE_SENSE
GND_SENSE
L
R
G
M
RING2
SLEEVE
RING2
GNDFET
SLEEVE
GNDFET
RING2
DFET
SLEEVE
DFET
S1
S2
GND
GNDA
GND
FM
Receiver
图 17. FM Support Transmission Path
注
FM support should be enabled before an accessory is inserted. Toggling the FM
support bit after a headset is inserted can cause a pop noise to be heard by the end
user.
版权 © 2014–2015, Texas Instruments Incorporated
23
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
9.5 Register Maps
The I2C address of the TS3A227E is b’0111011X or 77h read and 76h write.
Addr
(xxh)
Name
Device ID
Interrupt
Type
R
Reset
11h
Bit7
Bit6
Bit5
0
Bit4
Bit3
Bit2
Bit1
0
Bit0
00h
0
0
1
0
0
1
ADC
Conversion
01h
02h
R
00h
Reserved
DC
Ins/Rem Event
Key Press
Interrupts
Key 4
Release
R
00h
08h
Key 4 Press
Key 3 Release
Key 3 Press
Key 2 Release
INT Disable
FM Support
Key 2 Press
Key 1 Release
Key 1 Press
ADC
Conversion
INT Disable
DC INT
Disable
Ins/Rem Event
INT Disable
03h
Interrupt Disable
R/W
Reserved
Manual Switch
Control
Auto DET
Enable
04h
05h
06h
Device Settings
Device Setting 1
Device Setting 2
R/W
R/W
R/W
23h
00h
0Eh
Reset
DET Trigger
Insertion De-bounce Time
Key Press
Enable
Reserved
Raw Data En
ADC Trigger
Key Release
De-bounce
Reserved
MICBIAS Setting
Key Press De-bounce
RING2
GNDFET
SLEEVE
GNDFET
SLEEVE
DFET
07h
08h
09h
0Ah
0Bh
Switch Control 1
Switch Control 2
Switch Status 1
Switch Status 2
R/W
R/W
R
00h
00h
0Ch
00h
00h
Reserved
Reserved
RING2 DFET
S3PR
Switch 2
S3GS
Switch 1
S3GR
Reserved
S3PS
RING2
GNDFET
SLEEVE
GNDFET
SLEEVE
DFET
RING2 DFET
S3PR
Switch 2
S3GS
Switch 1
S3GR
R
Reserved
Reserved
S3PS
Accessory
Status
Insertion
Status
4-Pole
Standard
R
4-pole OMTP
3-pole
0Ch
0Dh
0Eh
0Fh
ADC Output
Threshold 1
Threshold 2
Threshold 3
R
00h
20h
40h
68h
ADC
R/W
R/W
R/W
KP Threshold 1
KP Threshold 2
KP Threshold 3
Interrupt and Key Press Interrupt register notes:
•
The device will continue to automatically run type detection and key press detection even if the host has not
serviced the interrupts.
•
Consecutive reads of an interrupt register at 400 kHz will not allow time for the internal registers to clear and
will appear. The internal digital core requires 200 µs to clear the register after it has been read.
9.6 Register Field Descriptions
9.6.1 Device ID Register Field Descriptions (Address 00h)
图 18. Device ID Register Field Descriptions (Address 00h)
Bit
Field
Type
Reset
11h
Description
Unique Revision number
7-0
Device ID
R
24
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
9.6.2 Interrupt Register Field Descriptions (Address 01h)
表 2. Interrupt Register Field Descriptions (Address 01h)
Bit
7-3
2
Field
Type
Reset
0h
Description
Reserved
ADC Conversion
R
R
0h
0h
ADC Conversion complete Interrupt. Flagged after a manual ADC conversion is
complete.
Interrupt bit is cleared after being read through I2C or after a removal event.
0h = Default state
1h = ADC Conversion Complete
1
0
DC
R
Detection Complete interrupt. Flagged after detection is completed for an
insertion sequence. This bit is also flagged after completion of a manually
triggered detection.
Interrupt bit is cleared after being read through I2C or after a removal event.
0h = Default state
1h = Detection Completed
Ins/Rem Event
R
0h
Insertion or removal interrupt indicator. This bit is set if there is an insertion or
removal event. The Insertion status bit of the Accessory Status register (0Bh)
must be checked if this bit is set.
Interrupt bit is cleared after being read through I2C
0h = Default state
1h = Accessory has been inserted or removed
9.6.3 Key Press Interrupt Register Field Descriptions (Address 02h)
表 3. Key Press Interrupt Register Field Descriptions (Address 02h)
Bit
Field
Type
Reset
0h
Description
7
Key 4 Release
R
This interrupt bit is set after the user has released key 4 on the accessory for a
duration longer than the Key Release De-bounce timer.
This bit will auto-clear on the following conditions:
●
●
Host reads the register through I2C
The KP Enable bit is set to ‘0’
—
The KP Enable bit is set to ‘0’ automatically after a removal
●
The Key 4 press bit is set ot '1'
0h = Default State
1h = Key 4 was released
6
Key 4 Press
R
0h
This interrupt bit is set after the user has pressed key 4 on the accessory for a
duration longer than the Key Press De-bounce timer.
This bit will auto-clear on the following conditions:
●
●
Host reads the register through I2C
The KP Enable bit is set to ‘0’
—
The KP Enable bit is set to ‘0’ automatically after a removal
0h = Default State
1h = Key 4 was released
5
Key 3 Release
R
0h
This interrupt bit is set after the user has pressed Key 3 on the accessory for a
duration longer than the Key Release De-bounce timer.
This bit will auto-clear on the following conditions:
●
●
Host reads the register through I2C
The KP Enable bit is set to ‘0’
—
The KP Enable bit is set to ‘0’ automatically after a removal
●
The Key 3 Press bit is set to ‘1’
0h = Default State
1h = Key 3 was released
版权 © 2014–2015, Texas Instruments Incorporated
25
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
表 3. Key Press Interrupt Register Field Descriptions (Address 02h) (接下页)
Bit
Field
Type
Reset
Description
4
Key 3 Press
R
0h
This interrupt bit is set after the user has pressed Key 3 on the accessory for a
duration longer than the Key Press De-bounce timer.
This bit will auto-clear on the following conditions:
●
●
Host reads the register through I2C
The KP Enable bit is set to ‘0’
—
The KP Enable bit is set to ‘0’ automatically after a removal
0h = Default State
1h = Key 3 was released
3
Key 2 Release
R
0h
This interrupt bit is set after the user has pressed Key 2 on the accessory for a
duration longer than the Key Release De-bounce timer.
This bit will auto-clear on the following conditions:
●
●
Host reads the register through I2C
The KP Enable bit is set to ‘0’
—
The KP Enable bit is set to ‘0’ automatically after a removal
●
The Key 2 Press bit is set to ‘1’
0h = Default State
1h = Key 2 was released
2
Key 2 Press
R
0h
This interrupt bit is set after the user has pressed Key 2 on the accessory for a
duration longer than the Key Press De-bounce timer.
This bit will auto-clear on the following conditions:
●
●
Host reads the register through I2C
The KP Enable bit is set to ‘0’
—
The KP Enable bit is set to ‘0’ automatically after a removal
0h = Default State
1h = Key 2 was released
1
Key 1 Release
R
0h
This interrupt bit is set after the user has pressed Key 1 on the accessory for a
duration longer than the Key Release De-bounce timer. This bit is used for raw
data release events.
This bit will auto-clear on the following conditions:
●
●
Host reads the register through I2C
The KP Enable bit is set to ‘0’
—
The KP Enable bit is set to ‘0’ automatically after a removal
●
The Key 1 Press bit is set to ‘1’
0h = Default State
1h = Key 1 was released
0
Key 1 Press
R
0h
This interrupt bit is set after the user has pressed Key 1 on the accessory for a
duration longer than the Key Press De-bounce timer. This bit is used for raw data
press events.
This bit will auto-clear on the following conditions:
●
●
Host reads the register through I2C
The KP Enable bit is set to ‘0’
—
The KP Enable bit is set to ‘0’ automatically after a removal
0h = Default State
1h = Key 1 was released
26
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
9.6.4 Interrupt Disable Register Field Descriptions (Address 03h)
表 4. Interrupt Disable Register Field Descriptions (Address 03h)
Bit
7-3
+3
Field
Type
Reset
0h
Description
Reserved
INT Disable
R
R/W
1h
Enables or disables all interrupts. Disabling the interrupts will cause the INT to
not assert but the bits will still populate.
0h = interrupts are enabled
1h = interrupts are disabled
2
ADC Conversion
INT Disable
R/W
0h
Enables or disables the ADC conversion interrupt. Disabling the interrupt will
cause INT to not assert but the interrupt bit will still be set .
In the use case that this bit is == ‘1’ and a key is pressed, the Key Press
interrupt will still assert the INT pin. If the host issues a software ADC trigger
after the key has been pressed, the interrupt will not assert as that ADC
conversion is the only interrupt present.
0h = ADC Conversion interrupt is enabled
1h = ADC Conversion interrupt is disabled
1
0
DC INT Disable
R/W
0h
0h
Enables or disables the DC interrupt. Disabling the interrupt will cause INT to
not assert but the interrupt bit will still be set.
0h = DC interrupt is enabled
1h = DC interrupt is disabled
Ins/Rem Event INT R/W
Disable
Enables or disables the Ins/Rem Event interrupt. Disabling the interrupt will
cause INT to not assert but the interrupt bit will still be set.
0h = Ins/Rem Event interrupt is enabled
1h = Ins/Rem Event interrupt is disabled
9.6.5 Device Settings Field Descriptions (Address 04h)
表 5. Device Settings Field Descriptions (Address 04h)
Bit
Field
Type
R/W
Reset
0h
Description
7
Reset
Initiates software reset of the TS3A227E. This will interrupt any on-going
operation internal to the device.
0h = Default state
1h = Initiates a reset
6
Manual Switch
Control
R/W
0h
Enables Manual control of the TS3A227E switches. After enabling manual switch
control the switch status will immediately reflect the values in the switch control
registers provided accessory type.
0h = Manual switch control disabled
1h = Manual switch control enabled
5
4
Auto DET Enable
DET Trigger
R/W
R/W
1h
0h
Controls whether detection is automatically ran after an insertion.
0h = Auto accessory detection is disabled
1h = Auto accessory detection is enabled
Manually triggers detection. This bit is auto cleared after detection is completed.
A DET Trigger request will be ignored in the following cases:
●
●
●
A detection event is currently being service.
The interrupt register is not cleared (Register 02h must be = 00h)
There is no accessory inserted (/DET_TRIGGER is high)
0h = Default value
1h = Manually trigger detection
3
FM Support
R/W
0h
Turns on FM support. This will turn off the depletion FETs if any accessory is
inserted allowing FM transmission through the ground FETs at the cost of
increased current consumption.
0h = FM not supported and depletion FETs are on after an insertion
1h = FM supported and depletion FETs are off after an insertion
版权 © 2014–2015, Texas Instruments Incorporated
27
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
表 5. Device Settings Field Descriptions (Address 04h) (接下页)
Bit
Field
Type
Reset
Description
2.0
Insertion De-bounce
Time
R/W
3h
Controls the insertion de-bounce timer. Values below are typical values that have
±30% variation. Values in addition have a ±1 ms variation though this will only
really affect the 2 ms timer.
0h = 2 ms
1h = 30 ms
2h = 60 ms
3h = 90 ms
4h = 120 ms
5h = 150 ms
6h = 1 s
7h = 2 s
9.6.6 Key Press Settings 1 Field Descriptions (Address 05h)
表 6. Device Settings 1 Field Descriptions (Address 05h)
Bit
7-3
2
Field
Type
Reset
0h
Description
Reserved
R
Key Press Enable
R/W
0h
Enables the Key Press detection of the TSA227E. This bit auto clears after a
removal event.
If the Key Press Enable bit is set ‘1’ and the Manual Switch Control bit is set to
‘1’, the S3 matrix must be in one of the two correct position as described in the
Key Press Detection section for the TS3A227E to run key press detection.
0h = Default state
1h = Enables Key Press detection
1
Raw Data En
R/W
0h
Enables the Raw data mode for Key Press Detection. This bit auto clears if the
Key Press Enable bit is set to ‘0’.
Enabling raw data mode will not clear the KP interrupt register. After enabling
Raw Data any key press and release event is recorded using the Key 1 Press
and Key 2 Press Release event. The ADC conversion will be recorded in the
ADC output register.
0h = Raw Data is not enabled
1h = Raw Data is enabled
0
ADC Trigger
R/W
0h
Causes a manual ADC trigger if the Key Press Enable and Raw Data EN bits are
both set to ‘1’. After the ADC conversion is complete the ADC Conversion
interrupt will be set and the ADC Output register will be populated.
This bit auto clears after the ADC Conversion is complete. A new ADC
Conversion can be initiated even if the ADC Conversion interrupt has not been
serviced.
0h = Default State
1h = Triggers ADC conversion
28
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
9.6.7 Key Press Settings 2 Field Descriptions (Address 06h)
表 7. Device Settings 2 Field Descriptions (Address 06h)
Bit
7-6
5-3
Field
Type
Reset
0h
Description
Reserved
R
MICBIAS Setting
R/W
1h
This controls the key press threshold. Set this setting closest to the intended
MICBIAS voltage
0h = 2.1 V
1h = 2.2 V (Default)
2h = 2.3 V
3h = 2.4 V
4h = 2.5 V
5h = 2.6 V
6h = 2.7 V
7h = 2.8 V
2
Key Release De-
bounce
R/W
R/W
1h
2h
Controls the Key-Release de-bounce timer. Values below are typical values that
have ±30% variation. Values in addition have a ±1 ms variation though this will
only really affect the 2 ms timer.
0h = 2 ms
1h = 20 ms (Default)
1-0
Key Press De-
bounce
Controls the key press de-bounce timer. Values below are typical values that
have ±30% variation. Values in addition have a ±1 ms variation though this will
only really affect the 2 ms timer.
0h = 2 ms
1h = 40 ms
2h = 80 ms (Default)
3h = 120 ms
版权 © 2014–2015, Texas Instruments Incorporated
29
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
9.6.8 Switch Control 1 Field Descriptions (Address 07h)
表 8. Switch Control 1 Field Descriptions (Address 07h)
Bit
7-6
5
Field
Type
Reset
0h
Description
Reserved
R
SLEEVE GNDFET R/W
0h
0h
0h
0h
0h
0h
Configures the state of the SLEEVE GNDFET if manual switch control is enabled.
If manual switch control is not enabled this bit is ignored.
0h = SLEEVE GNDFET switch off
1h = SLEEVE GNDFET switch on
4
3
2
1
0
RING2 DFET
SLEEVE DFET
RING2 DFET
Switch 2
R/W
R/W
R/W
R/W
R/W
Configures the state of the RING2 GNDFET if manual switch control is enabled. If
manual switch control is not enabled this bit is ignored.
0h = RING2 GNDFET switch off
1h = RING2 GNDFET switch on
Configures the state of the SLEEVE DFET if manual switch control is enabled. If
manual switch control is not enabled this bit is ignored.
0h = SLEEVE DFET switch off
1h = SLEEVE DFET switch on
Configures the state of the RING2 DFET if manual switch control is enabled. If
manual switch control is not enabled this bit is ignored.
0h = RING2 DFET switch off
1h = RING2 DFET switch on
Configures the state of the Switch 2 if manual switch control is enabled. If manual
switch control is not enabled this bit is ignored.
0h = Switch 2 off
1h = Switch 2 on
Switch 1
Configures the state of the Switch 1 if manual switch control is enabled. If manual
switch control is not enabled this bit is ignored.
0h = Switch 1 off
1h = Switch 1 on
9.6.9 Switch Control 2 Field Descriptions (Address 08h)
表 9. Switch Control 2 Field Descriptions (Address 08h)
Bit
7-4
3
Field
Type
Reset
0h
Description
Reserved
S3PS
R
R/W
R/W
R/W
R/W
0h
0h
0h
0h
Configures the state of the S3PS if manual switch control is enabled. If manual
switch control is not enabled this bit is ignored.
0h = S3PS switch off
1h = S3PS switch on
2
1
0
S3PR
S3GS
S3GR
Configures the state of the S3PR if manual switch control is enabled. If manual
switch control is not enabled this bit is ignored.
0h = S3PR switch off
1h = S3PR switch on
Configures the state of the S3GS if manual switch control is enabled. If manual
switch control is not enabled this bit is ignored.
0h = S3GS off
1h = S3GS on
Configures the state of the S3GR if manual switch control is enabled. If manual
switch control is not enabled this bit is ignored.
0h = S3GR off
1h = S3GR on
30
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
9.6.10 Switch Status 1 Field Descriptions (Address 09h)
表 10. Switch Status 1 Field Descriptions (Address 09h)
Bit
7-6
5
Field
Type
Reset
0h
Description
Reserved
R
SLEEVE GNDFET
R
R
R
R
R
R
0h
0h
1h
1h
0h
0h
Indicates the status of SLEEVE GNDFET
0h = SLEEVE GNDFET switch is off
1h = SLEEVE GNDFET switch is on
4
3
2
1
0
RING2 GNDFET
SLEEVE DFET
RING2 DFET
Switch 2
Indicates the status of RING2 GNDFET
0h = RING2 GNDFET switch is off
1h = RING2 GNDFET switch is on
Indicates the status of SLEEVE DFET
0h = SLEEVE DFET switch is off
1h = SLEEVE DFET switch is on
Indicates the status of RING2 DFET
0h = RING2 DFET switch is off
1h = RING2 DFET switch is on
Indicates the status of Switch 2
0h = Switch 2 is off
1h = Switch 2 is on
Switch 1
Indicates the status of Switch 1
0h = Switch 1 is off
1h = Switch 1 is on
9.6.11 Switch Status 2 Field Descriptions (Address 0Ah)
表 11. Switch Status 2 Field Descriptions (Address 0Ah)
Bit
7-4
3
Field
Type
Reset
0h
Description
Reserved
S3PS
R
R
R
R
R
0h
0h
0h
0h
Indicates the status of S3PS
0h = S3PS switch is off
1h = S3PS switch is on
2
1
0
S3PR
S3GS
S3GR
Indicates the status of S3PR
0h = S3PR switch is off
1h = S3PR switch is on
Indicates the status of S3GS
0h = S3GS is off
1h = S3GS is on
Indicates the status of S3GR
0h = S3GR is off
1h = S3GR is on
版权 © 2014–2015, Texas Instruments Incorporated
31
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
9.6.12 Detection Results Field Descriptions (Address 0Bh)
表 12. Detection Results Field Descriptions (Address 0Bh)
Bit
7-4
3
Field
Type
Reset
0h
Description
Reserved
Insertion Status
R
R
0h
Indicates if an accessory is inserted the jack or not. This bit is set to the
corresponding state after an accessory is inserted or removed and should be
read after the Ins/Rem Event interrupt has been set to ‘1’.
0h = An accessory is not in the jack
1h = An accessory is in the jack
2
1
0
4-pole Standard
4-pole OMTP
3-pole
R
R
R
0h
0h
0h
Indicates if a 4-pole Standard headset is detected. Bit is set after a completed
detection sequence.
0h = Default state
1h = 4-pole standard headset detected
Indicates if a 4-pole OMTP headset is detected. Bit is set after a completed
detection sequence.
0h = Default state
1h = 4-pole OMTP headset detected
Indicates if a 3-pole headphone is detected. Bit is set after a completed
detection sequence.
0h = Default state
1h = 3-pole headphone detected
9.6.13 ADC Output Field Descriptions (Address 0Ch)
表 13. ADC Output Field Descriptions (Address 0Ch)
Bit
7-1
0
Field
Type
R/W
R
Reset
00h
0h
Description
This field contains the output of the key press detection ADC as described in
the key press detection register
ADC
Reserved
9.6.14 Threshold 1 Field Descriptions (Address 0Dh)
表 14. Threshold 1 Field Descriptions (Address 0Dh)
Bit
7-01
0
Field
Type
R/W
R
Reset
20h
0h
Description
This field sets the key 1 and key 2 boundary threshold. This value must always
be lower than the Threshold 2 register for proper operation.
KP Threshold 1
Reserved
9.6.15 Threshold 2 Field Descriptions (Address 0Eh)
表 15. Threshold 2 Field Descriptions (Address 0Eh)
Bit
7-1
0
Field
Type
R/W
R
Reset
40h
0h
Description
This field sets the key 2 and key 3 boundary threshold. This value must
always be lower than the Threshold 3 register and higher than the threshold 2
register for proper operation.
KP Threshold 2
Reserved
9.6.16 Threshold 3 Field Descriptions (Address 0Fh)
表 16. Threshold 3 Field Descriptions (Address 0Fh)
Bit
7-1
0
Field
Type
R/W
R
Reset
68h
0h
Description
This field sets the key 3 and key 4 boundary threshold. This value must
always be higher than the Threshold 2 register for proper operation.
KP Threshold 3
Reserved
32
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
10 Application and Implementation
10.1 Application Information
图 19 shows how a standard application schematic for the TS3A227E. The DSBGA package pin connections will
be the same except for the lack of thermal pad. The following sections discuss how the TS3A227E works with
different headsets and how the key press detection operates.
10.2 Typical Application
3.3 V
C1
C2
R4
R3
R5
R2
R1
4
16
9
15
14
7
VDD
DET_TRIGGER
TIP
Application
Processor
MIC_PRESENT
SCL
RING2_SENSE
SLEEVE_SENSE
RING2
3
8
SDA
MICBIAS
13
6
12
10
11
2
INT
R6
C3
MICI
MICP
SLEEVE
GND_SENSE
5
GND_SENSE
GND
GNDA
C4
FM Network
1
GND
L1
TS3A227ERVAR
图 19. Typical Application Schematic
表 17. Component List
COMPONENT
VALUE
4.7 kΩ
4.7 kΩ
4.7 kΩ
4.7 kΩ
10 kΩ
NOTES
R1
R2
R3
R4
R5
R6
C1
C2
C3
Pullup resistor must be sized to not exceed max IOL specification for INT pin
Pullup resistor must be sized to not exceed max IOL specification for INT pin
Pullup resistor must be sized to not exceed max IOL specification for INT pin
Pullup resistor must be sized to not exceed max IOL specification for INT pin
Pulldown resistor for high to low transition on DET_TRIGGER
MICBIAS pullup resistor must be ±1% for Key Press Detection to function properly
De-coupling capacitor for VDD
2.2 kΩ ±1%
10 µF
100 nF
1 µF
De-coupling capacitor for VDD
Value can vary depending on codec needs
Value can vary depending on FM matching network needs. If FM transmission is not being
supported by the application this capacitor is not needed
C4
L1
47 nF
Value can vary depending on FM matching network needs. If FM transmission is not being
supported by the application this inductor is not needed and GNDA must be shorted to GND
180 nF
10.2.1 Design Requirements
10.2.1.1 Standard I2C Interface Details
The bi-directional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
版权 © 2014–2015, Texas Instruments Incorporated
33
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
I2C communication with this device is initiated by the master sending a START condition, a high-to-low transition
on the SDA line while the SCL line is high. After the start condition, the device address byte is send, MSB first,
including the data direction bit (R/W). This device does not respond to the general call address. After receiving
the valid address byte (0x77 read, 0x76 write), this device responds with an ACK, a low on the SDA line during
the high of the ACK-related clock pulse.
The data byte follows the address ACK. The R/W bit is kept low for transfer from the master to the slave. The
data byte is followed by an ACK sent from this device. Data are output only if complete bytes are received and
acknowledged. The output data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle
for the ACK.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (START or STOP).
A Stop condition, a low-to-high transition on the SDA line while the SCL line is high, is sent by the master. The
number of data bytes transferred between the start and the stop conditions from the transmitter to receiver is not
limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the
receiver can send an ACK bit.
A slave receiver that is addressed must generate an ACK after the reception of each byte. The device that
acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during
the high pulse of the ACK-related clock period. Setup and fold times must be taken into account.
Start
Clock pulse for
acknowledgment
Condition
ST
SCL
1
2
8
9
SDA Output
by
Transmitter
NACK
SDA Output
by Receiver
ACK
图 20. Acknowledgment on the I2C Bus
10.2.1.2 Write Operations
Data is transmitted to the TS3A227E by send the device salve address and setting the LSB to a logic 0. The
command byte is sent after the address and determines which register receives the data that follows the
command byte. The next byte is written to the specified register on the rising edge of the ACK clock pulse. See
Figure 2 and Figure 3 for different modes of write operations.
Slave Address
Sub Address
Data Byte
Data Byte
ST A6 A5 A4 A3 A2 A1 A0
0
A
0
0
0
0
0
0
0
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
SP
START
R/W
Register Address N
Data to Register N
Data to Register N
STOP
ACK From slave
Auto Increment
ACK From slave
ACK From slave
ACK From slave
图 21. Repeated Data Write to a Single Register
34
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
图 22. Burst Data Write to Multiple Registers
10.2.1.3 Read Operations
The bus master must send the TS3A227E slave address with the LSB set to logic 0. The command byte is sent
after the address and determines which register is accessed. After a restart, the device slave address is sent
again but this time the LSB is set to logic 1. Data from the register defined by the command byte then is sent
back to the host by the TS3A227E. Data is clicked into the SDA output shift register on the rising edge of the
ACK clock pulse. 图 23 and 图 24 show read operations that use a restart between the sub-address write and
the read operation. A Stop and start condition between the sub-address write and the read operation is also
acceptable.
Notes:
1. SDA is pulled low on ACK from the slave or master.
2. Register write always a require sub-address write before writing the first data.
3. Repeated data writes to a single register continue indefinitely until n I2C Stop or Re-start.
4. Repeated data reads from a single register continue indefinitely until an I2C NACK is received from the
master
5. Burst data writes start at the specified register address, then advance to the next register address, even
to the read-only registers and continue until the Stop or Re-start. For the read-only registers, data write
appears to occur, although the register contents are not changed by the write operations.
6. Burst data reads start at the specified register address, then advance to the next register address and
continues until an I2C NACK is received from the master.
Slave Address
Sub Address
Slave Address
Data Byte
ST A6 A5 A4 A3 A2 A1 A0
0
A
0
0
0
0
0
0
0
0
A
RS A6 A5 A4 A3 A2 A1 A0
1
A
D7 D6 D5 D4 D3 D2 D1 D0
A
START
R/W
Register Address N
ACK From slave
R/W
Data from Register N
ACK From master
ACK From slave
Auto Increment
Re-start
ACK From slave
Data Byte
Data Byte
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Data from Register N
ACK From master
Data from Register N
NACK From master
Stop
图 23. Repeated Data Read From a Single Register
版权 © 2014–2015, Texas Instruments Incorporated
35
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
Slave Address
Sub Address
Slave Address
Data Byte
ST A6 A5 A4 A3 A2 A1 A0
0
A
0
0
0
0
0
0
0
0
A
RS A6 A5 A4 A3 A2 A1 A0
1
A
D7 D6 D5 D4 D3 D2 D1 D0
A
START
R/W
Register Address N
ACK From slave
R/W
Data from Register N
ACK From master
ACK From slave
Auto Increment
Re-start
ACK From slave
Data Byte
Data Byte
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Data from Register N
ACK From master
Data from Register N
NACK From master
Stop
图 24. Burst Data Read From Multiple Registers
10.2.2 Detailed Design Procedure
10.2.2.1 Accessory Insertion
The TS3A227E monitors the DET_TRIGGER pin to determine when an insertion event occurs. A high to low
transition one the DET_TRIGGER pin will start the internal de-bounce timer (default 90 ms). This transition is
shown in 图 19. Once the de-bounce timer has expired, it is determined that an accessory is inserted and the
detection algorithm is performed to determine what the accessory is and where the ground line is located.
Audio Jack
TS3A227E
VDD
RING1
DET_TRIGGER
High to Low
TIP
L
R
?
?
S3PR
S3PS
S3GS
S3GR
RING2
MICP
SLEEVE
GND_SENSE
RING2
GNDFET
SLEEVE
GNDFET
RING2
DFET
SLEEVE
DFET
S1
S2
GND
GNDA
GND
图 25. DET_TRIGGER Transition Diagram
Once a DET_TRIGGER transition has occurred, any I2C register changes will not be serviced until after the de-
bounce and detection sequence have completed. If DET_TRIGGER transitions from Low to High before the de-
bounce period has expired. The I2C register changes will be serviced before a new de-bounce timer is started
from another High to Low transition on the DET_TRIGGER pin. The I2C communication has to complete before
the next High to Low transition to take effect.
10.2.2.2 Audio Jack Selection
The audio jack the system uses plays a key role in how the system performs and the experience the end user
has with the equipment. In real-world scenarios a user might plug in the headset to the audio jack very slowly.
This creates a challenging case for the TS3A227E detection mechanism and detection error can occur if care is
not taken when designing the components around the TS3A227E.
36
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
The main concern for slow plug-in is the detection process may have already started before the headset is fully
inserted into the jack. If the detection is running with the headset out of position, a false impedance
measurement may occur. For best performance a jack should be chosen that puts the detection mechanism on
the TIP pin at the end of physical jack to ensure that it is fully inserted.
The TS3A227E EVM contains test points for all the jack pins and can be blue wired to prototype audio jacks for
testing.
10.2.2.3 Switch Status
表 18 depicts the switch status for each device configuration. A switch diagram is provided in 图 26.
表 18. Switch Status
RING2
GNDFET GNDFET
SLEEVE
RING2
DFET
SLEEVE
DFET
Device State
S1
S2
S3PS
S3PR
S3GS
S3GR
Default State (No insertion
or VDD = 0 V)
High-Z High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
On
On
Detection running
3-pole
High-Z
On
On
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
On
High-Z
On
High-Z
On
High-Z
On
High-Z
On
High-Z
On
High-Z
On
High-Z
High-Z
3-pole with FM support
4-pole OMTP
On
High-Z
On
On
On
High-Z
On
High-Z
High-Z
High-Z
On
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z
High-Z
4-pole OMTP with FM
support
High-Z
On
On
On
High-Z
On
High-Z
On
On
High-Z
On
High-Z
High-Z
High-Z
4-pole Standard
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
4-pole Standard with FM
support
On
On
On
High-Z
TS3A227E
S3PR
RING 2_SENSE
MICP
S3PS
S3GS
S3GR
SLEEVE_SENSE
GND_SENSE
RING2
SLEEVE
RING2
GNDFET
SLEEVE
GNDFET
RING2
DFET
SLEEVE
DFET
S1
S2
GND
GNDA
GND
图 26. Switch Diagram
版权 © 2014–2015, Texas Instruments Incorporated
37
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
10.2.2.3.1 Switch Status Diagrams
Closed switches are red in 图 27 through 图 31. The diagrams reflect switch states when manual switch control is
not enabled.
TS3A227E
S3PR
RING2_SENSE
MICP
S3PS
S3GS
S3GR
Audio Jack
SLEEVE_SENSE
GND_SENSE
RING2
SLEEVE
RING2
GNDFET
SLEEVE
GNDFET
RING2
DFET
SLEEVE
DFET
S1
S2
GND
GNDA
GND
图 27. Default Switch State With No Accessory Inserted
TS3A227E
S3PR
RING2_SENSE
MICP
S3PS
Audio Jack
S3GS
SLEEVE_SENSE
GND_SENSE
L
R
?
?
S3GR
RING2
SLEEVE
RING2
GNDFET
SLEEVE
GNDFET
RING2
DFET
SLEEVE
DFET
S1
S2
GND
GNDA
GND
图 28. Switch State During Detection
38
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
TS3A227E
S3PR
S3PS
S3GS
S3GR
RING2_SENSE
MICP
Audio Jack
SLEEVE_SENSE
GND_SENSE
L
R
G
RING2
SLEEVE
RING2
GNDFET
SLEEVE
GNDFET
RING2
DFET
SLEEVE
DFET
S1
S2
GND
GNDA
GND
图 29. Switch State After Detecting a 3-Pole Headphone
TS3A227E
S3PR
RING2_SENSE
MICP
S3PS
Audio Jack
S3GS
SLEEVE_SENSE
GND_SENSE
L
R
M
G
S3GR
RING2
SLEEVE
RING2
GNDFET
SLEEVE
GNDFET
RING2
DFET
SLEEVE
DFET
S1
S2
GND
GNDA
GND
图 30. Switch State After Detection a 4-pole OMTP Headset
版权 © 2014–2015, Texas Instruments Incorporated
39
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
TS3A227E
S3PR
RING2_SENSE
MICP
S3PS
Audio Jack
S3GS
SLEEVE_SENSE
GND_SENSE
L
R
G
M
S3GR
RING2
SLEEVE
RING2
GNDFET
SLEEVE
GNDFET
RING2
DFET
SLEEVE
DFET
S1
S2
GND
GNDA
GND
图 31. Switch State After Detecting a 4-Pole Standard Headset
40
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
10.2.2.4 Key Press Detection
10.2.2.4.1 Key Press Thresholds
The TS3A227E features the ability to adjust the key press thresholds on the fly. The default key press bins are
shown below with the default values of the threshold registers optimized to detect these keys. The values for the
bins represent the equivalent resistance of the key being pressed with the microphone in parallel. Any equivalent
resistance outside these bins is not guaranteed to be detected correctly.
KEY
Key 1
Key 2
Key 3
Key 4
TYPICAL RESISTANCE
EQUIVALENT RESISTANCE RANGE
0 Ω – 66 Ω
50 Ω
135 Ω
240 Ω
470 Ω
126 Ω – 156 Ω
228 Ω – 264 Ω
360 Ω – 680 Ω
The Threshold 1 register (Address 0Dh) adjusts the detection boundary between Key 1 and Key2. The Threshold
2 register (Address 0Eh) adjusts the detection boundary between Key 2 and Key 3. The Threshold 3 register
(Address 0Fh adjusts the detection boundary between Key 3 and Key4.
The thresholds are 7 bit values that can be adjusted for the following formula.
Target bin boundary = KP Threshold[6:0] × 6 Ω
(1)
It is important for the proper operation of the KP detection algorithm that the thresholds be ordered correctly: KP
Threshold 1< KP Threshold 2 < KP Threshold 3. Placing them out of order will cause incorrect keys to be
detected. For information on defining the key press gray zones see the Key Press Gray Zones section.
10.2.2.4.2 System Requirements
The Key Press detection algorithm has the following system requirements to be function properly:
•
•
•
MICBIAS output voltage equivalent to key press settings 2 register value within 2.5%
MICBIAS pullup resistance equal to 2.2 kΩ ±1%
Audio jack contact resistance must be limited to < 100 mΩ. See further information below.
图 32 depicts the resistor network without the TS3A227E switches for simplicity.
MICBIAS
2.2 kΩ
SLEEVE/RING2
Key2
Key3
Key4
Key1
MIC
图 32. Headset Microphone and Key Network
When the user presses a key it creates a voltage divider network between the MICBIAS output of the codec and
the system ground. This will be a measurable voltage on the SLEEVE/RING2 pin that follows Equation 2. Note
that this is simplified because it does not include the TS3A227E switches or the contact resistance of the jack
itself.
版权 © 2014–2015, Texas Instruments Incorporated
41
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
REQ
2.2k + D
VSLEEVE/RING2 = V
(
+DVMICBIAS ´
)
MICBIAS
+R
(
)
2.2k
EQ
(2)
The REQ can be calculated with the following:
MIC ´RKEY
REQ =
R
RMIC +RKEY
(3)
As a result of the above calculations, an ADC attempting to detect the voltage on SLEEVE/RING2 to determine
which key is pressed (whichever is the microphone pin) is reliant on the accuracy on the MICBIAS output and the
2.2 kΩ pull-up resistor. The key press bins are targeted assuming ideal values for these system conditions and
then the gray zone between the bins takes into account the system variations. As a result the better the accuracy
of the MICBIAS output and pull-up resistor the better the accuracy of the key press detection.
In addition to the above, the contact resistance of the audio jack itself can play a role in how accurate the key
press detection is. A general rule is less contact resistance is better. In the figure below a more complete picture
of the system and the voltage the TS3A227E will detect is shown.
MICBIAS
R Audio
2.2 kΩ
RING2_SENSE
L Audio
32 Ω speakers
Key REQ
KP ADC
20-100 mohm
Jack contact
resistance
SLEEVE _SENSE
SLEEVE
Trace routing
resistance
The red line denotes the current path for the output of the codec to follow when it enters the speakers and
eventually sinks into the GNDFETs of the TS3A227E. This audio current adds a voltage offset at the audio jack
contact resistance, the trace routing resistance, and the GNDFET itself. Because the TS3A227E has kelvin
connections to the jack via the SLEEVE_SENSE RING2_SENSE pins the trace routing resistance and GNDFET
induced voltage offsets can be compensated.
However, the jack contact resistance is not visible by the device and cannot be compensated for. To maintain the
default bin targets the system must ensure that for a given audio jack contact resistance the max current being
output by the codec/amplifier lies below the curve in 图 34. This ensures a max error introduced of 5 mV into the
KP detection algorithm.
42
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
10.2.2.4.3 Key Press Grey Zones
When defining custom bins and thresholds it is important to also correctly define the “gray zone” between the
bins to ensure that the system will always correctly identify the key that is being pressed. The gray zone region
accounts for the absolute error in key press detection, encompasses the error of the internal ADC along with
errors from system tolerances and variation. The equation below can be used to determine the gray zone
required between each of the bins. Note that the size of the gray zone will vary depending on the actual value of
the key press threshold.
Gray Zone = ± [(Ɛ(ADC,GAIN) + ƐMICBIAS + ƐRBIAS + Ɛ(CONT,GAIN) ) × R(KP Threshold) + (Ɛ(ADC,OFF) + Ɛ(CONT,OFF) + KBUFF ) × 6 Ω] (4)
TERM
Ɛ(ADC,GAIN)
ƐMICBIAS
DESCRIPTION
VALUE
0.015%
0.025%(1)
UNIT
Internal ADC gain error
Codec MICBIAS output voltage variation. Default bin values assume an output variation of 2.5%.
MICBIAS resistor variation. Default bin values assume a 1% tolerance of the 2.2 kΩ MICBIAS
resistor.
ƐRBIAS
0.01%(1)
RContact ´IMAX
ƐCONT.GAIN
Gain error introduced by contact resistance of the audio jack.
VMICBIAS
KP threshold target identified by system. E.g. the KP Threshold between bins 1 and 2 for the
default key press bins is 96 Ω.
Defined by
system(1)
ƐKP Threshold
ƐADC,OFF
Ω
Internal ADC offset and linearity error
1.5
LSB
R
´I
MAX
Contact
ƐCONT,OFF
Offset error introduced by contact resistance of the audio jack.
LSB
LSB
VMICBIAS
128
Buffer constant added to total system gray zone to ensure bin values are detected correctly. It is
recommended to use a minimum of 2 for this when defining key gray zones to ensure system
level margins.
KBUFF
2
Defined by
system(1)
RContact
IMAX
Max contact resistance of audio jack
Ω
A
V
Defined by
system(1)
Maximum combined (Right and Left) audio output current into the jack.
MICBIAS output voltage of the codec
Defined by
system(1)
VMICBIAS
(1) These values can vary depending on the system
Example Calculation
The default KP Threshold 1 value for the TS3A227E is 10h or 96 Ω. Using the Gray Zone equation the specified
gray zone between keys 1 and 2 can be confirmed assuming the following:
•
•
•
•
VMICBIAS = 2.2 V
IMAX × RContact = 5 mV
R(KP Threshold) = 96 Ω
Default values for all other terms
é
ù
ú
ú
ú
æ
ç
ö
÷
ê
5mV
2.2
5mV
2.2
æ
ö
GrayZone = ± 0.015+ 0.025+ 0.01+
´96 W+ 1.5+
+2 ´ 6W
ê
ç
÷
ç
÷
è
ø
ê
ç
÷
ç
÷
ê
ú
128
è
ø
ë
û
(5)
This yields a gray zone of ± 27 Ω. The KP Threshold 1 gray zone can be used to identify the upper limit of key 1
and the lower limit of key 2:
Bin 1 upper limit = KP Threshold 1 – Gray Zone 1
Bin 2 lower limit = KP Threshold 1 + Gray Zone 1
This formula yields an upper limit of 69 Ω. Because each LSB is 6 Ω we round down to the even number of 66 Ω.
For the beginning of key 2 we set the value at (96 Ω + 27 Ω) or 126 Ω (123 Ω rounded up to the nearest LSB).
This method can be used to define the rest of the key bin thresholds.
版权 © 2014–2015, Texas Instruments Incorporated
43
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
10.2.2.4.4 Behavior
The TS3A227E can monitor the microphone line of a 4-pole headset to detect up to 4 key presses/releases and
report the key press events back to the host. The key press detection must be activated manually by setting the
KP Enable bit of the Device Settings 2 register. To ensure proper operation the MICBIAS voltage must be
applied to MICP before enabling key press detection.
MICBIAS
enabled
Enable
Insertion Event
4-pole inserted?
MICBIAS Stable ?
Key Press Detection
图 33. Proper Key Press Enable Sequence
The TS3A227E monitors the S3 switch matrix to determine the location of the microphone. If the Manual Switch
Control bit is set to ‘1’, the S3 matrix must be configured in one of the following 2 configurations for the key press
detection to operate. Other configurations are not supported with key press detection.
S3PR
On
S3PS
High-Z
On
S3GR S3GS
MIC LOCATION
RING2
High-Z
On
On
High-Z
High-Z
SLEEVE
If the voltage on the microphone line drops below the key press detection threshold for a duration longer than the
key press de-bounce time, the key press is considered to be valid. At this point the detected key has the
corresponding Key # Press interrupt bit set to ‘1’ and the interrupt is asserted. The corresponding Key # Release
interrupt is cleared at the same time the Key # Press interrupt is set.
Once the key is released for a duration longer than the key release de-bounce time, a Key Release interrupt is
generated to inform the host that the key has been released. The corresponding Key # released interrupt bit is
set to ‘1’ and the interrupt is asserted.
The Key Press interrupt register will clear the contents and return to the default status of 0h when Key Press
detection is disabled via an I2C write or a removal event.
Notes about key press detection:
•
The MICBIAS setting adjusts the detection threshold and must be set to the value that is closest to the
MICBIAS output of the codec. If the MICBIAS voltage being used is between different MICBIAS settings of
the TS3A227E then the closest value that is greater than the MICBIAS voltage should be used.
–
E.G. if the codec output is 2.2 V, the 2.3 V MICBIAS setting in the TS3A227E should be used.
•
If any pending interrupt is not read by the host and a key is pressed, the TS3A227E will continue to run key
press detection until the Key Press Enable bit is set to ‘0’
The host will interpret Key Press and Release interrupts using the following pseudo-code:
If (Key # Press && Key # Release) {
Key # was pressed one time and is not being held.
}
else if (Key # Release ) {
Key # is being pressed, start the key press duration timer
}
else if (Key # Release) {
Key # has been released, end the key press duration timer
}
The key press duration timer the host starts after reading that a key is pressed can be used as follows:
If (Key # Press Duration Timer > XXX ms) {
The Key # is being held down, handle accordingly.
E.g. if Key # is the volume up key, the system will increment the volume until the Key #
Release interrupt is read from the TS3A227E
}
10.2.2.4.5 Single Key Press Timing
The diagram below depicts a key press event where the MIC is on the SLEEVE pin. If the MIC is on RING2 the
timing diagram will be same.
44
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
Key Press
De-bounce
Key Release
De-bounce
SLEEVE Voltage
INT
Key 1 Press
Key 1 Release
(B)
(D) (E) (F)
(A)
(C)
A. At this point the SLEEVE voltage has stopped glitching and the Key Press De-bounce timer will no longer restart.
B. Point B is the end of the key press de-bounce period. INT will be asserted with the Key Press bit set.
C. The host read and clears the interrupt register, de-asserting the INT pin.
D. Here the key is released and the key release de-bounce period begins.
E. The key release de-bounce period ends and the INT pin is asserted again with the Key Release bit set.
F. Here the host reads and clears the interrupt register, de-asserting the INT pin.
10.2.2.4.6 Multiple Key Press Timing
The diagram below depicts a multiple key press event in which the host does not immediately read the interrupt
register. The MIC is on the SLEEVE pin in this diagram. If the MIC is on RING2 the timing diagram will be the
same.
注
If the KP Enable bit is set to ‘0’ during key press detection, key press detection will stop
immediately and all the key press/release bits will be cleared.
版权 © 2014–2015, Texas Instruments Incorporated
45
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
Key Press
De-bounce
Key Press
De-bounce
Key Press
De-bounce
Host I2C Read
Key Release
De-bounce
Key Release
De-bounce
Key 1 Pressed
Key 2 Pressed
Key 1 Pressed
Sleeve Voltage
INT
Key 1 Press
Key 1 Release
Key 2 Press
Key 2 Release
Key 3 Press
Key 3 Release
Key 4 Press
Key 4 Release
(A) (B) (C) (D)
(E) (F) (G) (H)
(I) (J) (K)
A. The SLEEVE voltage drops below the Key Press Detection threshold and the Key Press De-bounce timer is started
B. The end of the key press de-bounce timer. Key 1 is detected, the Key 1 Press interrupt is set and the interrupt line is
asserted. The Key 1 Release interrupt is cleared.
C. The SLEEVE voltage rises to MICBIAS as the key is released. The Key Release de-bounce timer is started.
D. The Key Release de-bounce timer expires. The Key 1 Release bit is set and the interrupt is asserted.
E. The SLEEVE voltage drops below the Key Press Detection threshold and the Key Press De-bounce timer is started
F. The end of the key press de-bounce timer. Key 2 is detected, the Key 2 Press interrupt is set and the interrupt line is
asserted. The Key 2 Release interrupt is cleared.
G. The SLEEVE voltage rises to MICBIAS as the key is released. The Key Release de-bounce timer is started.
H. The Key Release de-bounce timer expires. The Key 2 Release bit is set and the interrupt is asserted.
I.
The SLEEVE voltage drops below the Key Press Detection threshold and the Key Press De-bounce timer is started
J. The end of the key press de-bounce timer. Key 1 is detected, the Key 1 Press interrupt is set and the interrupt line is
asserted. The Key 1 Release interrupt is cleared.
K. The host reads the I2C interrupt register and sees the following interrupts:
mmm● Key 1 Press
mmm● Key 2 Press
mmm● Key 2 Release
Using the pseudo-code in the key press detection section this is interpreted as:
mmm● Key 2 was pressed one time and is not being held
mmm● Key 1 is currently pressed, start the key press duration timer
46
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
10.2.2.4.7 Raw Data Key Press Detection
In addition to threshold adjustment the TS3A227E features the ability to utilize the internal ADC raw output with
the Raw Data En bit of the Device Setting 2 register.
Notes on using the Raw ADC Output:
•
Key Press/Release interrupts that have not been serviced will not be cleared upon setting the Raw Data En
bit to ‘1’.
•
By Setting the Raw Data En bit to ‘1’ the Key Press Threshold registers will be ignored. Instead of reporting
key 1 through 4 press and releases the TS3A227E will only use Key 1 Press to indicate that a key is pressed
and the Key 1 Release interrupt to report that the key was released.
•
The ADC Output register will only be cleared after the Raw Data En bit is cleared. The Raw Data En bit is
cleared if the Key Press Enable bit is set to ‘0’. Consequently the ADC Output register clears if the Raw Data
En bit is set to ‘0’, the Key Press Enable bit is set to ‘0’, or a removal event occurs. This means the ADC
Output register will not clear after it is read.
•
•
A manual software trigger can be initiated after a key was pressed to run the ADC detection again. This will
not set the Key 1 Press interrupt.
The ADC Output is updated after a Key is detected or if the manual ADC trigger bit is set to ‘1’. If an ADC
conversion has completed the ADC Conversion interrupt bit will be set to ‘1’ regardless if there was a
software initiated trigger or if a new key press was detected.
•
If the ADC has completed a conversion the output is always non 0 meaning the lowest possible detection
threshold of the ADC is 01h. If the ADC Output register is 00h a conversion has not been completed or the
ADC Output was cleared.
The previous section on gray zones should be applied to any bins create for the raw ADC mode.
10.2.3 Application Curves
300
250
200
150
100
50
0
20
30
40
50
60
70
80
90
100
Contact Resistance (m:)
D001
图 34. Max Current vs Contact Resistance
11 Power Supply Recommendations
The TS3A227E is designed to operate from an input voltage supply range between 2.5 V and 4.5 V. This input
supply is recommended to be decoupled to ground via two de-coupling capacitors of 0.1µF and 1µF placed as
close as possible to the TS3A227E. To ensure a POR trip during a power-down and power-on event the power
supply should follow the minimum and maximum VDD rise and fall times specified in the electrical specifications
section.
The TS3A227E features the ability to power the digital IO pins at a different rail than the supply. This allows
systems to run the TS3A227E at 3.3 V and still use a 1.8 V eliminating the need for a translator. Have the 1.8 V
rail while the device is powered from a higher voltage will increase the current consumption of the device due to
CMOS shoot through current. This increased supply current is documented in the electrical specifications table.
版权 © 2014–2015, Texas Instruments Incorporated
47
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
•
•
•
The VDD pin must have de-coupling capacitors places as closely to the device as possible. Typically
recommended capacitors are a 0.1 µF and 1 µF capacitor.
If FM support is not needed connect GNDA to system GND along with the GND connections with the shortest
connections possible.
RING2 and SLEEVE should be routed on the same layer as the audio jack for best performance with less
than 50 mΩ to the audio jack pins. These two pins should have priority in layout over other pins. It is
recommended to not use vias on these traces and pair the device with an audio jack that facilitates this type
of layout.
•
The RING2_SENSE and SLEEVE_SENSE pins are kelvin connections to the audio jack and should be
shorted to RING2 and SLEEVE as close to the audio jack as possible. If there are 0 Ω resistors between the
SLEEVE/RING2 pins and the jack, connect the SENSE lines to the jack sleeve and ring2 contacts. If a
microphone is connected one of the SENSE lines will carry the microphone signal and the MICBIAS supply. It
is recommended that these traces not have more than 1 Ω impedance to the jack.
•
Route the I2C and digital signals away from the audio signals to prevent coupling onto the audio lines.
12.2 Layout Example (QFN)
VIA to Power Ground Plane
VIA to Bottom Copper or internal layer
Top Layer Routing
Bottom Layer Routing
Board Edge
SLEEVE
RING2
MIC_PRESENT
INT
16
15
14
13
TIP
RING1
GND
1
2
3
4
12
RING2
GND
SDA
11
10
9
GNDA
3.5 mm Jack
DET
SCL
VDD
5
6
7
8
Analog
Ground
to codec
图 35. QFN Layout Example
48
版权 © 2014–2015, Texas Instruments Incorporated
TS3A227E
www.ti.com.cn
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
12.3 Layout Example (DSBGA)
WCSP PAD
VIA to Power Ground Plane
VIA to Bottom Copper or internal layer
Top Layer Routing
Bottom Layer Routing
Board Edge
3.5 mm Jack
/DET_
TRIGGER
SLEEVE
RING2
/MIC_
PRESENT
RING1
TIP
Analog Ground
DET
图 36. DSBGA Layout Example
版权 © 2014–2015, Texas Instruments Incorporated
49
TS3A227E
ZHCSD70B –NOVEMBER 2014–REVISED FEBRUARY 2015
www.ti.com.cn
13 器件和文档支持
13.1 商标
All trademarks are the property of their respective owners.
13.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
50
版权 © 2014–2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TS3A227ERVAR
TS3A227EYFFR
ACTIVE
ACTIVE
VQFN
RVA
YFF
16
16
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 85
-40 to 85
227
DSBGA
SNAGCU
227E
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS3A227ERVAR
TS3A227EYFFR
VQFN
RVA
YFF
16
16
3000
3000
330.0
180.0
12.4
8.4
3.75
1.94
3.75
1.94
1.15
0.69
8.0
4.0
12.0
8.0
Q2
Q1
DSBGA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TS3A227ERVAR
TS3A227EYFFR
VQFN
RVA
YFF
16
16
3000
3000
346.0
182.0
346.0
182.0
33.0
20.0
DSBGA
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0016
DSBGA - 0.625 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
0.05 C
0.30
0.12
BALL TYP
1.2 TYP
D
C
B
SYMM
1.2
D: Max = 1.786 mm, Min =1.726 mm
E: Max = 1.786 mm, Min =1.726 mm
TYP
0.4 TYP
A
1
2
3
4
0.3
0.2
16X
0.015
SYMM
C A B
0.4 TYP
4219386/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0016
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
16X ( 0.23)
(0.4) TYP
4
3
1
2
A
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219386/A 05/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0016
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
16X ( 0.25)
1
2
3
4
A
(0.4) TYP
B
SYMM
METAL
TYP
C
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219386/A 05/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明