TPSM82810 [TI]

采用 3mm x 4mm uSIL 封装、具有可调节频率和跟踪功能的 2.75V 至 6V、4A 降压模块;


型号：	TPSM82810
厂家：	TEXAS INSTRUMENTS
描述：	采用 3mm x 4mm uSIL 封装、具有可调节频率和跟踪功能的 2.75V 至 6V、4A 降压模块
文件：	总30页 (文件大小：2135K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPSM82810, TPSM82813

ZHCSKB4A –SEPTEMBER 2019 –REVISED DECEMBER 2020

具有集成电感器和频率同步功能的TPSM8281x 2.75V 至6V 输入4A 和3A 降压

MicroSiP™ 电源模块

1 特性

3 说明

• 输入电压范围：2.75V 至6V

• 输出电压范围：0.6V 至5.5V

• 可调和可同步开关频率为1.8MHz 至4MHz

• 展频时钟- 可选

• 可选强制PWM 或PFM/PWM 运行

• 输出电压精度为±1%（PWM 运行）

• 具有窗口比较器的电源正常输出

• 100% 占空比

TPSM8281x 是具有集成电感器、引脚对引脚兼容的

3A 和 4A 高效、易于使用的同步降压直流/直流电源模

块系列。它们基于固定频率峰值电流模式控制拓扑，用

于具有高功率密度和易用性要求的电信、测试和测量以

及医疗应用领域。低阻开关可在高温环境下支持高达

4A 的持续输出电流。用户可通过外部方式在 1.8MHz

至 4MHz 范围内调节开关频率，亦可在该频率范围内

将其同步至外部时钟。在 PWM/PFM 模式下，

TPSM8281x 会在轻负载情况下自动进入省电模式，从

而在整个负载范围内维持高效率。TPSM8281x 可在

PWM 模式下提供 1% 的输出电压精度，这有助于实现

具有高输出电压精度的电源设计。SS/TR 引脚可设置

启动时间或跟踪向外部源提供的输出电压。此特性可实

现不同电源轨的外部定序并限制启动期间的浪涌电流。

• 输出放电

• 精密使能输入可实现

– 用户定义的欠压锁定

– 准确排序

• 15µA 静态电流（典型值）

• 可调软启动或跟踪

器件信息

封装⁽¹⁾

2 应用

封装尺寸（标称值）

3mm x 4mm x 2.4mm

器件型号

• 光学模块、数据中心互连

• 信号测量、源生成、仪表

• 患者监护和诊断

TPSM82810

TPSM82813

µSiL

• 无线基础设施

• 加固型通信：传感器、成像和雷达

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

原理图

效率与输出电流间的关系；V_IN= 5V；

PFM；f_S= 1.8MHz；T_A= 25°C

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDN6

TPSM82810, TPSM82813

ZHCSKB4A –SEPTEMBER 2019 –REVISED DECEMBER 2020

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Table of Contents

9.4 Device Functional Modes..........................................12

10 Application and Implementation................................15

10.1 Application Information........................................... 15

10.2 Typical Application.................................................. 15

10.3 System Examples................................................... 20

11 Power Supply Recommendations..............................22

12 Layout...........................................................................22

12.1 Layout Guidelines................................................... 22

12.2 Layout Example...................................................... 22

13 Device and Documentation Support..........................24

13.1 Device Support....................................................... 24

13.2 Documentation Support.......................................... 24

13.3 接收文档更新通知................................................... 24

13.4 支持资源..................................................................24

13.5 Trademarks.............................................................24

13.6 静电放电警告.......................................................... 24

13.7 术语表..................................................................... 24

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................2

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings ....................................... 4

7.2 ESD Ratings .............................................................. 4

7.3 Recommended Operating Conditions ........................4

7.4 Thermal Information ...................................................4

7.5 Electrical Characteristics ............................................5

7.6 Typical Characteristics................................................7

8 Parameter Measurement Information............................8

8.1 Schematic................................................................... 8

9 Detailed Description........................................................9

9.1 Overview.....................................................................9

9.2 Functional Block Diagram...........................................9

9.3 Feature Description.....................................................9

Information.................................................................... 24

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (September 2019) to Revision A (December 2020)

Page

• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1

• 更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1

5 Device Comparison Table

DEVICE NUMBER

TPSM82810SIL

TPSM82810SSIL

TPSM82813SIL

TPSM82813SSIL

OUTPUT CURRENT

SPREAD SPECTRUM CLOCKING

4 A

3 A

OFF

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6 Pin Configuration and Functions

TOP VIEW

BOTTOM VIEW

GND

VIN

GND

VIN

GND

VIN

VOUT

VIN

图6-1. 14-pin μSiL Package (Top View)

表6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

This is the enable pin of the device. Connect to logic low to disable the device. Pull high to

enable the device. Do not leave this pin unconnected.

Voltage feedback input. Connect the output voltage resistor divider to this pin.

Ground pin

GND

6, 10, 13, 14

The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,

the device runs in forced PWM mode. Do not leave this pin unconnected. The MODE/SYNC

pin can also be used to synchronize the device to an external frequency. See 节10.3.2.

MODE/SYNC

COMP/FSET

Device compensation and frequency set input. A resistor from this pin to GND defines the

compensation of the control loop as well as the switching frequency if not externally

synchronized. The switching frequency is set to 2.25 MHz if the pin is tied to GND or VIN.

See 表9-1. Do not leave this pin unconnected.

Open-drain power-good output with window comparator. This pin is pulled to GND while

VOUT is outside the power-good threshold. It can be left open or tied to GND if not used. A

pullup resistor can be connected to any voltage not larger than VIN.

Soft-start/tracking pin. A capacitor connected from this pin to GND defines the output voltage

rise time. The pin can also be used as an input for tracking and sequencing - see 节10.3.1.

SS/TR

VOUT

VIN

Output voltage pin. This pin is internally connected to the integrated inductor.

Power supply input. Connect the input capacitor as close as possible between the VIN and

GND pins.

1, 11, 12

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating junction temperature range (unless otherwise noted) ⁽¹⁾

MIN

-0.3

MAX

6.5

UNIT

Pin voltage

I_{SINK_PG}

T_J

VIN, VOUT, EN, MODE/SYNC

PG, SS/TR, COMP/FSET

Sink current at PG pin

Operating junction temperature

Storage temperature

V_IN+0.3

°C

-40

125

T_stg

125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC

JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22- V C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN

2.75

0.6

NOM

MAX

UNIT

V_IN

Supply voltage range

V_OUT

C_OUT

C_IN

Output voltage range

5.5

470

Effective output capacitance⁽¹⁾

Effective input capacitance⁽¹⁾

µF

kΩ

°C

R_CF

T_J

4.5

-40

100

125

Operating junction temperature

(1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias

effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the

manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Please see Section 9.3.3 about the output

capacitance vs compensation setting and output voltage.

7.4 Thermal Information

TPSM8281x

THERMAL METRIC⁽¹⁾

µSiL (JEDEC 51-5)

UNIT

14 PINS

52.4

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

16.9

12.8

ψ_JT

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TPSM8281x

THERMAL METRIC⁽¹⁾

µSiL (JEDEC 51-5)

14 PINS

UNIT

Junction-to-board characterization parameter

16.9

°C/W

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report and Section 12.3 - Thermal Consideration.

7.5 Electrical Characteristics

Over operating junction temperature (T_J= -40 °C to +125 °C) and V_IN= 2.75 V to 6 V. Typical values at V_IN= 5 V and T_J= 25

°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

EN = high, I_OUT= 0 mA, Device

not switching

I_Q

Operating Quiescent Current

Shutdown Current

µA

I_SD

EN = 0 V

0.11

2.6

2.5

170

2.75

2.6

µA

Rising Input Voltage

Falling Input Voltage

2.5

V_UVLO

Undervoltage Lockout Threshold

2.25

Thermal Shutdown Temperature Rising Junction Temperature

Thermal Shutdown Hysteresis

T_SD

°C

CONTROL (EN, SS/TR, PG, MODE/SYNC)

High Level Input Voltage for

MODE/SYNC Pin

V_IH

1.1

Low Level Input Voltage for

MODE/SYNC Pin

V_IL

0.3

Frequency Range on MODE/

f_SYNC

1.8

40%

1.06

0.96

MHz

SYNC Pin for Synchronization

Duty Cycle of Synchronization

Signal at MODE/SYNC Pin

50%

1.1

60%

1.15

1.05

150

Input Threshold Voltage for EN

Rising EN

Falling EN

V_IH

V_IL

Input Threshold Voltage for EN

1.0

Input Leakage Current for EN,

MODE/SYNC Pins

I_LKG

EN, MODE/SYNC = V_INor GND

UVP Power Good Threshold

Rising (%V_FB

)

92%

87%

95%

90%

98%

93%

UVP Power Good Threshold

V_{TH_PG}

Falling (%V_FB

)

OVP Power Good Threshold

Rising (%V_FB

)

107%

104%

110%

107%

113%

111%

OVP Power Good Threshold

Power Good De-glitch Time

Falling (%V_FB

)

for a high level to low level

transition on power good

µs

V_{OL_PG}

I_{LKG_PG}

I_SS/TR

Power Good Output Low Voltage I_PG= 2 mA

0.07

0.3

100

2.8

Input Leakage Current for PG

V_PG= 5 V

µA

SS/TR Pin Source Current

Tracking Gain

2.1

2.5

V_FB/ V_SS/TR

Tracking Offset

FB pin with V_SS/TR= 0 V

POWER SWITCH

High-Side MOSFET ON-

Resistance

R_DS(ON)

V_IN≥5 V

mΩ

Low-Side MOSFET ON-

Resistance

R_DS(ON)

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7.5 Electrical Characteristics (continued)

Over operating junction temperature (T_J= -40 °C to +125 °C) and V_IN= 2.75 V to 6 V. Typical values at V_IN= 5 V and T_J= 25

°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

100% mode. Maximum value at

V_IN= 3.3 V, T_J= 85°C

R_DP

Dropout resistance

mΩ

High-Side MOSFET Current

Limit ⁽¹⁾

I_LIMH

TPSM82810; V_IN= 3 V to 6 V

4.8

3.9

5.6

6.55

5.25

High-Side MOSFET Current

Limit⁽¹⁾

I_LIMH

I_LIMNEG

f_S

TPSM82813; V_IN= 3 V to 6 V

MODE/SYNC = HIGH

4.5

-1.8

2.25

Negative Current Limit ⁽¹⁾

PWM Switching Frequency

Range

1.8

2.025

-19%

MHz

PWM Switching Frequency

with COMP/FSET tied to VIN or

GND

f_S

2.25

2.475

MHz

PWM Switching Frequency

Tolerance

using a resistor from COMP/

FSET to GND

18%

t_on,min

Minimum on-time

Minimum off-time

V_IN= 3.3 V

t_off,min

OUTPUT

594

600

606

612

V_IN≥V_OUT+ 1 V; PWM mode

V_IN≥V_OUT+ 1 V; PFM mode

V_FB

Feedback Voltage Accuracy

_OUT≥1.5 V; C_OUT,eff≥27 μF

1 V ≤V_OUT< 1.5 V; PFM mode

_OUT,eff≥47 μF

594

297

600

615

I_{LKG_FB}

V_FB

Input Leakage Current (FB pin)

V_FB= 0.6 V

Feedback Voltage Accuracy with

Voltage Tracking

V_IN≥V_OUT+ 1 V; PWM mode

V_SS/TR= 0.3 V

300

321

R_dis

Output Discharge Resistance

I_OUT= 0 mA, time from EN = high

to start switching; V_INapplied

already

t_delay

Start-up Delay Time

135

100

200

150

450

200

µs

I_OUT= 0 mA, time from first

switching pulse until 95% of

nominal output voltage

t_ramp

Ramp time; SS/TR Pin Open

(1) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And

Short Circuit Protection section).

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7.6 Typical Characteristics

图7-2. Shutdown Current

图7-1. Quiescent Current

图7-4. Dropout Resistance

图7-3. Oscillator Frequency vs Temperature

(COMP/FSET tied to VIN or GND)

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8 Parameter Measurement Information

8.1 Schematic

图8-1. Measurement Setup for TPSM8281x

表8-1. List of Components

DESCRIPTION

REFERENCE

MANUFACTURER ⁽¹⁾

C_IN

C_OUT

C_SS

R_CF

C_FF

R₁

TPSM82810 or TPSM82813

Texas Instruments

22 µF / X7T / 10 V; GRM21BD71A226ME44

3 x 22 µF / X7T / 10 V; GRM21BD71A226ME44

4.7 nF

Murata

Any

10 kΩ

10 pF

Any

Depending on VOUT

100 kΩ

Any

R₂

Any

R₃

Any

(1) See the Third-party Products Disclaimer.

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9 Detailed Description

9.1 Overview

The TPSM8281x synchronous switch mode DC/DC converter power modules are based on a fixed-frequency

peak current-mode control topology. The control loop is internally compensated. To optimize the bandwidth of the

control loop to the wide range of output capacitance that can be used with the TPSM8281x, one of three internal

compensation settings can be selected. See 节 9.3.3. The compensation setting is selected either by a resistor

from COMP/FSET to GND, or by the logic state of this pin. The regulation network achieves fast and stable

operation with small external components and low-ESR ceramic output capacitors.

The devices support fixed-frequency forced PWM operation with the MODE/SYNC pin tied to a logic high level.

When the MODE/SYNC pin is set to a logic low level, the device operates in power save mode (PFM) at low-

output currents and automatically transitions to fixed-frequency PWM mode at higher output currents. In PFM

mode, the switching frequency decreases linearly based on the load to sustain high efficiency down to very low

output currents. The device can be synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz

applied to the MODE/SYNC pin.

9.2 Functional Block Diagram

VOUT

VIN

470nH

Bias

Regulator

Gate Drive and Control

Rdis

Izero

Ipeak

MODE

Output

Discharge

GND

Oscillator

Device

Control

V_FB

SS/TR

COMP/FSET

Thermal

Shutdown

9.3 Feature Description

9.3.1 Precise Enable (EN)

The TPSM8281x starts operation when the rising EN threshold is exceeded. For proper operation, the EN pin

must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown. In this

mode, the internal high-side and low-side MOSFETs are turned off and the entire internal control circuitry is

switched off. The voltage applied at the EN pin of the TPSM8281x is compared to a fixed threshold of 1.1 V for a

rising voltage.

The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The

Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the

input of the EN pin. The Precise Enable input also allows you to drive the pin by a slowly changing voltage and

enables the use of an external RC network to achieve a precise power-up delay. See the Achieving a Clean

Start-up by Using a DC/DC Converter with a Precise Enable-pin Threshold Technical Brief for more details.

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9.3.2 Output Discharge

The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is

disabled and keep the output voltage close to 0 V when the device is off. The output discharge feature is only

active once the TPSM8281x has been enabled at least once since the supply voltage was applied. The

discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage lockout.

The minimum supply voltage required for the discharge function to remain active is typically 1 V.

9.3.3 COMP/FSET

This pin sets two different parameters independently:

• Internal compensation settings for the control loop (three settings available)

• The switching frequency in PWM mode from 1.8 MHz to 4 MHz

A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change

in compensation adapts the device to different values of output capacitance. The resistor must be placed close

to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting is set after

enabling the converter, so a change in the resistor during operation only has an effect on the switching frequency

but not on the compensation.

To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined switching

frequency and compensation. Do not leave the pin floating.

The switching frequency must be selected based on the maximum input voltage and the output voltage to meet

the specifications for the minimum on-time. Using V_IN= 5.5 V and V_OUT= 1.1 V as an example, the minimum

duty cycle given with Equation 1 is 0.2, which results in a maximum switching frequency of 2.67 MHz according

to Equation 2.

V_OUT

D_min

IN, max

(1)

f_{s, max}

t_{on, min}ìD_min

(2)

The compensation range has to be chosen based on the minimum effective capacitance used. The capacitance

can be increased from the minimum value as given in 表 9-1 up to the maximum of 470 µF in all of the three

compensation ranges. If the capacitance of an output changes during operation, for example, when load

switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for the

minimum capacitance on the output. With large output capacitance, the compensation must be done based on

that large capacitance to get the best load transient response. Compensating for large output capacitance but

placing less capacitance on the output can lead to instability.

The switching frequency for the different compensation setting is determined by the following equations.

For compensation (comp) setting 1:

18MHz ×kW

RCF(kW) =

fS(MHz)

(3)

For compensation (comp) setting 2:

60MHz ×kW

RCF(kW) =

fS(MHz)

(4)

For compensation (comp) setting 3:

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180MHz ×kW

RCF(kW) =

(MHz)

(5)

表9-1. Switching Frequency and Compensation

MINIMUM OUTPUT

CAPACITANCE FOR 1 V ≤

MINIMUM OUTPUT

CAPACITANCE

MINIMUM OUTPUT

CAPACITANCE

COMPENSATION

R_CF

SWITCHING FREQUENCY

FOR VOUT < 1 V

VOUT < 3.3 V

FOR VOUT ≥3.3 V

for smallest output

capacitance

(comp setting 1)

1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)

53 µF

100 µF

200 µF

53 µF

32 µF

60 µF

27 µF

50 µF

10 kΩ... 4.5 kΩ

33 kΩ... 15 kΩ

100 kΩ... 45 kΩ

tied to GND

according to Equation 3

for medium output

capacitance

(comp setting 2)

1.8 MHz (33 kΩ) ... 4 MHz (15 kΩ)

according to Equation 4

for large output

capacitance

(comp setting 3)

1.8 MHz (100 kΩ) ... 4 MHz (45 kΩ)

120 µF

32 µF

100 µF

27 µF

according to Equation 5

for smallest output

capacitance

(comp setting 1)

internally fixed 2.25 MHz

for large output

capacitance

tied to V_IN

200 µF

120 µF

100 µF

(comp setting 3)

Refer to 节 10.2.2.4 for further details on the output capacitance required depending on the output voltage. All

values are the effective value of capacitance.

A too high resistor value for R_CFis read as "tied to V_IN", and a value below the lowest range as "tied to GND".

The minimum output capacitance in 表9-1 is for capacitors close to the output of the device. If the capacitance is

distributed, a lower compensation setting can be required.

9.3.4 MODE/SYNC

When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current. The

MODE/SYNC pin forces PWM mode when set high. The pin also allows you to apply an external clock in a

frequency range from 1.8 MHz to 4 MHz for external synchronization. When an external clock is applied, the

device operates in PWM mode. As with the switching frequency selection, the specification for the minimum on-

time has to be observed when applying the external clock signal. When using external synchronization, it is

recommended to set the internal switching frequency as set by R_CFto a similar value as the externally applied

clock. This ensures that, if the external clock fails, the switching frequency stays in the same range and the

settling time to the internal clock is reduced. When there is no resistor from COMP/FSET to GND, but the pin is

pulled high or low, external synchronization is not possible. An internal PLL allows you to change from an

internal clock to external clock during operation. The synchronization to the external clock is done on the falling

edge of the applied clock to the rising edge of the internal SW pin. The MODE/SYNC pin can be changed during

operation.

9.3.5 Spread Spectrum Clocking (SSC) - TPSM8281xS

These devices offer spread spectrum clocking, where the switching frequency is randomly changed in PWM

mode when the internal clock is used. The frequency variation is typically between the nominal switching

frequency and up to 288 kHz above the nominal switching frequency. When the device is externally

synchronized, the TPSM8281xS follows the external clock and the internal spread spectrum block is turned off.

SSC is also disabled during soft start.

9.3.6 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the

MOSFETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the input

voltage goes below the falling threshold.

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9.3.7 Power-Good Output (PG)

The device has a power good output with window comparator. The PG pin goes high impedance once the FB pin

voltage is above 95% and less than 107% of the nominal voltage, and is driven low once the voltage falls below

typically 90% or higher than 110% of the nominal voltage. 表 9-2 shows the typical PG pin logic. The PG pin is

an open-drain output and is specified to sink up to 2 mA. The power good output requires a pullup resistor

connected to any voltage rail less than VIN. The PG signal can be used for sequencing of multiple rails by

connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND.

表9-2. Power Good Pin Logic

PG LOGIC STATUS

DEVICE STATE

HIGH IMPEDANCE

LOW

0.57 V ≤V_FB≤0.642 V

√

Enabled (EN = High)

V_FB< 0.54 V or V_FB> 0.66 V

√

Shutdown (EN = Low)

UVLO

2 V ≤V_IN< V_UVLO

T_J> T_JSD

Thermal Shutdown

√

Power Supply Removal

√

V_IN< 2 V

The PG pin has a 40-μs deglitch time on the falling edge.

9.3.8 Thermal Shutdown

The junction temperature (T_J) of the device is monitored by an internal temperature sensor. If T_Jexceeds 170°C

(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG

goes low. When T_Jdecreases below the hysteresis amount of typically 15°C, the converter resumes normal

operation, beginning with soft start. During PFM, the thermal shutdown is not active.

9.4 Device Functional Modes

9.4.1 Pulse Width Modulation (PWM) Operation

The TPSM8281x has two operating modes: Forced PWM mode and PFM/PWM mode.

With the MODE/SYNC pin set to high, the TPSM8281x operates with pulse width modulation in continuous

conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP/FSET pin to

GND or by an external clock signal applied to the MODE/SYNC pin.

9.4.2 Power Save Mode Operation (PFM/PWM)

When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as

the peak inductor current is above the PFM threshold of about 1.2 A. When the peak inductor current drops

below the PFM threshold, the device starts to skip switching pulses.

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In power save mode, the switching frequency decreases linearly with the load current to maintain high efficiency.

The linear behavior of the switching frequency in power save mode is shown in 图9-1.

图9-1. Switching frequency versus Output Current (V_IN= 5 V, V_OUT= 1.8 V)

9.4.3 100% Duty-Cycle Operation

The device offers a low input-to-output voltage differential by entering 100% duty cycle mode. When the

minimum off-time of typically 30 ns is reached, the TPSM8281x skips switching cycles while it approaches 100%

mode. In 100% mode, the high-side MOSFET switch is constantly turned on. This is particularly useful in battery-

powered applications to achieve longest operation time by taking full advantage of the whole battery voltage

range. The minimum input voltage to maintain a minimum output voltage is given by:

V_{IN (min)}= V_{OUT (min)}+ I_OUT× R_DP

(6)

where

• R_DPis the resistance from V_INto V_OUT, which includes the high-side MOSFET on-resistance and DC

resistance of the inductor

• V_{OUT (min)}is the minimum output voltage the load can accept

9.4.4 Current Limit and Short Circuit Protection

The TPSM8281x is protected against overload and short circuit events. If the inductor current exceeds the

current limit I_LIMH, the high-side MOSFET is turned off and the low-side MOSFET is turned on to ramp down the

inductor current. The high-side MOSFET turns on again only if the current in the low-side MOSFET has

decreased below the low-side current limit. Due to internal propagation delays, the actual current can exceed the

static current limit. The dynamic current limit is given as:

Ipeak(typ) = ILIMH

×tPD

(7)

where

• I_LIMHis the static current limit, as specified in the electrical characteristics

• L is the effective inductance (typically 470 nH)

• V_Lis the voltage across the inductor (V_IN- V_OUT

)

• t_PDis the internal propagation delay of typically 50 ns

The dynamic peak current is calculated as follows:

IN -VOUT

Ipeak(typ) = ILIMH

×50ns

(8)

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The low-side MOSFET also contains a negative current limit to prevent excessive current from flowing back

through the inductor to the input. If the low-side sinking current limit is exceeded, the low-side MOSFET is turned

off. In this scenario, both MOSFETs are off until the start of the next cycle. The negative current limit is only

active in Forced PWM mode.

9.4.5 Soft Start / Tracking (SS/TR)

The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush

current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high

impedance power sources or batteries. When EN is set high, the device starts switching after a delay of about

200 μs. Then V_OUTrises with a slope controlled by an external capacitor connected to the SS/TR pin.

A capacitor connected from SS/TR to GND is charged with 2.5 µA by an internal current source during soft start

until it reaches the reference voltage of 0.6 V. After reaching 0.6 V, the SS/TR pin voltage is clamped internally

while the SS/TR pin voltage keeps rising to a maximum of about 3.3 V. The capacitance required to set a certain

ramp-time (t_ramp) is:

(9)

Leaving the SS/TR pin un-connected provides the fastest start-up ramp of 150 µs typically. If the device is set to

shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS/TR pin to

GND to ensure a proper low level. Returning from those states causes a new start-up sequence.

A voltage applied at the SS/TR pin can also be used to track a master voltage. The output voltage follows this

voltage in both directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based

on the load current. An external voltage applied on SS/TR is internally clamped to the feedback voltage (0.6 V).

It is recommended to set the final value of the external voltage on SS/TR to be slightly above 0.6 V to make sure

the device operates with its internal reference voltage when the power-up sequencing is finished. See 节10.3.1.

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10 Application and Implementation

Note

以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

The TPSM8281x are synchronous step-down converter power modules. The required power inductor is

integrated inside the TPSM8281x. The inductor is shielded and has an inductance of 470 nH with approximately

a ±20% tolerance. The TPSM82810 and TPSM82813 are pin-to-pin and BOM-to-BOM compatible, differing only

in their rated output current.

10.2 Typical Application

图10-1. Typical Application Schematic

10.2.1 Design Requirements

The design guidelines provide a component selection to operate the device within the recommended operating

conditions.

10.2.2 Detailed Design Procedure

10.2.2.1 Programming the Output Voltage

The output voltage of the TPSM8281x is adjustable. Choose resistors R1 and R2 to set the output voltage within

a range of 0.6 V to 5.5 V according to Equation 10. To keep the feedback (FB) net robust from noise, set R2

equal to or lower than 100 kΩto have at least 6 µA of current in the voltage divider. Lower values of FB resistors

achieve better noise immunity, and lower light load efficiency, as explained in the Design Considerations for a

Resistive Feedback Divider in a DC/DC Converter Technical Brief.

≈

∆

’

V_OUT

V_FB

OUT

≈

’

R1= R2ì

-1 = R2ì

-1

∆

0.6V

◊

(10)

10.2.2.2 Feedforward capacitor

A feedforward capacitor (C_FF) is recommended in parallel with R₁in order to improve the transient response.

Regardless of the FB resistor values, the C_FFvalue should always be 10 pF.

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10.2.2.3 Input Capacitor

For most applications, a 22-µF nominal ceramic capacitor is recommended. The input capacitor buffers the input

voltage for transient events and also decouples the converter from the supply. A X7R or X7T multilayer ceramic

capacitor (MLCC) is recommended for best filtering and must be placed between VIN and GND as close as

possible to those pins. For applications with ambient temperatures below 85°C, a capacitor with X5R dielectric

can be used. Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective

capacitance. Choose the right capacitor carefully in combination with considering its package size and voltage

rating. The minimum required input capacitance is 5 µF.

10.2.2.4 Output Capacitor

The architecture of the TPSM8281x allows the use of ceramic output capacitors which have low equivalent

series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its

low resistance up to high frequencies and to get a narrow capacitance variation with temperature, it is

recommended to use an X7R or X7T dielectric. At temperatures below 85°C, an X5R dielectric can be used.

Using a higher capacitance value has advantages like smaller voltage ripple and a tighter DC output accuracy in

power save mode. By changing the device compensation with a resistor from COMP/FSET to GND, the device

can be compensated in three steps based on the minimum capacitance used on the output. The maximum

capacitance is 470 µF in any of the compensation settings. The minimum capacitance required on the output

depends on the compensation setting and output voltage as shown in 表 9-1. For output voltages below 1 V, the

minimum required capacitance increases linearly from 32 µF at 1 V to 53 µF at 0.6 V with the compensation

setting for smallest output capacitance. Other compensation settings scale the same. Ceramic capacitors have a

DC-Bias effect, which has a strong influence on the final effective capacitance. Choose the right capacitor

carefully in combination with considering its package size and voltage rating.

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10.2.2.5 Application Curves

T_A= 25°C, V_IN= 5 V, V_OUT= 1.8 V, 1.8 MHz, PWM mode, BOM = 表8-1 unless otherwise noted.

V_IN= 3.3 V

PFM

T_A= 25°C

V_IN= 3.3 V

PWM

T_A= 25°C

图10-2. Efficiency versus Output Current

图10-3. Efficiency versus Output Current

V_IN= 3.3 V

PFM

T_A= 85°C

V_IN= 3.3 V

PWM

T_A= 85°C

图10-4. Efficiency versus Output Current

图10-5. Efficiency versus Output Current

V_IN= 5 V

PFM

T_A= 25°C

V_IN= 5 V

PWM

T_A= 25°C

图10-6. Efficiency versus Output Current

图10-7. Efficiency versus Output Current

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V_IN= 5 V

PFM

T_A= 85°C

V_IN= 5 V

PWM

T_A= 85°C

图10-8. Efficiency versus Output Current

图10-9. Efficiency versus Output Current

V_OUT= 3.3 V

T_A= 25°C

V_OUT= 2.5 V

T_A= 25°C

图10-10. Output Voltage versus Output Current

图10-11. Output Voltage versus Output Current

V_OUT= 1.8 V

T_A= 25°C

V_OUT= 1.2 V

T_A= 25°C

图10-12. Output Voltage versus Output Current

图10-13. Output Voltage versus Output Current

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V_OUT= 1.8 V

V_IN= 5.0 V

PWM

T_A= 25°C

I_OUT= 0 A to 4 A to 0 A

V_OUT= 0.6 V

T_A= 25°C

图10-15. Load Transient Response

图10-14. Output Voltage versus Output Current

V_OUT= 1.8 V

V_IN= 5.0 V

PFM

T_A= 25°C

V_OUT= 1.8 V

I_OUT= 4 A

PWM

T_A= 25 °C

I_OUT= 0 A to 4 A to 0 A

V_IN= 5.0 V

BW = 20 MHz

图10-16. Load Transient Response

图10-17. Output and Input Voltage Ripple

V_OUT= 1.8 V

I_OUT= 0 A

PFM

T_A= 25°C

V_OUT= 1.8 V

I_OUT= 4 A

PWM

T_A= 25°C

V_IN= 5.0 V

BW = 20 MHz

V_IN= 5 V

C_SS= 4.7 nF

图10-18. Output and Input Voltage Ripple

图10-19. Start-Up Timing

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V_OUT= 1.8 V

I_OUT= 0 A

PFM

T_A= 25°C

V_IN= 5 V

C_SS= 4.7 nF

图10-20. Start-Up Timing

10.3 System Examples

10.3.1 Voltage Tracking

The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application

circuit is shown in Figure 10-21. From 0 V to 0.6 V, the internal reference voltage to the internal error amplifier

follows the SS/TR pin voltage. When the SS/TR pin voltage is above 0.6 V, the voltage tracking is disabled and

the FB pin voltage is regulated at 0.6 V. The device achieves ratiometric or coincidental (simultaneous) output

tracking, as shown in Figure 10-22.

The R2 value should be set properly to achieve accurate voltage tracking by taking the 2.5-μA charging current

into account. 1 kΩor smaller is a sufficient value for R2. For decreasing SS/TR pin voltage, the device does not

sink current from the output when the device is in PFM mode. The resulting decrease of the output voltage can

be slower than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do

not exceed the voltage rating of the SS/TR pin which is VIN+0.3 V.

V_out1

V_out2

TPSM8281x

SS/TR FB

图10-21. Schematic for Output Voltage Tracking

图10-22. Output Voltage Tracking

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10.3.2 Synchronizing to an External Clock

The TPSM8281x can be synchronized by applying a clock on the MODE/SYNC pin. There is no need for any

additional circuitry. See Figure 10-23. The clock can be applied, changed, and removed during operation. The

value of the R_CFresistor is recommended to be chosen such that the internally defined frequency and the

externally-applied frequency are close to each other in order to have a fast settling time to the external clock.

Synchronizing to a clock is not possible, if the COMP/FSET pin is connected to Vin or GND. Figure 10-24 and

Figure 10-25 show the external clock being applied and removed. When an external clock is applied, the device

operates in PWM mode.

图10-23. Frequency Synchronization

V_IN= 5 V

I_OUT= 0.1 A

V_IN= 5 V

I_OUT= 1 A

R_CF= 8.06 kΩ

V_OUT= 1.8 V

f_EXT= 2.5 MHz

V_OUT= 1.8 V

f_EXT= 2.5 MHz

图10-24. Applying and Removing the

图10-25. Applying and Removing the

Synchronization Signal (PFM)

Synchronization Signal (FPWM)

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11 Power Supply Recommendations

The TPSM8281x device family has no special requirements for its input power supply. The output current of the

input power supply needs to be rated according to the supply voltage, output voltage, and output current of the

TPSM8281x.

12 Layout

12.1 Layout Guidelines

A proper layout is critical for the operation of any switched mode power supply, especially at high switching

frequencies. Therefore, the PCB layout of the TPSM8281x demands careful attention to ensure best

performance. A poor layout can lead to issues like bad line and load regulation, instability, increased EMI

radiation, and noise sensitivity. Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter

Technical Brief for a detailed discussion of general best practices. Specific recommendations for the device are

listed below.

• The input capacitor should be placed as close as possible to the VIN and GND pins of the device. This is the

most critical component placement. Route the input capacitor directly to the VIN and GND pins avoiding vias.

• Place the output capacitor ground close to the VOUT and GND pins and route it directly avoiding vias.

• Place the FB resistors, R1 and R2, and the feedforward capacitor C_FFclose to the FB pin and place C_SS

close to the SS/TR pin to minimize noise pickup.

• Place the R_CFresistor close to the COMP/FSET pin to minimize the parasitic capacitance.

• The recommended layout is implemented on the EVM and shown in its TPSM82810EVM-089 Evaluation

Module User's Guide and in Section 12.2.

• The recommended land pattern for the TPSM8281x is shown at the end of this data sheet. For best

manufacturing results, it is important to create the pads as solder mask defined (SMD), when some pins

(such as VIN, VOUT, and GND) are connected to large copper planes. Using SMD pads keeps each pad the

same size and avoids solder pulling the device during reflow.

12.2 Layout Example

VOUT

VIN

CFF

GND

图12-1. Example Layout

12.2.1 Thermal Consideration

The TPSM8281x module temperature must be kept less than the maximum rating of 125°C. The following are

three basic approaches for enhancing thermal performance:

• Improve the power dissipation capability of the PCB design.

• Improve the thermal coupling of the component to the PCB.

• Introduce airflow into the system.

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To estimate the approximate module temperature of the TPSM8281x, apply the typical efficiency stated in this

data sheet to the desired application condition to compute the power dissipation of the module. Then, calculate

the module temperature rise by multiplying the power dissipation by its thermal resistance. For more details on

how to use the thermal parameters in real applications, see the application notes: Thermal Characteristics of

Linear and Logic Packages Using JEDEC PCB Designs and Semiconductor and IC Package Thermal Metrics.

The thermal values in 节7.4 used the recommended land pattern, shown at the end of this data sheet, including

the 18 vias as they are shown. The TPSM8281x was simulated on a PCB defined by JEDEC 51-7. The 9 vias on

the GND pins were connected to copper on other PCB layers, while the remaining 9 vias were not connected to

other layers.

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13 Device and Documentation Support

13.1 Device Support

13.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, TPSM82810EVM-089 Evaluation Module

13.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

13.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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17-Mar-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPSM82810SILR

TPSM82810SSILR

TPSM82813SILR

TPSM82813SSILR

ACTIVE

uSiP

SIL

3000 RoHS & Green

ENEPIG

Level-2-260C-1 YEAR

-40 to 125

Samples

ENEPIG

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Mar-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

SIL0014B

uSIP^TM- 2.4 mm max height

MICRO SYSTEM IN PACKAGE

3.1

2.9

PIN 1 INDEX

AREA

(3.2)

4.1

3.9

PICK AREA

NOTE 3

(2.5)

2.4 MAX

0.08 C

4X 0.3 0.03

2X 1.75

1.19

1.11

10X (0.05)

4X (0.075)

0.54

0.46

2X 3.1

SYMM

4X 0.8 0.03

2X 1.3

2X 1.15

4X 0.65

0.28

0.22

0.1

C A B

PIN 1 ID

(OPTIONAL)

0.05

SYMM

2.4

0.79

0.71

2X 0.9

0.1

C A B

0.05

4225112/E 11/2020

MicroSiP is a trademark of Texas Instruments

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Pick and place nozzle 1.3 mm or smaller recommended.

4. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

SIL0014B

uSIP - 2.4 mm max height

MICRO SYSTEM IN PACKAGE

2X (2)

(0.3)

METAL UNDER

SOLDER MASK

TYP

COPPER KEEP-OUT AREA

(0.05) TYP

SOLDER MASK

OPENING

TYP

4X (1.925)

4X (1.425)

6X (0.75)

4X (0.45)

(3.25)

2X (3.35)

6X (0.25)

4X (0.575)

0.000 PKG

4X (0.65)

4X (0.8)

(R0.05) TYP

4X (1.425)

4X (1)

4X (1.925)

SEE DETAILS

4X (1.4)

(0.3)

4X (0.3)

(2.65)

(

0.2) TYP

VIA

LAND PATTERN EXAMPLE

SCALE:15X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

PADS 1, 5, 6, 10 AND 11 - 14

SOLDER MASK DETAILS

NOT TO SCALE

4225112/E 11/2020

NOTES: (continued)

5. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

SIL0014B

uSIP - 2.4 mm max height

MICRO SYSTEM IN PACKAGE

2X (2)

4X (0.45)

(R0.1) TYP

SYMM

6X (0.75)

6X (0.25)

4X (0.575)

2X (3.35)

SYMM

6X (0.65)

4X (0.8)

4X (1)

4X (1.4)

4X (0.3)

(2.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:25X

4225112/E 11/2020

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPSM82810 [TI]

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