TPSM5D1806E [TI]
工作温度为 -55°C 的 4.5V 至 15V 输入、双路 6A/单路 12A 输出电源模块;
| 型号： | TPSM5D1806E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 工作温度为 -55°C 的 4.5V 至 15V 输入、双路 6A/单路 12A 输出电源模块 电源电路 |
| 文件： | 总37页 (文件大小：1947K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPSM5D1806E
ZHCSP41 –JANUARY 2022
TPSM5D1806E 工作温度范围为–55°C 至+125°C 的4.5V 至15V 输入、双路6A/
单路12A 输出电源模块
1 特性
3 说明
• 独立双路6A 输出
• 并行单路12A 输出
• 输出电压范围：0.5V 至5.5V
• 0.5V，温度范围内的电压基准精度为±1.25%
• 具有相位延迟的频率同步
• 针对每个输出的独立使能和电源正常指示功能
• 启动至预偏置输出
TPSM5D1806E 双路6A 输出电源模块是一款灵活的高
度集成直流/直流电源，采用紧凑型 8mm × 5.5mm ×
1.8mm QFN 封装。输入电压范围为 4.5 V 至15 V，因
此可对宽电压范围的中间总线以及标准 5V 和 12V 电
压轨进行电压转换。两个 6A 输出可以针对两个单独的
电源轨分别配置，也可以合并为一个两相12A 输出。
具有出色封装布局的低厚度 51 引脚 QFN 封装可提高
热性能。–55°C 的增强温度性能可实现外部机舱安装
模块或飞行控制单元等环境中的航天应用。该封装的所
有信号引脚均分布在外围，器件下方有一些大型散热焊
盘，可在制造过程中实现简单布局和轻松处理。
• UV 和OV 电源正常输出
• 可选开关频率选项：
500kHz、1.0MHz、1.5MHz 和2.0MHz
• 符合EN55011 辐射EMI 限值
• 工作结温范围：–55°C 至+125°C
• 工作环境温度范围：-55°C 至+105°C
• 8mm × 5.5mm × 1.8mm 标准QFN 封装
• 使用TPSM5D1806E 并借助WEBENCH® Power
Designer 创建定制设计方案
集成的电源设计省去了设计流程中的环路补偿和磁性元
件选型。该器件可为每路输出提供独立的使能控制和电
源正常信号。开关频率和相位偏移可以使用引脚束带进
行配置。该器件还提供了过流和热关断保护。
器件信息
封装(1)
2 应用
封装尺寸（标称值）
器件型号
• 支持航天和国防
• 医疗成像
• 加固型通信
TPSM5D1806E
QFN
8mm × 5.5mm × 1.8mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 航电设备和飞机控制
VIN
PG1
VIN
VOUT1
VOUT1
CIN
RFBT1
COUT1
PGND
FB1
RFBB1
TPSM5D1806E
PG2/CLKO
EN1
VOUT2
VOUT2
EN2/Ishare
SYNC
RFBT2
COUT2
FB2/Vshare
MODE2
SS
RFBB2
AGND
MODE1
10 k
输出配置
RM2
RM2
双路输出简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEP8
TPSM5D1806E
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Table of Contents
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application (Dual Outputs)............................22
9 Power Supply Recommendations................................27
10 Layout...........................................................................28
10.1 Layout Guidelines................................................... 28
10.2 Layout Examples.................................................... 28
11 Device and Documentation Support..........................31
11.1 Device Support........................................................31
11.2 接收文档更新通知................................................... 31
11.3 支持资源..................................................................31
11.4 Trademarks............................................................. 31
11.5 Electrostatic Discharge Caution..............................31
11.6 术语表..................................................................... 31
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics (VIN = 12 V)............................8
6.7 Typical Characteristics (VIN = 5 V)............................10
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................13
Information.................................................................... 32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
January 2022
*
Initial release
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5 Pin Configuration and Functions
EN1
PGOOD2/CLKO
PGOOD1
VIN
1
2
3
4
5
6
7
8
9
38 MODE2
37 MODE1
36 SYNC
35 VIN
47
PGND
VIN
34 VIN
48
PGND
VIN
33 VIN
DNC
32 DNC
49
PGND
DNC
31 DNC
SW2
30 SW1
50
PGND
PGND 10
PGND 11
PGND 12
VOUT2 13
VOUT2 14
VOUT2 15
29 PGND
28 PGND
27 PGND
26 VOUT1
25 VOUT1
24 VOUT1
51
PGND
图5-1. 51-Pin RDB QFN Package (Top View)
表5-1. Pin Functions
Pin
Type(1)
Description
Name
No.
Analog ground for the internal analog control circuit. Connect to PGND at one single point, away
from noisy circuitry.
AGND
42, 43
G
O
Output of the internal 5-V regulator. Bypass this pin with a minimum of 1.5 µF of effective
capacitance to AGND. Can be used as a pullup voltage for PGOOD signals.
BP5
DNC
EN1
44
7, 8, 31, 32
1
Do not connect. Do not connect these pins to AGND, PGND, to another DNC pin, or to any
other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an
isolated pad.
—
Channel 1 enable input. Float or pull high to enable. Can also be used to externally adjust EN
UVLO by connecting a resistor divider between VIN and AGND.
I
Multi-function pin
Dual output configuration: Channel 2 enable input. Float or pull high to enable. Can also be used
to externally adjust EN UVLO by connecting resistor divider between VIN and AGND.
Parallel output configuration: Current balance node of the internal regulators. Leave this pin
open.
EN2/ISHARE
FB1
46
40
I/O
I
Channel 1 feedback input. Connect to the output voltage of channel 1 with a resistor divider.
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表5-1. Pin Functions (continued)
Pin
Type(1)
Description
Name
No.
Multi-function pin
Dual output configuration: Channel 2 Feedback input. Connect to the output voltage of channel
2 with a resistor divider.
FB2/VSHARE
45
I/O
Parallel output configuration: The COMP voltage of the internal regulators. Leave this pin open.
Mode setting pin. Programs channel configuration as either dual or parallel outputs and
programs channel interleaving using a resistor between the MODE1 pin and AGND. A 10-kΩ
resistor is required between the MODE1 pin and MODE2 pin.
MODE1
MODE2
37
38
I
I
Mode setting pin. Select from four pre-set switching frequencies using a resistor between the
MODE2 pin and AGND. A 10-kΩresistor is required between MODE1 pin and MODE2 pin.
Power ground of the device. This is the return current path for the power stage of the device.
Connect these pins to the bypass capacitors associated with VIN and VOUT. Connect pads 47,
48, 49, 50, and 51 to the PCB ground planes using multiple vias for optimal thermal
performance. All pins must be connected together externally with a copper plane or pour directly
under the device.
10–12,
27–29,
47–51
PGND
G
O
O
Channel 1 power-good indicator output. This pin is an open-drain output, which asserts low
during any fault condition. When used, a pullup resistor to BP5 or other external supply is
required. Leave this pin open if unused.
PGOOD1
3
2
Multi-function pin
Dual output configuration: Channel 2 power-good indicator output. This pin is an open-drain
output, which asserts low during any fault condition. When used, a pullup resistor to BP5 or
another external supply is required. Leave this pin open if unused.
Parallel output configuration: 180° clock output. Leave this pin open if unused.
PGOOD2/CLKO
For parallel output applications, this pin functions as remote sense negative input to the
differential amplifier. Connect this pin to the point of ground regulation using a kelvin trace. For
dual output configurations, this pin must be tied to AGND.
41
39
G
I
RS–
External soft start when configured for parallel output operation. Place a capacitor from SS to
AGND to set output voltage rise time. For independent dual channel configurations, leave this
pin open.
SS
SW1
SW2
SYNC
30
9
O
O
I
Channel 1 power stage switch node. Can be used to monitor the switch node.
Channel 2 power stage switch node. Can be used to monitor the switch node.
This pin synchronizes to external clock or the CLKO pin of another device.
36
Power conversion input pins. Pins 4, 5, and 6 are not internally connected to pins 33, 34, and
35. Connection must be made using the PCB VIN plane. Bypass VIN pins with ceramic
capacitance to PGND, close to the device.
4–6, 33–
VIN
I
35
Channel 1 output voltage. These pins are connected to the internal output inductor. Connect to
the output load. Place external bypass capacitors between these pins and PGND.
VOUT1
VOUT2
O
O
20–26
13–19
Channel 2 output voltage. These pins are connected to the internal output inductor. Connect to
the output load. Place external bypass capacitors between these pins and PGND.
(1) G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VIN
16
–0.3
BP5, EN1, EN2/ISHARE, FB1, FB2/VSHARE, MODE1, MODE2,
PGOOD1, PGOOD2/CLKO, SS, SYNC
Input voltage
6
V
–0.3
0.3
6
RS–, PGND to AGND
–0.3
–0.3
–0.3
–3
VOUT1, VOUT2
Output voltage
SW1, SW2
16
V
SW1, SW2 transient (10ns)
18
TJ
Operating IC junction temperature
Storage temperature
125
125
260
3
°C
°C
°C
–55
–55
Tstg
Peak reflow case temperature
Maximum number or reflows allowed
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
Mechanical shock
500
20
G
G
Mechanical vibration
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
4.5(2)
0.5
NOM
MAX
15
UNIT
V
VIN
Input voltage
VOUT
IOUT
VEN
Output voltage
5.5
6
V
Output current per channel, continuous
EN voltage
A
0
5.5
5.5
125
V
VPGOOD
TA
PGOOD pull-up voltage
Operating ambient temperature
V
°C
–55
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure
specific performance limits. For ensured specifications, see the Electrical Characteristics table.
(2) See the Minimum Input Voltage section for the recommended minimum input voltage at higher output voltages.
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UNIT
6.4 Thermal Information
TPSM5D1806
THERMAL METRIC(1)
RDB (QFN)
51 PINS
13.9
RθJA
ΨJT
Junction-to-ambient thermal resistance (2)
Junction-to-top characterization parameter (3)
Junction-to-board characterization parameter (4)
Thermal Shutdown Temperature
°C/W
°C/W
°C/W
°C
1.8
9.4
ΨJB
TSHDN
TSHDN
165
Thermal Shutdown Hysteresis
20
°C
(1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 100 mm × 100 mm, 6-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow reduces RθJA
.
(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB
is the temperature of the board 1 mm from the device.
6.5 Electrical Characteristics
Limits apply over TA = –55°C to +125°C, VIN = 12 V (unless otherwise noted); Minimum and maximum limits are specified
through production test or by design. Typical values represent the most likely parametric norm and are provided for reference
only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT VOLTAGE (VIN)
VIN
Operating input voltage range
VIN turn on
4.5(1)
3.5
15
V
V
VIN increasing
3.7
3.9
UVLO
Hysteresis
200
mV
Non-switching, VFB1, VFB2 > 0.5 V, TA = 25°C, EN1 = EN2 =
5 V
IQ
Quiescent current
4
mA
µA
ISHDN
Shutdown supply current
TA = 25°C, EN1 = EN2 = 0 V
270
INTERNAL LDO (BP5)
BP5
Regulation voltage
4.8
5.0
0.5
5.2
V
V
6 V ≤VIN ≤15 V, ILOAD = 70 mA
FEEDBACK
Feedback voltage
Temperature accuracy
Load regulation
TJ = 25°C
+1.25%
TJ = –55°C to 125°C
–1.25%
V(FB1), V(FB2)
TA = +25°C, over IOUT range
TA = +25°C, IOUT = 0 A, over VIN range
0.2%
0.1%
Line regulation
OUTPUT CURRENT
Output current
Per channel
0
6(2)
A
A
A
IOUT
Overcurrent threshold source current DC current
6.6
-2.8
15%
1
Overcurrent threshold sink current
DC current
OUT ≥3 A per channel
I
ISH(acc)
Output current sharing accuracy
IOUT < 3 A per channel
Wait time to attempt re-start
Cycles before hiccup
A
OCP hiccup wait time
OCP hiccup entry time
7
ms
16
cycles
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6.5 Electrical Characteristics (continued)
Limits apply over TA = –55°C to +125°C, VIN = 12 V (unless otherwise noted); Minimum and maximum limits are specified
through production test or by design. Typical values represent the most likely parametric norm and are provided for reference
only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SOFT START
tSS
Default soft-start time
Time from switching to PGOOD high without CSS
1
2
ms
µA
Ω
ISS
Soft-start charge current
Soft-start discharge resistance
TSS ≤50 ms, CSS < 0.3 µF
Rss
600
ENABLE (EN)
EN rising
EN falling
1.2
1.1
100
1.4
0.3
1.3
V
V
Enable threshold voltage
VEN
1
Hysteresis on Enable
mV
µA
ms
Enable pullup current
EN floating
Enable to start switching time
VIN ≥4.5 V, toggle EN
SWITCH NODE (SW)
SW1, SW2 Discharge FET
32
40
Ω
SW1, SW2 minimum on time
SW1, SW2 minimum off time
50
ns
ns
150
200
SWITCHING FREQUENCY
Fsw1
450
900
500
1000
1500
2000
550 kHz
1100 kHz
1650 kHz
2200 kHz
MODE2 resistor = 10.7 kΩ
MODE2 resistor = 17.4 kΩ
MODE2 resistor = 28.7 kΩ
MODE2 resistor = 53.6 kΩ
Fsw2
Fsw3
Fsw4
1350
1800
SYNCHRONIZATION (SYNC)
VIH(SYNC)
VIL(sync)
High-level input
Low-level input
Input duty cycle
2
V
0.6
V
20%
80%
Sync frequency versus internal
oscillator setting
-20%
+20%
CLOCK OUTPUT (CLKO)
VOH(CLKO) High-level output
VOL(CLKO)
IO = 20 µA
IO = 20 µA
2.2
V
V
Low-level output
0.4
Pulse width output
80
ns
POWER GOOD WARNING (PGOOD1, PGOOD2)
VFB1, VFB2 falling (warning)
VFB1, VFB2 rising (good)
VFB1, VFB2 falling (good)
VFB1, VFB2 rising (warning)
VPGOOD = 5.5 V
87%
90%
90%
93%
93%
96%
110%
113%
1
PGOOD thresholds
104%
107%
107%
110%
PGOOD
PGOOD leakage current
PGOOD output low voltage
Minimum VIN for asserted output
µA
V
BP5 = 5 V, IPGOOD = 6mA
0.5
1.5
V
V
PGOOD ≤0.5 V, IPGOOD = 1 mA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE FAULT PROTECTION
OV fault threshold
UV fault threshold
VFB1, VFB2 rising (fault)
VFB1, VFB2 falling (fault)
120%
80%
(1) See the Minimum and Maximum Input Voltage section for the recommended minimum input voltage at higher output voltages.
(2) See Safe Operating Area plots in the Typical Characteristics sections of the data sheet.
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6.6 Typical Characteristics (VIN = 12 V)
TA = 25°C, unless otherwise noted
100
95
90
85
80
75
70
3
2.5
2
VOUT, FSW
5.0V, 2MHz
3.3V, 2MHz
3.3V, 1.5MHz
1.8V, 1.5MHz
1.8V, 1MHz
1.2V, 1MHz
1.0V, 1MHz
1.5
1
VOUT, FSW
65
60
55
50
5.0V, 2MHz
3.3V, 2MHz
3.3V, 1.5MHz
1.8V, 1.5MHz
1.8V, 1MHz
1.2V, 1MHz
1.0V, 1MHz
0.5
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current per channel (A)
Output Current per channel (A)
图6-1. Efficiency vs Output Current
图6-2. Power Dissipation vs Output Current
6.1
115
105
95
FSW
6
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5
500kHz
1MHz
1.5MHz
2MHz
85
75
65
55
45
35
25
Airflow
400LFM
200LFM
100LFM
Nat conv
4.9
0
1
2
3
4
Output Current per channel (A)
5
6
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Output Voltage (V)
Fsw = 1.0 MHz
Dual 1.2-V outputs
IOUT1 = IOUT2
Refer to 表7-1
图6-4. Safe Operating Area (VOUT = 1.2 V)
图6-3. Maximum Output Current
115
105
95
115
105
95
85
85
75
75
65
65
55
55
45
Airflow
45
35
25
Airflow
400LFM
400LFM
200LFM
100LFM
Nat conv
200LFM
100LFM
Nat conv
35
25
0
1
2
Output Current per channel (A)
3
4
5
6
0
1
2
Output Current per channel (A)
3
4
5
6
Fsw = 1.5 MHz
Dual 1.8-V outputs
IOUT1 = IOUT2
Fsw = 2.0 MHz
Dual 3.3-V outputs
IOUT1 = IOUT2
图6-5. Safe Operating Area (VOUT = 1.8 V)
图6-6. Safe Operating Area (VOUT = 3.3 V)
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115
105
95
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
0
1
2
3
4
Output Current per channel (A)
5
6
Fsw = 2.0 MHz
Dual 5-V outputs
IOUT1 = IOUT2
图6-7. Safe Operating Area (VOUT = 5 V)
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6.7 Typical Characteristics (VIN = 5 V)
TA = 25°C unless otherwise noted
100
95
90
85
80
75
70
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
VOUT, FSW
3.3V, 1.5MHz
1.8V, 1.5MHz
1.8V, 1MHz
1.2V, 1.5MHz
1.2V, 1MHz
1.0V, 1.5MHz
1.0V, 1MHz
0.8V, 1MHz
VOUT, FSW
3.3V, 1.5MHz
1.8V, 1.5MHz
1.8V, 1MHz
1.2V, 1.5MHz
1.2V, 1MHz
1.0V, 1.5MHz
1.0V, 1MHz
0.8V, 1MHz
65
60
55
50
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Current per channel (A)
Output Current per channel (A)
图6-8. Efficiency vs Output Current
图6-9. Power Dissipation vs Output Current
6.1
115
105
95
6
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5
85
75
65
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
55
45
35
25
Airflow
400LFM
FSW
500kHz
200LFM
100LFM
Nat conv
1MHz
1.5MHz
2MHz
0
1
2
3
4
Output Current per channel (A)
5
6
0.5
1
1.5
2
2.5
3
3.5
3.9
Output Voltage (V)
Fsw = 1.0 MHz
Dual 0.8-V outputs
IOUT1 = IOUT2
Refer to 表7-1
图6-11. Safe Operating Area (VOUT = 0.8 V)
图6-10. Maximum Output Current
115
105
95
115
105
95
85
85
75
75
65
65
55
55
45
Airflow
45
35
25
Airflow
400LFM
400LFM
200LFM
100LFM
Nat conv
200LFM
100LFM
Nat conv
35
25
0
1
2
Output Current per channel (A)
3
4
5
6
0
1
2
Output Current per channel (A)
3
4
5
6
Fsw = 1.5 MHz
Dual 1.2-V outputs
IOUT1 = IOUT2
Fsw = 1.5 MHz
Dual 1.8-V outputs
IOUT1 = IOUT2
图6-12. Safe Operating Area (VOUT = 1.2 V)
图6-13. Safe Operating Area (VOUT = 1.8 V)
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115
105
95
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
0
1
2
3
4
Output Current per channel (A)
5
6
Fsw = 2.0 MHz
Dual 3.3-V outputs
IOUT1 = IOUT2
图6-14. Safe Operating Area (VOUT = 3.3 V)
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7 Detailed Description
7.1 Overview
The TPSM5D1806E device is a dual output, step-down DC-DC power module with 4.5-V to 15-V input voltage
range. Each device has two output channels and is capable of delivering up to 6-A of load current per channel.
The device features exceptional efficiency and thermal performance in a very small solution size. The device is
configurable as two independent 6-A outputs or a single 2-phase output to deliver up to 12 A. The
TPSM5D1806E uses a fixed frequency, proprietary advanced current mode control architecture. The device
operates in forced PWM (FPWM) operation to maintain constant switching frequency over the load range. The
device is internally compensated, which reduces design time and requires fewer external components. The
switching frequency and the phase operation are configured using pin strapping. The MODE1 pin sets the phase
operation. 表 7-4 shows the resistor values that are required to set the phase operation and the correct phase
offset. The switching frequency can be selected from pre-set values of 500 kHz, 1.0 MHz, 1.5 MHz, and 2.0 MHz
through pin-strapping on the MODE2 pin. The TPSM5D1806E is also capable of synchronization to an external
clock. The four switching frequency options allow the device to meet a wide range of design requirements. The
module also features the following:
• Power-good (PGOOD) flag for each channel
• Precision enable for each channel
• Internal or adjustable soft-start rate
• Start-up into pre-bias voltage
The device has a pinout designed for simple, optimum PCB layout, low EMI, and excellent thermal performance.
7.2 Functional Block Diagram
BP5
TPSM5D1806
Linear
Regulator
VIN
SS
Remote Sense
Amp
FB1
RS-
+
0.47 µH
Control
VREF
VOUT1
SW1
PWM
and
Driver
Control
EN1
OV/UV,
Thermal
Protection,
Supervisory
PGOOD1
PGND
VIN
MUX
MUX
EN2/ISHARE
Overcurrent
Protection and
Current Balance
PGOOD2/CLKO
0°
MODE1
Mode
Decode
Oscillator
MODE2
SYNC
180°
0.47 µH
PWM
and
Driver
Control
VOUT2
SW2
VREF
Control
FB2/VSHARE
SS
PGND
AGND
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7.3 Feature Description
7.3.1 Adjustable Output Voltage
When operating the TPSM5D1806E as a dual output device, the two output voltages (VOUT1 and VOUT2) are
set using resistor dividers between the output voltages and AGND with the mid-point of the resistor divider
connecting to the corresponding feedback pin (FB1 and FB2). See 图7-4.
Select a bottom feedback resistor of 10 kΩ and calculate the value for the top feedback resistor (RFBT) using the
following equation. Use divider resistors with 1% tolerance or better and with a temperature coefficient of 100
ppm or lower.
=
RFBT 20 x VOUT - 0.5
(kꢀ)
(
)
(1)
When connecting the two outputs of the TPSM5D1806E for current sharing, the output voltage is set using only
a single feedback divider connected to FB1. The FB pin of the second channel, FB2, must be left floating as
shown in 图7-2. Use 方程式1 to calculate the RFBT
.
VOUT1
VOUT1
VOUT1
VOUT1
FB1
RFBT1
RFBT1
FB1
10kꢀ
10kꢀ
VOUT2
VOUT2
VOUT2
RFBT2
FB2/Vshare
FB2/Vshare
AGND
AGND
10kꢀ
图7-1. Single Device, Dual Output
图7-2. Single Device, Current Sharing
7.3.2 Frequency Selection
The TPSM5D1806E can be set to one of four switching frequencies:
• 500 kHz
• 1.0 MHz
• 1.5 MHz
• 2.0 MHz
The switching frequency is set using the MODE2 pin on the device. When setting the switching frequency, both
channels of the device are set to the same frequency. Not all input voltage and output voltage combinations can
operate at all switching frequencies. Check 表 7-1 for allowable switching frequencies. Select the appropriate
resistor from 表7-5 to set the switching frequency.
7.3.2.1 Synchronization
The TPSM5D1806E can also be synchronized to an external clock that is within ±20% of the switching frequency
set by the MODE2 pin. The external clock signal can be applied to the SYNC pin before or after powering up.
When the device is synchronized to an external clock signal, if the clock signal is removed, the device transitions
to an intermediate frequency, which is 75% of the programmed frequency for approximately eight clock cycles.
After eight clock cycles, the device transitions to the switching frequency set by the MODE2 pin.
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7.3.2.2 Allowable Switching Frequency
The TPSM5D1806E can be operated over a wide input voltage range with a wide output voltage setting range
and at four selectable switching frequencies. However, not all input voltage, output voltage, and switching
frequency combinations can be achieved due to timing and current limitations.
When setting the switching frequency, both channels of the device are set to the same frequency. When
operating in dual output configuration, make sure that both channels can be operated at the desired switching
frequency by referencing 表7-1.
表7-1. Allowable Switching Frequency
VIN = 5 V
VIN = 12 V
Switching
Frequency
(kHz)
Output Current
per Channel
VOUT Range
VOUT Range
Min
Max
Min
0.5
0.7
1.0
1.4
0.5
0.7
1.0
1.4
0.5
0.7
1.0
1.4
Max
0.8
1.6
2.4
3.2
0.9
2.0
3.6
5.5
0.9
2.0
3.6
5.5
500
1000
1500
2000
500
—
—
0.5
0.5
0.6
0.5
0.5
0.5
0.6
0.5
0.5
0.5
0.6
0.8
1.3
1.8
0.8
1.8
3.3
2.8
0.9
3.9
3.5
2.8
6 A
5 A
1000
1500
2000
500
1000
1500
2000
≤4 A
7.3.3 Minimum and Maximum Input Voltage
The minimum input voltage of the TPSM5D1806E is 4.5 V, however, the minimum recommended input voltage
increases at higher output voltages. Refer to 表 7-2 to determine the minimum recommended input voltage for
each switching frequency. Also reference 表 7-1 to ensure that the output voltage can be operated at the
selected switching frequency. Control the turn ON and turn OFF of the device at an input voltage greater than
the minimum using a resistor divider on the EN1 (EN2) pin between VIN and AGND (see 节7.3.10).
表7-2. Minimum Input Voltage
Switching Frequency (kHz)
Minimum Input Voltage
500
4.5 V
1000
1500
2000
4.5 V or VOUT × 1.3 (whichever is greater)
4.5 V or VOUT × 1.6 (whichever is greater)
4.5 V or VOUT × 1.75 (whichever is greater)
Additionally, the maximum input voltage of the TPSM5D1806E is 15 V, however, the maximum recommended
input voltage decreases at lower output voltages and higher switching frequencies. See 图 7-3 for the maximum
recommended input voltage for each of the allowable switching frequencies across the output voltage range.
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16
15
14
13
12
11
10
9
8
7
FSW
500 kHz
6
1.0 MHz
1.5 MHz
2.0 MHz
5
4
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
Output Voltage (V)
图7-3. Maximum Input Voltage
7.3.4 Recommended Settings
表 7-3 lists the recommended operating settings for several common output voltages. The table takes into
account the minimum and maximum input voltage limits along with timing and current limitations. The table also
lists the minimum required effective output capacitance for each output voltage. Also included in this table is the
minimum required input voltage and required enable divider resistors to ensure safe turn ON at the minimum
input voltage.
Refer to 表 7-1 for the allowable switching frequency. The recommended switching frequency typically results in
the highest efficiency. When operating at a switching frequency other than the recommended, consult 节 7.3.3
for the minimum and maximum allowable input voltage.
When setting the switching frequency, both channels of the device are set to the same frequency. When
operating in dual output configuration, make sure that both channels can be operated at the desired switching
frequency by referencing.
表7-3. Recommended Settings
Top
Bottom
Enable
Minimum
Input
Voltage
(V)
Feedback
Resistor
MODE2
Resistor
(kΩ)
Output
Voltage
(V)
Minimum
COUT
FSW
(kHz)
(2)
Resistor
(1)
(3)
RFBT
RENB
(µF)
(kΩ)
open
6.04
8.06
10.0
12.1
14.0
20.0
26.1
40.2
49.9
56.2
69.8
80.6
90.9
(kΩ)
(4)
0.5
0.8
0.9
1.0
1.1
1.2
1.5
1.8
2.5
3.0
3.3
4.0
4.5
5.0
500
10.7
10.7
17.4
17.4
17.4
17.4
17.4
17.4
28.7
28.7
28.7
53.6
53.6
53.6
400
280
265
250
235
220
180
140
100
85
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.8
5.3
7.1
7.9
8.8
—
500
—
—
1000
1000
1000
1000
1000
1000
1500
1500
1500
2000
2000
2000
—
—
—
—
—
—
29.4
26.1
18.2
16.2
14.3
75
65
60
50
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表7-3. Recommended Settings (continued)
Top
Bottom
Enable
Minimum
Feedback
Resistor
MODE2
Resistor
(kΩ)
Output
Voltage
(V)
Minimum
COUT
FSW
(kHz)
Input
Voltage
(V)
(2)
Resistor
(1)
(3)
RFBT
RENB
(µF)
(kΩ)
(kΩ)
5.5
100
2000
53.6
45
9.6
13.0
(1) RFBB = 10 kΩ
(2) Minimum COUT listed is the effective value, taking into account the effects of DC bias and
temperature variation.
(3) RENT = 100 kΩ
(4) "—" means not required.
7.3.5 Device Mode Configuration
The TPSM5D1806E provides a wide range of configurations through pin strapping of two pins: MODE1 and
MODE2. These pins are used to configure the device outputs, set the phase offset, and set the switching
frequency. The operating mode of the device can be either two independent 6-A outputs or both outputs
connected together in parallel for increased current up to 12 A. In either application, a 10-kΩresistor is required
from MODE1 to MODE2.
7.3.5.1 MODE1 (Operating Mode and Phase Position)
Place a 10-kΩresistor from MODE1 to MODE2.
Place a resistor from MODE1 to AGND to set the device in the desired operating mode. The MODE1 resistor
also selects the phase position for each channel. See 表 7-4 for MODE1 resistor values and the corresponding
settings.
表7-4. Operating Mode and Phase Position Settings
Mode1 Resistor
Channel 1
Phase Position (°)
Channel 2
Phase Position (°)
Operating Mode
Comments
(kω)
Sets phase position for both
channels to 0° and 180°.
0
90(1)
0
180
270(1)
180
15.4
24.9
10.7
Dual outputs
Sets phase position for both
channels to 90° and 270° from
SYNC signal.
Paralleled outputs
(2 phase)
Sets phase positions for both
channels of the device.
(1) Requires synchronization to an external clock signal.
7.3.5.2 MODE2 (Setting the Switching Frequency)
Place a resistor from MODE2 to AGND to set the switching frequency of the device. See 表 7-5 for MODE2
resistor values and the corresponding settings. For dual-output applications, check 表 7-1 to make sure both
outputs can operate at the selected switching frequency.
If synchronizing to an external clock, the TPSM5D1806E can only be synchronized to a frequency that is within
±20% of the switching frequency set by the MODE2 pin.
表7-5. Switching Frequency Settings
MODE2 Resistor
Switching Frequency
(kHz)
(kΩ)
500
10.7
17.4
28.7
53.6
1000
1500
2000
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7.3.6 Input Capacitors
The TPSM5D1806E requires a minimum input capacitance of 88 μF (4 × 22 μF or 2 × 47 μF) of ceramic type.
High-quality, ceramic-type X5R or X7R capacitors with sufficient voltage rating are required. Place input
capacitors, as close as possible to both VIN sides of the device, between VIN and PGND as shown in 图 7-4.
Applications with transient load requirements can benefit from adding additional bulk capacitance to the input as
well.
VIN
(4,5,6)
VIN
(33,34,35)
47µF
47µF
PGND
(7,8,9)
PGND
(27,28,29)
图7-4. Input Capacitors Pin Connections
7.3.7 Minimum Required Output Capacitance
The TPSM5D1806E requires a minimum amount of ceramic output capacitance (per phase) depending on the
output voltage setting. The amount of required output capacitance is shown in 图 7-5 and is the amount of
effective capacitance. The effects of DC bias and temperature variation must be considered when using ceramic
capacitance. For ceramic capacitors, the package size, voltage rating, and dielectric material contributes to
differences between the standard rated value and the actual effective value of the capacitance. When adding
additional capacitance above the minimum, the capacitance can be ceramic type, low-ESR polymer type, or a
combination of the two.
400
375
350
325
300
275
250
225
200
175
150
125
100
75
50
25
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Output Voltage (V)
图7-5. Minimum Required Output Capacitance (per Phase)
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7.3.8 Ambient Temperature Versus Total Power Dissipation
When operating the TPSM5D1806E in dual channel configuration with different output voltages, the maximum
operating ambient temperature can be determined using the total power dissipation of both channels. Refer to
the power dissipation curves, 图 6-2 and 图 6-9, to determine the power dissipation for each output. Sum the
power dissipation of both outputs to calculate the total power dissipation. Refer to 图 7-6 to determine the
maximum allowable operating ambient temperature for a given total power dissipation. Increasing the airflow
allows operation at a higher ambient temperature.
115
105
95
85
75
65
55
45
Airflow
400LFM
200LFM
35
100LFM
Nat Conv
25
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Total Power Dissipation (W)
图7-6. Ambient Temperature Versus Total Power Dissipation
7.3.9 Remote Sense
The TPSM5D1806E supports differential remote sense for accurate output regulation when operated in multi-
phase configuration. In multi-phase configuration, FB1 and RS– pins are used for remote sensing. The FB1 pin
must be connected to the mid-point of the resistor divider. Additionally, the RS– pin must be connected to the
negative sensing point. The FB1 and RS– pins are extremely high-impedance input terminals of the true
differential remote sense amplifier. The feedback resistor divider must use resistor values much less than 100
kΩ to reduce susceptibility to noise. A simple rule of thumb is to use a 10-kΩ lower divider resistor and then
size the upper resistor to achieve the desired ratio.
When configured as a dual-output device, connect the RS–pin to AGND.
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7.3.10 Enable (EN) and Undervoltage Lockout (UVLO)
The precision enable feature of the TPSM6D1806E allows the voltage on the EN pin (VEN) to control the
ON/OFF functionality of the device. The EN pin has an internal pullup. Floating the EN pin allows the device to
start up when a valid input voltage is applied. The TPSM5D1806 switching action and output regulation are
enabled when VEN is greater than 1.2 V (typical). While the device is switching, if the EN voltage falls below 1.1
V (typical), the device stops switching.
It is recommended to control the turn-on and turn-off of the device at a voltage greater than the minimum input
voltage as shown in 表 7-2. An external UVLO control can be added using a resistor divider on the EN1 (EN2)
pin, between VIN and AGND (see 图 7-7). Select a top enable resistor of 100 kΩ and calculate the value for the
bottom enable resistor (RENB) using 方程式 2. It is recommended to use divider resistors with 1% tolerance or
better and with temperature coefficient of 100 ppm or lower.
=
RENB 110 ÷ VIN - 1.1
(kꢀ)
(
)
(2)
VIN
VIN
100kO
EN1 (EN2)
AGND
RENB
图7-7. Adjustable UVLO Control
7.3.11 Soft Start
The TPSM5D1806E soft-start feature limits the inrush current from the input supply when the device is powered
up. For dual-output configuration, the soft-start time is internally programmed to 1 ms. The soft-start pin must be
left floating in dual-output configuration.
The external soft start is enabled when the device is configured in parallel-output operation. In parallel-output
applications, if the SS pin is left open, the default soft-start time is also 1 ms. Applications that deliver high load
current can have a large amount of capacitance at the output and can require longer soft-start time. The soft-
start time for such applications can be extended by connecting an external capacitor, CSS, from the soft-start pin
to AGND. With external CSS, the soft-start time is the longer of 1 ms or the programmed external soft-start time.
An internal current source (ISS = 2 μA) charges CSS and generates a ramp from 0 V to VFB (0.5 V) to control the
ramp-up rate of the output voltage. The external soft-start time can be selected from 表 7-6 or calculated using
方程式3.
0.5 × CSS
tSS
=
2 µA
(3)
表7-6. CSS Values and Soft-Start Times
CSS (nF)
tSS (ms)
Open
6.2
8.2
10
12
20
1
1.5
2
2.5
3
5
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The soft-start capacitor is discharged when VOUT is shut down by either fault protection or when VEN is below
the enable threshold.
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7.3.12 Power Good
The Power Good pins (PGOOD1, PGOOD2) are open-drain outputs that require a pullup resistor of 1 kΩ to 100
kΩ to a voltage source of 5.5 V or less to indicate the output voltage is within the PGOOD range. The BP5
output can be used as the pullup voltage source. The PGOOD detection is activated after soft start is completed.
When the output voltage is within a range of ±10% of the target, the PGOOD goes high after a 50-µs internal
delay. During operation, if the output voltage falls outside of ±10% of target voltage, PGOOD is pulled low after a
10-µs delay. The PGOOD feature is active while the voltage at the VIN pin is either equal to or greater than
1.5 V.
7.3.13 Safe Start-Up into Pre-Biased Outputs
The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output.
7.3.14 BP5
The BP5 pin is the output of an internal 5-V regulator. Bypass this pin with a minimum of 1.5 μF of effective
capacitance to AGND. Place the capacitor as close as possible to the BP5 pin. This pin can be used as a pullup
voltage for power-good signals.
7.3.15 Overcurrent Protection
For protection against load faults, the TPSM5D1806E implements a cycle-by-cycle peak current protection.
When the inductor current hits the peak current limit threshold, the high-side FET turns off and the low-side FET
turns on. The device monitors the valley current threshold during the high-side FET off time. If the inductor
current clears the valley current threshold, the high-side FET will turn on at the next clock edge. However, if the
inductor current remains higher than the valley current threshold, the next high-side FET cycle is skipped, the
low-side FET remains on, and an internal counter is incremented. This counter increments every clock edge as
long as the inductor current remains higher than the valley current threshold. If the current falls below the valley
current threshold at the next clock edge, the counter is reset. If the counter increments 16 consecutive clock
cycles, a current limit fault is identified and the device enters hiccup mode to reduce power dissipation. In hiccup
mode, the module continues in a cycle of successive shutdown and power up until the load fault is removed.
During this period, the average current flowing into the fault is significantly reduced, which reduces power
dissipation. Once the fault is removed, the module automatically recovers and returns to normal operation.
7.3.16 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
165°C typically. The device re-initiates the power-up sequence when the junction temperature drops below
145°C typically.
7.4 Device Functional Modes
7.4.1 Active Mode
The TPSM5D1806E is in active mode when VIN is above the turn-on threshold and the EN pin voltage is above
the EN high threshold. Floating the EN pin allows the device to start-up when a valid input voltage is applied.
This allows self start-up of the TPSM5D1806E when the input voltage is in the operation range of 4.5 V to 15 V.
Connecting a resistor divider between VIN, EN, and AGND increases the UVLO threshold.
7.4.2 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPSM5D1806E. When the EN pin voltage is below
the EN low threshold, the device is in shutdown mode. In shutdown mode, the standby current is 250 μA typical.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPSM5D1806E is a dual 6-A output, step-down, DC/DC power module. It is used to convert a higher DC
voltage to two separate 6-A power rails or one combined 12-A power rail. The following design procedure can be
used to select components for the TPSM5D1806. Alternately, the WEBENCH® software can be used to generate
complete designs. When generating a design, the WEBENCH® software uses an iterative design procedure and
accesses comprehensive databases of components. See www.ti.com for more details.
8.2 Typical Application (Dual Outputs)
图8-1 shows a typical TPSM5D1806M-ET schematic for a dual-output design.
12 V
PGOOD1
VOUT1
VIN
1.0 V
47 µF 47 µF
10 k
10 k
PGND
BP5
FB1
3 x 100 µF
RS-
PGOOD2/CLKO
VOUT2
2.2 µF
EN1
1.8 V
EN2/Ishare
SYNC
26 k
10 k
FB2/Vshare
SS
AGND
MODE1
MODE2
2 x 100 µF
10 k
15.4 k
28.7 k
图8-1. TPSM5D1806E Dual Output Typical Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 8-1 as the input parameters and follow the design
procedures in 节8.2.2.
表8-1. Design Example Parameters
Design Parameter
Value
12 V typical
1.0 V
Input voltage VIN
Output voltage VOUT1
Output voltage VOUT2
Switching frequency
Output current rating
1.8 V
1.5 MHz
Up to 6 A / output
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8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM5D1806E device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the TPSM5D1806E device is externally adjustable using a resistor divider. The
recommended value of RFBB is 10 kΩ. The value for RFBT can be calculated using 方程式4:
=
RFBT 20 x VOUT - 0.5
(kꢀ)
(
)
(4)
For the desired output voltage of 1.0 V, the formula yields a value of 10 kΩ. Choose the closest available value
of 10.0 kΩfor RFBT
.
For the desired output voltage of 1.8 V, the formula yields a value of 26 kΩ. Choose the closest available value
of 26.1 kΩfor RFBT
.
8.2.2.3 Input Capacitors
The TPSM5D1806E requires a minimum input capacitance of 88 μF of ceramic type. High-quality ceramic type
X5R or X7R capacitors with sufficient voltage rating are recommended. An additional 100 µF of non-ceramic
capacitance is recommended for applications with transient load requirements. The voltage rating of the input
capacitors must be greater than the maximum input voltage.
For this design example, two 47-µF, 25-V ceramic capacitors are used.
8.2.2.4 Output Capacitor Selection
The TPSM5D1806E requires a minimum amount of output capacitance for proper operation. The minimum
amount of required output varies depending on the output voltage. See 图 7-5 for the required output
capacitance.
For this design example, three 100-µF, 6.3-V ceramic capacitors are selected for the 1.0-V output. For the 1.8-V
output, two 100-µF, 6.3-V ceramic capacitors are selected. Additional output capacitance can be needed to meet
transient requirements.
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8.2.3 Application Curves
VIN = 12 V
IOUT1 = 3 A
VOUT = 1.2 V
IOUT2 = 3 A
VIN = 12 V
IOUT1 = 3 A
IOUT2 = 3 A
COUT = 4 × 100 µF
VOUT = 1.2 V
COUT = 4 × 100 µF
图8-2. Enable Turn-On with Load
图8-3. Enable Turn-Off with Load
VIN = 12 V
VOUT = 1.2 V
COUT = 4 × 100 µF
(Nominal)
VIN = 12 V
VOUT = 1.2 V
COUT = 4 × 100 µF
(Nominal)
Slew rate: 1 A/µs
IOUT = 2 A to 4 A
Slew rate: 1 A/µs
IOUT = 2 A to 4 A
图8-5. Transient Response VOUT1
图8-4. Transient Response VOUT2
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VIN = 12 V
VOUT = 1.2 V
COUT = 4 × 100 µF
(Nominal)
VIN = 12 V
VOUT = 1.2 V
COUT = 4 × 100 µF
(Nominal)
图8-6. Enable Turn-On Without Load
图8-7. Enable Turn-Off Without Load
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8.2.4 Typical Application (Paralleled Outputs)
The dual outputs of the TPSM5D1806E can be combined to create a higher current (up to 12 A), single output.
图8-8 shows a typical TPSM5D1806E schematic for a paralleled output design.
图8-8. TPSM5D1806E Parallel Outputs Typical Schematic
8.2.4.1 Design Requirements
For this design example, use the parameters listed in 表 8-2 as the input parameters and follow the design
procedures in 节8.2.4.2.
表8-2. Design Example Parameters
Design Parameter
Value
12 V typical
0.9 V
Input voltage VIN
Output voltage
Switching frequency
Output current rating
1.0 MHz
Up to 12 A
8.2.4.2 Detailed Design Procedure
8.2.4.2.1 Output Voltage Setpoint
The output voltage of the TPSM5D1806E device is externally adjustable using a resistor divider. The
recommended value of RFBB is 10 kΩ. The value for RFBT can be calculated using 方程式5:
=
RFBT 20 x VOUT - 0.5
(kꢀ)
(
)
(5)
For the desired output voltage of 0.9 V, the formula yields a value of 8 kΩ. Choose the closest available value of
8.06 kΩfor RFBT or place two resistors in series to come closer to the exact value.
8.2.4.2.2 Input Capacitors
The TPSM5D1806E requires a minimum input capacitance of 88 μF of ceramic type. High-quality ceramic type
X5R or X7R capacitors with sufficient voltage rating are recommended. An additional 100 µF of non-ceramic
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capacitance is recommended for applications with transient load requirements. The voltage rating of the input
capacitors must be greater than the maximum input voltage.
For this design example, two 47-µF, 25-V ceramic capacitors are used.
8.2.4.2.3 Output Capacitor Selection
The TPSM5D1806E requires a minimum amount of output capacitance for proper operation. The minimum
amount of required output varies depending on the output voltage. See 图 7-5 for the required output
capacitance.
For this design example, six 100-µF, 6.3-V ceramic capacitors are selected for the 0.9-V output. Additional
output capacitance can be needed to meet transient requirements.
9 Power Supply Recommendations
The TPSM5D1806E is designed to operate from an input voltage supply range between 4.5 V and 15 V. This
input supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage.
The resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the TPSM5D1806E supply voltage that can cause a false UVLO fault triggering and system
reset.
If the input supply is located more than a few centimeters from the TPSM5D1806E, additional bulk capacitance
can be required in addition to the ceramic bypass capacitors. The typical amount of bulk capacitance is a 47-µF
electrolytic type capacitor.
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10 Layout
The performance of any switching power supply depends as much on the layout of the PCB as the component
selection. The following guidelines help users design a PCB with the best power conversion performance,
optimal thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图10-1 and 图10-2
show typical PCB layouts. The following are some considerations for an optimized layout.
• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Connect AGND to PGND at a single point.
• Place RFBT and RFBB as close as possible to the FB pin.
• Use multiple vias to connect the power planes to internal layers.
10.2 Layout Examples
Single Device Dual Output
图10-1. Typical Dual-Output Layout
Single Device Parallel Output
图10-2. Typical Parallel-Output Layout
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10.2.1 Package Specifications
TPSM5D1806
Value
Unit
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
89.3
MHrs
10.2.2 EMI
The TPSM5D1806E is compliant with EN55011 Class-B radiated emissions. 图 10-3 and 图 10-4 show typical
examples of radiated emissions plots for the TPSM5D1806E. The graphs include the plots of the antenna in the
horizontal and vertical positions.
EMI plots were measured using the standard TPSM5D1806EVM with ferrite beads (Murata, BLM18SG330SN1)
in series with the input wires.
图10-3. Radiated Emissions 5-V Input, 1.8-V Outputs, 6-A/Output Load
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图10-4. Radiated Emissions 12-V Input, 5-V Output, 6-A/Output Load
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM5D1806E device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPSM5D1806MRDBR-ET
ACTIVE
B0QFN
RDB
51
2000
RoHS Exempt
& Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
TPSM5D1806M
ET
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
RDB0051A
B0QFN - 1.9 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK-NO LEAD
5.6
5.4
B
A
PIN 1 INDEX AREA
8.1
7.9
1.9
1.7
C
SEATING PLANE
0.08 C
0.674
0.574
4X
2X 3.5
0.35
4X
0.25
2.55
5X
(0.13) TYP
2.45
4X (0.175)
0.55
0.45
30X
12X
16
23
15
24
4X
0.35
0.25
1.05
0.95
42X
51
50
49
0.5
2.065 0.1
1.02 0.1
SYMM
2X 7
48
47
46X (0.2)
0.82 0.05
PADS 48, 49, 50
0.87 0.05
PADS 47 & 51
38
1
0.3
0.2
0.1
46
39
42X
PIN 1 ID
(45 X 0.4)
SYMM
C A B
C
4X (0.2)
0.05
4X (0.525)
4225676/B 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RDB0051A
B0QFN - 1.9 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
2X (3.5)
(2.5)
38X (0.5)
4X (0.825)
4X (0.5)
4X (0.3)
SYMM
46
4X (R0.1)
39
1
38
4X (0.525)
4X (0.3)
42X (0.25)
(R0.05) TYP
SYMM
47
2X (6)
(5) (7.7)
(0.5)
(1)
12X (1.2)
(
0.2) TYP
VIA
24
15
30X (0.7)
23
16
(1)
(4.7)
(5.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.05 MAX
0.05 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225676/B 04/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RDB0051A
B0QFN - 1.9 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
4X (2.75)
(0.625)
4X (2.275)
4X (0.3)
4X (0.5)
4X (0.4)
4X (0.3)
TYP
46
39
1
38
4X (0.525)
38X (0.5)
4X (3.625)
42X (0.25)
SYMM
(1) TYP
47
2X (6)
(7.7)
30X (0.7)
12X (1.2)
(R0.05) TYP
10X (0.65)
10X
(0.95)
24
15
EXPOSED METAL
23
16
SYMM
2X (3.5)
(4.7)
(5.2)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 12X
SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 47: 49%
4225676/B 04/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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TPSM63603RDHR
TPSM63606 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 6-A Power Module With Enhanced HotRod⢠QFN Package
TI
TPSM63603S
TPSM63606 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 6-A Power Module With Enhanced HotRod⢠QFN Package
TI
TPSM63603SRDHR
TPSM63606 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 6-A Power Module With Enhanced HotRod⢠QFN Package
TI
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