TPS929160-Q1 [TI]
汽车级 16 通道 40V 高侧 LED 和 OLED 驱动器;
| 型号： | TPS929160-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级 16 通道 40V 高侧 LED 和 OLED 驱动器 驱动 驱动器 |
| 文件： | 总127页 (文件大小：8604K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS929160-Q1
ZHCSNG0 – APRIL 2023
TPS929160-Q1 具有 FlexWire™ 接口的 16 通道汽车类 40V 高侧 (O)LED 驱动器
1 特性
2 应用
•
符合面向汽车应用的 AEC-Q100 标准：
•
•
•
•
汽车外部尾灯
汽车外部前照灯
车内环境照明灯
汽车仪表组显示器
– 温度等级 1：–40°C 至 +125°C，TA
16 通道精密高侧电流输出：
– 器件电源电压为 4.5V 至 40V
– LED 电源电压为 4V 至 36V
– 由电阻器设置的高达 100mA 的通道电流
– 2 位全局、6 位独立电流设置
– 高电流精度：电流为 5mA 至 100mA 时，精度 <
±5%
•
3 说明
随着汽车照明领域对动画的需求不断增加，必须对
LED 进行单独控制。因此，具有数字接口的 LED 驱
动器对于有效驱动像素控制的照明应用来说至关重要。
在外部照明中，多种灯功能通常位于用非板载线相互连
接的不同 PCB 板上。传统的单端接口很难满足严格
的 EMC 要求。通过使用业界通用的 CAN 物理层，
TPS929160-Q1 基于 UART 的 FlexWire 接口可轻松
实现长距离的非板载通信，而不会影响 EMC 性能。
– 低压降：电流为 100 mA 时为 750 mV
– 12 位独立 PWM 调光
– 可编程 PWM 频率高达 20kHz
– 相移 PWM 调光
– EN 和 NSTB 引脚支持睡眠模式下的超低静态电
流
TPS929160-Q1 是一款 16 通道 40V 高侧 LED
驱动器，可控制 8 位输出电流和 12 位 PWM 占空
比。该器件具有 LED 开路、接地短路和单 LED 短路
诊断功能，可满足多种调节要求。在失去 MCU 连接
时，可配置的看门狗还可以自动设置失效防护状态。借
助可编程的 EEPROM，可以针对不同应用场景灵活设
置 TPS929160-Q1。
– 线性调光与指数调光方法
•
•
FlexWire™ 控制接口
– 高达 1MHz 的时钟频率
– 一条灵活导线总线最多可连接 16 个器件
– 一帧的数据事务高达 24 字节
– 5V LDO 输出为 CAN 收发器供电
诊断和保护：
封装信息
– 可编程失效防护状态
器件型号
封装(1)
封装尺寸（标称值）
– LED 开路检测
DCP（HTSSOP，
38）
– LED 短路检测
TPS929160-Q1
9.70mm × 4.40mm
– 单 LED 短路诊断
– 可编程低电源检测
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 漏极开路 ERR 故障指示
– 适用于灵活导线接口的看门狗和 CRC
– 可进行引脚电压测量的 8 位 ADC
– 过温保护
RX
RX
OUTA0
OUTA1
CAN
CANH
CANL
VLDO
GND
Transceiver
(optional)
TX
TX
TPS929160-Q1
NSTB
INH
NSTB
EN
OUTH0
OUTH1
ERR
DC/DC
Converter
(optional)
SUPPLY
SUPPLY
VBAT
FS0
VBAT
ADDR3
ADDR2
ADDR1
ADDR0
Address
Setting
FS1
REF
LED Driver
LED
典型应用图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSG60
TPS929160-Q1
ZHCSNG0 – APRIL 2023
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................9
6.7 Typical Characteristics..............................................10
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................17
7.4 Device Functional Modes..........................................43
7.5 Programming............................................................ 45
7.6 Register Maps...........................................................54
8 Application and Implementation................................ 116
8.1 Application Information............................................116
8.2 Typical Application.................................................. 116
8.3 Power Supply Recommendations...........................120
8.4 Layout..................................................................... 120
9 Device and Documentation Support..........................121
9.1 接收文档更新通知................................................... 121
9.2 支持资源..................................................................121
9.3 Trademarks.............................................................121
9.4 静电放电警告.......................................................... 121
9.5 术语表..................................................................... 121
10 Mechanical, Packaging, and Orderable
Information.................................................................. 121
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
April 2023
*
Initial Release
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English Data Sheet: SLVSG60
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ZHCSNG0 – APRIL 2023
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5 Pin Configuration and Functions
RX
VLDO
GND
ADDR3
ADDR2
ADDR1
ADDR0
OUTA0
OUTA1
OUTB0
OUTB1
NC
1
2
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
3
TX
4
NSTB
REF
5
6
7
ERR
8
EN
TPS929160-Q1
DCP
VBAT
SUPPLY
9
OUTC0
OUTC1
NC
10
SUPPLY 11
FS1 12
OUTD0
OUTD1
NC
FS0
OUTH1
OUTH0
13
14
15
OUTE0
OUTG1 16
OUTG0
17
22 OUTE1
21
20 OUTF0
Exposed Pad
NC 18
NC
OUTF1 19
图 5-1. DCP Package 38-Pin HTSSOP with PowerPAD™ Integrated Circuit Package Top View
表 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
RX
I
FlexWire RX
2
VLDO
GND
Power
5-V regulator output
3
̶
Ground
4
TX
O
FlexWire TX
5
NSTB
REF
O
FlexWire NSTB Output
Device current reference setting
Open-drain error indication
Device Enable Pin
6
I/O
7
ERR
I/O
8
EN
I
9
VBAT
SUPPLY
SUPPLY
FS1
Power
Power supply for analog and digital circuit
Power supply for current output channels
Power supply for current output channels
Fail-safe input 1
10
11
12
13
14
15
16
17
18
19
20
Power
Power
I
FS0
I
Fail-safe input 0
OUTH1
OUTH0
OUTG1
OUTG0
NC
O
O
O
O
̶
Current output channel H1
Current output channel H0
Current output channel G1
Current output channel G0
No Connection
OUTF1
OUTF0
O
O
Current output channel F1
Current output channel F0
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English Data Sheet: SLVSG60
TPS929160-Q1
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表 5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
NAME
NC
̶
No Connection
OUTE1
OUTE0
NC
O
O
̶
Current output channel E1
Current output channel E0
No Connection
OUTD1
OUTD0
NC
O
O
̶
Current output channel D1
Current output channel D0
No Connection
OUTC1
OUTC0
NC
O
O
̶
Current output channel C1
Current output channel C0
No Connection
OUTB1
OUTB0
OUTA1
OUTA0
ADDR0
ADDR1
ADDR2
ADDR3
O
O
O
O
I
Current output channel B1
Current output channel B0
Current output channel A1
Current output channel A0
Device address setting (Bit0)
Device address setting (Bit1)
Device address setting (Bit2)
Device address setting (Bit3)
I
I
I
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English Data Sheet: SLVSG60
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
UNIT
SUPPLY, VBAT Device supply voltage
45
V
V
V
V
FS0, FS1, EN
OUTXn
High-voltage input
High-voltage outputs
High-voltage output
V(VBAT) + 0.3
–0.3 V(SUPPLY) + 0.3
ERR
–0.3
22
ADDR3,
ADDR2,
ADDR1,
ADDR0, REF,
RX
Low-voltage input
–0.3
5.5
V
VLDO, TX,
NSTB
Low-voltage output
–0.3
5.5
V
TJ
Junction temperature
Storage temperature
–40
–65
150
150
°C
°C
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 1C
±2000
V(ESD) Electrostatic discharge
Corner pins (RX, ADDR3, OUTF0,
OUTF1)
V
Charged device model (CDM), per
AEC Q100-011
CDM ESD Classification Level C4B
±750
±500
Other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
4
NOM
MAX
40
UNIT
V
VBAT
Device supply voltage
SUPPLY
IOUTXn
FS0, FS1
TX
Power supply for output current channel
Channel output current
36
V
0.5
0
100
V(BAT)
5
mA
V
External fail-safe selection input
FlexWire TX output
0
V
RX
FlexWire RX input
0
5
V
VLDO
I(VLDO)
Internal 5-V LDO output
LDO external current load
0
5
V
0
80
mA
ADDR3, ADDR2,
ADDR1, ADDR0
Device address selection
0
5
V
REF
ERR
t(r_RX)
t(f_RX)
fCLK
Current reference setting
Error feedback open-drain output
RX risetime
0
0
5
20
V
V
5%/fCLK
5%/fCLK
1000
RX falltime
FlexWire frequency
10
kHz
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over operating free-air temperature range (unless otherwise noted)
MIN
45
NOM
MAX
UNIT
%
DSYNC
TA
Synchronization pulse dutycycle
Ambient temperature
50
55
125
150
–40
–40
°C
TJ
Junction temperature
°C
6.4 Thermal Information
TPS929160-Q1
THERMAL METRIC(1)
HTSSOP (DCP)
UNIT
38 PINS
27.7
16.6
8.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJB
8.3
RθJC(bot)
1.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = –40°C to 150°C, V(VBAT) = 4.5-40 V, V(SUPPLY) = 4-36 V, for digital outputs, C(LOAD) = 20 pF, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BIAS
V(VBAT)
ISD(VBAT)
Operating input voltage
4.5
12
5
40
10
V
Shutdown current, VBAT pin
V(VBAT) = 12 V, EN = L
µA
Quiescent current, all-channels-off,
VBAT pin
V(VBAT) = 12 V, EN = H, R(REF) = 8.45
kΩ, REFRANGE = 11b, all-output OFF
1.6
2.8
2.0
4.0
mA
mA
IQ(VBAT)
V(VBAT) = 12 V, EN = H, R(REF) = 8.45
kΩ, REFRANGE = 11b, PWMOUTXn
= 0, all-output ON
Quiescent current, all-channels-on,
VBAT pin
V(VBAT) = 12 V, V(SUPPLY) = 12 V, EN
= H, R(REF) = 8.45 kΩ, REFRANGE =
11b, all-output OFF
Quiescent current, all-channels-off,
SUPPLY pin
4.9
5.2
10
µA
IQ(SUPPLY)
V(VBAT) = 12 V, V(SUPPLY) = 12 V, EN
= H, R(REF) = 8.45 kΩ, REFRANGE =
11b, PWMOUTXn = 0, all-output ON
Quiescent current, all-channels-on,
SUPPLY pin
8.0
mA
Quiescent current, fail-safe state fault V(VBAT) = 12 V, V(SUPPLY) = 12 V, fail-
mode, VBAT pin safe state, all-output OFF, ERR = LOW
IFAULT(VBAT)
1.3
5
2.0
10
mA
µA
Quiescent current, fail-safe state fault V(VBAT) = 12 V, V(SUPPLY) = 12 V, fail-
IFAULT(SUPPLY)
mode, SUPPLY pin
safe state, all-output OFF, ERR = LOW
ILKG(SUPPLY)
V(POR_rising)
V(POR_falling)
V(LDO)
Supply leakage current
V(SUPPLY) = 36 V, EN = L
0.08
4.2
4
5
4.4
µA
V
Power-on-reset rising threshold
Power-on-reset falling threshold
LDO output voltage
4
3.8
4.2
V
V(VBAT) > 5.6 V, I(LDO) = 80 mA
4.75
5
5.25
80
V
I(LDO)
LDO output current capability
LDO output current limit
mA
mA
V
I(LDO_LIMIT)
V(LDO_DROP)
V(LDO_DROP)
V(LDO_POR_rising)
V(LDO_POR_falling)
110
LDO maximum dropout voltage
LDO maximum dropout voltage
LDO power-on-reset rising threshold
LDO power-on-reset falling threshold
I(LDO) = 80 mA
I(LDO) = 50 mA
0.5
0.3
0.9
0.6
3.25
3
V
2.75
2.5
3.00
2.75
V
V
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English Data Sheet: SLVSG60
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TJ = –40°C to 150°C, V(VBAT) = 4.5-40 V, V(SUPPLY) = 4-36 V, for digital outputs, C(LOAD) = 20 pF, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
10 µF
+2.5% MHz
Supported LDO loading capacitance
range
C(LDO)
1
f(OSC)
Internal oscillator frequency
-2.5%
32.15
ERR, NSTB
VIL(ERR)
VIH(ERR)
IPD(ERR)
ILKG(ERR)
Input logic low voltage, ERR
Input logic high voltage, ERR
ERR pull-down current capability
ERR leakage current
1.045
1.14
3
1.1
1.2
5
1.155
1.26
9
V
V
V(ERR) = 0.4 V
mA
µA
0.02
1
High level voltage drop NSTB with
respect to V(LDO)
ΔV(NSTB)
I(NSTB) = 1 mA
40
1
100
mV
RPD(NSTB)
ILKG(NSTB)
NSTB pull-down resistor
NSTB leakage current
2
4
MΩ
µA
V(NSTB) = 0 V
-4
FLEXWIRE INTERFACE
VIL(RX)
Input logic low voltage, RX
0.7
V
V
VIH(RX)
Input logic high voltage, RX
Low-level output voltage, TX
High-level output voltage, TX
TX, RX
2
0
VOL(TX)
Isink = 5 mA,
0.04
4.9
0.3
5.0
1
V
VOH(TX)
Isource = 5 mA, Vpull-up = 5 V
4.7
–1
V
Ilkg
µA
EN, ADDRESS, FS
Input logic low voltage, EN, ADDR3,
ADDR2, ADDR1, ADDR0
VIL(ADDR)
VIH(ADDR)
0.7
V
V
Input logic high voltage, EN, ADDR3,
ADDR2, ADDR1, ADDR0
2
VIL(IO)
VIH(IO)
Input logic low voltage FS1, FS0
Input logic high voltage, FS1, FS0
1.045
1.14
1.1
1.2
1.155
1.26
V
V
Internal pull down resistance, ADDR3,
ADDR2, ADDR1, ADDR0
RPD(ADDR)
200
240
300
kΩ
ADC
DNL
Differential nonlinearity
Integral nonlinearity
–1(1)
–2(1)
1(1)
2(1)
LSB
LSB
INL
OUTPUT DRIVERS
f(PWM_200)
f(PWM_1000)
200 Hz selection
1 kHz selection
200
Hz
Hz
1000
R(REF) = 8.45 kOhm, REFRANGE =
11b, DC = 63
–5
–5
–5
–5
–3
–3
–5
–7
0
0
0
0
0
0
0
0
5
5
5
5
3
3
5
7
R(REF) = 8.45 kOhm, REFRANGE =
10b, DC = 63
Device-to-device accuracy ΔI(OUT_d2d)
= 1- Iavg(OUT) / Iideal(OUT)
ΔI(OUT_d2d)
%
R(REF) = 8.45 kOhm, REFRANGE =
01b, DC = 63
R(REF) = 8.45 kOhm, REFRANGE =
00b, DC = 63
R(REF) = 8.45 kOhm, REFRANGE =
11b, DC = 63
R(REF) = 8.45 kOhm, REFRANGE =
10b, DC = 31
Channel-to-channel accuracy
ΔI(OUT_c2c) = 1- I(OUTx) / Iavg(OUT)
ΔI(OUT_c2c)
%
R(REF) = 8.45 kOhm, REFRANGE =
01b, DC = 15
R(REF) = 31.6 kOhm, REFRANGE =
01b, DC = 12
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English Data Sheet: SLVSG60
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TJ = –40°C to 150°C, V(VBAT) = 4.5-40 V, V(SUPPLY) = 4-36 V, for digital outputs, C(LOAD) = 20 pF, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
R(REF) = 6.34 kOhm, REFRANGE =
11b, DC = 63
I(OUT_100mA)
I(OUT_75mA)
I(OUT_50mA)
I(OUT_20mA)
I(OUT_1mA)
100
mA
R(REF) = 8.45 kOhm, REFRANGE =
11b, DC = 63
75
50
mA
mA
mA
mA
R(REF) = 12.7 kOhm, REFRANGE =
11b, DC = 63
R(REF) = 31.6 kOhm, REFRANGE =
11b, DC = 63
20
R(REF) = 31.6 kOhm, REFRANGE =
01b, DC = 12
1
R(REF) = 8.45 kOhm, REFRANGE =
11b, DC = 38, I(OUTx) = 45 mA
450
600
750
700
1000
1200
mV
mV
mV
R(REF) = 8.45 kOhm, REFRANGE =
11b, DC = 63, I(OUTx) = 75 mA
V(OUT_drop)
Output dropout voltage
R(REF) = 6.34 kOhm, REFRANGE =
11b, DC = 63, I(OUTx) = 100 mA
R(REF)
1
0
50
4.7
kΩ
nF
V
C(REF)
V(REF)
1.228
1.235
512
256
128
64
1.242
K(REF_11)
REFRANGE = 11b
REFRANGE = 10b
REFRANGE = 01b
REFRANGE = 00b
K(REF_10)
K(REF_01)
K(REF_00)
I(REF_OPEN_th)
I(REF_OPEN_th_hyst)
V(REF_SHORT_th)
DIAGNOSTICS
V(SUPUV_th_rising)
V(SUPUV_th_falling)
V(SUPUV_th_hyst)
7
8.5
10
µA
uA
V
4
0.54
0.565
0.59
SUPPLY undervoltage rising threshold
SUPPLY undervoltage falling threshold
SUPPLY undervoltage hysteresis
2.73
2.49
2.875
2.625
250
3.02
2.76
V
V
mV
SUPPLY low rising
threshold, LOWSUPTH = 0
V(SUPLOW_th_rising)
V(SUPLOW_th_falling)
V(SUPLOW_th_hyst)
4.05
3.8
4.25
4.0
4.45
4.2
V
V
SUPPLY low falling threshold,
LOWSUPTH = 0
SUPPLY low hysteresis, LOWSUPTH
= 0
250
mV
V(OPEN_th_rising)
V(OPEN_th_falling)
V(OPEN_th_hyst)
V(SG_th_rising)
V(SG_th_falling)
V(SG_th_hyst)
LED open rising threshold
LED open falling threshold
V(SUPPLY) - V(OUTx)
V(SUPPLY) - V(OUTx)
200
300
400
500
100
0.9
1.2
0.3
600
700
mV
mV
mV
V
Short-to-ground rising threshold
Short-to-ground falling threshold
Short-to-ground hysteresis
0.8
1.1
1
1.3
V
V
Single-LED short rising threshold,
SLSTHx = 0
V(SLS_th_rising)
V(SLS_th_falling)
2.35
2.65
2.5
2.85
275
2.65
3.05
V
V
Single-LED short falling threshold,
SLSTHx = 0
Single-LED short hysteresis, SLSTHx
= 0
V(SLS_th_hyst)
mV
EEPROM
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TJ = –40°C to 150°C, V(VBAT) = 4.5-40 V, V(SUPPLY) = 4-36 V, for digital outputs, C(LOAD) = 20 pF, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
N(EEP)
Number of programming cycles
V(VBAT) = 12 V
1000
TEMPERATURE
T(PRETSD)
Pre-thermal warning threshold
Pre-thermal warning hysteresis
135
5
oC
oC
T(PRETSD_HYS)
Over-temperature
protection threshold
T(TSD1)
160
175
185
15
190
oC
oC
oC
oC
Over-temperature
shutdown threshold
T(TSD2)
Over-temperature
protection hysteresis
T(TSD1_HYS)
T(TSD2_HYS)
Over-temperature
shutdown hysteresis
15
(1) Guaranteed by design only
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
µs
t(BLANK)
Diagnostics pulse-width, BLANK = 0h
100
96
96
57
8
t(SUPLOW_deg)
t(SUPUV_deg)
t(CONV)
Low supply deglitch timer
µs
Supply undervoltage deglitch timer
µs
time needed to complete one AD conversion
Open-circuit deglitch timer
µs
t(OPEN_deg)
t(SHORT_deg)
t(SLS_deg)
µs
Short-circuit deglitch timer
8
µs
Single-LED short-circuit deglitch timer
Fault retry timer
8
µs
t(SLS_retry)
10
ms
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6.7 Typical Characteristics
3.25
3.2
100
90
80
70
60
50
40
30
20
10
0
TA = -40 °C
TA = 25 °C
TA = 125 °C
3.15
3.1
3.05
3
2.95
2.9
2.85
2.8
2.75
2.7
2.65
2.6
2.55
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
REF Resistor (k)
REF Resistor (k)
REFRANGE = 11b
PWMOUTXn=0, all-output ON
图 6-1. Standby Current vs REF Resistor
REFRANGE = 11b
IOUTXn[5:0]=3Fh
图 6-2. Output Current vs REF Resistor
140
120
100
80
55
50
45
40
35
30
25
20
15
10
5
IOUT = 5 mA
IOUT = 50 mA
IOUT = 100 mA
60
40
20
TA = -40 °C
TA = 25 °C
TA = 125 °C
0
0
0
0.6
1.2
1.8
2.4
3
3.6
4.2
0
0.5
1
1.5
2
2.5
3
3.5
4
Dropout Voltage (V)
Dropout Voltage (V)
图 6-3. Output Current vs Dropout Voltage
图 6-4. Output Current vs Dropout Voltage
IOUT = 50 mA
150
125
100
75
70
60
50
40
30
20
10
0
IOUT = 5 mA
IOUT = 50 mA
IOUT = 100 mA
50
25
0
0
6
12
18
24
30
36
42
0
32
64
96
128
160
192
224
255
Supply Voltage (V)
PWMOUT[7:0]
图 6-5. Output Current vs Supply Voltage
图 6-6. Average Current vs PWMOUT[7:0]
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6.7 Typical Characteristics
120
5.6
5.4
5.2
5
IOUT = 50 mA TA = -40 °C
IOUT = 100 mA TA = -40 °C
IOUT = 50 mA TA = 25 °C
IOUT = 100 mA TA = 25 °C
IOUT = 50 mA TA = 125 °C
IOUT = 100 mA TA = 125 °C
TA = -40 °C
TA = 25 °C
TA = 125 °C
100
80
60
40
20
0
4.8
4.6
4.4
4.2
4
0
8
16
24
32
40
48
56
63
0
4
8
12
16
20
24
28
32
36
40
IOUT[5:0]
Battery voltage (V)
图 6-7. Output DC Current vs IOUT[5:0]
图 6-8. LDO Output Line Regulation
5.04
5.03
5.02
5.01
5
40
35
30
25
20
15
10
5
4.99
4.98
4.97
4.96
4.95
4.94
4.93
0
0
10
20
30
40
50
60
70
80
90 100
0
5
10
15
20
25
30
35
40
LDO Output Current (mA)
Supply Voltage (V)
图 6-9. LDO Output Load Regulation
图 6-10. ADC sampling result vs sampled supply voltage
40
35
30
25
20
15
10
5
0
0
5
10
15
20
25
30
35
40
CH0 Voltage (V)
图 6-11. ADC sampling result vs sampled channel voltage
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Ch3 = V(OUTB0)
Ch3 = V(OUTB0)
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6.7 Typical Characteristics (continued)
Ch1 = V(SUPPLY)
Ch4 = I(OUTC0)
Ch2 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTC0)
Ch2 = V(OUTA0)
Ch3 = V(OUTB0)
图 6-13. PWM Dimming at 2000 Hz
图 6-12. PWM Dimming at 200 Hz
Ch1 = V(SUPPLY)
Ch4 = I(OUTC0)
图 6-14. Phase shift PWM Dimming at 200 Hz
Ch2 = V(OUTA0)
Ch3 = V(OUTB0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTC0)
图 6-15. Phase shift PWM Dimming at 2000 Hz
Ch2 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
图 6-17. Transient Undervoltage
Ch2 = V(ERR)
Ch3 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTC0)
Ch2 = V(OUTA0)
Ch3 = V(ERR)
图 6-16. Supply dimming in FAIL-SAFE mode at 200 Hz
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6.7 Typical Characteristics (continued)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
图 6-18. Transient Overvoltage
图 6-19. Jump Start
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
图 6-20. Superimposed Alternating Voltage 15 Hz
Ch2 = V(ERR)
Ch3 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
图 6-21. Superimposed Alternating Voltage 1 kHz
Ch1 = V(SUPPLY)
Ch4 = V(LDO)
Ch2 = V(ERR)
Ch5 = I(OUTA0)
Ch3 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = V(LDO)
Ch2 = V(ERR)
Ch5 = I(OUTA0)
Ch3 = V(OUTA0)
图 6-22. Slow Decrease and Quick Increase of Supply Voltage
图 6-23. Slow Decrease and Slow Increase of Supply Voltage
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6.7 Typical Characteristics (continued)
Ch1 = V(SUPPLY)
Ch4 = I(LDO)
Ch2 = V(ERR)
Ch3 = V(LDO)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
图 6-24. LDO Output Load Transient
图 6-25. LED Open-Circuit Detection in Normal Mode
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
图 6-26. LED Short-Circuit Detection in Normal Mode
Ch2 = V(ERR)
Ch3 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
图 6-27. Single-LED Short-Circuit Detection in Normal Mode
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
图 6-28. LED Open-Circuit Detection in FS Mode
图 6-29. LED Open-Circuit Recovery in FS Mode
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6.7 Typical Characteristics (continued)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
图 6-30. LED Short-Circuit Detection in Fail-Safe Mode
图 6-31. LED Short-Circuit Recovery in Fail-Safe Mode
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
Ch1 = V(SUPPLY)
Ch4 = I(OUTA0)
Ch2 = V(ERR)
Ch3 = V(OUTA0)
图 6-32. Single-LED Short-Circuit Detection in Fail-Safe Mode
图 6-33. Single-LED Short-Circuit Recovery in Fail-Safe Mode
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7 Detailed Description
7.1 Overview
TPS929160-Q1 is an automotive, 16-channel LED driver with FlexWire interface to address increasing
requirements for individual control of each LED string. Each of the device channels can support both analog
dimming and pulse-width-modulation (PWM) dimming, configured through its FlexWire serial interface. The
internal electrically erasable programmable read-only memory (EEPROM) allows users to configure device in the
scenario of communication loss to fulfill system level safety requirements.
The FlexWire interface is a robust address-based master-slave interface with flexible baud rate. The
interface is based on multi-frame universal, asynchronous, receiver-transmitter (UART) protocol. The unique
synchronization frame of FlexWire reduces system cost by saving external crystal oscillators. It also supports
various physical layer with the help of external physical layer transceiver such as CAN or LIN transceivers. The
embedded CRC correction is able to ensure robust communication in automotive environments. The FlexWire
interface is easily supported by most of MCUs in the markets.
Each output is a constant current source with individually programmable current output and PWM duty cycle.
PWM phase shift is supported for the output channels to improve the EMC performance and reduce the output
noise. Each channel features various diagnostics including LED open-circuit, short-circuit and single-LED short-
circuit detection. The on-chip analog-digital convertor (ADC) allows the controller to real-time monitor loading
conditions.
To further increase robustness, the unique fail-safe of the device state machine allows automatic switching
to FAIL-SAFE states in the case of communication loss, for example, MCU failure. The device supports
programming fail-safe settings with user-programmable EEPROM. In FAIL-SAFE states, the device supports
different configurations if output fails, such as one-fails-all-fail or one-fails-others-on. Each channel can be
independently programmed as on or off in FAIL-SAFE states. The FAIL-SAFE state machine also allows the
system to function with pre-programmed EEPROM settings without presence of any controller in the system,
also known as stand-alone operation.
The microcontroller can access each of the devices through the FlexWire interface. By setting and reading back
the registers, the master, which is the microcontroller, has full control over the device and LEDs. All EEPROMs
are pre-programmed to default values. TI recommends that users program the EEPROM at the end-of-line for
application-specific settings and FAIL-SAFE configurations.
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7.2 Functional Block Diagram
TPS929160-Q1
VBAT
REF
SUPPLY
OUTXn
Bias
VLDO
16-Ch Output
ERR
Error Feedback
TX
RX
Diagnostics
ADC
FlexWire
Interface
Digital Core
FS0
FS1
Fail-safe
Interface
EEPROM
ADDR2
ADDR1
GND
Device Address
ADDR0
Fail-Safe Statemachine
Main analog blocks
Main digital blocks
Input and output interface
7.3 Feature Description
7.3.1 Device Bias and Power
7.3.1.1 Power Bias (VBAT)
The TPS929160-Q1 is AEC-Q100 qualified for automotive applications. The bias voltage input to the device
through VBAT pin can be low to 4.5 V and up to 40 V for automotive battery directly powered systems. All the
internal analog and digital circuits except for the current output channels are powered by VBAT.
7.3.1.2 Enable and Shutdown (EN)
The TPS929160-Q1 device has an enable input. When EN is low, the device is in sleep mode with ultra low
quiescent current I(SD). This low current helps to save system-level current consumption in applications where
battery voltage directly connects to the device without high-side switches.
When the EN voltage rises above VIL(EN) and V(VBAT) is above V(POR_rising), the TPS929160-Q1 immediately
starts up the internal voltage regulator to provide a stable VLDO, 5V bias to internal analog and digital circuit.
When the EN voltage falls below VIL(EN) and V(VBAT) is above V(POR_rising), the TPS929160-Q1 shuts down all
current output immediately.
7.3.1.3 5-V Low-Drop-Out Linear Regulator (VLDO)
The TPS929160-Q1 has an integrated low-drop-out linear regulator to provide power supply to external CAN
transceivers, such as TCAN1042-Q1. The internal LDO powered by input voltage V(VBAT) provides a stable 5-V
output with up to 80-mA constant current capability. TI recommends a ceramic capacitor from 1 µF to 10 µF
on the VLDO pin. The LDO has an internal current limit I(LDO_LIMIT) for protection and soft start. The capacitor
charging time must be considered to total start-up time period, because the device is held in POR state if the
capacitor voltage is not charged to above UVLO threshold.
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7.3.1.4 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
To ensure clean start-up, the TPS929160-Q1 uses UVLO and POR circuitry to clear its internal registers upon
power up and to reset registers with its default values.
The TPS929160-Q1 has internal UVLO circuits so that when either input voltage V(VBAT) or LDO output voltage
V(LDO) is lower than its UVLO threshold, POR is triggered. In POR state, the device resets digital core and all
registers to default value. FLAG_POR and FLAG_ERR register are set to 1 for each POR cycle to indicate the
POR history.
Before both powers are above UVLO thresholds, the TPS929160-Q1 stays in POR state with all outputs off
and ERR pulled down. Once both power supplies are above UVLO threshold, the device enters INIT mode for
initialization releasing ERR pulldown. A programmable timer starts counting in INIT state, the timer length can
be set by EEPROM register INITTIMER. When the timer is completed, the device switches to NORMAL state. In
INIT state, setting CLRPOR to 1 clears FLAG_POR, disables the timer, and sets the device to NORMAL state.
Upon powering up, the TPS929160-Q1 automatically loads all settings stored in EEPROM to correlated registers
and sets the other registers to default value which don't have correlated EEPROM. All channels are powered up
in OFF state by default to avoid unwanted blinking.
Writing 1 to REGDEFAULT manually loads EEPROM setting to the correlated registers and set the other
registers to default value. After REGDEFAULT is set, the FLAG_POR is cleared to 0. Writing 1 to CLRPOR also
resets the FLAG_POR register to 0. TI recommends setting REGDEFAULT to 1 to clear the internal registers
every time after POR. The REGDEFAULT automatically resets to 0.
7.3.1.5 Power Supply (SUPPLY)
The TPS929160-Q1 has two additional SUPPLY input pins for powering all 16 high-side current output channels.
The supply voltage input to the device through two SUPPLY pin can be low to 3.5 V and up to 36 V for either
automotive battery directly powered systems or an external DC to DC converter output. An external DC to DC
converter can provide a regulated voltage for required LED output forward voltage from wide automotive battery
voltage range.
The TPS929160-Q1 has an internal undervoltage detection circuit for SUPPLY input. When the SUPPLY input
voltage is lower than its undervoltage threshold, V(SUPUV_th_falling), all 16 current output channels are disabled
with ERR pin constantly pulled low and register flags set to 1 including FLAG_ERR bit and FLAG_SUPUV bit. 表
7-6 shows the detailed fault behavior in NORMAL state.
7.3.1.6 Programmable Low Supply Warning
The TPS929160-Q1 uses its internal comparator to monitor supply voltage V(SUPPLY). If the supply is below
allowable working threshold, the output voltage can be insufficient to keep the LED operating with desired
brightness output as expected. The supply voltage is automatically compared with threshold set by register
LOWSUPTH. When the supply voltage is below threshold, the device sets warning flag register FLAG_LOWSUP
and FLAG_ERR to 1 in the status register. CLRFAULT is able to clear the FLAG_LOWSUP as well as other fault
registers. Low-supply warning will clear LED open and single-LED short fault. In addition, the LED open-circuit
and single LED short-circuit detection is disabled if the supply voltage is below threshold to avoid LED open
circuit and to prevent the single LED short-circuit fault from being mis-triggered. The 5-bit register LOWSUPTH
has a total of 32 options covering from 4 V to 35 V at 1-V interval.
7.3.2 Constant Current Output
7.3.2.1 Reference Current with External Resistor (REF)
The TPS929160-Q1 must have an external resistor R(REF) to set the internal current reference I(REF) as shown in
图 7-1.
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IOUTA0[5:0]
REFRANGE[1:0]
2-bit range selection
OUTA0
OUTA1
I(FULL_RANGE)
K(REF)
×512
6-bit DAC
CHA0
CHA1
×256
×128
×64
IOUTA1[5:0]
6-bit DAC
Recommended
CREF
IOUTXn[5:0]
6-bit DAC
REF
V(REF)
Vbg
1.235V
1.235V
OUTXn
RREF
CHXn
Analog blocks
图 7-1. Output Current Setting
The internal current reference, I(FULL_RANGE), is generated based on the I(REF) multiplied by factor K(REF) to
provide the full range current reference for each OUTXn channel. The K(REF) is programmable by 2-bit register
REFRANGE with four different options. Use the following equation to calculate the I(FULL_RANGE)
.
V
(REF)
I(FULL _RANGE)
=
ìK(REF)
R(REF)
(1)
where
•
•
V(REF) = 1.235 V typically
K(REF) = 64, 128, 256, or 512 (default)
The following table lists the recommended resistor values of R(REF) and amplifier ratios of K(REF)
.
表 7-1. Reference Current Range Setting
FULL RANGE CURRENT (mA)
REFRANGE
K(REF)
R(REF) = 6.34 kΩ
R(REF) = 8.45 kΩ
R(REF) = 12.7 kΩ
R(REF) = 31.6 kΩ
11b(default)
10b
512
256
128
64
100
50
75
50
25
20
10
5
37.5
01b
25
18.75
9.375
12.5
6.25
00b
12.5
2.5
Place the R(REF) resistor as close as possible to the REF pin with an up to 2.2-nF ceramic capacitor in parallel to
improve the noise immunity. The off-board R(REF) setup is not allowed due to the concern of instability reference
current. TI recommends a 1-nF ceramic capacitor in parallel with R(REF)
.
7.3.2.2 64-Step Programmable High-Side Constant-Current Output
TPS929160-Q1 has 16 channels of high-side current sources. Each channel has its own enable configuration
register ENOUTXn. Setting ENOUTXn to 1 enables the channel output; clearing the register to 0 disables the
channel output. To completely turn off the channel current, the user can clear channel enable bit ENOUTXn to 0.
Upon power up, ENOUTXn is automatically reset to 0 to avoid unwanted blinking.
Each OUTXn channel supports individual 64-step programmable current setting, also known as dot correction
(DC). The DC feature can be used to set binning values for output LEDs or to calibrate the LEDs to achieve high
brightness homogeneity based on external visual system to further save binning cost. The 6-bit register IOUTXn
sets the current independently, where X is the channel group from A to H, n is the channel number 0 or 1 in each
group. Use the following equation to calculate the OUTXn current.
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IOUTXn +1
64
I(OUTXn)
=
ìI(FULL _RANGE)
(2)
where
•
•
•
IOUTXn is programmable from 0 to 63.
X is from A to H, n is 0 or 1 for different output channel.
Use 方程式 1 to calculate I(FULL_RANGE)
.
7.3.3 PWM Dimming
TPS929160-Q1 integrates independent 12-bit PWM generators for each OUTXn channel. The current output for
each OUTXn channel is turned on and off controlled by the integrated PWM generator. The average current of
each OUTXn can be adjusted by PWM duty cycle independently, therefore, to control the brightness for LEDs in
each channel.
7.3.3.1 PWM Generator
The 12-bit PWM generator constructs the cyclical PWM output based on a 12-bit digital binary input to control
the output current ON and OFF. Basically the PWM generator counts 4096 pulses at base high frequency for
PWM output cycle period and counts number of pulses determined by 12-bit binary input at the same frequency
for PWM ON period. The base high frequency is generated by internal oscillator, which is 4096 times of the
frequency programmable by PWMFREQ. 图 7-2 is the signal path diagram for the PWM generator.
EXPEN
1: LUT EN
0: LUT DIS
Exponential
Look-Up Table
PWMOUTXn[7:0]
1
8
8
12
12-bit PWM
Generator
PWMOUT
MUX
0
8
AND
12
12
12
Linear
12
12
PWMLOWOUTXn[3:0]
ENOUTXn
1: Enabled
0: Disabled
PWMFREQ[3:0]
0h: 200Hz 8h: 1000Hz
1h: 250Hz 9h: 1200Hz
2h: 300Hz Ah: 2000Hz
3h: 350Hz Bh: 4000Hz
4h: 400Hz Ch: 5900Hz
5h: 500Hz Dh: 7800Hz
6h: 600Hz Eh: 9600Hz
7h: 800Hz Fh: 20800Hz
Base Frequency
Internal Oscillator
Digital blocks
图 7-2. PWM Generator Path Diagram
7.3.3.2 PWM Dimming Frequency
The frequency for PWM dimming is programmable by 4-bit register PWMFREQ with 16 options covering from
200 Hz to 20.8 kHz. Select the frequency for PWM dimming based on the minimum brightness requirement in
application. TPS929160-Q1 supports down to 1-µs minimum pulse current for all 16 channel outputs.
7.3.3.3 Blank Time
Because the TPS929160-Q1 supports PWM control for adjusting LED brightness, the voltage on OUTXn is like
a pulse waveform. The output voltage and current ramp up to the target value in a certain period of time after
the channel is turned on depending on the value of capacitor on the OUTXn pin. The ramping up period is
proportional to the capacitance value of the capacitor. To avoid the output voltage of each OUTXn is measured
in the ramping up transient period, the TPS929160-Q1 integrates a t(BLANK) timer which is programmable by a
4-bit register BLANK to setup the blanking time for all OUTXn. The device does not start the OUTXn diagnostics
and ADC measurement until the t(BLANK) timer is overflow. The t(BLANK) timer is programmable from 20 μs to 4
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ms as described in the 表 7-2. TI recommends to set the t(BLANK) less than the PWM dimming period which is
programmable by PWMFREQ register, otherwise the OUTXn diagnostics and ADC measurement only operates
properly when PWM duty cycle is set to 100%.
表 7-2. Blank Time
Blank Time
Binary Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
t(BLANK) (μs)
100
20
30
50
80
150
200
300
500
800
1000 1200 1500 2000 3000 4000
7.3.3.4 Phase Shift PWM Dimming
The TPS929160-Q1 supports both PWM dimming method and phase shift PWM dimming method. In PWM
dimming mode, all 16 current output channels are turned on and off together at the same time at PWM dimming
frequency set by PWMFREQ register as the following figure illustrates.
OUTA0
Current
OUTA1
Current
OUTXn
Current
图 7-3. PWM Dimming Mode
The phase shift PWM dimming mode is enabled by setting PSEN to 1. In phase shift PWM dimming mode,
every three current output channels are formed as one group, so a total of eight current output groups are turned
on and off at PWM dimming frequency set by PWMFREQ register with a constant delay as the following figure
illustrates. The detailed group information is also listed in the below table.
Group A
Current
T(Delay)
Group B
Current
T(Delay)
Group C
Current
T(Delay)
Group D
Current
T(Delay)
Group E
Current
T(Delay)
Group F
Current
T(Delay)
Group G
Current
T(Delay)
T(Delay)
Group H
Current
图 7-4. Phase Shift Dimming Mode
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表 7-3. Phase Shift Dimming Groups
Phase
Phase 0
Groups
Output Channels
OUTA1
Group A
Group B
Group C
Group D
Group E
Group F
Group G
Group H
OUTA0
OUTB0
OUTC0
OUTD0
OUTE0
OUTF0
OUTG0
OUTH0
Phase 1
OUTB1
Phase 2
OUTC1
Phase 3
OUTD1
Phase 4
OUTE1
Phase 5
OUTF1
Phase 6
OUTG1
Phase 7
OUTH1
The phase delay interval is 1/8 of PWM dimming cycle time between two neighboring groups. The phase delay
can be calculated with the below equation.
1
T
=
(Delay)
8ìF
(PWM)
(3)
where
F(PWM) is PWM dimming frequency set by PWMFREQ.
7.3.3.5 Linear Brightness Control
•
When register EXPEN is set to 0, the MSB 8 bits of 12-bit binary input to PWM generator are directly copied
from 8-bit register PWMOUTXn, and the LSB 4 bits are directly copied from 4-bit register PWMLOWOUTXn.
The PWM output duty cycle can be calculated with the following equation. The PWM output duty cycle is
linearly controlled by the register PWMOUTXn and PWMLOWOUTXn, which provides the linear brightness
control to each channel output. When PWMOUTXn is FFh, and PWMLOWOUTXn is Fh, the duty cycle is 100%
exceptionally.
16ìPWMOUTXn + PWMLOWOUTXn
(
)
ì100%
D(OUTXn)
=
4096
(4)
where
•
•
•
PWMOUTXn is decimal number from 0 to 255.
PWMLOWOUTXn is decimal number from 0 to 15.
X is from A to H, n is 0 or 1 for different output channel.
Because the 12-bit PWM duty cycles require 2 bytes of write operation to update the completed data, the output
PWM duty cycle is not changed in between of the two bytes data transmission. TPS929160-Q1 only updates
PWM duty cycle of any output when its high 8-bit PWMOUTXn is written. When very fast brightness change
is needed, for example, fade-in and fade-out effects, simultaneous PWM duty cycle change of all channels is
required. Setting SHAREPWM to 1 enables all channels using the PWM duty cycle setting of channel A0 to save
communication latency. When disabling the SHAREPWM, PWM outputs of all the channels remain unchanged
until the corresponding PWM duty cycle setting registers are modified.
To reduce the data transmission for large quantity of the LED pixel control, 8-bit PWM duty cyle resolution can be
adopted by writing 0 to 12BIT in DIM register. The master only needs to update high 8-bit PWMOUTXn register
to change the brightness of target output channel. The low 4-bit registers PWMLOWOUTXn are ignored. The
PWM duty-cycle calculation is shown in he below equation. When PWMOUTXn is FFh, the duty cycle is 100%
exceptionally.
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D(OUTXn)
where
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PWMOUTXn
256
=
ì100%
(5)
•
•
PWMOUTXn is decimal number from 0 to 255.
X is from A to H, n is 0 or 1 for different output channel.
7.3.3.6 Exponential Brightness Control
The TPS929160-Q1 can also generate PWM duty-cycle output following exponential curve. EXPEN bit selects
the dimming method between linear or exponential. When register EXPEN is set to 1, the integrated look-
up table provides a one-to-one conversion from 8-bit register PWMOUTXn to 12-bit binary code following
exponential increment, as the following figure illustrates. When exponential control path is selected, the
PWMLOWOUTXn data is neglected. By using the exponential brightness control, LED brightness change by
one LSB is invisible to human eyes especially at low brightness range.
4096
3584
3072
2560
2048
1536
1024
512
0
0
32
64
96
128
160
192
224
256
8-Bit PWMOUTXn[7:0]
图 7-5. PWM Duty Cycle vs 8-Bit Code for Exponential Dimming
During power up or in FAIL-SAFE state, the registers EXPEN, and PWMFREQ are automatically reset to their
default values stored in their corresponding EEPROM. Both PWMOUTXn and PWMLOWOUTXn are reset to
00h during power up, but load their EEPROM content in FAIL-SAFE state.
7.3.4 FAIL-SAFE State Operation
The TPS929160-Q1 supports independent channel brightness control through the FlexWire interface. The
brightness of each channel is adjustable according to its DC current register IOUTXn, PWM duty cycle register
PWMOUTXn/PWMLOWOUTXn and channel enable register ENOUTXn setting. The brightness of each channel
reflects to its register setting value immediately after register is successfully updated through the FlexWire
interface by master unit. However, the master unit loses the control for all current channels if the FlexWire
communication fails between master unit and the TPS929160-Q1. For example, the interface cable is broken
by accident. As a consequence, the brightness for all output channels of the TPS929160-Q1 are stuck and the
ON and OFF control for all output channels are missed too. To keep the basic ON and OFF control for each
output channels, the TPS929160-Q1 provides a FAIL-SAFE state when the communication to master is lost. For
detailed description for FAIL-SAFE state entering and quitting criteria, refer to Device Functional Modes.
When the TPS929160-Q1 is entering FAIL-SAFE state, all the registers are set to default value or reloaded from
EEPROM including IOUTXn, PWMOUTXn, PWMLOWOUTXn and ENOUTXn. The pre-programmed settings in
the EEPROM are loaded and the corresponding registers are reset to the default values. The TPS929160-Q1
provides two hardware input pins, FS0 and FS1 to turn on or off corresponding current output channels in
FAIL-SAFE state. Each current output channel has its own register, FSOUTXn to set the mapping to FS0 or
FS1. When FSOUTXn is set to 0, the corresponding current output channel is controlled by FS0 input, otherwise
it is controlled by FS1 input. If the voltage of FSx input is higher than its high threshold, VIH(IO), all current
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output channels mapped to FSx input are turned on. When the voltage of FSx input drops below low threshold,
VIL(IO), all current out channels mapped to FSx input are turned off. The flag register FLAG_EXTFSx shows the
FSx input level at real-time. If FSx pin input voltage is logic high, the FLAG_EXTFSx is set to 1. All FSOUTXn
registers load their corresponding EEPROM data when the TPS929160-Q1 enters FAIL-SAFE state.
The PWM generator and phase shift dimming are both supported in FAIL-SAFE state. 图 7-6 is the signal path
diagram for PWM generator in FAIL-SAFE state.
FSOUTXn
1: FS1
0: FS0
FS1
1
MUX
FS0
PWMOUT
0
AND
ENOUTXn
1: Enabled
0: Disabled
EXPEN
1: LUT EN
0: LUT DIS
Exponential
Look-Up Table
PWMOUTXn[7:0]
1
8
8
12
12-bit PWM
Generator
MUX
0
8
12
12
Linear
12
PWMLOWOUTXn[3:0]
PWMFREQ[3:0]
0h: 200Hz 8h: 1000Hz
1h: 250Hz 9h: 1200Hz
2h: 300Hz Ah: 2000Hz
3h: 350Hz Bh: 4000Hz
4h: 400Hz Ch: 5900Hz
5h: 500Hz Dh: 7800Hz
6h: 600Hz Eh: 9600Hz
7h: 800Hz Fh: 20800Hz
Base Frequency
Internal Oscillator
Digital blocks
图 7-6. Output Current Control Path in FAIL-SAFE State
The FAIL-SAFE state also allows the TPS929160-Q1 operating as a standalone device without master
controlling in the system. The ERR pin is used as a fault indicator to achieve one-fails-all-fail or one-fails-others-
on diagnostics requirement. When low quiescent current in fault mode is required, the device must be set as
one-fails-all-fail. In this case, if fault is triggered, the device goes into low current fault mode.
7.3.5 On-Chip, 8-Bit, Analog-to-Digital Converter (ADC)
The TPS929160-Q1 has integrated a successive-approximation-register (SAR) ADC for diagnostics.
To manually read the voltage of an ADC channel as listed in the below table, the user must write the 5-bit
register ADCCHSEL to select channel. After ADCCHSEL register is written, the one-time ADC conversion starts
and clears FLAG_ADCDONE register. As long as the ADC conversion is completed, the ADC result is available
in an 8-bit register ADC_OUT and sets FLAG_ADCDONE to 1. Reading the ADC_OUT register also clears
FLAG_ADCDONE and starts a new ADC conversion. The FLAG_ADCDONE is set to 0 after reading completion.
TI recommends to write the ADCCHSEL register after turning on or changing current output duty cycle at
assigned OUTXn with delay of one PWM cycle time which is set by the PWMFREQ register.
The analog value can be calculated based on the read back binary code with the below equation and table.
AnalogValue = a + k ì ADC_OUT
(
)
(6)
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where
•
ADC_OUT is a decimal number from 0 to 255.
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表 7-4. ADC Channel
ADC
ADC
CHANNEL
CALCULATION CALCULATION
ADCCHSEL
NAME
COMMENT
NO.
PARAMETER
(a)
PARAMETER
(k)
0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
REF
SUPPLY
VLDO
0.007 V
0.1346 V
0.0465 V
–242.35°C
0.7592 µA
0.1346 V
0.1346 V
RESERVED
0.1346 V
0.1346 V
0.0101 V/LSB
0.1608 V/LSB
0.022 V/LSB
2.152°C/LSB
0.7461 µA/LSB
0.1608 V/LSB
0.1608 V/LSB
RESERVED
Reference voltage
SUPPLY voltage
1
2
5V LDO output voltage
Internal temperature sensor
Reference current
3
TEMPSNS
IREF
4
5
VBAT
VBAT Voltage
6
MAXOUT
RESERVED
OUTA0
Maximum channel output voltage
RESERVED
7
8
0.1608 V/LSB
0.1608 V/LSB
Output voltage channel A0
Output voltage channel A1
RESERVED
9
OUTA1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RESERVED
OUTB0
0.1346 V
0.1346 V
0.1608 V/LSB
0.1608 V/LSB
RESERVED
0.1608 V/LSB
0.1608 V/LSB
RESERVED
0.1608 V/LSB
0.1608 V/LSB
RESERVED
0.1608 V/LSB
0.1608 V/LSB
RESERVED
0.1608 V/LSB
0.1608 V/LSB
RESERVED
0.1608 V/LSB
0.1608 V/LSB
RESERVED
0.1608 V/LSB
0.1608 V/LSB
RESERVED
Output voltage channel B0
Output voltage channel B1
RESERVED
OUTB1
RESERVED
OUTC0
RESERVED
0.1346 V
Output voltage channel C0
Output voltage channel C1
RESERVED
OUTC1
0.1346 V
RESERVED
OUTD0
RESERVED
0.1346 V
Output voltage channel D0
Output voltage channel D1
RESERVED
OUTD1
0.1346 V
RESERVED
OUTE0
RESERVED
0.1608 V/LSB
0.1346 V
Output voltage channel E0
Output voltage channel E1
RESERVED
OUTE1
RESERVED
OUTF0
RESERVED
0.1346 V
Output voltage channel F0
Output voltage channel F1
RESERVED
OUTF1
0.1346 V
RESERVED
OUTG0
RESERVED
0.1346 V
Output voltage channel G0
Output voltage channel G1
RESERVED
OUTG1
0.1346 V
RESERVED
OUTH0
RESERVED
0.1346 V
Output voltage channel H0
Output voltage channel H1
RESERVED
OUTH1
0.1346 V
RESERVED
RESERVED
7.3.5.1 Minimum On Time for ADC Measurement
Because the TPS929160-Q1 supports PWM control for adjusting LED brightness, the voltage on OUTXn is
like a pulse waveform. When the current output is enabled by setting ENOUTXn to 1, the ADC measures the
voltage on assigned OUTXn after the output is turned on with t(BLANK) delay time, which is programmable by
4-bit register BLANK. The minimum current output pulse on assigned OUTXn must be longer than t(BLANK) + 3 ×
t(CONV) to make sure the correct measured result for OUTXn at ON state. When the output is disabled by setting
ENOUTXn to 0, the ADC samples the voltage on assigned OUTXn at OFF state.
TI recommends to set 100% duty cycle on assigned OUTXn for ADC measurement by writing FFh to
PWMOUTXn and 0Fh to PWMLOWOUTXn register when the PWM dimming period t(DIM_cycle) has to be less
than t(BLANK) + 3 × t(CONV)
.
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7.3.5.2 ADC Auto Scan
In ADC auto scan mode, If the MAXOUT channel is selected by writing 06h to ADCCHSEL, the maximum
voltage of OUTXn is recorded into ADC_OUT register. The maximum channel output voltage is available
after at least nine output PWM cycles are completed. The ADC measures every two outputs as one group
when the group is turned on and move to measure the next group in next PWM dimming cycle until all eight
groups are completed no matter in PWM dimming mode or phase shift PWM dimming mode. The device sets
FLAG_ADCDONE to 1 and stops ADC auto scan after the measurements for all eight groups are done. The
FLAG_ADCDONE is cleared to 0 by reading the ADC_OUT, and ADC auto scan restarts again if the data of
ADCCHSEL is still 06h. FLAG_ADCDONE is also cleared to 0 by writing ADCCHSEL register, and ADC restarts
after FLAG_ADCDONE is cleared. The minimum current pulse for each output must be longer than t(BLANK) + 3 ×
t (CONV) in auto scan mode. The channel is skipped if it is disabled in auto scan mode.
Based on the measured maximum output voltage and supply voltage, the microcontroller is able to regulate
supply voltage from previous power stage to minimize the power consumption on the TPS929160-Q1. Basically,
the microcontroller must program the output voltage of previous power stage to be just higher than the measured
maximum channel output voltage plus the required dropout voltage V(OUT_drop) of the TPS929160-Q1. In this
way, the TPS929160-Q1 takes minimum power consumption, and overall power efficiency optimizes.
7.3.5.3 ADC Error
The TPS929160-Q1 integrates a digital comparator to measure the PWM dimming period t(DIM_cycle) and t(BLANK)
+ 3 × t(CONV) at real time when ADC is started by writing ADCCHSEL register or reading ADC_OUT register. The
device stops the ADC measurement and sets the FLAG_ADCERR register to 1 if the t(DIM_cycle) time is measured
less than t(BLANK) + 3 × t(CONV) time. The FLAG_ADCERR register is cleared to 0 by writing 1 to the CLRFAULT
register.
7.3.6 NSTB Output
The TPS929160-Q1 device provides a NSTB output to control external CAN transciever enter into sleep mode.
The NSTB ouput is an open drain structure with internal pulling up path to VLDO, and it is recommended to be
pulled down to GND through an external 100-kΩ resistor. The internal pull up of NSTB output is turned on by
default and only turned off when NSTB register is set to 1h. The pulling up path is turned on again when the
NSTB register is set to 0h. Which means that the NSTB output always exhibits VLDO voltage output after device
is enabled by pulling high EN pin, and it goes to low once the NSTB register is set to 1h or the TPS929160-Q1 is
disabled.
With this NSTB output, the TPS929160-Q1 can set an external CAN transciever such as TCAN1043-Q1 into
sleep mode by controlling the nSTB input pin of TCAN1043-Q1 to minimize the power consumption. The
TCAN1043-Q1 can also remove the pulling up of the EN pin of TPS929160-Q1 by its INH output to shutdown
the TPS929160-Q1 after entering the sleep mode. The TCAN1043-Q1 can be waked up again by a specified
WUP pattern and release INH output to turn on the TPS929160-Q1 as well. 图 7-7 and 图 7-8 are the typical
application and timing diagram for TPS929160-Q1 cooperating with TCAN1043-Q1 to achieve the low current
consumption in sleep mode.
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VSUP
VBAT
INH
TX
EN
TX
RX
TCAN1043-Q1
TPS929160-Q1
RX
VIO
EN
VCC
VLDO
NSTB
NSTB
nSTB
图 7-7. Sleep Mode Typical Application Diagram
Normal Mode
Sleep Mode
Normal Mode
VBAT
VSUP
TCAN1043-Q1
receive WUP
pull up INH
INH set to floating by TCAN1043-Q1
after Tgo-to-sleep time
EN
INH
Tgo-to-sleep
VLDO
VCC/VIO/EN
Write 1 to NSTB register
TPS929160-Q1 set NSTB
to floating
NSTB
nSTB
图 7-8. Sleep Mode Access and Exit Timing Diagram
7.3.7 Diagnostic and Protection in NORMAL state
The TPS929160-Q1 has full-diagnostics coverage for supply voltage, current output, and junction temperature.
In NORMAL state, the device detects all failures and reports the status out through the ERR or FLAG registers,
without any actions taken by the device except VBAT UVLO, supply undervoltage and overtemperature
protection. The master controller must handle all fault actions, for example, retry several times and shut down
the outputs if the error still exists. The fault behavior in NORMAL state can be found in 表 7-6.
7.3.7.1 VBAT Undervoltage Lockout Diagnostics in NORMAL state
When VBAT or VLDO voltage drops below its UVLO threshold, the device enters POR state. Upon voltage
recovery, the device automatically switches to INIT state with FLAG_POR and FLAG_ERR set to 1. The master
controller can write 1 to register CLRPOR to clear the FLAG_POR and FLAG_ERR, and the CLRPOR bit
automatically returns to 0.
7.3.7.2 Low-Supply Warning Diagnostics in NORMAL State
The TPS929160-Q1 continuously monitors the SUPPLY voltage and compares the results with internal threshold
V(LOWSUPTH) set by LOWSUPTH for low-supply voltage warning.
If the supply voltage is lower than threshold, the device pulls ERR pin down with one pulsed current sink for 50
µs to report the fault and set flag registers including FLAG_LOWSUP and FLAG_ERR to 1.
The fault is latched in flag registers. When the supply voltage rises above low-supply warning threshold, the
master controller must write 1 to register CLRFAULT to clear FLAG_LOWSUP and FLAG_ERR. The CLRFAULT
bit automatically returns to 0.
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The low-supply warning is also used to disable the LED open-circuit detection and single-LED short-circuit
detection. When the voltage applied on SUPPLY pin is higher than the threshold V(LOWSUPTH), the TPS929160-
Q1 enables LED open-circuit and single-LED short-circuit diagnosis. When V(SUPPLY) is lower than the threshold
V(LOWSUPTH), the device disables LED-open-circuit detection and single-LED short-circuit diagnosis. Because
when V(SUPPLY) drops below the maximum total LED forward voltage plus required V(OUT_drop) at required
current, the TPS929160-Q1 is not able to deliver sufficient current output. The device pulls the voltage of each
output channel as close as possible to the V(SUPPLY). In this condition, the LED open-circuit fault or single-LED
short-circuit fault can be detected and reported by mistake. Setting the low-supply warning threshold high
enough can avoid the LED open-circuit and single LED short-circuit fault being detected when V(SUPPLY) drops to
low. The V(LOWSUPTH) is programmable from 4 V to 35 V at 1-V interval.
7.3.7.3 Supply Undervoltage Diagnostics in NORMAL State
The TPS929160-Q1 provides internal analog comparator to monitor the supply voltage for undervoltage
protection.
If the supply voltage falls below the internal threshold, V(SUPUV_th_falling), the device pulls the ERR pin low with
constant current sink to report the fault and set flag registers including FLAG_SUPUV and FLAG_ERR to 1.
The supply undervoltage detection is used to disable all current output. When the voltage applied on the
SUPPLY pin is higher than the threshold V(SUPUV_th_rising), the TPS929160-Q1 enables all current outputs. When
V(SUPPLY) is lower than the threshold V(SUPUV_th_falling), the device disables every output to avoid the unwanted
LED flickering or output fault triggered improperly.
The fault is latched in flag registers. When the supply voltage rises above V(SUPUV_th_rising), the master controller
must write register CLRFAULT to 1 to clear FLAG_SUPUV and FLAG_ERR. The CLRFAULT bit automatically
returns to 0.
7.3.7.4 Reference Diagnostics in NORMAL state
The TPS929160-Q1 integrates diagnostics for REF resistor open and short fault. The device monitors the
reference current I(REF) set by external resistor R(REF). The I(REF) can be calculated with the following equation.
V
(REF)
I(REF)
=
R(REF)
(7)
where
V(REF) = 1.235 V typically
•
If the current output from REF pin I(REF) is lower than I(REF_OPEN_th), the reference resistor open-circuit fault
is reported. The reference resistor short-circuit fault is reported if the voltage of REF pin V(REF) is lower than
V(REF_SHORT_th). The device pulls the ERR pin down with constant current sink and set flag registers including
FLAG_REF and FLAG_ERR to 1.
The fault is latched in flag registers. After the REF pin I(REF) and V(REF) recover to normal, the device releases
ERR pin pulldown automatically and the master controller must send CLRFAULT to clear FLAG_REF and
FLAG_ERR. The CLRFAULT automatically returns to 0.
In NORMAL state, the device does not perform any actions automatically when the reference resistor fault is
detected. However, the output can not work properly and the output current can be operating at high current
level. TI recommends for master controller to shut down the device outputs and report error to upper level control
system such as Body Control Module (BCM).
7.3.7.5 Pre-Thermal Warning in NORMAL state
The TPS929160-Q1 has pre-thermal warning at typical 135°C.
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When the junction temperature, T(J), of TPS929160-Q1 rises above pre-thermal warning threshold, the device
reports pre-thermal warning, pull ERR pin with pulsed current sink for 50 µs and sets the flag registers including
FLAG_PRETSD and FLAG_ERR to 1.
The fault is latched in flag registers. When the junction temperature of TPS929160-Q1 falls below pre-thermal
warning threshold, the master controller must write 1 to CLRFAULT register to clear FLAG_PRETSD and
FLAG_ERR. The CLRFAULT bit automatically returns to 0.
When more accurate thermal measurement on LED unit is required, one current output channel can be
sacrificed to provide current bias to external thermal resistor such as PTC or NTC. The voltage of external
thermal resistor can be measured by integrated ADC to acquire the temperature information of thermal resistor
located area. The master controller can determine actions based on the acquired temperature information to turn
off or reduce current output.
7.3.7.6 Overtemperature Protection in NORMAL state
The TPS929160-Q1 has overtemperature protection at T(TSD1), typical 175°C.
When device junction temperature T(J) further rises above overtemperature protection threshold, the device turns
off all output drivers, pulls the ERR pin low with constant current sink to report fault, and sets the flag registers
including FLAG_TSD and FLAG_ERR to 1.
The fault is latched in flag registers. When the junction temperature falls below T(TSD1) – T(TSD1_HYS), the device
resumes all outputs and releases ERR pin pulldown. The master controller must write 1 to CLRFAULT to clear
FLAG_TSD and FLAG_ERR. The CLRFAULT bit automatically returns to 0.
7.3.7.7 Overtemperature Shutdown in NORMAL state
When the T(J) rises too high above T(TSD2), 180°C typically, the TPS929160-Q1 turns off the internal linear
regulator, VLDO output to shutdown all the analog and digital circuit. The ERR pin is pulled down by constant
current sink to report the fault, and the FLAG_POR and FLAG_ERR are all set to 1.
When the T(J) drops below T(TSD2) – T(TSD2_HYS), the TPS929160-Q1 restarts from POR state with all the
registers cleared to default value and ERR pin released. The master controller must write 1 to CLRPOR to clear
both FLAG_POR and FLAG_ERR after fault removal. The CLRPOR bit automatically returns to 0.
7.3.7.8 LED Open-Circuit Diagnostics in NORMAL state
The TPS929160-Q1 integrates LED open-circuit diagnostics to allow users to monitor LED status real time. The
device monitors voltage difference between SUPPLY and OUTXn to judge if there is any open-circuit failure. The
SUPPLY voltage is also monitored in parallel with programmable threshold to determine if supply voltage is high
enough for open-circuit diagnostics.
The open-circuit monitor is only effective during PWM-ON state with programmable minimal pulse width greater
than t(BLANK) + t(OPEN_deg). The t(BLANK) is programmed by register BLANK. If PWM on-time is less than t(BLANK)
+
t(OPEN_deg), the device does not report any open-circuit fault. When the device supply voltage V(SUPPLY) is below
the threshold V(LOWSUPTH) set by register LOWSUPTH, the LED open-circuit is not detected nor reported.
When the voltage difference V(SUPPLY) – V(OUTXn) is below threshold V(OPEN_th_rising) with duration longer than
t(BLANK) + t(OPEN_deg), and the device supply voltage V(SUPPLY) is above the threshold V(LOWSUPTH) set by register
LOWSUPTH, the TPS929160-Q1 pulls the ERR pin down with one pulsed current sink for 50 µs to report fault
and set flag registers including FLAG_OPENOUTXn, FLAG_OUT and FLAG_ERR to 1. In NORMAL state, the
device does not take any actions in response the LED open-circuit fault and waits for the master controller to
determine the protection behavior.
The fault is latched in flag registers. When the voltage difference V(SUPPLY) – V(OUTXn) rises above threshold
V(OPEN_th_rising) with duration longer than t(BLANK) + t(OPEN_deg), or the device supply voltage V(SUPPLY) is below
the threshold V(LOWSUPTH), the master controller must write 1 to CLRFAULT to clear FLAG_OPENOUTXn,
FLAG_OUT and FLAG_ERR. The CLRFAULT bit automatically returns to 0.
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7.3.7.9 LED Short-Circuit Diagnostics in NORMAL state
The TPS929160-Q1 has internal analog comparators to monitor all channel outputs with respect to a fixed
threshold for reporting OUTXn short to GND fault.
The short-circuit detection is only effective during PWM-ON state with programmable minimal pulse width of
t(BLANK) + t(SHORT_deg). The t(BLANK) is programmable by register BLANK. If PWM on-time is less than t(BLANK)
t(SHORT_deg), the device can not report any short-circuit fault.
+
When the voltage V(OUTXn) is below threshold V(SG_th_rising) with duration longer than deglitch timer length of
t(BLANK) + t(SHORT_deg), the device pulls the ERR pin down with pulsed current sink for 50 µs to report fault and set
flag registers including FLAG_SHORTOUTXn, FLAG_OUT and FLAG_ERR. In NORMAL state, the device does
not take any actions in response the LED short-circuit fault and waits for the master controller to determine the
protection behavior.
The fault is latched in flag registers. When the voltage V(OUTXn) rises above threshold V(SG_th_falling) with duration
longer than deglitch timer length of t(BLANK) + t(SHORT_deg), the master controller must write 1 to CLRFAULT to
clear FLAG_SHORTOUTXn, FLAG_OUT and FLAG_ERR. The CLRFAULT bit automatically returns to 0.
7.3.7.10 Single-LED Short-Circuit Detection in NORMAL state
The TPS929160-Q1 also integrates analog comparators to monitor all outputs with respect to two alternative
threshold for single-LED short-circuit diagnostic. Setting the register SLSEN to 1 enables the single-LED short-
circuit detection.
The single-LED, short-circuit detection is only effective during PWM-ON state with programmable minimal pulse
width of t(BLANK) + t(SLS_deg). The t(BLANK) is programmable by register BLANK. If PWM on-time is less than
t(BLANK) + t(SLS_deg), the device cannot report any single-LED short-circuit fault. When the device supply voltage
V(SUPPLY) is below the threshold V(LOWSUPTH) set by register LOWSUPTH, the single-LED short-circuit is not
detected nor reported.
When the voltage V(OUTXn) is below threshold V(SLSTHx) with duration longer than deglitch timer length of
t(BLANK) + t(SLS_deg), and the device supply voltage V(SUPPLY) is above the threshold V(LOWSUPTH) set by register
LOWSUPTH, the device pulls the ERR pin down with pulsed current sink for 50 µs to report fault and set
flag registers including FLAG_SLSOUTXn, FLAG_OUT and FLAG_ERR. The TPS929160-Q1 provides two
alternative thresholds V(SLSTH0) and V(SLSTH1) for single-LED short-circuit detection selected by SLSTHOUTXn
independently for each current output. The V(SLSTH0) is selected for current OUTXn when SLSTHOUTXn is set
to 0, however V(SLSTH1) is selected when SLSLTHOUTXn is set to 1. The actual voltage value for V(SLSTH0)
and V(SLSTH1) is programmable by two 8-bit registers SLSTH0 and SLSTH1 from 2.5 V to 34.375 V at 125-mV
interval. In NORMAL state, the device does not take any actions in response the single-LED short-circuit fault
and waits for the master controller to determine the protection behavior.
The fault is latched in flag registers. When the voltage V(OUTXn) rises above threshold V(SLSTHx) + 275 mV with
duration longer than deglitch timer length of t(BLANK) + t(SLS_deg), or the device supply voltage V(SUPPLY) is below
the threshold V(LOWSUPTH), the master controller must write 1 to register CLRFAULT to clear FLAG_SLSOUTXn,
FLAG_OUT and FLAG_ERR. The CLRFAULT automatically returns to 0.
7.3.7.11 EEPROM CRC Error in NORMAL state
The TPS929160-Q1 implements a EEPROM CRC check after loading the EEPROM code to configuration
register in NORMAL state.
The calculated CRC result is sent to register CALC_EEPCRC and compared to the data in register EEPCRC,
which stores the CRC code for all EEPROM registers except for DIM-R reserved register. The reserved DIM-R
register value is not included in the EEPCRC calculation. The TPS929160-Q1 EEPROM configuration tool are
available on ti.com to help calculate the EEPCRC value. If the code in register CALC_EEPCRC is not matched
to the code in register EEPCRC, the TPS929160-Q1 pulls the ERR pin down with pulsed current sink for 50
µs to report the fault and set the registers including FLAG_EEPCRC and FLAG_ERR to 1. The TPS929160-Q1
only loads EEPROM to corresponding registers one time during initialization state. Parity check is used to detect
whether the internal configuration parameters are correctly loaded from trim EEPROM or not. When there is
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internal trim EEPROM error, the FLAG_EEPPAR is set to 1. The master controller can write 1 to REGDEFAULT
to reset all the regiters to default value and reload the EEPROM to corresponding registers in NORMAL state.
Reloading the EEPROM triggers the EEPROM CRC check.
The master controller must write CLRFAULT to 1 to clear the fault flags, and the CLRFAULT bit automatically
returns to 0.
The CRC code for all the EEPROM registers must be burnt into EEPROM register of EEPCRC in the end of
production line. The CRC code algorithm for multiple bytes of binary data is based on the polynomial, X8 + X5 +
X4 + 1. The CRC code contain 8 bits binary code, and the initial value is FFh. As described in the below figure,
all bits code shift to MSB direction for 1 bit with three exclusive-OR calculation. A new CRC code for one byte
input canbe generated after repeating the 1 bit shift and three exclusive-OR calculation for eight times. Based
on this logic, the CRC code can be calculated for all the EEPROM register byte. When the EEPROM design for
production is finalized, the corresponding CRC code based on the calculation must be burnt to EEPROM register
EEPCRC together with other EEPROM registers in the end of production line. If the DC current for each output
channel must be calibrated in the end of production for different LED brightness bin, the CRC code for each
production devices must be calculated independent and burnt during the calibration. The CRC algorithm must be
implemented into the LED calibration system in the end of production line.
XOR
Bit Input
LSB First
CRC
Bit 0
CRC
Bit 1
CRC
Bit 2
CRC
Bit 6
CRC
Bit 5
CRC
Bit 4
CRC
Bit 3
CRC
Bit 7
XOR
XOR
图 7-9. CRC Algorithm Diagram
7.3.7.12 Communication Loss Diagnostic in NORMAL state
The TPS929160-Q1 monitors the FlexWire interface for the communication with an internal watchdog timer.
Any successful non-broadcast communication with correct CRC and address matching target device
automatically resets the timer. If the watchdog timer overflows, device automatically switches to FAIL-SAFE
state and sets the FLAG_FS to 1. The master controller can access the TPS929160-Q1 and write 1 to CLRFS to
set the device to NORMAL state again when the communication recovers.
The watchdog timer is programmable by 4-bit register WDTIMER. The TPS929160-Q1 can directly enter FAIL-
SAFE states from NORMAL state by burning EEPROM of WDTIMER to Fh. Disabling the watchdog timer by
setting WDTIMER to 0h prevents the device from getting into FAIL-SAFE state.
7.3.7.13 Fault Masking in NORMAL state
The TPS929160-Q1 provides fault masking capability using masking registers. The device is capable of masking
faults by channels or by fault types. The fault masking does not disable diagnostics features but only prevents
fault reporting to FLAG_OUT register, FLAG_ERR register, and ERR output. The below table lists the detailed
description for each fault mask register in NORMAL state.
To disable diagnostics on a single channel, setting DIAGENOUTXn registers to 0 disables open-circuit, LED
short-circuit and single-LED short circuit diagnostics of channel x and thus no fault of this channel is reported to
FLAG_OPENOUTXn, FLAG_SHORTOUTXn, FLAG_SLSOUTXn, FLAG_OUT or FLAG_ERR registers, or to the
ERR output.
表 7-5. Fault Masking in NORMAL state
Fault Detected
Mask Register
MASKLOWSUP = 1
MASKLOWSUP = 0
FLAG Name
ERR PIN
FLAG_LOWSUP = 1
FLAG_ERR = 0
No action
Low-supply warning
FLAG_LOWSUP = 1
FLAG_ERR = 1
One pulse pulled down for 50 μs
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表 7-5. Fault Masking in NORMAL state (continued)
Fault Detected
Mask Register
FLAG Name
ERR PIN
FLAG_SUPUV = 1
FLAG_ERR = 0
MASKSUPUV = 1
No action
Supply undervoltage
Reference fault
FLAG_SUPUV = 1
FLAG_ERR = 1
MASKSUPUV = 0
MASKREF = 1
Constant pulled down
No action
FLAG_REF = 1
FLAG_ERR = 0
FLAG_REF = 1
FLAG_ERR = 1
MASKREF = 0
Constant pulled down
No action
FLAG_PRETSD = 1
FLAG_ERR = 0
MASKPRETSD = 1
MASKPRETSD = 0
MASKTSD = 1
Pre-thermal warning
Overtemperature protection
EEPROM CRC error
FLAG_PRETSD = 1
FLAG_ERR = 1
One pulse pulled down for 50 μs
No action
FLAG_TSD = 1
FLAG_ERR = 0
FLAG_TSD = 1
FLAG_ERR = 1
MASKTSD = 0
Constant pulled down
No action
FLAG_EEPCRC = 1
FLAG_ERR = 0
MASKEEPCRC = 1
MASKEEPCRC = 0
FLAG_EEPCRC = 1
FLAG_ERR = 1
One pulse pulled down for 50 μs
FLAG_OPENOUTXn = 1
FLAG_OUT = 0
FLAG_ERR = 0
MASKOPEN = 1
MASKOPEN = 0
MASKSHORT = 1
MASKSHORT = 0
MASKSLS = 1
No action
LED open-circuit fault
FLAG_OPENOUTXn = 1
FLAG_OUT = 1
FLAG_ERR = 1
One pulse pulled down for 50 μs
No action
FLAG_SHORTOUTXn = 1
FLAG_OUT = 0
FLAG_ERR = 0
LED short-circuit fault
FLAG_SHORTOUTXn = 1
FLAG_OUT = 1
FLAG_ERR = 1
One pulse pulled down for 50 μs
No action
FLAG_SLSOUTXn = 1
FLAG_OUT = 0
FLAG_ERR = 0
Single LED short-circuit fault
FLAG_SLSOUTXn = 1
FLAG_OUT = 1
MASKSLS = 0
One pulse pulled down for 50 μs
FLAG_ERR = 1
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表 7-6. Diagnostics Table in NORMAL State
FAULT TYPE
DETECTION CRITERIA
CONDITIONS
FAULT ACTIONS
FAULT OUTPUT
ERR PIN
RECOVERY
V(VBAT) < V(POR_falling)
or
V(LDO) < V(LDO_POR_falling)
Device switch to INIT state when all
voltage rails are good.
Clear fault flag with CLRPOR.
Device switch to
POR state
FLAG_POR
FLAG_ERR
Constant pulled
down
VBAT UVLO
Automatically recovery upon fault
removal.
Clear fault flag with CLRFAULT.
FLAG_LOWSUP
FLAG_ERR (maskable)
One pulse pulled
down for 50 µs
Low-supply warning
Supply undervoltage
V(SUPPLY) < V(LOWSUPTH)
Disable fault type *
Turn off all outputs
Automatically recovery and release
ERR pin upon fault removal.
Clear fault flag with CLRFAULT.
FLAG_SUPUV
FLAG_ERR (maskable)
Constant pulled
down (maskable)
V(SUPPLY) < V(SUPUV_th_falling)
V(REF) < V(REF_SHORT_th)
or
I(REF) < I(REF_OPEN_th)
Automatically release ERR pin upon
fault removal.
Clear fault flag with CLRFAULT.
FLAG_REF
FLAG_ERR (maskable)
Constant pulled
down (maskable)
Reference fault
No action
No action
FLAG_PRETSD
FLAG_ERR(maskable)
One pulse pulled
down for 50 µs
Pre-thermal warning
T(J) > T(PRETSD)
Clear fault flag with CLRFAULT
Automatically recover upon fault
removal.
Clear fault flag with CLRFAULT.
Overtemperature
protection
FLAG_TSD
FLAG_ERR (maskable)
Constant pulled
down (maskable)
T(J) > T(TSD1)
Turn off all outputs
Device switch to INIT state when all
voltage rails are good.
Clear fault flag with CLRPOR.
Overtemperature
shutdown
FLAG_POR
FLAG_ERR
Constant pulled
down
T(J) > T(TSD2)
Turn off LDO
No action
PWM pulse width greater than
t(BLANK) + t(OPEN_deg)
ENOUTXn = 1
V(SUPPLY) - V(OUTXn) < V(OPEN_th_rising)
and
FLAG_OPENOUTXn
FLAG_OUT (maskable)
FLAG_ERR (maskable)
One pulse pulled
down for 50 µs
(maskable)
LED open-circuit
fault *
Clear fault flag with CLRFAULT
Clear fault flag with CLRFAULT
V(SUPPLY) > V(LOWSUPTH)
DIAGENOUTXn = 1
PWM pulse width greater than
t(BLANK) + t(SHORT_deg)
ENOUTXn = 1
FLAG_SHORTOUTXn
FLAG_OUT (maskable)
FLAG_ERR (maskable)
One pulse pulled
down for 50 µs
(maskable)
LED short-circuit
fault
V(OUTXn) < V(SG_th_rising)
No action
DIAGENOUTXn = 1
PWM pulse width greater than
t(BLANK)+ t(SLS_deg)
ENOUTXn = 1
DIAGENOUTXn = 1
SLSEN = 1
V(OUTXn) < V(SLSTH)
and
V(SUPPLY) > V(LOWSUPTH)
FLAG_SLSOUTXn
FLAG_OUT
FLAG_ERR (maskable)
Single-LED short
circuit *
One pulse pulled
down for 50 µs
No action
No action
Clear fault flag with CLRFAULT
Clear fault flag with CLRFAULT
One pulse pulled
down for 50 µs
(maskable)
FLAG_EEPCRC
FLAG_ERR (maskable)
EEPROM CRC error
CALC_EEPCRC is different EEPCRC
T(WDTIMER) overflows
Communication loss
fault
Enter FAIL-SAFE
states
Set CLRFS to 1 to set the device to
NORMAL state
FLAG_FS
No action
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7.3.8 Diagnostic and Protection in FAIL-SAFE states
In FAIL-SAFE state, the TPS929160-Q1 also detects all failures and reports the status out by ERR or FLAG
registers. 表 7-8 lists the summary of the fault detection criteria and the device behavior after the fault is
detected. Basically, the TPS929160-Q1 actively takes the action to turn off the failed output channels, retry on
the failed channels, or restart the device to keep device operating without controlled by master. The EEPROM
register OFAF can be used to set the fault behavior for LED open-circuit, LED short-circuit and single-LED
short-circuit faults. The one-fails-all-fail behavior is selected when the register OFAF is burnt to 1; otherwise,
the one-fails-others-on behavior is chosen. The TPS929160-Q1 turns off all output channels when any type
of LED fault is detected on any one of output channels for one-fails-all-fail behavior. On the other hand, the
TPS929160-Q1 only turns off the failed channel and keeps all other normal channels on.
In FAIL-SAFE state, the fault flag registers of TPS929160-Q1 still can be accessed again through FlexWire
interface in case the communication is rebuilt.
7.3.8.1 Supply Undervoltage Lockout Diagnostics in FAIL-SAFE states
When VBAT or VLDO voltage drops below its UVLO threshold, the device enters POR state. Upon voltage
recovery, the device automatically switches to INIT state with FLAG_POR and FLAG_ERR set to 1. The master
controller can write 1 to register CLRPOR to clear the FLAG_POR and FLAG_ERR, and the CLRPOR bit
automatically returns to 0.
7.3.8.2 Low-Supply Warning Diagnostics in FAIL-SAFE states
The TPS929160-Q1 continuously monitors the SUPPLY voltage and compares the results with internal threshold
V(LOWSUPTH) set by LOWSUPTH for low-supply voltage warning.
If the supply voltage is lower than threshold, the device sets flag registers including FLAG_LOWSUP and
FLAG_ERR to 1.
The fault is latched in flag registers. When the supply voltage rises above low-supply warning threshold, the
master controller must write register CLRFAULT to 1 to reset FLAG_LOWSUP and FLAG_ERR. The CLRFAULT
bit automatically returns to 0.
The low-supply warning is also used to disable the LED open-circuit detection and single-LED short-circuit
detection. When the voltage applied on SUPPLY pin is higher than the threshold V(LOWSUPTH), the TPS929160-
Q1 enables LED open-circuit and single-LED short-circuit diagnosis. When V(SUPPLY) is lower than the threshold
V(LOWSUPTH), the device disables LED-open-circuit detection and single-LED short-circuit diagnosis. Because
when V(SUPPLY) drops below the maximum total LED forward voltage plus required V(OUT_drop) at required
current, the TPS929160-Q1 is not able to deliver sufficient current output to pull the voltage of each output
channel as close as possible to the V(SUPPLY). In this condition, the LED open-circuit fault or single-LED short-
circuit fault might be detected and reported by mistake. Setting the low-supply warning threshold high enough
can avoid the LED open-circuit and single LED short-circuit fault being detected when V(SUPPLY) drops to low.
The V(LOWSUPTH) is programmable from 4 V to 35 V at 1-V interval.
7.3.8.3 Supply Undervoltage Diagnostics in FAIL-SAFE State
The TPS929160-Q1 provides internal analog comparator to monitor the supply voltage for undervoltage
protection in FAIL-SAFE state.
If the supply voltage falls below the internal threshold, V(SUPUV_th_falling), the device pulls the ERR pin low with
constant current sink to report the fault and set flag registers including FLAG_SUPUV and FLAG_ERR to 1.
The supply undervoltage detection is used to disable all current output. When V(SUPPLY) is lower than the
threshold V(SUPUV_th_falling), the device disables every outputs to avoid the unwanted LED flickering or output fault
triggered improperly. When the voltage applied on SUPPLY pin rises above the threshold V(SUPUV_th_rising), the
TPS929160-Q1 enables all current outputs automatically.
The fault is latched in flag registers. When the supply voltage rises above V(SUPUV_th_rising), the TPS929160-Q1
releases ERR pin and the master controller must write register CLRFAULT to 1 to clear FLAG_SUPUV and
FLAG_ERR. The CLRFAULT bit automatically returns to 0.
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7.3.8.4 Reference Diagnostics in FAIL-SAFE states
The TPS929160-Q1 integrates diagnostics for REF resistor open and short fault in FAIL-SAFE state. The device
monitors the reference current I(REF) set by external resistor R(REF). Use 方程式 7 to calculate the I(REF)
.
If the current output from REF pin I(REF) is lower than I(REF_OPEN_th), the reference resistor open-circuit fault
is reported. The reference resistor short-circuit fault is reported if the voltage of REF pin V(REF) is lower than
V(REF_SHORT_th). The device pulls the ERR pin down with constant current sink and sets flag registers including
FLAG_REF and FLAG_ERR to 1.
The fault is latched in flag registers. After the REF pin I(REF) and V(REF_SHORT_th) recover to normal, the device
releases ERR pin pulldown automatically and the master controller must send CLRFAULT to clear FLAG_REF
and FLAG_ERR. The CLRFAULT automatically returns to 0.
In FAIL-SAFE state, the device turns off all output channels when reference fault is detected. The device
automatically recovers and turns on all enabled channel after fault removal.
7.3.8.5 Pre-Thermal Warning in FAIL-SAFE state
The TPS929160-Q1 has pre-thermal warning at typical 135°C in FAIL-SAFE state.
When the junction temperature T(J) of TPS929160-Q1 rises above pre-thermal warning threshold, the device
reports pre-thermal warning and sets the flag registers including FLAG_PRETSD and FLAG_ERR to 1.
The fault is latched in flag registers. When the junction temperature of TPS929160-Q1 falls below pre-thermal
warning threshold, the master controller must write 1 to CLRFAULT register to clear FLAG_PRETSD and
FLAG_ERR. The CLRFAULT bit automatically returns to 0.
7.3.8.6 Overtemperature Protection in FAIL-SAFE state
The TPS929160-Q1 has overtemperature protection at T(TSD1), typical 175°C in FAIL-SAFE state.
When device junction temperature T(J) further rises above overtemperature protection threshold, the device turns
off all output drivers, pulls the ERR pin low with constant current sink to report fault, and sets the flag registers
including FLAG_TSD and FLAG_ERR to 1.
The fault is latched in flag registers. When the junction temperature falls below T(TSD1) – T(TSD1_HYS), the device
resumes all outputs and releases ERR pin pulldown. The master controller must write 1 to CLRFAULT to clear
FLAG_TSD and FLAG_ERR. The CLRFAULT bit automatically returns to 0.
7.3.8.7 Overtemperature Shutdown in FAIL-SAFE state
When the T(J) rises too high above T(TSD2), typical 180°C typically, the TPS929160-Q1 turns off the internal linear
regulator, VLDO output to shutdown all the analog and digital circuit. The ERR pin is pulled down by constant
current sink to report the fault, and the FLAG_POR and FLAG_ERR are all set to 1.
When the T(J) drops below T(TSD2) – T(TSD2_HYS), the TPS929160-Q1 restarts from POR state with all the
registers cleared to default value and ERR pin released. The master controller must write 1 to CLRPOR to clear
both FLAG_POR and FLAG_ERR after fault removal. The CLRPOR bit automatically returns to 0.
7.3.8.8 LED Open-Circuit Diagnostics in FAIL-SAFE state
The TPS929160-Q1 integrates LED open-circuit diagnostics to allow users to monitor LED status real time in
FAIL-SAFE state. The device monitors voltage difference between SUPPLY and OUTXn to judge if there is any
open-circuit failure. The SUPPLY voltage is also monitored in parallel with programmable threshold to determine
if supply voltage is high enough for open-circuit diagnostics.
The open-circuit monitor is only effective during PWM-ON state with programmable minimal pulse width greater
than t(BLANK) + t(OPEN_deg). The t(BLANK) is programmed by register BLANK. If PWM on-time is less than t(BLANK)
+
t(OPEN_deg), the device does not report any open-circuit fault. When the device supply voltage V(SUPPLY) is below
the threshold V(LOWSUPTH) set by register LOWSUPTH, the LED open-circuit fault is not detected nor reported.
When the voltage difference V(SUPPLY) – V(OUTXn) is below threshold V(OPEN_th_rising) with duration longer
than t(BLANK) + t(OPEN_deg), and the device supply voltage V(SUPPLY) is above the threshold V(LOWSUPTH), the
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TPS929160-Q1 pulls the ERR pin down with constant current sink to report fault and set flag registers including
FLAG_OPENOUTXn, FLAG_OUT and FLAG_ERR to 1. In FAIL-SAFE state, the TPS929160-Q1 shuts down
the normal current regulation and PWM dutycycle for the error output, then the device sources a current I(RETRY)
to faulty output every t(SLS_Retry), 10 ms for retrying. I(RETRY) is programed by IRETRY register. The current
I(RETRY) can be calculated with the below equation. When the voltage difference V(SUPPLY) – V(OUTXn) of error
output rises above threshold V(OPEN_th_rising) with duration longer than t(BLANK) + t(OPEN_deg), or the supply voltage
V(SUPPLY) is above the threshold V(LOWSUPTH), the device automatically resumes the normal current and PWM
duty cycle setup and releases the ERR pin.
IRETRY ì 4 + 4
64
I(RETRY)
=
ìI(FULL _RANGE)
(8)
where
•
•
IRETRY is programmable from 0 to 15.
Use 方程式 1 to calculate I(FULL_RANGE)
.
The fault is latched in flag registers. When the open-circuit failure is removed, the master controller must write
1 to CLRFAULT to clear FLAG_OPENOUTXn, FLAG_OUT and FLAG_ERR. The CLRFAULT bit automatically
returns to 0.
7.3.8.9 LED Short-Circuit Diagnostics in FAIL-SAFE state
The TPS929160-Q1 has internal analog comparators to monitor all channel outputs with respect to a fixed
threshold for reporting OUTXn short to GND fault in FAIL-SAFE state.
The short-circuit detection is only effective during PWM-ON state with programmable minimal pulse width of
t(BLANK) + t(SHORT_deg). The t(BLANK) is programmable by register BLANK. If PWM on-time is less than t(BLANK)
t(SHORT_deg), the device cannot report any short-circuit fault.
+
When the voltage V(OUTXn) is below threshold V(SG_th_rising) with duration longer than deglitch timer length of
t(BLANK) + t(SHORT_deg), the device pulls ERR pin down with constant current sink to report fault and set flag
registers including FLAG_SHORTOUTXn, FLAG_OUT and FLAG_ERR. In FAIL-SAFE state, the TPS929160-
Q1 shuts down the normal current regulation and PWM duty cycle for the faulty output, then the device sources
a pulse current to faulty output every t(SLS_Retry), 10 ms for retrying. I(RETRY) is programed by IRETRY register.
Use 方程式 8 to calculate the current, I(RETRY). When the voltage V(OUTXn) of error output rises above threshold
V(SG_th_falling) with duration longer than t(BLANK) + t(SHORT_deg), the device automatically resumes the normal
current and PWM dutycycle setup and releases the ERR pin.
The fault is latched in flag registers. When the short-circuit failure is removed, the master controller must write
1 to CLRFAULT to clear FLAG_OPENOUTXn, FLAG_OUT and FLAG_ERR. The CLRFAULT bit automatically
returns to 0.
7.3.8.10 Single-LED Short-Circuit Detection in FAIL-SAFE state
The TPS929160-Q1 also integrates analog comparators to monitor all outputs with respect to two alternative
threshold for single-LED short-circuit diagnostic in FAIL-SAFE state. Setting the register SLSEN to 1 enables the
single-LED short-circuit detection.
The single-LED short-circuit detection is only effective during PWM-ON state with programmable minimal pulse
width of t(BLANK) + t(SLS_deg). The t(BLANK) is programmable by register BLANK. If PWM on-time is less than
t(BLANK) + t(SLS_deg), the device cannot report any single-LED short-circuit fault. When the device supply voltage
V(SUPPLY) is below the threshold V(LOWSUPTH) set by register LOWSUPTH, the single-LED short-circuit is not
detected nor reported.
When the voltage V(OUTXn) is below threshold V(SLSTHx) with duration longer than deglitch timer length of t(BLANK)
+ t(SLS_deg), and the device supply voltage V(SUPPLY) is above the threshold V(LOWSUPTH), the device pulls the
ERR pin down with constant current sink to report fault and set flag registers including FLAG_SLSOUTXn,
FLAG_OUT and FLAG_ERR. The TPS929160-Q1 provides two alternative threshold V(SLSTH0) and V(SLSTH1)
for single-LED short-circuit detection selected by SLSTHOUTXn independently for each current output. The
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V(SLSTH0) is selected for current OUTXn when LSTHOUTXn is set to 0, however V(SLSTH1) is selected when
SLSLTHOUTXn is set to 1. The actual voltage value for V(SLSTH0) and V(SLSTH1) is programmable by two 8-bit
registers SLSTH0 and SLSTH1 from 2.5 V to 34.375 V at 125-mV interval. In FAIL-SAFE state, the TPS929160-
Q1 shuts down the normal current regulation and PWM duty cycle for the faulty output, then the device sources
a pulse current, I(OUTXn) programed by IOUTXn register to the faulty output every t(SLS_Retry), 10 ms for retrying.
When the voltage V(OUTXn) of error output rises above threshold V(SLSTHx) + 275 mV with duration longer than
t(BLANK) + t(SLS_deg) during retrying, or the supply voltage V(SUPPLY) is below the threshold V(LOWSUPTH), the device
automatically resumes the normal current and PWM dutycycle setup and releases the ERR pin.
The fault is latched in flag registers. When the single-LED short-circuit fault is removed, the master controller
must write 1 to register CLRFAULT to clear FLAG_SLSOUTXn, FLAG_OUT and FLAG_ERR. The CLRFAULT
automatically returns to 0.
7.3.8.11 EEPROM CRC Error in FAIL-SAFE state
The TPS929160-Q1 automatically reloads all EEPROM code into the corresponding configuration registers
every time after entering the FAIL-SAFE state. The TPS929160-Q1 implements a EEPROM CRC check after
loading the EEPROM code to configuration register in FAIL-SAFE state. The calculated CRC results are sent
to register CALC_EEPCRC and compared to the data in EEPROM register EEPCRC, which stores the CRC
code for all EEPROM registers except for DIM-R reserved register. The reserved DIM-R register value is not
included in the EEPCRC calculation. The TPS929160-Q1 EEPROM configuration tool are available on ti.com to
help calculate the EEPCRC value. If the code in register CALC_EEPCRC is not matched to the code in register
EEPCRC, the TPS929160-Q1 turns off all channels output, pulls the ERR pin down with constant current sink to
report the fault, and sets the registers including FLAG_EEPCRC and FLAG_ERR to 1. The CRC code for all the
EEPROM registers must be burnt into EEPROM register EEPCRC in the end of production line. The CRC code
algorithm is described in EEPROM CRC Error in NORMAL state.
7.3.8.12 Fault Masking in FAIL-SAFE state
The TPS929160-Q1 provides fault masking capability using masking registers. The device is capable of masking
faults by channels or by fault types. The fault masking does not disable diagnostics features but only prevents
fault reporting to FLAG_OUT register, FLAG_ERR register, and ERR output. The below table gives the detailed
description for each fault mask register in NORMAL state.
To disable diagnostics on a single channel in FAIL-SAFE state, burning EEPROM of DIAGENOUTXn registers
to 0 disables open-circuit, LED short-circuit and single-LED short-circuit diagnostics of channel x, and thus no
fault of this channel is reported to FLAG_OPENOUTXn, FLAG_SHORTOUTXn, FLAG_SLSOUTXn, FLAG_OUT
or FLAG_ERR registers, or to the ERR output.
表 7-7. Fault Masking in FAIL-SAFE State
Fault Detected
Mask Register
FLAG Name
ERR PIN
FLAG_LOWSUP = 1
FLAG_ERR = 0
MASKLOWSUP = 1
No action
No action
No action
Low-supply warning
FLAG_LOWSUP = 1
FLAG_ERR = 1
MASKLOWSUP = 0
MASKSUPUV = 1
MASKSUPUV = 0
MASKREF = 1
FLAG_SUPUV = 1
FLAG_ERR = 0
Supply undervoltage
Reference fault
FLAG_SUPUV = 1
FLAG_ERR = 1
Constant pulled down
No action
FLAG_REF = 1
FLAG_ERR = 0
FLAG_REF = 1
FLAG_ERR = 1
MASKREF = 0
Constant pulled down
No action
FLAG_PRETSD = 1
FLAG_ERR = 0
MASKPRETSD = 1
MASKPRETSD = 0
Pre-thermal warning
FLAG_PRETSD = 1
FLAG_ERR = 1
No action
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表 7-7. Fault Masking in FAIL-SAFE State (continued)
Fault Detected
Mask Register
FLAG Name
ERR PIN
FLAG_TSD = 1
FLAG_ERR = 0
MASKTSD = 1
No action
Overtemperature protection
EEPROM CRC error
FLAG_TSD = 1
FLAG_ERR = 1
MASKTSD = 0
Constant pulled down
No action
FLAG_EEPCRC = 1
FLAG_ERR = 0
MASKEEPCRC = 1
MASKEEPCRC = 0
FLAG_EEPCRC = 1
FLAG_ERR = 1
Constant pulled down
FLAG_OPENOUTXn = 1
FLAG_OUT = 0
FLAG_ERR = 0
MASKOPEN = 1
MASKOPEN = 0
MASKSHORT = 1
MASKSHORT = 0
MASKSLS = 1
No action
LED open-circuit fault
FLAG_OPENOUTXn = 1
FLAG_OUT = 1
FLAG_ERR = 1
Constant pulled down
No action
FLAG_SHORTOUTXn = 1
FLAG_OUT = 0
FLAG_ERR = 0
LED short-circuit fault
FLAG_SHORTOUTXn = 1
FLAG_OUT = 1
FLAG_ERR = 1
Constant pulled down
No action
FLAG_SLSOUTXn = 1
FLAG_OUT = 0
FLAG_ERR = 0
Single LED short-circuit fault
FLAG_SLSOUTXn = 1
FLAG_OUT = 1
MASKSLS = 0
Constant pulled down
FLAG_ERR = 1
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表 7-8. Diagnostics Table in FAIL-SAFE state
FAULT TYPE
DETECTION CRITERIA
CONDITIONS
FAULT ACTIONS
FAULT OUTPUT
ERR PIN
RECOVERY
V(VBAT) < V(POR_falling)
or
V(LDO) < V(LDO_POR_falling)
Device switch to INIT state when
all voltage rails are good.
Clear fault flag with CLRPOR.
Device switch to FLAG_POR
POR state FLAG_ERR
Constant pulled
down
VBAT UVLO
Automatically recovery upon fault
removal.
Clear fault flag with CLRFAULT.
Low-supply
warning
Disable fault type FLAG_LOWSUP
V(SUPPLY) < V(LOWSUPTH)
No action
*
FLAG_ERR (maskable)
Automatically recovery and
release ERR pin upon fault
FLAG_ERR (maskable) down (maskable) removal.
Clear fault flag with CLRFAULT.
Supply
undervoltage
Turn off all
outputs
FLAG_SUPUV
Constant pulled
V(SUPPLY) < V(SUPUV_th_falling)
Automatically recover and
release ERR pin upon fault
FLAG_ERR (maskable) down (maskable) removal.
Clear fault flags with CLRFAULT.
V(REF) < V(REF_SHORT_th)
or
I(REF) < I(REF_OPEN_th)
Turn off all
outputs
FLAG_REF
Constant pulled
Reference fault
Pre-thermal
warning
FLAG_PRETSD
FLAG_ERR(maskable)
T(J) > T(PRETSD)
No action
No action
Clear fault flag with CLRFAULT
Automatically recover and
release ERR pin upon fault
FLAG_ERR (maskable) down (maskable) removal.
Clear fault flags with CLRFAULT.
Overtemperature
protection
Turn off all
outputs
FLAG_TSD
Constant pulled
T(J) > T(TSD1)
Device switch to INIT state when
all voltage rails are good.
Clear fault flag with CLRPOR.
Overtemperature
shutdown
FLAG_POR
FLAG_ERR
Constant pulled
down
T(J) > T(TSD2)
Turn off LDO
PWM pulse width greater than
t(BLANK) + t(OPEN_deg)
ENOUTXn = 1
Automatically recover and
release ERR pin upon fault
down (maskable) removal.
V(SUPPLY) - V(OUTXn) < V(OPEN_th_rising)
and
Turn off the failed FLAG_OPENOUTXn
outputs and retry FLAG_OUT (maskable)
LED open-circuit
fault *
Constant pulled
V(SUPPLY) > V(LOWSUPTH)
every 10 ms
FLAG_ERR (maskable)
DIAGENOUTXn = 1
Clear fault flags with CLRFAULT.
PWM pulse width greater than
t(BLANK) + t(SHORT_deg)
ENOUTXn = 1
Automatically recover and
release ERR pin upon fault
down (maskable) removal.
Turn off the failed FLAG_SHORTOUTXn
outputs and retry FLAG_OUT (maskable)
LED short-circuit
fault
Constant pulled
V(OUTXn) < V(SG_th_rising)
every 10 ms
FLAG_ERR (maskable)
DIAGENOUTXn = 1
Clear fault flags with CLRFAULT.
PWM pulse width greater than
t(BLANK)+ t(SLS_deg)
ENOUTXn = 1
DIAGENOUTXn = 1
SLSEN = 1
Automatically recover and
release ERR pin upon fault
removal.
V(OUTXn) < V(SLSTHx)
and
V(SUPPLY) > V(LOWSUPTH)
Turn off the failed FLAG_SLSOUTXn
outputs and retry FLAG_OUT (Maskable)
Auto single-LED
short-circuit *
Constant pulled
down
every 10 ms
FLAG_ERR (Maskable)
Clear fault flags with CLRFAULT.
EEPROM CRC
error
Turn off all
outputs
FLAG_EEPCRC
FLAG_ERR (maskable) down (maskable)
Constant pulled
CALC_EEPCRC is different EEPCRC
Clear fault flag with CLRFAULT
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7.3.9 OFAF Setup In FAIL-SAFE state
The TPS929160-Q1 has a unique setup for failure behavior in FAIL-SAFE state. If there is a failure detected in
FAIL-SAFE state, the TPS929160-Q1 automatically reacts to the failure. The register OFAF determines whether
the result behavior of output failure is one-fails-all-fail or one-fails-others-on.
In FAIL-SAFE state, the TPS929160-Q1 shuts down all enabled current outputs except the faulty output when
OFAF is set to 1. Otherwise the TPS929160-Q1 keeps regulation for all enable current outputs except the faulty
output when OFAF is set to 0. 表 7-9 provides details.
7.3.10 ERR Output
The ERR pin is a programmable fault indicator pin. This pin can be used as an interrupt output to master
controller in case there is any fault in NORMAL state. In FAIL-SAFE states, the ERR pin can be used as an
output to other ERR pin of other TPS929160-Q1 to achieve one-fails-all-fail at system level. The ERR pin is an
open-drain output with current limit up to IPD(ERR). TI recommends a < 10-kΩ external pullup resistor from the
ERR pin to the same IO voltage of the master controller.
In NORMAL state, when a fault is triggered, depending on the fault type, the ERR pin is either pulled down
constantly or pulled down for a single pulse. After an ERR output is triggered, the master controller must take
action to deal with the failure and reset the fault flag. For non-critical faults, the TPS929160-Q1 pulls down the
ERR pin with a duration of 50 µs and release; for critical faults, device constantly pulls down ERR as described
in 表 7-6. In NORMAL state, basically, the TPS929160-Q1 only reports the faults to the master controller for
most of the failure and takes no actions except supply or LDO UVLO, reference fault, and overtemperature. The
master controller determines what action to take according to the type of the failure.
The TPS929160-Q1 provides a forced-error feature to validate the error feedback-loop integrity in NORMAL
state. In NORMAL state, if the microcontroller sets FORCEERR to 1, the FLAG_ERR is set 1 and pulls down
ERR output with a pulse of 50 µs accordingly. The FORCEERR automatically returns to 0.
In FAIL-SAFE states, the ERR pin is used as fault bus. When there is any output failure reported, the ERR is
pulled down by internal current sink IPD(ERR). The TPS929160-Q1 monitors the voltage of the ERR pin. If the
one-fails-all-fail diagnostics is enabled by setting register OFAF to 1, all current output channels are turned off,
as well as diagnostics, when the ERR pin voltage is low. If register OFAF is 0, the device only turns off the failed
channel with alive channels diagnostics enabled.
表 7-9. One-Fails-All-Fail Feature in Fail-Safe State
OFAF = 1
OFAF = 0
All OUT channel OFF except failure detected
OUT retries every 10 ms
ERR pulled low internally
ERR pulled low externally
Only failure detected OUT OFF
All OUT channel ON
All OUT channel OFF
If multiple TPS929160-Q1 devices are used in one application, tying the ERR pins together achieves the
one-fails-all-fail behavior in FAIL-SAFE states without master controlling. Any one of TPS929160-Q1 reports fault
by pulling the ERR pin to low, and the low voltage on ERR bus is detected by other TPS929160-Q1 as 图 7-10
illustrated. If the register OFAF is set to 1 for all TPS929160-Q1 devices having the ERR pins tied together, all
TPS929160-Q1 devices turn off current for all output channels.
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VIO
10 k
TPS929160-Q1
ERR
Digital
Core
FLAG_ERR
TPS929160-Q1
ERR
Digital
Core
FLAG_ERR
Analog blocks
图 7-10. ERR Internal Block Diagram
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7.4 Device Functional Modes
POR
POR State
(POR)
EN = Logic High
VBAT Good and
LDO Good
Initialization State
(INIT)
Configurable Init Delay
INITTIMER
0h: 0ms 8h: 200us
1h: 50ms 9h: 100us
2h: 20ms Ah: 50us
3h: 10ms Bh: 50us
4h: 5ms
5h: 2ms
6h: 1ms
Ch: 50us
Dh: 50us
Eh: 50us
WDTimer overflows or
FORCEFS = 1
7h: 500us Fh: 50us
Normal State
(NORMAL)
Fail-Safe State
(FAILSAFE)
Clear Fail-safe
CLRFS = 1
Channel Directly
Controlled by FS0 or FS1
pins
EEPROM Program Sequence:
Write serial code to EEPGATE
EEPMODE = 1
EEPMODE = 0
WDTimer
WDTIMER
0h: Disable 8h: 50ms
Program State
(PROG)
1h: 200us
2h: 500us
3h: 1ms
9h: 100ms
Ah: 200ms
Bh: 500ms
4h: 2ms
5h: 5ms
6h: 10ms
7h: 20ms
Ch: Direct to FS
Dh: Direct to FS
Eh: Direct to FS
Fh: Direct to FS
Functional states
图 7-11. Device Functional Mode Statemachine
7.4.1 POR State
Upon power up, the TPS929160-Q1 enters POWER_ON_RESET (POR) state. In this state, registers are
cleared to default value, outputs are disabled, and the device cannot be accessed through the FlexWire
interface.
After both the VBAT input and the LDO output are above their UVLO threshold, the device switches to
INITIALIZATION state (INIT). If any of the supply fails below UVLO threshold or EN pin is pulled low in other
states, the device immediately switches to POR state.
7.4.2 INITIALIZATION state
The INITIALIZATION state is designed to allow master controller to have enough time to power up before the
device automatically gets into FAIL-SAFE states. INIT mode has a configurable delay programmed by 4-bit
register INITTIMER. After the delay counter is reached, the device changes to NORMAL state. In INIT state,
the communication between master controller and the TPS929160-Q1 is enabled through FlexWire interface.
In INITIALIZATION state, device automatically load register map default values, which can be programmed
in corresponding EEPROM. The master controller sets CLRPOR to 1 in INITIALIZATION state, the device
immediately switches to NORMAL state. Only write CLRPOR to TPS929160-Q1 in INITIALIZATION state.
7.4.3 NORMAL state
After the TPS929160-Q1 is in NORMAL state, the device operates under master control for LED animation
and diagnostics using a FlexWire interface. The TPS929160-Q1 integrates a watchdog timer to monitor the
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communication on FlexWire. The watchdog timer is programmable by a 4-bit register WDTIMER for 13 options.
The timer in TPS929160-Q1 starts to count when there is no instruction received from the master controller.
The TPS929160-Q1 enters FAIL-SAFE states when the timer overflows. The device can be also forced into
FAIL-SAFE states anytime in NORMAL state by setting FORCEFS to 1. The FORCEFS register automatically
returns to 0.
7.4.4 FAIL-SAFE state
When the TPS929160-Q1 is entering FAIL-SAFE state from NORMAL state, all the registers are set to default
value or reloaded from EEPROM.
The Flexwire interface keeps alive in FAIL-SAFE state. Setting FORCEFS to 1 forces the device into FAIL-SAFE
state from NORMAL state. The TPS929160-Q1 can quit from FAIL-SAFE state to NORMAL state by setting
CLRFS to 1 with FLAG_FS register cleared.
7.4.5 PROGRAM state
The TPS929160-Q1 can enter EEPROM PROGRAM state by writing multiple configuration registers to
EEPGATE and setting 1 to EEPMODE. For details of getting into PROGRAM state, refer to EEPROM
Programming.
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7.5 Programming
7.5.1 FlexWire Protocol
7.5.1.1 Protocol Overview
The FlexWire is a UART-based protocol supported by most microcontroller units (MCU). Each frame contains
multiple bytes started with a synchronization byte. The synchronization byte allows LED drivers to synchronize
with master MCU frequency, therefore saving the extra cost on high precision oscillators that are commonly used
in UART / CAN interfaces. Each byte has 1 start bit, 8 data bits, 1 stop bit, no parity check. The LSB data follows
the start bit as the below figure describes. The FlexWire supports adaptive communication frequency ranging
from 10 kHz to 1 MHz. The protocol supports master-slave with star-connected topology.
Start
Stop
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
图 7-12. One Byte Data Structure
The FlexWire is designed robust for automotive environment. After the slave device receives a communication
frame, it firstly verifies its CRC byte. Only when CRC is verified, the slave device sends out response frame
and clears the watchdog timer. In addition, if one communication frame is interrupted in the middle without any
bus toggling for a period longer than timeout timer t(DBWTIMER), the TPS929160-Q1 resets the communication
and waits for next communication starting from synchronization byte. It is also required for idle period between
bytes within t(DBWTIMER). The timeout timer t(DBWTIMER) is programmable by configuration register DBWTIMER. TI
recommends using a longer timeout setting for low baud rate communication to avoid unintended timeout and
using a shorter timeout setting for high baud rate communication.
If communication CRC check fails, the TPS929160-Q1 ignores the message without sending the feedback. The
master does not receive any feedback if the communication is unsuccessful. In this case, the communication can
be reset by keeping communication bus idle for t(DBWTIMER), which forces the TPS929160-Q1 to clear its cache
and be ready for new communication.
FlexWire supports both write and readback. Both write or readback communication supports burst mode for high
throughput and single-byte mode. 图 7-13 describes the frame structure of a typical single-byte write action. The
master frame consists of SYNC, DEV_ADDR, REG_ADDR, DATA and CRC bytes. After CRC is verified, the
slave immediately feeds back ACK byte. 图 7-14 describes the frame structure of a typical single-byte readback
action. The master frame consists of SYNC, DEV_ADDR, REG_ADDR, and CRC bytes. After CRC is verified,
the slave immediately feeds back DATA and ACK bytes.
SYNC
DEV_ADDR
REG_ADDR
DATA
CRC
RX
STATUS
CRC
TX
图 7-13. Single-Byte Write Command with Status Feedback
SYNC
DEV_ADDR
REG_ADDR
CRC
RX
TX
DATA
CRC
图 7-14. Single-Byte Readback Command
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表 7-10. Frame-Byte Description
BYTE NAME
SYNC
LENGTH (byte)
DESCRIPTION
Synchronization byte from master
Device address bit, r/w, broadcast, burst mode
Register address
1
DEV_ADDR
REG_ADDR
DATA_N
1
1
Variable (1, 4, 16, 24)
N-th byte data content
Cyclic redundancy check (CRC) for DEV_ADDR, REG_ADDR and all
DATA bytes
CRC
1
1
STATUS
Acknowledgment (Return FLAG_ERR register value)
7.5.1.2 UART Interface Address Setting
Each FlexWire bus supports maximum 16 slave devices. The TPS929160-Q1 has three pinouts including
ADDR3, ADDR2, ADDR1, and ADDR0 for slave address configuration. There are additional 4-bit EEPROM
register to program the slave address of the TPS929160-Q1. The register INTADDR sets the device slave
address by either address pins setup or internal EEPROM register code.
If INTADDR is 1, the device uses the binary code in register DEVADDR[3:0] as slave address as shown in the
below table.
If INTADDR is 0, the device uses external inputs on ADDR3, ADDR2, ADDR1 and ADDR0 as shown in 表 7-11
and ignore DEVADDR[3:0] code.
The address 0h to Fh can be used as slave address for up to 16 pieces of TPS929160-Q1 in the same
FlexWire bus. Do not have two TPS929160-Q1 sharing the same slave address either setting by internal register
DEVADDR or address pins configuration on ADDR3, ADDR2, ADDR1 and ADDR0.
The default value for DEVADDR[3:0] is 0h.
表 7-11. Device Address Setting
INTERNAL ADDRESS SETTING
BIT2 BIT1
DEVADDR[3] DEVADDR[2] DEVADDR[1] DEVADDR[0]
EXTERNAL ADDRESS SETTING
Address(HEX)
BIT3
BIT0
BIT3
BIT2
BIT1
BIT0
ADDR3
ADDR2
ADDR1
ADDR0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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7.5.1.3 Status Response
When the TPS929160-Q1 as a slave device receives a non-broadcast frame, it first verifies the CRC byte. After
CRC check is succeeded, the TPS929160-Q1 sends out the device status of FLAG_ERR register byte followed
by CRC byte. The response is disabled by setting register ACKEN to 0. The response sent from TPS929160-Q1
is enabled by default.
Every communication requires CRC verification to make sure the integrity for the data transaction. In broadcast
mode, TPS929160-Q1 does not send out a response.
7.5.1.4 Synchronization Byte
The first byte data sent from master controller to TPS929160-Q1 is synchronization frame (SYNC). The master
controller sends the clock signal to TPS929160-Q1 through outputting 01010101 binary code in first frame.
The TPS929160-Q1 adaptively uses the same clock to communicate with master by synchronization of internal
high frequency clock. To avoid clock drift over time, the synchronization byte is always required for each new
instruction transaction on FlexWire interface. With this approach, the communication reliability is improved, and
the cost for external crystal oscillator is saved. 图 7-15 is the timing diagram for synchronization frame and
device address frame.
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
ST
1
0
1
0
1
0
1
0
SP
ST
0
0
0
1
0
0
0
1
SP
RX
Sync Frame
0x55
DEV_ADDR Frame
0x88
图 7-15. Synchronization Byte
7.5.1.5 Device Address Byte
The device address byte, DEV_ADDR frame follows the SYNC frame. There are total 8 bits binary code in
the device address byte. The below table provides detailed definition for each bit function. The DEVICE_ADDR
register is required to set to 0000b for broadcast mode, otherwise the broadcast mode cannot be enabled. The
broadcast mode is only effective for writing mode. The READ/WRITE bit must be 1 for broadcast mode.
表 7-12. DEV_ADDR Byte
BIT
FIELD
DESCRIPTION
3-0
DEVICE_ADDR
Target device address
00b: Single-byte mode with 1 byte of data; 01b: Bust mode with 4 bytes of data;
10b: Burst mode with 16 bytes of data; 11b: Burst mode with 24 bytes of data
5-4
DATA_LENGTH
6
7
BROADCAST
READ/WRITE
Broadcast mode. 1: Broadcast (DEVICE_ADDR =0000b); 0: Single-device only
Read / Write mode. 1: Write mode; 0: Read mode
7.5.1.6 Register Address Byte
The register address byte, REG_ADDR frame follows the device address frame. There are total 8 bits binary
code in register address byte. The maximum allowed register address is 255. The below figure is the timing
diagram for register address frame and data frame.
表 7-13. REG_ADDR Byte
BIT
FIELD
DESCRIPTION
0 - 7
REG_ADDR
Register address
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Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
ST
1
1
1
0
1
0
1
0
SP
ST
0
1
0
1
0
0
0
1
SP
RX
REG_ADDR Frame
0x57
Data Frame N
0x8A
图 7-16. Address and Data Bytes
7.5.1.7 Data Frame
The data bytes, data frame follows the register address byte. The TPS929160-Q1 supports single-data-byte, or
multiple-data-byte writing in one time data transaction. The number of data byte is defined in the device address
byte as introduced in 表 7-12. There are four options including 1 data byte, 4, 16, or 24 data bytes.
表 7-14. DATA Byte
BIT
FIELD
DESCRIPTION
0 - 7
DATA
Data
7.5.1.8 CRC Frame
The CRC data byte follows the data byte as the final byte in the end of one data transaction to ensure the
TPS929160-Q1 correctly receiving all the data bytes from master controller. The master controller must calculate
the CRC value for all bytes binary code including device address byte, register address byte, data bytes and
sends it to TPS929160-Q1 to end the one time communication. The TPS929160-Q1 receives all bytes data,
calculates the CRC and compares the calculated CRC code with received CRC code. If two CRC codes do
not match each other, the TPS929160-Q1 ignores the data transaction and waits for the next data transaction
without reset FlexWire watchdog timer, WDTIMER. The CRC algorithm is the same to the EEPROM CRC
diagnostics as described in EEPROM CRC Error in NORMAL state. The initial code for CRC is FFh as well.
表 7-15. CRC Byte
BIT
FIELD
DESCRIPTION
0 - 7
CRC
CRC Residual
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
ST
0
0
0
1
0
1
0
1
SP
RX
CRC
0xA8
图 7-17. CRC Byte
7.5.1.9 Burst Mode
The TPS929160-Q1 with FlexWire protocol supports burst mode for multiple data bytes writing and reading in
one data transaction cycle to accelerate the communication between the master controller and slaves. 图 7-18
shows the data format for multiple data bytes write, and 图 7-19 shows the data format for multiple data bytes
read. The DATA_1 is written to the register in REG_ADDR address, and the following DATA_2 to DATA_N are
written to the registers in REG_ADDR+1 to REG_ADDR+N address sequentially for multiple bytes write. For
multiple data read, the DATA_1 is read from the register in REG_ADDR address, and the following DATA_2 to
DATA_N are read from the registers in REG_ADDR+1 to REG_ADDR+N address sequentially.
SYNC
DEV_ADDR
REG_ADDR
DATA_1
DATA_N
CRC
RX
STATUS
CRC
TX
图 7-18. Multiple Data Bytes Write in Burst Mode
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SYNC
RX
DEV_ADDR
REG_ADDR
CRC
DATA_1
DATA_N
CRC
TX
图 7-19. Multiple Data Bytes Read in Burst Mode
7.5.2 Registers Lock
The TPS929160-Q1 provides registers content lock feature to prevent unintended modification of registers.
There are four register lock bits for different type of registers covering all registers as the below table illustrates.
TI recommends locking the register after register writing operations.
表 7-16. Registers Lock Table
Register IP Name
BRT (PWMMx)
Address
Lock Register Name
Lock Register Default
00h~17h
20h~37h
40h~44h
50h~67h
70h~83h
84h~87h
90h and 91h
92h~95h
96h
BRT (PWMLx)
BRT
BRTLOCK
0 (unlock)
IOUT
IOUTLOCK
CONFLOCK
1 (lock)
1 (lock)
CONF
CONF
Always locked except in EEPROM program state
No Lock Register
CTRL (ADCCH and CLR)
CTRL
Unlock by sending serial code to CTRLGATE register
No Lock Register
CTRL (CTRLGATE)
CTRL (EEP)
CTRL (EEPGATE)
97h
Unlock by sending serial code to EEPGATE register
No Lock Register
98h
The below instruction is required to access and exit the CTRL (92h to 95h) register.
•
•
•
Write 43h, 4Fh, 44h, 45h to 8-bit register CTRLGATE one-byte by one-byte sequentially to access.
Write any 8-bit data to register CTRLGATE to exit active mode of the CTRL register.
Write any data to register CTRLGATE also reset LOCK register (93h) to default value.
The below instruction is required to access and exit the EEP (97h) register.
•
•
Write 00h, 04h, 02h, 09h, 02h, 09h to 8-bit register EEPGATE one-byte by one-byte sequentially to access.
Keep accessible state until write any 8-bit data to register EEPGATE to exit.
7.5.3 Register Default Data
The TPS929160-Q1 has three types of registers. The register IP name BRT with address between 00h to 17h,
20h to 37h and 40h to 44h, have the same set of EEPROM. These registers reset to 00h from POR, EN toggling
or setting 1 to REGDEFAULT, and they load the code from the corresponding EEPROM value by the following
operations:
•
•
•
•
The TPS929160-Q1 enters FAIL-SAFE state by watchdog timer overflow.
Writing FORCEFS to 1 to force TPS929160-Q1 into FAIL-SAFE state.
Writing EEPLOAD to 1 to load all corresponding EEPROM content.
Writing EEPMODE to 1 to enter EEPROM program state.
The register IP name IOUT and CONF with address between 50h to approximately 67h and 70h to
approximately 87h, have the same set of EEPROM. These registers always load EEPROM value by the
following operation:
•
•
•
•
The TPS929160-Q1 starts from POR.
The TPS929160-Q1 restarts from EN toggled.
The TPS929160-Q1 restarts from VBAT or LDO UVLO triggered.
The TPS929160-Q1 enters FAIL-SAFE state by watchdog timer overflow.
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•
•
•
•
Writing FORCEFS to 1 to force TPS929160-Q1 into FAIL-SAFE state.
Writing EEPLOAD to 1 to load all corresponding EEPROM content.
Writing REGDEFAULT to 1 to reset all registers to default code.
Writing EEPMODE to 1 to enter EEPROM program state.
The register IP name CTRL and FLAG with address between 90h to 98h and A0h to approximately AFh, have
no corresponding EEPROM cells. These registers always set to manufacture default value by the following
operation:
•
•
•
The TPS929160-Q1 starts from POR.
The TPS929160-Q1 restarts from EN toggled.
The TPS929160-Q1 restarts from VBAT or LDO UVLO triggered.
表 7-17. Registers Default Value Table
POR Default
Register IP Name Register Address
and
REGDEFAULT
EEPLOAD
FAIL-SAFE state
EEPMODE
SOFTRESET
BRT (PWMMx)
00h~17h
20h~37h
40h~44h
50~67h
00h
00h
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Only reset 93h to
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
BRT (PWMLx)
BRT
00h
00h
00h
00h
IOUT
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
CONF
70h~87h
Manufacture
default
CTRL
FLAG
90h~98h
A0~AFh
No action
No action
No action
default, no action Set 93h to 00h
on other registers
Only clear
Manufacture
default
FLAG_POR to 0h
and no action on
other registers
No action
No action
7.5.4 EEPROM Programming
The TPS929160-Q1 has a user-programmable EEPROM with high reliability for automotive applications. All the
EEPROM registers can be burnt through writing the target data into its corresponding register. The TPS929160-
Q1 supports two solutions for individual chip selection through pulling the REF pin high or through device
address configuration by address pin.
7.5.4.1 Chip Selection by Pulling REF Pin High
The TPS929160-Q1 supports using REF pin as chip-select during EEPROM programming. Considering multiple
TPS929160-Q1 devices connected on one FlexWire bus before burning EEPROM, the slave address for all
TPS929160-Q1 are all same before programming in case internal EEPROM register DEVADDR is used for
slave address setup. The EEPROM burning instruction can be sent to target TPS929160-Q1 by pulling the
REF pin of the target TPS929160-Q1 to 5 V. After the REF pin is pulled up to 5 V, the TPS929160-Q1 ignores
the device address setup by ADDR3/ADDR2/ADDR1/ADDR0 pins or EEPROM programmed device address in
EEP_DEVADDR. The master controller must send out data to target TPS929160-Q1 with device address as 0h
and not in broadcast mode.
7.5.4.2 Chip Selection by ADDR Pins Configuration
The TPS929160-Q1 also supports using configuration on ADDR3/ADDR2/ADDR1/ADDR0 pins to determine
the slave address for TPS929160-Q1 if multiple TPS929160-Q1 devices are connected on the same FlexWire
interface. TI recommends to use this approach for applications of multiple TPS929160-Q1 in the same FlexWire
interface. The master controller can send out register data to target TPS929160-Q1 with device address
matched to the ADDR3/ADDR2/ADDR1/ADDR0 pins configuration and not in broadcast mode.
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7.5.4.3 EEPROM Register Access and Burn
After selecting the target TPS929160-Q1 for EEPROM burning, the master controller must send a serial data
bytes to register EEPGATE and set 1 to register EEPMODE one by one in below sequence to finally enable the
EEPROM register access. Each data written must be a single-byte operation instead of burst-mode operation.
The chip is selected by pulling REF pin high, below instruction is required to access the EEPROM register.
•
•
Write 09h, 02h, 09h, 02h, 04h, 00h to 8-bit register EEPGATE one-byte by one-byte sequentially.
Write 1 to 1-bit register EEPMODE
The chip is selected by ADDR pins configuration. The below instruction is required to access the EEPROM
register.
•
•
Write 00h, 04h, 02h, 09h, 02h, 09h to 8-bit register EEPGATE one-byte by one-byte sequentially.
Write 1 to 1-bit register EEPMODE.
The EEPROM registers of the TPS929160-Q1 can be overwritten after the access enabled. The TPS929160-
Q1 first loads all data stored in EEPROM to corresponding registers right after entering EEPROM program
state. Then the master controller must write the target EEPROM value and the correlated CRC value into
its corresponding registers and set EEPPROG to 1 to start the burning of all the EEPROM registers. If
DEVADDR[3] or DEVADDR[3:0] is used for addressing and is modified during the EEPROM registers writing
process, the device address will be updated immediately. The master should use the new device address for the
next frame communication. It is not needed to write target EEPROM value to its corresponding register if the
target value EEPROM value is same to its present value, because the EEPROM present value is automatically
loaded into its corresponding register after entering the EEPROM PROGRAM state. The data is lost after POR
cycle if it is not burnt to EEPROM cell. The EEPPROG automatically returns to 0 at the next clock cycle. The
programming takes around 200 ms and flag register FLAG_PROGDONE is 0 during programming. Keep the
device power supply stable for at least 200 ms after writing 1 to EEPPROG to make sure solid and robust
burning. After programming is done, the FLAG_PROGDONE is automatically set to 1. 图 7-20 lists the detailed
flow chart. The EEPMODE and EEPPROG registers are not writable if the serial codes are not written to
EEPGATE one-byte by one-byte sequentially.
The EEPROM cells for TPS929160-Q1 can be overwritten and burnt for up to 1000 times. The one time
EEPROM burning is counted after the register EEPPROG is set to 1 even though the EEPROM data is not
changed at all.
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START
ADDRx pins for
device address?
Y
N
Write 1h to
EEPMODE
Pull High REF Pin
DEVADDR = 00h
Write data to
registers including
CRC
Write 00h to
EEPGATE
Write 09h to
EEPGATE
Write 04h to
EEPGATE
Write 02h to
EEPGATE
Write 01h to
EEPPROG
Write 02h to
EEPGATE
Write 09h to
EEPGATE
Keep supply stable
and wait for 200ms
Y
Write 09h to
EEPGATE
Write 02h to
EEPGATE
ADDRx pins for
device address?
N
Write 02h to
EEPGATE
Write 04h to
EEPGATE
Release REF pin
Write 0h to
EEPMODE to Normal
mode
Write 09h to
EEPGATE
Write 00h to
EEPGATE
END
EEP burning sequence
图 7-20. Programming Sequence
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7.5.4.4 EEPROM PROGRAM state Exit
The REF pin can be released after EEPROM burning if it is pulled high to 5 V for chip selection. The REF pin
must be kept high during all of EEPROM PROGRAM state.
The TPS929160-Q1 can quit the EEPROM PROGRAM state to NORMAL state after burning by writing 0 to
register EEPMODE. TI recommends reloading the EEPROM data to the registers after EEPROM burning by set
1 to REGDEFAULT.
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7.6 Register Maps
CAUTION
All the RESERVED bits in register are set to 0b in TI manufacture. All the RESERVED bits in regester must be written to 0b in case of
unavoidable register writing.
表 7-18. Register Map
EEPROM
DEFAULT
ADDR
NAME
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
DEFAULT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
PWMMA0
PWMMA1
PWMMB0
PWMMB1
PWMMC0
PWMMC1
PWMMD0
PWMMD1
PWMME0
PWMME1
PWMMF0
PWMMF1
PWMMG0
PWMMG1
PWMMH0
PWMMH1
PWMMR0
PWMMR1
PWMMR2
PWMMR3
PWMMR4
PWMMR5
PWMMR6
PWMMR7
PWMOUTA0
PWMOUTA1
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
PWMOUTB0
PWMOUTB1
PWMOUTC0
PWMOUTC1
PWMOUTD0
PWMOUTD1
PWMOUTE0
PWMOUTE1
PWMOUTF0
PWMOUTF1
PWMOUTG0
PWMOUTG1
PWMOUTH0
PWMOUTH1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
20h
PWMLA0
RESERVED
RESERVED
RESERVED
RESERVED
PWMLOWOUTA0
00h
0Fh
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ADDR
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表 7-18. Register Map (continued)
EEPROM
NAME
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
DEFAULT
DEFAULT
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
00h
00h
00h
00h
00h
00h
00h
00h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
PWMLA1
PWMLB0
PWMLB1
PWMLC0
PWMLC1
PWMLD0
PWMLD1
PWMLE0
PWMLE1
PWMLF0
PWMLF1
PWMLG0
PWMLG1
PWMLH0
PWMLH1
PWMLR0
PWMLR1
PWMLR2
PWMLR3
PWMLR4
PWMLR5
PWMLR6
PWMLR7
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PWMLOWOUTA1
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
PWMLOWOUTB0
PWMLOWOUTB1
PWMLOWOUTC0
PWMLOWOUTC1
PWMLOWOUTD0
PWMLOWOUTD1
PWMLOWOUTE0
PWMLOWOUTE1
PWMLOWOUTF0
PWMLOWOUTF1
PWMLOWOUTG0
PWMLOWOUTG1
PWMLOWOUTH0
PWMLOWOUTH1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
40h
41h
42h
43h
44h
OUTEN0
OUTEN1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ENOUTB1
ENOUTD1
ENOUTF1
ENOUTH1
RESERVED
ENOUTB0
ENOUTD0
ENOUTF0
ENOUTH0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ENOUTA1
ENOUTC1
ENOUTE1
ENOUTG1
ENOUTA0
ENOUTC0
ENOUTE0
ENOUTG0
00h
00h
00h
00h
00h
33h
33h
33h
33h
00h
RESERVED
RESERVED
RESERVED
OUTEN2
OUTEN3
PWMSHARE
SHAREPWM
50h
51h
52h
IOUTA0
IOUTA1
IOUTB0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
IOUTA0
EEPROM
EEPROM
EEPROM
3Fh
3Fh
3Fh
IOUTA1
IOUTB0
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表 7-18. Register Map (continued)
ADDR
NAME
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
DEFAULT
DEFAULT
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
3Fh
00h
00h
00h
00h
00h
00h
00h
00h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
IOUTB1
IOUTC0
IOUTC1
IOUTD0
IOUTD1
IOUTE0
IOUTE1
IOUTF0
IOUTF1
IOUTG0
IOUTG1
IOUTH0
IOUTH1
IOUTAR
IOUTBR
IOUTCR
IOUTDR
IOUTER
IOUTFR
IOUTGR
IOUTHR
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
IOUTB1
IOUTC0
IOUTC1
IOUTD0
IOUTD1
IOUTE0
IOUTE1
IOUTF0
IOUTF1
IOUTG0
IOUTG1
IOUTH0
IOUTH1
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
70h
71h
72h
73h
DIAGEN0
DIAGEN1
DIAGEN2
DIAGEN3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DIAGENOUTB DIAGENOUTB
RESERVED
RESERVED
RESERVED DIAGENOUTA1 DIAGENOUTA0 EEPROM
33h
33h
33h
33h
1
0
DIAGENOUTD DIAGENOUTD
RESERVED
RESERVED
RESERVED
DIAGENOUTC DIAGENOUTC EEPROM
1
0
1
0
RESERVED DIAGENOUTF1 DIAGENOUTF0 RESERVED
DIAGENOUTE DIAGENOUTE EEPROM
1
0
RESERVED
DIAGENOUTH DIAGENOUTH
RESERVED
DIAGENOUTG DIAGENOUTG EEPROM
1
0
1
0
74h
75h
76h
SLSTHSEL0
SLSTHSEL1
SLSTHSEL2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SLSTHOUTB1 SLSTHOUTB0
SLSTHOUTD1 SLSTHOUTD0
SLSTHOUTF1 SLSTHOUTF0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SLSTHOUTA1 SLSTHOUTA0 EEPROM
SLSTHOUTC1 SLSTHOUTC0 EEPROM
SLSTHOUTE1 SLSTHOUTE0 EEPROM
00h
00h
00h
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ADDR
ZHCSNG0 – APRIL 2023
表 7-18. Register Map (continued)
EEPROM
NAME
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
DEFAULT
DEFAULT
77h
78h
79h
7Ah
7Bh
7Ch
SLSTHSEL3
SLSDAC0
SLSDAC1
REFERENCE
DIAG
RESERVED
RESERVED
SLSTHOUTH1 SLSTHOUTH0
RESERVED
RESERVED
SLSTHOUTG1 SLSTHOUTG0 EEPROM
00h
SLSTH0
SLSTH1
EEPROM
EEPROM
EEPROM
00h
00h
SLSEN
REFRANGE
IRETRY
LOWSUPTH
60h
BLANK
EEPROM
EEPROM
00h
DIAGMASK
MASKLOWSU MASKSUPUV
P
MASKREF
MASKPRETSD
MASKTSD
MASKEEPCRC RESERVED
RESERVED
MASKSLS
00h
7Dh
7Eh
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
OUTMASK
DIM
RESERVED
EXPEN
RESERVED
PSEN
RESERVED
12BIT
RESERVED
PSMEN
RESERVED
MASKOPEN
MASKSHORT
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
00h
30h
00h
00h
00h
00h
00h
01h
00h
10h
81h
PWMFREQ
DIM-R
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FSOUTB1
FSOUTD1
FSOUTF1
FSOUTH1
RESERVED
FSOUTB0
FSOUTD0
FSOUTF0
FSOUTH0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DBWTIMER
RESERVED
FSOUTA1
FSOUTC1
FSOUTE1
FSOUTG1
RESERVED
FSOUTA0
FSOUTC0
FSOUTE0
FSOUTG0
ACKEN
FSMAP0
FSMAP1
FSMAP2
FSMAP3
FLEXWIRE0
FLEXWIRE1
FLEXWIRE2
CRC
WDTIMER
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
INTADDR
OFAF
DEVADDR
INITTIMER
EEPCRC
90h
91h
92h
93h
94h
95h
96h
97h
98h
ADCCH
CLR
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ADCCHSEL
00h
00h
00h
03h
00h
00h
00h
00h
00h
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CLRFS
CLRFAULT
FORCEFS
CONFLOCK
EEPLOAD
RESERVED
CLRPOR
FORCEERR
IOUTLOCK
REGDEFAULT
NSTB
DEBUG
LOCK
RESERVED
BRTLOCK
CLRREG
NSTB
SOFTRESET
RESERVED
CTRLGATE
EEP
CTRLGATE
RESERVED
RESERVED
RESERVED
FLAG_REF
RESERVED
RESERVED
RESERVED
EEPPROG
FLAG_OUT
EEPMODE
EEPGATE
EEPGATE
FLAG_LOWSU
P
FLAG_PRETS
D
FLAG_EEPCR
C
A0h
FLAG_ERR
FLAG_SUPUV
FLAG_TSD
FLAG_FS
FLAG_ERR
FLAG_POR
01h
FLAG_EEPPA
R
FLAG_PROGD
ONE
FLAG_ADCDO FLAG_ADCER
NE
A1h
A2h
FLAG_STATUS
FLAG_ADC
FLAG_EXTFS1 FLAG_EXTFS0
01h
00h
R
ADC_OUT
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EEPROM
ZHCSNG0 – APRIL 2023
表 7-18. Register Map (continued)
ADDR
NAME
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
DEFAULT
DEFAULT
FLAG_SLSOU FLAG_SLSOU
TB1 TB0
FLAG_SLSOU FLAG_SLSOU
TA1 TA0
A3h
FLAG_SLS0
RESERVED
RESERVED
RESERVED
RESERVED
00h
FLAG_SLSOU FLAG_SLSOU
TD1 TD0
FLAG_SLSOU FLAG_SLSOU
TC1 TC0
A4h
A5h
FLAG_SLS1
FLAG_SLS2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
00h
00h
FLAG_SLSOU FLAG_SLSOU
TF1 TF0
FLAG_SLSOU FLAG_SLSOU
TE1 TE0
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
FLAG_SLS3
FLAG_OPEN0
FLAG_OPEN1
FLAG_OPEN2
FLAG_OPEN3
FLAG_SHORT0
FLAG_SHORT1
FLAG_SHORT2
FLAG_SHORT3
FLAG_EEPCRC
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FLAG_SLSOU FLAG_SLSOU
TH1 TH0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FLAG_SLSOU FLAG_SLSOU
TG1 TG0
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FLAG_OPENO FLAG_OPENO
UTB1 UTB0
FLAG_OPENO FLAG_OPENO
UTA1 UTA0
FLAG_OPENO FLAG_OPENO
UTD1 UTD0
FLAG_OPENO FLAG_OPENO
UTC1 UTC0
FLAG_OPENO FLAG_OPENO
UTF1 UTF0
FLAG_OPENO FLAG_OPENO
UTE1 UTE0
FLAG_OPENO FLAG_OPENO
UTH1 UTH0
FLAG_OPENO FLAG_OPENO
UTG1 UTG0
FLAG_SHORT FLAG_SHORT
OUTB1 OUTB0
FLAG_SHORT FLAG_SHORT
OUTA1 OUTA0
FLAG_SHORT FLAG_SHORT
OUTD1 OUTD0
FLAG_SHORT FLAG_SHORT
OUTC1 OUTC0
FLAG_SHORT FLAG_SHORT
OUTF1 OUTF0
FLAG_SHORT FLAG_SHORT
OUTE1 OUTE0
FLAG_SHORT FLAG_SHORT
OUTH1 OUTH0
FLAG_SHORT FLAG_SHORT
OUTG1 OUTG0
CALC_EEPCRC
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7.6.1 BRT Registers
表 7-19 lists the memory-mapped registers for the BRT registers. All register offset addresses not listed in 表
7-19 should be considered as reserved locations and the register contents should not be modified.
Control Register
表 7-19. BRT Registers
Offset
0h
Acronym
PWMMA0
PWMMA1
PWMMB0
PWMMB1
PWMMC0
PWMMC1
PWMMD0
PWMMD1
PWMME0
PWMME1
PWMMF0
PWMMF1
PWMMG0
PWMMG1
PWMMH0
PWMMH1
PWMMR0
PWMMR1
PWMMR2
PWMMR3
PWMMR4
PWMMR5
PWMMR6
PWMMR7
PWMLA0
PWMLA1
PWMLB0
PWMLB1
PWMLC0
PWMLC1
PWMLD0
PWMLD1
PWMLE0
PWMLE1
PWMLF0
PWMLF1
PWMLG0
PWMLG1
PWMLH0
PWMLH1
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
8-MSB Output PWM Duty-cycle Setting for OUTA0
8-MSB Output PWM Duty-cycle Setting for OUTA1
8-MSB Output PWM Duty-cycle Setting for OUTB0
8-MSB Output PWM Duty-cycle Setting for OUTB1
8-MSB Output PWM Duty-cycle Setting for OUTC0
8-MSB Output PWM Duty-cycle Setting for OUTC1
8-MSB Output PWM Duty-cycle Setting for OUTD0
8-MSB Output PWM Duty-cycle Setting for OUTD1
8-MSB Output PWM Duty-cycle Setting for OUTE0
8-MSB Output PWM Duty-cycle Setting for OUTE1
8-MSB Output PWM Duty-cycle Setting for OUTF0
8-MSB Output PWM Duty-cycle Setting for OUTF1
8-MSB Output PWM Duty-cycle Setting for OUTG0
8-MSB Output PWM Duty-cycle Setting for OUTG1
8-MSB Output PWM Duty-cycle Setting for OUTH0
8-MSB Output PWM Duty-cycle Setting for OUTH1
Reserved Register
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h
11h
12h
13h
14h
15h
16h
17h
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
4-LSB Output PWM Duty-cycle Setting for OUTA0
4-LSB Output PWM Duty-cycle Setting for OUTA1
4-LSB Output PWM Duty-cycle Setting for OUTB0
4-LSB Output PWM Duty-cycle Setting for OUTB1
4-LSB Output PWM Duty-cycle Setting for OUTC0
4-LSB Output PWM Duty-cycle Setting for OUTC1
4-LSB Output PWM Duty-cycle Setting for OUTD0
4-LSB Output PWM Duty-cycle Setting for OUTD1
4-LSB Output PWM Duty-cycle Setting for OUTE0
4-LSB Output PWM Duty-cycle Setting for OUTE1
4-LSB Output PWM Duty-cycle Setting for OUTF0
4-LSB Output PWM Duty-cycle Setting for OUTF1
4-LSB Output PWM Duty-cycle Setting for OUTG0
4-LSB Output PWM Duty-cycle Setting for OUTG1
4-LSB Output PWM Duty-cycle Setting for OUTH0
4-LSB Output PWM Duty-cycle Setting for OUTH1
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表 7-19. BRT Registers (continued)
Offset
30h
31h
32h
33h
34h
35h
36h
37h
40h
41h
42h
43h
44h
Acronym
Register Name
Section
Go
PWMLR0
PWMLR1
PWMLR2
PWMLR3
PWMLR4
PWMLR5
PWMLR6
PWMLR7
OUTEN0
OUTEN1
OUTEN2
OUTEN3
PWMSHARE
Reserved Register
Reserved Register
Go
Reserved Register
Go
Reserved Register
Go
Reserved Register
Go
Reserved Register
Go
Reserved Register
Go
Reserved Register
Go
OUTAn, OUTBn Enable Setting
OUTCn, OUTDn Enable Setting
OUTEn, OUTFn Enable Setting
OUTGn, OUTHn Enable Setting
Go
Go
Go
Go
PWM Duty-cycle Sharing for All Enabled Output
Go
Complex bit access types are encoded to fit into small table cells. 表 7-20 shows the codes that are used for
access types in this section.
表 7-20. BRT Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.1.1 PWMMA0 Register (Offset = 0h) [Reset = 00h]
PWMMA0 is shown in 图 7-21 and described in 表 7-21.
Return to the Summary Table.
图 7-21. PWMMA0 Register
7
6
5
4
3
2
1
0
PWMOUTA0
R/W-0h
表 7-21. PWMMA0 Register Field Descriptions
Bit
7-0
Field
PWMOUTA0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTA0
7.6.1.2 PWMMA1 Register (Offset = 1h) [Reset = 00h]
PWMMA1 is shown in 图 7-22 and described in 表 7-22.
Return to the Summary Table.
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图 7-22. PWMMA1 Register
7
6
5
4
3
2
1
0
PWMOUTA1
R/W-0h
表 7-22. PWMMA1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PWMOUTA1
R/W
0h
8-MSB output PWM duty-cycle setting for OUTA1
7.6.1.3 PWMMB0 Register (Offset = 2h) [Reset = 00h]
PWMMB0 is shown in 图 7-23 and described in 表 7-23.
Return to the Summary Table.
图 7-23. PWMMB0 Register
7
6
5
4
3
2
1
0
PWMOUTB0
R/W-0h
表 7-23. PWMMB0 Register Field Descriptions
Bit
7-0
Field
PWMOUTB0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTB0
7.6.1.4 PWMMB1 Register (Offset = 3h) [Reset = 00h]
PWMMB1 is shown in 图 7-24 and described in 表 7-24.
Return to the Summary Table.
图 7-24. PWMMB1 Register
7
6
5
4
3
2
1
0
PWMOUTB1
R/W-0h
表 7-24. PWMMB1 Register Field Descriptions
Bit
7-0
Field
PWMOUTB1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTB1
7.6.1.5 PWMMC0 Register (Offset = 4h) [Reset = 00h]
PWMMC0 is shown in 图 7-25 and described in 表 7-25.
Return to the Summary Table.
图 7-25. PWMMC0 Register
7
6
5
4
3
2
1
0
PWMOUTC0
R/W-0h
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表 7-25. PWMMC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PWMOUTC0
R/W
0h
8-MSB output PWM duty-cycle setting for OUTC0
7.6.1.6 PWMMC1 Register (Offset = 5h) [Reset = 00h]
PWMMC1 is shown in 图 7-26 and described in 表 7-26.
Return to the Summary Table.
图 7-26. PWMMC1 Register
7
6
5
4
3
2
1
0
PWMOUTC1
R/W-0h
表 7-26. PWMMC1 Register Field Descriptions
Bit
7-0
Field
PWMOUTC1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTC1
7.6.1.7 PWMMD0 Register (Offset = 6h) [Reset = 00h]
PWMMD0 is shown in 图 7-27 and described in 表 7-27.
Return to the Summary Table.
图 7-27. PWMMD0 Register
7
6
5
4
3
2
1
0
PWMOUTD0
R/W-0h
表 7-27. PWMMD0 Register Field Descriptions
Bit
7-0
Field
PWMOUTD0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTD0
7.6.1.8 PWMMD1 Register (Offset = 7h) [Reset = 00h]
PWMMD1 is shown in 图 7-28 and described in 表 7-28.
Return to the Summary Table.
图 7-28. PWMMD1 Register
7
6
5
4
3
2
1
0
PWMOUTD1
R/W-0h
表 7-28. PWMMD1 Register Field Descriptions
Bit
7-0
Field
PWMOUTD1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTD1
7.6.1.9 PWMME0 Register (Offset = 8h) [Reset = 00h]
PWMME0 is shown in 图 7-29 and described in 表 7-29.
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Return to the Summary Table.
图 7-29. PWMME0 Register
7
6
5
4
3
2
1
0
PWMOUTE0
R/W-0h
表 7-29. PWMME0 Register Field Descriptions
Bit
7-0
Field
PWMOUTE0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTE0
7.6.1.10 PWMME1 Register (Offset = 9h) [Reset = 00h]
PWMME1 is shown in 图 7-30 and described in 表 7-30.
Return to the Summary Table.
图 7-30. PWMME1 Register
7
6
5
4
3
2
1
0
0
0
PWMOUTE1
R/W-0h
表 7-30. PWMME1 Register Field Descriptions
Bit
7-0
Field
PWMOUTE1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTE1
7.6.1.11 PWMMF0 Register (Offset = Ah) [Reset = 00h]
PWMMF0 is shown in 图 7-31 and described in 表 7-31.
Return to the Summary Table.
图 7-31. PWMMF0 Register
7
6
5
4
3
2
1
PWMOUTF0
R/W-0h
表 7-31. PWMMF0 Register Field Descriptions
Bit
7-0
Field
PWMOUTF0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTF0
7.6.1.12 PWMMF1 Register (Offset = Bh) [Reset = 00h]
PWMMF1 is shown in 图 7-32 and described in 表 7-32.
Return to the Summary Table.
图 7-32. PWMMF1 Register
7
6
5
4
3
2
1
PWMOUTF1
R/W-0h
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表 7-32. PWMMF1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PWMOUTF1
R/W
0h
8-MSB output PWM duty-cycle setting for OUTF1
7.6.1.13 PWMMG0 Register (Offset = Ch) [Reset = 00h]
PWMMG0 is shown in 图 7-33 and described in 表 7-33.
Return to the Summary Table.
图 7-33. PWMMG0 Register
7
6
5
4
3
2
1
0
PWMOUTG0
R/W-0h
表 7-33. PWMMG0 Register Field Descriptions
Bit
7-0
Field
PWMOUTG0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTG0
7.6.1.14 PWMMG1 Register (Offset = Dh) [Reset = 00h]
PWMMG1 is shown in 图 7-34 and described in 表 7-34.
Return to the Summary Table.
图 7-34. PWMMG1 Register
7
6
5
4
3
2
1
0
PWMOUTG1
R/W-0h
表 7-34. PWMMG1 Register Field Descriptions
Bit
7-0
Field
PWMOUTG1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTG1
7.6.1.15 PWMMH0 Register (Offset = Eh) [Reset = 00h]
PWMMH0 is shown in 图 7-35 and described in 表 7-35.
Return to the Summary Table.
图 7-35. PWMMH0 Register
7
6
5
4
3
2
1
0
PWMOUTH0
R/W-0h
表 7-35. PWMMH0 Register Field Descriptions
Bit
7-0
Field
PWMOUTH0
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTH0
7.6.1.16 PWMMH1 Register (Offset = Fh) [Reset = 00h]
PWMMH1 is shown in 图 7-36 and described in 表 7-36.
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Return to the Summary Table.
图 7-36. PWMMH1 Register
7
6
5
4
3
2
1
0
PWMOUTH1
R/W-0h
表 7-36. PWMMH1 Register Field Descriptions
Bit
7-0
Field
PWMOUTH1
Type
Reset
Description
R/W
0h
8-MSB output PWM duty-cycle setting for OUTH1
7.6.1.17 PWMMR0 Register (Offset = 10h) [Reset = 00h]
PWMMR0 is shown in 图 7-37 and described in 表 7-37.
Return to the Summary Table.
图 7-37. PWMMR0 Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R-0h
表 7-37. PWMMR0 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.18 PWMMR1 Register (Offset = 11h) [Reset = 00h]
PWMMR1 is shown in 图 7-38 and described in 表 7-38.
Return to the Summary Table.
图 7-38. PWMMR1 Register
7
6
5
4
3
2
RESERVED
R-0h
表 7-38. PWMMR1 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.19 PWMMR2 Register (Offset = 12h) [Reset = 00h]
PWMMR2 is shown in 图 7-39 and described in 表 7-39.
Return to the Summary Table.
图 7-39. PWMMR2 Register
7
6
5
4
3
2
RESERVED
R-0h
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表 7-39. PWMMR2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RESERVED
R
0h
Reserved
7.6.1.20 PWMMR3 Register (Offset = 13h) [Reset = 00h]
PWMMR3 is shown in 图 7-40 and described in 表 7-40.
Return to the Summary Table.
图 7-40. PWMMR3 Register
7
6
5
4
3
2
1
1
1
0
RESERVED
R-0h
表 7-40. PWMMR3 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.21 PWMMR4 Register (Offset = 14h) [Reset = 00h]
PWMMR4 is shown in 图 7-41 and described in 表 7-41.
Return to the Summary Table.
图 7-41. PWMMR4 Register
7
6
5
4
3
2
0
RESERVED
R-0h
表 7-41. PWMMR4 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.22 PWMMR5 Register (Offset = 15h) [Reset = 00h]
PWMMR5 is shown in 图 7-42 and described in 表 7-42.
Return to the Summary Table.
图 7-42. PWMMR5 Register
7
6
5
4
3
2
0
RESERVED
R-0h
表 7-42. PWMMR5 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.23 PWMMR6 Register (Offset = 16h) [Reset = 00h]
PWMMR6 is shown in 图 7-43 and described in 表 7-43.
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Return to the Summary Table.
图 7-43. PWMMR6 Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R-0h
表 7-43. PWMMR6 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.24 PWMMR7 Register (Offset = 17h) [Reset = 00h]
PWMMR7 is shown in 图 7-44 and described in 表 7-44.
Return to the Summary Table.
图 7-44. PWMMR7 Register
7
6
5
4
3
2
RESERVED
R-0h
表 7-44. PWMMR7 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.25 PWMLA0 Register (Offset = 20h) [Reset = 00h]
PWMLA0 is shown in 图 7-45 and described in 表 7-45.
Return to the Summary Table.
图 7-45. PWMLA0 Register
7
6
5
4
3
2
RESERVED
R-0h
PWMLOWOUTA0
R/W-0h
表 7-45. PWMLA0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTA0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTA0
7.6.1.26 PWMLA1 Register (Offset = 21h) [Reset = 00h]
PWMLA1 is shown in 图 7-46 and described in 表 7-46.
Return to the Summary Table.
图 7-46. PWMLA1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTA1
R/W-0h
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表 7-46. PWMLA1 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
PWMLOWOUTA1
R
0h
Reserved
R/W
0h
4-LSB output PWM duty-cycle setting for OUTA1
7.6.1.27 PWMLB0 Register (Offset = 22h) [Reset = 00h]
PWMLB0 is shown in 图 7-47 and described in 表 7-47.
Return to the Summary Table.
图 7-47. PWMLB0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTB0
R/W-0h
表 7-47. PWMLB0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTB0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTB0
7.6.1.28 PWMLB1 Register (Offset = 23h) [Reset = 00h]
PWMLB1 is shown in 图 7-48 and described in 表 7-48.
Return to the Summary Table.
图 7-48. PWMLB1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTB1
R/W-0h
表 7-48. PWMLB1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTB1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTB1
7.6.1.29 PWMLC0 Register (Offset = 24h) [Reset = 00h]
PWMLC0 is shown in 图 7-49 and described in 表 7-49.
Return to the Summary Table.
图 7-49. PWMLC0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTC0
R/W-0h
表 7-49. PWMLC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTC0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTC0
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7.6.1.30 PWMLC1 Register (Offset = 25h) [Reset = 00h]
PWMLC1 is shown in 图 7-50 and described in 表 7-50.
Return to the Summary Table.
图 7-50. PWMLC1 Register
7
6
5
4
3
2
1
0
0
0
RESERVED
R-0h
PWMLOWOUTC1
R/W-0h
表 7-50. PWMLC1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTC1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTC1
7.6.1.31 PWMLD0 Register (Offset = 26h) [Reset = 00h]
PWMLD0 is shown in 图 7-51 and described in 表 7-51.
Return to the Summary Table.
图 7-51. PWMLD0 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTD0
R/W-0h
表 7-51. PWMLD0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTD0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTD0
7.6.1.32 PWMLD1 Register (Offset = 27h) [Reset = 00h]
PWMLD1 is shown in 图 7-52 and described in 表 7-52.
Return to the Summary Table.
图 7-52. PWMLD1 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTD1
R/W-0h
表 7-52. PWMLD1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTD1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTD1
7.6.1.33 PWMLE0 Register (Offset = 28h) [Reset = 00h]
PWMLE0 is shown in 图 7-53 and described in 表 7-53.
Return to the Summary Table.
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图 7-53. PWMLE0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTE0
R/W-0h
表 7-53. PWMLE0 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
PWMLOWOUTE0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTE0
7.6.1.34 PWMLE1 Register (Offset = 29h) [Reset = 00h]
PWMLE1 is shown in 图 7-54 and described in 表 7-54.
Return to the Summary Table.
图 7-54. PWMLE1 Register
7
6
5
4
3
2
1
0
0
0
RESERVED
R-0h
PWMLOWOUTE1
R/W-0h
表 7-54. PWMLE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTE1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTE1
7.6.1.35 PWMLF0 Register (Offset = 2Ah) [Reset = 00h]
PWMLF0 is shown in 图 7-55 and described in 表 7-55.
Return to the Summary Table.
图 7-55. PWMLF0 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTF0
R/W-0h
表 7-55. PWMLF0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTF0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTF0
7.6.1.36 PWMLF1 Register (Offset = 2Bh) [Reset = 00h]
PWMLF1 is shown in 图 7-56 and described in 表 7-56.
Return to the Summary Table.
图 7-56. PWMLF1 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTF1
R/W-0h
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图 7-56. PWMLF1 Register (continued)
表 7-56. PWMLF1 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
PWMLOWOUTF1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTF1
7.6.1.37 PWMLG0 Register (Offset = 2Ch) [Reset = 00h]
PWMLG0 is shown in 图 7-57 and described in 表 7-57.
Return to the Summary Table.
图 7-57. PWMLG0 Register
7
6
5
4
3
2
1
0
0
0
RESERVED
R-0h
PWMLOWOUTG0
R/W-0h
表 7-57. PWMLG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTG0
R/W
0h
4-LSB output PWM duty-cycle setting for OUTG0
7.6.1.38 PWMLG1 Register (Offset = 2Dh) [Reset = 00h]
PWMLG1 is shown in 图 7-58 and described in 表 7-58.
Return to the Summary Table.
图 7-58. PWMLG1 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTG1
R/W-0h
表 7-58. PWMLG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTG1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTG1
7.6.1.39 PWMLH0 Register (Offset = 2Eh) [Reset = 00h]
PWMLH0 is shown in 图 7-59 and described in 表 7-59.
Return to the Summary Table.
图 7-59. PWMLH0 Register
7
6
5
4
3
2
1
RESERVED
R-0h
PWMLOWOUTH0
R/W-0h
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表 7-59. PWMLH0 Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
PWMLOWOUTH0
R
0h
Reserved
R/W
0h
4-LSB output PWM duty-cycle setting for OUTH0
7.6.1.40 PWMLH1 Register (Offset = 2Fh) [Reset = 00h]
PWMLH1 is shown in 图 7-60 and described in 表 7-60.
Return to the Summary Table.
图 7-60. PWMLH1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
PWMLOWOUTH1
R/W-0h
表 7-60. PWMLH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
3-0
RESERVED
R
0h
Reserved
PWMLOWOUTH1
R/W
0h
4-LSB output PWM duty-cycle setting for OUTH1
7.6.1.41 PWMLR0 Register (Offset = 30h) [Reset = 00h]
PWMLR0 is shown in 图 7-61 and described in 表 7-61.
Return to the Summary Table.
图 7-61. PWMLR0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-61. PWMLR0 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.42 PWMLR1 Register (Offset = 31h) [Reset = 00h]
PWMLR1 is shown in 图 7-62 and described in 表 7-62.
Return to the Summary Table.
图 7-62. PWMLR1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-62. PWMLR1 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
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7.6.1.43 PWMLR2 Register (Offset = 32h) [Reset = 00h]
PWMLR2 is shown in 图 7-63 and described in 表 7-63.
Return to the Summary Table.
图 7-63. PWMLR2 Register
7
6
5
4
3
2
1
1
1
1
0
0
0
0
RESERVED
R-0h
表 7-63. PWMLR2 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.44 PWMLR3 Register (Offset = 33h) [Reset = 00h]
PWMLR3 is shown in 图 7-64 and described in 表 7-64.
Return to the Summary Table.
图 7-64. PWMLR3 Register
7
6
5
4
3
2
RESERVED
R-0h
表 7-64. PWMLR3 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.45 PWMLR4 Register (Offset = 34h) [Reset = 00h]
PWMLR4 is shown in 图 7-65 and described in 表 7-65.
Return to the Summary Table.
图 7-65. PWMLR4 Register
7
6
5
4
3
2
RESERVED
R-0h
表 7-65. PWMLR4 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.46 PWMLR5 Register (Offset = 35h) [Reset = 00h]
PWMLR5 is shown in 图 7-66 and described in 表 7-66.
Return to the Summary Table.
图 7-66. PWMLR5 Register
7
6
5
4
3
2
RESERVED
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图 7-66. PWMLR5 Register (continued)
R-0h
表 7-66. PWMLR5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RESERVED
R
0h
Reserved
7.6.1.47 PWMLR6 Register (Offset = 36h) [Reset = 00h]
PWMLR6 is shown in 图 7-67 and described in 表 7-67.
Return to the Summary Table.
图 7-67. PWMLR6 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-67. PWMLR6 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.48 PWMLR7 Register (Offset = 37h) [Reset = 00h]
PWMLR7 is shown in 图 7-68 and described in 表 7-68.
Return to the Summary Table.
图 7-68. PWMLR7 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-68. PWMLR7 Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.1.49 OUTEN0 Register (Offset = 40h) [Reset = 00h]
OUTEN0 is shown in 图 7-69 and described in 表 7-69.
Return to the Summary Table.
图 7-69. OUTEN0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
ENOUTB1
R/W-0h
ENOUTB0
R/W-0h
RESERVED
R-0h
ENOUTA1
R/W-0h
ENOUTA0
R/W-0h
表 7-69. OUTEN0 Register Field Descriptions
Bit
7-6
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
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表 7-69. OUTEN0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
ENOUTB1
R/W
0h
Enable register for OUTB1
0h = Disabled
1h = Enabled
4
ENOUTB0
R/W
0h
Enable register for OUTB0
0h = Disabled
1h = Enabled
3-2
1
RESERVED
ENOUTA1
R
0h
0h
Reserved
R/W
Enable register for OUTA1
0h = Disabled
1h = Enabled
0
ENOUTA0
R/W
0h
Enable register for OUTA0
0h = Disabled
1h = Enabled
7.6.1.50 OUTEN1 Register (Offset = 41h) [Reset = 00h]
OUTEN1 is shown in 图 7-70 and described in 表 7-70.
Return to the Summary Table.
图 7-70. OUTEN1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
ENOUTD1
R/W-0h
ENOUTD0
R/W-0h
RESERVED
R-0h
ENOUTC1
R/W-0h
ENOUTC0
R/W-0h
表 7-70. OUTEN1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
ENOUTD1
R
0h
Reserved
R/W
0h
Enable register for OUTD1
0h = Disabled
1h = Enabled
4
ENOUTD0
R/W
0h
Enable register for OUTD0
0h = Disabled
1h = Enabled
3-2
1
RESERVED
ENOUTC1
R
0h
0h
Reserved
R/W
Enable register for OUTC1
0h = Disabled
1h = Enabled
0
ENOUTC0
R/W
0h
Enable register for OUTC0
0h = Disabled
1h = Enabled
7.6.1.51 OUTEN2 Register (Offset = 42h) [Reset = 00h]
OUTEN2 is shown in 图 7-71 and described in 表 7-71.
Return to the Summary Table.
图 7-71. OUTEN2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
ENOUTF1
R/W-0h
ENOUTF0
R/W-0h
RESERVED
R-0h
ENOUTE1
R/W-0h
ENOUTE0
R/W-0h
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表 7-71. OUTEN2 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
ENOUTF1
R
0h
Reserved
R/W
0h
Enable register for OUTF1
0h = Disabled
1h = Enabled
4
ENOUTF0
R/W
0h
Enable register for OUTF0
0h = Disabled
1h = Enabled
3-2
1
RESERVED
ENOUTE1
R
0h
0h
Reserved
R/W
Enable register for OUTE1
0h = Disabled
1h = Enabled
0
ENOUTE0
R/W
0h
Enable register for OUTE0
0h = Disabled
1h = Enabled
7.6.1.52 OUTEN3 Register (Offset = 43h) [Reset = 00h]
OUTEN3 is shown in 图 7-72 and described in 表 7-72.
Return to the Summary Table.
图 7-72. OUTEN3 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
ENOUTH1
R/W-0h
ENOUTH0
R/W-0h
RESERVED
R-0h
ENOUTG1
R/W-0h
ENOUTG0
R/W-0h
表 7-72. OUTEN3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
ENOUTH1
R
0h
Reserved
R/W
0h
Enable register for OUTH1
0h = Disabled
1h = Enabled
4
ENOUTH0
R/W
0h
Enable register for OUTH0
0h = Disabled
1h = Enabled
3-2
1
RESERVED
ENOUTG1
R
0h
0h
Reserved
R/W
Enable register for OUTG1
0h = Disabled
1h = Enabled
0
ENOUTG0
R/W
0h
Enable register for OUTG0
0h = Disabled
1h = Enabled
7.6.1.53 PWMSHARE Register (Offset = 44h) [Reset = 00h]
PWMSHARE is shown in 图 7-73 and described in 表 7-73.
Return to the Summary Table.
图 7-73. PWMSHARE Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SHAREPWM
R/W-0h
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图 7-73. PWMSHARE Register (continued)
表 7-73. PWMSHARE Register Field Descriptions
Bit
7-4
3-0
Field
Type
Reset
Description
RESERVED
SHAREPWM
R
0h
Reserved
R/W
0h
Set all Output PWM duty-cyce same to OUTA0
0~Eh = Each output PWM duty-cycle is set independently
Fh = All output PWM duty-cycle set to same to OUTA0
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7.6.2 IOUT Registers
表 7-74 lists the memory-mapped registers for the IOUT registers. All register offset addresses not listed in 表
7-74 should be considered as reserved locations and the register contents should not be modified.
Output Current Setting
表 7-74. IOUT Registers
Offset
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
Acronym
IOUTA0
IOUTA1
IOUTB0
IOUTB1
IOUTC0
IOUTC1
IOUTD0
IOUTD1
IOUTE0
IOUTE1
IOUTF0
IOUTF1
IOUTG0
IOUTG1
IOUTH0
IOUTH1
IOUTAR
IOUTBR
IOUTCR
IOUTDR
IOUTER
IOUTFR
IOUTGR
IOUTHR
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Output Current Setting for OUTA0
Output Current Setting for OUTA1
Output Current Setting for OUTB0
Output Current Setting for OUTB1
Output Current Setting for OUTC0
Output Current Setting for OUTC1
Output Current Setting for OUTD0
Output Current Setting for OUTD1
Output Current Setting for OUTE0
Output Current Setting for OUTE1
Output Current Setting for OUTF0
Output Current Setting for OUTF1
Output Current Setting for OUTG0
Output Current Setting for OUTG1
Output Current Setting for OUTH0
Output Current Setting for OUTH1
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Reserved Register
Complex bit access types are encoded to fit into small table cells. 表 7-75 shows the codes that are used for
access types in this section.
表 7-75. IOUT Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.2.1 IOUTA0 Register (Offset = 50h) [Reset = X]
IOUTA0 is shown in 图 7-74 and described in 表 7-76.
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Return to the Summary Table.
图 7-74. IOUTA0 Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R-0h
IOUTA0
R/W-X
表 7-76. IOUTA0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTA0
R
0h
Reserved
R/W
X
Output current setting for OUTA0
Load EEPROM register data when reset
7.6.2.2 IOUTA1 Register (Offset = 51h) [Reset = X]
IOUTA1 is shown in 图 7-75 and described in 表 7-77.
Return to the Summary Table.
图 7-75. IOUTA1 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTA1
R/W-X
表 7-77. IOUTA1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTA1
R
0h
Reserved
R/W
X
Output current setting for OUTA1
Load EEPROM register data when reset
7.6.2.3 IOUTB0 Register (Offset = 52h) [Reset = X]
IOUTB0 is shown in 图 7-76 and described in 表 7-78.
Return to the Summary Table.
图 7-76. IOUTB0 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTB0
R/W-X
表 7-78. IOUTB0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTB0
R
0h
Reserved
R/W
X
Output current setting for OUTB0
Load EEPROM register data when reset
7.6.2.4 IOUTB1 Register (Offset = 53h) [Reset = X]
IOUTB1 is shown in 图 7-77 and described in 表 7-79.
Return to the Summary Table.
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图 7-77. IOUTB1 Register
7
6
5
4
3
2
1
1
1
1
0
RESERVED
R-0h
IOUTB1
R/W-X
表 7-79. IOUTB1 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
IOUTB1
R
0h
Reserved
R/W
X
Output current setting for OUTB1
Load EEPROM register data when reset
7.6.2.5 IOUTC0 Register (Offset = 54h) [Reset = X]
IOUTC0 is shown in 图 7-78 and described in 表 7-80.
Return to the Summary Table.
图 7-78. IOUTC0 Register
7
6
5
4
3
2
0
0
0
RESERVED
R-0h
IOUTC0
R/W-X
表 7-80. IOUTC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTC0
R
0h
Reserved
R/W
X
Output current setting for OUTC0
Load EEPROM register data when reset
7.6.2.6 IOUTC1 Register (Offset = 55h) [Reset = X]
IOUTC1 is shown in 图 7-79 and described in 表 7-81.
Return to the Summary Table.
图 7-79. IOUTC1 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTC1
R/W-X
表 7-81. IOUTC1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTC1
R
0h
Reserved
R/W
X
Output current setting for OUTC1
Load EEPROM register data when reset
7.6.2.7 IOUTD0 Register (Offset = 56h) [Reset = X]
IOUTD0 is shown in 图 7-80 and described in 表 7-82.
Return to the Summary Table.
图 7-80. IOUTD0 Register
7
6
5
4
3
2
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图 7-80. IOUTD0 Register (continued)
RESERVED
IOUTD0
R-0h
R/W-X
表 7-82. IOUTD0 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
IOUTD0
R
0h
Reserved
R/W
X
Output current setting for OUTD0
Load EEPROM register data when reset
7.6.2.8 IOUTD1 Register (Offset = 57h) [Reset = X]
IOUTD1 is shown in 图 7-81 and described in 表 7-83.
Return to the Summary Table.
图 7-81. IOUTD1 Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R-0h
IOUTD1
R/W-X
表 7-83. IOUTD1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTD1
R
0h
Reserved
R/W
X
Output current setting for OUTD1
Load EEPROM register data when reset
7.6.2.9 IOUTE0 Register (Offset = 58h) [Reset = X]
IOUTE0 is shown in 图 7-82 and described in 表 7-84.
Return to the Summary Table.
图 7-82. IOUTE0 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTE0
R/W-X
表 7-84. IOUTE0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTE0
R
0h
Reserved
R/W
X
Output current setting for OUTE0
Load EEPROM register data when reset
7.6.2.10 IOUTE1 Register (Offset = 59h) [Reset = X]
IOUTE1 is shown in 图 7-83 and described in 表 7-85.
Return to the Summary Table.
图 7-83. IOUTE1 Register
7
6
5
4
3
2
RESERVED
IOUTE1
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图 7-83. IOUTE1 Register (continued)
R-0h
R/W-X
表 7-85. IOUTE1 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
IOUTE1
R
0h
Reserved
R/W
X
Output current setting for OUTE1
Load EEPROM register data when reset
7.6.2.11 IOUTF0 Register (Offset = 5Ah) [Reset = X]
IOUTF0 is shown in 图 7-84 and described in 表 7-86.
Return to the Summary Table.
图 7-84. IOUTF0 Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R-0h
IOUTF0
R/W-X
表 7-86. IOUTF0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTF0
R
0h
Reserved
R/W
X
Output current setting for OUTF0
Load EEPROM register data when reset
7.6.2.12 IOUTF1 Register (Offset = 5Bh) [Reset = X]
IOUTF1 is shown in 图 7-85 and described in 表 7-87.
Return to the Summary Table.
图 7-85. IOUTF1 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTF1
R/W-X
表 7-87. IOUTF1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTF1
R
0h
Reserved
R/W
X
Output current setting for OUTF1
Load EEPROM register data when reset
7.6.2.13 IOUTG0 Register (Offset = 5Ch) [Reset = X]
IOUTG0 is shown in 图 7-86 and described in 表 7-88.
Return to the Summary Table.
图 7-86. IOUTG0 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTG0
R/W-X
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图 7-86. IOUTG0 Register (continued)
表 7-88. IOUTG0 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
IOUTG0
R
0h
Reserved
R/W
X
Output current setting for OUTG0
Load EEPROM register data when reset
7.6.2.14 IOUTG1 Register (Offset = 5Dh) [Reset = X]
IOUTG1 is shown in 图 7-87 and described in 表 7-89.
Return to the Summary Table.
图 7-87. IOUTG1 Register
7
6
5
4
3
2
1
1
1
0
0
0
RESERVED
R-0h
IOUTG1
R/W-X
表 7-89. IOUTG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTG1
R
0h
Reserved
R/W
X
Output current setting for OUTG1
Load EEPROM register data when reset
7.6.2.15 IOUTH0 Register (Offset = 5Eh) [Reset = X]
IOUTH0 is shown in 图 7-88 and described in 表 7-90.
Return to the Summary Table.
图 7-88. IOUTH0 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTH0
R/W-X
表 7-90. IOUTH0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5-0
RESERVED
IOUTH0
R
0h
Reserved
R/W
X
Output current setting for OUTH0
Load EEPROM register data when reset
7.6.2.16 IOUTH1 Register (Offset = 5Fh) [Reset = X]
IOUTH1 is shown in 图 7-89 and described in 表 7-91.
Return to the Summary Table.
图 7-89. IOUTH1 Register
7
6
5
4
3
2
RESERVED
R-0h
IOUTH1
R/W-X
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表 7-91. IOUTH1 Register Field Descriptions
Bit
7-6
5-0
Field
Type
Reset
Description
RESERVED
IOUTH1
R
0h
Reserved
R/W
X
Output current setting for OUTH1
Load EEPROM register data when reset
7.6.2.17 IOUTAR Register (Offset = 60h) [Reset = 00h]
IOUTAR is shown in 图 7-90 and described in 表 7-92.
Return to the Summary Table.
图 7-90. IOUTAR Register
7
6
5
4
3
2
1
1
1
0
RESERVED
R-0h
表 7-92. IOUTAR Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.2.18 IOUTBR Register (Offset = 61h) [Reset = 00h]
IOUTBR is shown in 图 7-91 and described in 表 7-93.
Return to the Summary Table.
图 7-91. IOUTBR Register
7
6
5
4
3
2
0
RESERVED
R-0h
表 7-93. IOUTBR Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.2.19 IOUTCR Register (Offset = 62h) [Reset = 00h]
IOUTCR is shown in 图 7-92 and described in 表 7-94.
Return to the Summary Table.
图 7-92. IOUTCR Register
7
6
5
4
3
2
0
RESERVED
R-0h
表 7-94. IOUTCR Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
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7.6.2.20 IOUTDR Register (Offset = 63h) [Reset = 00h]
IOUTDR is shown in 图 7-93 and described in 表 7-95.
Return to the Summary Table.
图 7-93. IOUTDR Register
7
6
5
4
3
2
1
1
1
1
0
0
0
0
RESERVED
R-0h
表 7-95. IOUTDR Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.2.21 IOUTER Register (Offset = 64h) [Reset = 00h]
IOUTER is shown in 图 7-94 and described in 表 7-96.
Return to the Summary Table.
图 7-94. IOUTER Register
7
6
5
4
3
2
RESERVED
R-0h
表 7-96. IOUTER Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.2.22 IOUTFR Register (Offset = 65h) [Reset = 00h]
IOUTFR is shown in 图 7-95 and described in 表 7-97.
Return to the Summary Table.
图 7-95. IOUTFR Register
7
6
5
4
3
2
RESERVED
R-0h
表 7-97. IOUTFR Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.2.23 IOUTGR Register (Offset = 66h) [Reset = 00h]
IOUTGR is shown in 图 7-96 and described in 表 7-98.
Return to the Summary Table.
图 7-96. IOUTGR Register
7
6
5
4
3
2
RESERVED
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图 7-96. IOUTGR Register (continued)
R-0h
表 7-98. IOUTGR Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RESERVED
R
0h
Reserved
7.6.2.24 IOUTHR Register (Offset = 67h) [Reset = 00h]
IOUTHR is shown in 图 7-97 and described in 表 7-99.
Return to the Summary Table.
图 7-97. IOUTHR Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-99. IOUTHR Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
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7.6.3 CONF Registers
表 7-100 lists the memory-mapped registers for the CONF registers. All register offset addresses not listed in 表
7-100 should be considered as reserved locations and the register contents should not be modified.
Configuration Register
表 7-100. CONF Registers
Offset
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
Acronym
DIAGEN0
DIAGEN1
DIAGEN2
DIAGEN3
SLSTHSEL0
SLSTHSEL1
SLSTHSEL2
SLSTHSEL3
SLSDAC0
SLSDAC1
REFERENCE
DIAG
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
OUTAn, OUTBn Diagnostics Enable Setting
OUTCn, OUTDn Diagnostics Enable Setting
OUTEn, OUTFn Diagnostics Enable Setting
OUTGn, OUTHn Diagnostics Enable Setting
OUTAn, OUTBn Single-LED Short Threshold Selecting
OUTCn, OUTDn Single-LED Short Threshold Selecting
OUTEn, OUTFn Single-LED Short Threshold Selecting
OUTGn, OUTHn Single-LED Short Threshold Selecting
Single-LED Short Threshold0 Setting
Single-LED Short Threshold1 Setting
Reference Setting
Diagnostics Setting
DIAGMASK
OUTMASK
DIM
Diagnostics Mask Setting
OUTXn Diagnostics Mask Setting
Dimming Parameter Setting
DIM-R
Reserved Register
FSMAP0
OUTAn, OUTBn Fail-safe Mapping Setting
OUTCn, OUTDn Fail-safe Mapping Setting
OUTEn, OUTFn Fail-safe Mapping Setting
OUTGn, OUTHn Fail-safe Mapping Setting
FlewWire Parameter Setting
FSMAP1
FSMAP2
FSMAP3
FLEXWIRE0
FLEXWIRE1
FLEXWIRE2
CRC
FlewWire Parameter Setting
FlewWire Parameter Setting
EEPROM CRC
Complex bit access types are encoded to fit into small table cells. 表 7-101 shows the codes that are used for
access types in this section.
表 7-101. CONF Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.3.1 DIAGEN0 Register (Offset = 70h) [Reset = X]
DIAGEN0 is shown in 图 7-98 and described in 表 7-102.
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Return to the Summary Table.
图 7-98. DIAGEN0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
DIAGENOUTB1 DIAGENOUTB0
R/W-X R/W-X
RESERVED
R-0h
DIAGENOUTA1 DIAGENOUTA0
R/W-X R/W-X
表 7-102. DIAGEN0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
DIAGENOUTB1
R/W
X
Diagnostics enable register for OUTB1
Load EEPROM data when reset
0h = Disabled
1h = Enabled
4
DIAGENOUTB0
R/W
X
Diagnostics enable register for OUTB0
Load EEPROM data when reset
0h = Disabled
1h = Enabled
3-2
1
RESERVED
R
0h
X
Reserved
DIAGENOUTA1
R/W
Diagnostics enable register for OUTA1
Load EEPROM data when reset
0h = Disabled
1h = Enabled
0
DIAGENOUTA0
R/W
X
Diagnostics enable register for OUTA0
Load EEPROM data when reset
0h = Disabled
1h = Enabled
7.6.3.2 DIAGEN1 Register (Offset = 71h) [Reset = X]
DIAGEN1 is shown in 图 7-99 and described in 表 7-103.
Return to the Summary Table.
图 7-99. DIAGEN1 Register
7
6
5
4
3
2
1
DIAGENOUTC1 DIAGENOUTC0
R/W-X R/W-X
0
RESERVED
R-0h
DIAGENOUTD1 DIAGENOUTD0
R/W-X R/W-X
RESERVED
R-0h
表 7-103. DIAGEN1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
DIAGENOUTD1
R/W
X
Diagnostics enable register for OUTD1
Load EEPROM data when reset
0h = Disabled
1h = Enabled
4
DIAGENOUTD0
R/W
X
Diagnostics enable register for OUTD0
Load EEPROM data when reset
0h = Disabled
1h = Enabled
3-2
1
RESERVED
R
0h
X
Reserved
DIAGENOUTC1
R/W
Diagnostics enable register for OUTC1
Load EEPROM data when reset
0h = Disabled
1h = Enabled
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表 7-103. DIAGEN1 Register Field Descriptions (continued)
Bit
Field
DIAGENOUTC0
Type
Reset
Description
0
R/W
X
Diagnostics enable register for OUTC0
Load EEPROM data when reset
0h = Disabled
1h = Enabled
7.6.3.3 DIAGEN2 Register (Offset = 72h) [Reset = X]
DIAGEN2 is shown in 图 7-100 and described in 表 7-104.
Return to the Summary Table.
图 7-100. DIAGEN2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
DIAGENOUTF1 DIAGENOUTF0
R/W-X R/W-X
RESERVED
R-0h
DIAGENOUTE1 DIAGENOUTE0
R/W-X R/W-X
表 7-104. DIAGEN2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
DIAGENOUTF1
R/W
X
Diagnostics enable register for OUTF1
Load EEPROM data when reset
0h = Disabled
1h = Enabled
4
DIAGENOUTF0
R/W
X
Diagnostics enable register for OUTF0
Load EEPROM data when reset
0h = Disabled
1h = Enabled
3-2
1
RESERVED
R
0h
X
Reserved
DIAGENOUTE1
R/W
Diagnostics enable register for OUTE1
Load EEPROM data when reset
0h = Disabled
1h = Enabled
0
DIAGENOUTE0
R/W
X
Diagnostics enable register for OUTE0
Load EEPROM data when reset
0h = Disabled
1h = Enabled
7.6.3.4 DIAGEN3 Register (Offset = 73h) [Reset = X]
DIAGEN3 is shown in 图 7-101 and described in 表 7-105.
Return to the Summary Table.
图 7-101. DIAGEN3 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
DIAGENOUTH1 DIAGENOUTH0
RESERVED
R-0h
DIAGENOUTG DIAGENOUTG
1
0
R/W-X R/W-X
R/W-X
R/W-X
表 7-105. DIAGEN3 Register Field Descriptions
Bit
7-6
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
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表 7-105. DIAGEN3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
DIAGENOUTH1
R/W
X
Diagnostics enable register for OUTH1
Load EEPROM data when reset
0h = Disabled
1h = Enabled
4
DIAGENOUTH0
R/W
X
Diagnostics enable register for OUTH0
Load EEPROM data when reset
0h = Disabled
1h = Enabled
3-2
1
RESERVED
R
0h
X
Reserved
DIAGENOUTG1
R/W
Diagnostics enable register for OUTG1
Load EEPROM data when reset
0h = Disabled
1h = Enabled
0
DIAGENOUTG0
R/W
X
Diagnostics enable register for OUTG0
Load EEPROM data when reset
0h = Disabled
1h = Enabled
7.6.3.5 SLSTHSEL0 Register (Offset = 74h) [Reset = X]
SLSTHSEL0 is shown in 图 7-102 and described in 表 7-106.
Return to the Summary Table.
图 7-102. SLSTHSEL0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SLSTHOUTB1 SLSTHOUTB0
R/W-X R/W-X
RESERVED
R-0h
SLSTHOUTA1 SLSTHOUTA0
R/W-X R/W-X
表 7-106. SLSTHSEL0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
SLSTHOUTB1
R/W
X
Single-LED short-circuit threshold selection register for OUTB1
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
4
SLSTHOUTB0
R/W
X
Single-LED short-circuit threshold selection register for OUTB0
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
3-2
1
RESERVED
R
0h
X
Reserved
SLSTHOUTA1
R/W
Single-LED short-circuit threshold selection register for OUTA1
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
0
SLSTHOUTA0
R/W
X
Single-LED short-circuit threshold selection register for OUTA0
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
7.6.3.6 SLSTHSEL1 Register (Offset = 75h) [Reset = X]
SLSTHSEL1 is shown in 图 7-103 and described in 表 7-107.
Return to the Summary Table.
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图 7-103. SLSTHSEL1 Register
7
6
5
4
3
2
1
0
RESERVED
SLSTHOUTD1 SLSTHOUTD0
R/W-X R/W-X
RESERVED
R-0h
SLSTHOUTC1 SLSTHOUTC0
R/W-X R/W-X
R-0h
表 7-107. SLSTHSEL1 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
SLSTHOUTD1
R/W
X
Single-LED short-circuit threshold selection register for OUTD1
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
4
SLSTHOUTD0
R/W
X
Single-LED short-circuit threshold selection register for OUTD0
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
3-2
1
RESERVED
R
0h
X
Reserved
SLSTHOUTC1
R/W
Single-LED short-circuit threshold selection register for OUTC1
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
0
SLSTHOUTC0
R/W
X
Single-LED short-circuit threshold selection register for OUTC0
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
7.6.3.7 SLSTHSEL2 Register (Offset = 76h) [Reset = X]
SLSTHSEL2 is shown in 图 7-104 and described in 表 7-108.
Return to the Summary Table.
图 7-104. SLSTHSEL2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SLSTHOUTF1 SLSTHOUTF0
R/W-X R/W-X
RESERVED
R-0h
SLSTHOUTE1 SLSTHOUTE0
R/W-X R/W-X
表 7-108. SLSTHSEL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
SLSTHOUTF1
R/W
X
Single-LED short-circuit threshold selection register for OUTF1
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
4
SLSTHOUTF0
R/W
X
Single-LED short-circuit threshold selection register for OUTF0
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
3-2
1
RESERVED
R
0h
X
Reserved
SLSTHOUTE1
R/W
Single-LED short-circuit threshold selection register for OUTE1
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
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表 7-108. SLSTHSEL2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
SLSTHOUTE0
R/W
X
Single-LED short-circuit threshold selection register for OUTE0
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
7.6.3.8 SLSTHSEL3 Register (Offset = 77h) [Reset = X]
SLSTHSEL3 is shown in 图 7-105 and described in 表 7-109.
Return to the Summary Table.
图 7-105. SLSTHSEL3 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SLSTHOUTH1 SLSTHOUTH0
R/W-X R/W-X
RESERVED
R-0h
SLSTHOUTG1 SLSTHOUTG0
R/W-X R/W-X
表 7-109. SLSTHSEL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
SLSTHOUTH1
R/W
X
Single-LED short-circuit threshold selection register for OUTH1
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
4
SLSTHOUTH0
R/W
X
Single-LED short-circuit threshold selection register for OUTH0
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
3-2
1
RESERVED
R
0h
X
Reserved
SLSTHOUTG1
R/W
Single-LED short-circuit threshold selection register for OUTG1
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
0
SLSTHOUTG0
R/W
X
Single-LED short-circuit threshold selection register for OUTG0
Load EEPROM data when reset
0h = SLSTH0 is selected
1h = SLSTH1 is selected
7.6.3.9 SLSDAC0 Register (Offset = 78h) [Reset = X]
SLSDAC0 is shown in 图 7-106 and described in 表 7-110.
Return to the Summary Table.
图 7-106. SLSDAC0 Register
7
6
5
4
3
2
1
0
SLSTH0
R/W-X
表 7-110. SLSDAC0 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
SLSTH0
R/W
X
Single-LED short-circuit setting register for SLSTH0
Load EEPROM data when reset
V(SLSTH0) = SLSTH0*0.125V + 2.5V
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7.6.3.10 SLSDAC1 Register (Offset = 79h) [Reset = X]
SLSDAC1 is shown in 图 7-107 and described in 表 7-111.
Return to the Summary Table.
图 7-107. SLSDAC1 Register
7
6
5
4
3
2
1
0
SLSTH1
R/W-X
表 7-111. SLSDAC1 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
SLSTH1
R/W
X
Single-LED short-circuit setting register for SLSTH1
Load EEPROM data when reset
V(SLSTH1) = SLSTH1*0.125V + 2.5V
7.6.3.11 REFERENCE Register (Offset = 7Ah) [Reset = X]
REFERENCE is shown in 图 7-108 and described in 表 7-112.
Return to the Summary Table.
图 7-108. REFERENCE Register
7
6
5
4
3
2
1
0
SLSEN
R/W-X
REFRANGE
R/W-X
LOWSUPTH
R/W-X
表 7-112. REFERENCE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SLSEN
R/W
X
Enable register for single-LED short-ciruit diagnostics
Load EEPROM data when reset
0h = Disabled
1h = Enabled
6-5
4-0
REFRANGE
LOWSUPTH
R/W
R/W
X
X
Reference current ratio setting register
Load EEPROM data when reset
0h = 64
1h = 128
2h = 256
3h = 512
Supply low threshold setting register
Load EEPROM data when reset
V(LOWSUPTH) = LOWSUPTH*1V + 4V
7.6.3.12 DIAG Register (Offset = 7Bh) [Reset = X]
DIAG is shown in 图 7-109 and described in 表 7-113.
Return to the Summary Table.
图 7-109. DIAG Register
7
6
5
4
3
2
1
0
IRETRY
R/W-X
BLANK
R/W-X
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表 7-113. DIAG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
IRETRY
R/W
X
LED open-circuit and short-circuit retry current setting register
I(RETRY) = (IRETRY*4 + 4)/64*I(FULL_RANGE)
Load EEPROM data when reset
3-0
BLANK
R/W
X
Diagnostics blank time setting register
Load EEPROM data when reset
0h = 100µs
1h = 20µs
2h = 30µs
3h = 50µs
4h = 80µs
5h = 150µs
6h = 200µs
7h = 300µs
8h = 500µs
9h = 800µs
Ah = 1ms
Bh = 1.2ms
Ch = 1.5ms
Dh = 2ms
Eh = 3ms
Fh = 4ms
7.6.3.13 DIAGMASK Register (Offset = 7Ch) [Reset = X]
DIAGMASK is shown in 图 7-110 and described in 表 7-114.
Return to the Summary Table.
图 7-110. DIAGMASK Register
7
6
5
4
3
2
1
0
MASKLOWSUP MASKSUPUV
MASKREF
R/W-X
MASKPRETSD
R/W-X
MASKTSD
R/W-X
MASKEEPCRC
R/W-X
RESERVED
R-0h
R/W-X
R/W-X
表 7-114. DIAGMASK Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MASKLOWSUP
MASKSUPUV
MASKREF
R/W
X
Supply low fault mask register
Load EEPROM data when reset
0h = Fault report is enabled
1h = Fault report is disabled
6
5
4
3
R/W
R/W
R/W
R/W
X
X
X
X
Supply undervoltage fault mask register
Load EEPROM data when reset
0h = Fault report is enabled
1h = Fault report is disabled
REF pin fault mask register
Load EEPROM data when reset
0h = Fault report is enabled
1h = Fault report is disabled
MASKPRETSD
MASKTSD
Thermal pre-warning fault mask register
Load EEPROM data when reset
0h = Fault report is enabled
1h = Fault report is disabled
Thermal shutdown fault mask register
Load EEPROM data when reset
0h = Fault report is enabled
1h = Fault report is disabled
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表 7-114. DIAGMASK Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
MASKEEPCRC
R/W
X
EEPROM CRC fault mask register
Load EEPROM data when reset
0h = Fault report is enabled
1h = Fault report is disabled
1-0
RESERVED
R
0h
Reserved
7.6.3.14 OUTMASK Register (Offset = 7Dh) [Reset = X]
OUTMASK is shown in 图 7-111 and described in 表 7-115.
Return to the Summary Table.
图 7-111. OUTMASK Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
MASKOPEN
R/W-X
MASKSHORT
R/W-X
MASKSLS
R/W-X
表 7-115. OUTMASK Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
MASKOPEN
R
0h
Reserved
R/W
X
Output open-circuit fault mask register
Load EEPROM data when reset
0h = Fault report is enabled
1h = Fault report is disabled
1
0
MASKSHORT
MASKSLS
R/W
R/W
X
X
Output short-circuit fault mask register
Load EEPROM data when reset
0h = Fault report is enabled
1h = Fault report is disabled
Single-LED short-circuit fault mask register
Load EEPROM data when reset
0h = Fault report is enabled
1h = Fault report is disabled
7.6.3.15 DIM Register (Offset = 7Eh) [Reset = X]
DIM is shown in 图 7-112 and described in 表 7-116.
Return to the Summary Table.
图 7-112. DIM Register
7
6
5
4
3
2
1
0
EXPEN
R/W-X
PSEN
R/W-X
12BIT
R/W-X
PSMEN
R/W-X
PWMFREQ
R/W-X
表 7-116. DIM Register Field Descriptions
Bit
Field
Type
Reset
Description
7
EXPEN
R/W
X
Enable register for exponential dimming curve
Load EEPROM data when reset
0h = Disabled
1h = Enabled
6
PSEN
R/W
X
Enable register for phase shift dimming
Load EEPROM data when reset
0h = Disabled
1h = Enabled
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表 7-116. DIM Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
12BIT
R/W
X
Enable register for 12-bit dimming resolution diagnostics
Load EEPROM data when reset
0h = Disabled
1h = Enabled
4
PSMEN
R/W
R/W
X
X
Enable register for digital power save mode
Load EEPROM data when reset
0h = Disabled
1h = Enabled
3-0
PWMFREQ
PWM dimming frequency setting register
Load EEPROM data when reset
0h = 200Hz
1h = 250Hz
2h = 300Hz
3h = 350Hz
4h = 400Hz
5h = 500Hz
6h = 600Hz
7h = 800Hz
8h = 1000Hz
9h = 1200Hz
Ah = 2000Hz
Bh = 4000Hz
Ch = 5900Hz
Dh = 7800Hz
Eh = 9600Hz
Fh = 20800Hz
7.6.3.16 DIM-R Register (Offset = 7Fh) [Reset = 00h]
DIM-R is shown in 图 7-113 and described in 表 7-117.
Return to the Summary Table.
图 7-113. DIM-R Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
表 7-117. DIM-R Register Field Descriptions
Bit
7-0
Field
RESERVED
Type
Reset
Description
R
0h
Reserved
7.6.3.17 FSMAP0 Register (Offset = 80h) [Reset = X]
FSMAP0 is shown in 图 7-114 and described in 表 7-118.
Return to the Summary Table.
图 7-114. FSMAP0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FSOUTB1
R/W-X
FSOUTB0
R/W-X
RESERVED
R-0h
FSOUTA1
R/W-X
FSOUTA0
R/W-X
表 7-118. FSMAP0 Register Field Descriptions
Bit
7-6
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
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表 7-118. FSMAP0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
FSOUTB1
R/W
X
Fail-safe state control input mapping for OUTB1
Load EEPROM data when reset
0h = OUTB1 is mapped to FS0 in fail-safe state
1h = OUTB1 is mapped to FS1 in fail-safe state
4
FSOUTB0
R/W
X
Fail-safe state control input mapping for OUTB0
Load EEPROM data when reset
0h = OUTB0 is mapped to FS0 in fail-safe state
1h = OUTB0 is mapped to FS1 in fail-safe state
3-2
1
RESERVED
FSOUTA1
R
0h
X
Reserved
R/W
Fail-safe state control input mapping for OUTA1
Load EEPROM data when reset
0h = OUTA1 is mapped to FS0 in fail-safe state
1h = OUTA1 is mapped to FS1 in fail-safe state
0
FSOUTA0
R/W
X
Fail-safe state control input mapping for OUTA0
Load EEPROM data when reset
0h = OUTA0 is mapped to FS0 in fail-safe state
1h = OUTA0 is mapped to FS1 in fail-safe state
7.6.3.18 FSMAP1 Register (Offset = 81h) [Reset = X]
FSMAP1 is shown in 图 7-115 and described in 表 7-119.
Return to the Summary Table.
图 7-115. FSMAP1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FSOUTD1
R/W-X
FSOUTD0
R/W-X
RESERVED
R-0h
FSOUTC1
R/W-X
FSOUTC0
R/W-X
表 7-119. FSMAP1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
FSOUTD1
R
0h
Reserved
R/W
X
Fail-safe state control input mapping for OUTD1
Load EEPROM data when reset
0h = OUTD1 is mapped to FS0 in fail-safe state
1h = OUTD1 is mapped to FS1 in fail-safe state
4
FSOUTD0
R/W
X
Fail-safe state control input mapping for OUTC2
Load EEPROM data when reset
0h = OUTD0 is mapped to FS0 in fail-safe state
1h = OUTD0 is mapped to FS1 in fail-safe state
3-2
1
RESERVED
FSOUTC1
R
0h
X
Reserved
R/W
Fail-safe state control input mapping for OUTC1
Load EEPROM data when reset
0h = OUTC1 is mapped to FS0 in fail-safe state
1h = OUTC1 is mapped to FS1 in fail-safe state
0
FSOUTC0
R/W
X
Fail-safe state control input mapping for OUTC0
Load EEPROM data when reset
0h = OUTC0 is mapped to FS0 in fail-safe state
1h = OUTC0 is mapped to FS1 in fail-safe state
7.6.3.19 FSMAP2 Register (Offset = 82h) [Reset = X]
FSMAP2 is shown in 图 7-116 and described in 表 7-120.
Return to the Summary Table.
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图 7-116. FSMAP2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FSOUTF1
R/W-X
FSOUTF0
R/W-X
RESERVED
R-0h
FSOUTE1
R/W-X
FSOUTE0
R/W-X
表 7-120. FSMAP2 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
FSOUTF1
R
0h
Reserved
R/W
X
Fail-safe state control input mapping for OUTF1
Load EEPROM data when reset
0h = OUTF1 is mapped to FS0 in fail-safe state
1h = OUTF1 is mapped to FS1 in fail-safe state
4
FSOUTF0
R/W
X
Fail-safe state control input mapping for OUTF0
Load EEPROM data when reset
0h = OUTF0 is mapped to FS0 in fail-safe state
1h = OUTF0 is mapped to FS1 in fail-safe state
3-2
1
RESERVED
FSOUTE1
R
0h
X
Reserved
R/W
Fail-safe state control input mapping for OUTE1
Load EEPROM data when reset
0h = OUTE1 is mapped to FS0 in fail-safe state
1h = OUTE1 is mapped to FS1 in fail-safe state
0
FSOUTE0
R/W
X
Fail-safe state control input mapping for OUTE0
Load EEPROM data when reset
0h = OUTE0 is mapped to FS0 in fail-safe state
1h = OUTE0 is mapped to FS1 in fail-safe state
7.6.3.20 FSMAP3 Register (Offset = 83h) [Reset = X]
FSMAP3 is shown in 图 7-117 and described in 表 7-121.
Return to the Summary Table.
图 7-117. FSMAP3 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FSOUTH1
R/W-X
FSOUTH0
R/W-X
RESERVED
R-0h
FSOUTG1
R/W-X
FSOUTG0
R/W-X
表 7-121. FSMAP3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
FSOUTH1
R
0h
Reserved
R/W
X
Fail-safe state control input mapping for OUTH1
Load EEPROM data when reset
0h = OUTH1 is mapped to FS0 in fail-safe state
1h = OUTH1 is mapped to FS1 in fail-safe state
4
FSOUTH0
R/W
X
Fail-safe state control input mapping for OUTH0
Load EEPROM data when reset
0h = OUTH0 is mapped to FS0 in fail-safe state
1h = OUTH0 is mapped to FS1 in fail-safe state
3-2
1
RESERVED
FSOUTG1
R
0h
X
Reserved
R/W
Fail-safe state control input mapping for OUTG1
Load EEPROM data when reset
0h = OUTG1 is mapped to FS0 in fail-safe state
1h = OUTG1 is mapped to FS1 in fail-safe state
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表 7-121. FSMAP3 Register Field Descriptions (continued)
Bit
Field
FSOUTG0
Type
Reset
Description
0
R/W
X
Fail-safe state control input mapping for OUTG0
Load EEPROM data when reset
0h = OUTG0 is mapped to FS0 in fail-safe state
1h = OUTG0 is mapped to FS1 in fail-safe state
7.6.3.21 FLEXWIRE0 Register (Offset = 84h) [Reset = X]
FLEXWIRE0 is shown in 图 7-118 and described in 表 7-122.
Return to the Summary Table.
图 7-118. FLEXWIRE0 Register
7
6
5
4
3
2
1
0
WDTIMER
R/W-X
DBWTIMER
R/W-X
ACKEN
R/W-X
表 7-122. FLEXWIRE0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
WDTIMER
R/W
X
Communication watchdog timer setting register
Load EEPROM data when reset
0h = Disabled, do not automatically enter fail-safe state
1h = 200µs
2h = 500µs
3h = 1ms
4h = 2ms
5h = 5ms
6h = 10ms
7h = 20ms
8h = 50ms
9h = 100ms
Ah = 200ms
Bh = 500ms
Ch = 0µs, directly enter fail-safe state
Dh = 0µs, directly enter fail-safe state
Eh = 0µs, directly enter fail-safe state
Fh = 0µs, directly enter fail-safe state
3-1
DBWTIMER
R/W
X
Data transaction break waiting timer setting register
Load EEPROM data when reset
0h = 1ms
1h = 125µs
2h = 250µs
3h = 500µs
4h = 1.25ms
5h = 2.5ms
6h = 5ms
7h = 5ms
0
ACKEN
R/W
X
Enable register for acknowledgement
Load EEPROM data when reset
0h = Disabled
1h = Enabled
7.6.3.22 FLEXWIRE1 Register (Offset = 85h) [Reset = X]
FLEXWIRE1 is shown in 图 7-119 and described in 表 7-123.
Return to the Summary Table.
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图 7-119. FLEXWIRE1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
INTADDR
R/W-X
DEVADDR
R/W-X
表 7-123. FLEXWIRE1 Register Field Descriptions
Bit
7-5
4
Field
Type
Reset
Description
RESERVED
INTADDR
R
0h
Reserved
R/W
X
Devce address selection register
Load EEPROM data when reset
0h = Device address set by ADDR2/ADDR1 and ADDR0 pins
1h = Device address set by DEVADDR
3-0
DEVADDR
R/W
X
Device address setting register
Load EEPROM data when reset
0h = slave address is 0000b
1h = slave address is 0001b
2h = slave address is 0010b
3h = slave address is 0011b
4h = slave address is 0100b
5h = slave address is 0101b
6h = slave address is 0110b
7h = slave address is 0111b
8h = slave address is 1000b
9h = slave address is 1001b
Ah = slave address is 1010b
Bh = slave address is 1011b
Ch = slave address is 1100b
Dh = slave address is 1101b
Eh = slave address is 1110b
Fh = slave address is 1111b
7.6.3.23 FLEXWIRE2 Register (Offset = 86h) [Reset = X]
FLEXWIRE2 is shown in 图 7-120 and described in 表 7-124.
Return to the Summary Table.
图 7-120. FLEXWIRE2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
OFAF
R/W-X
INITTIMER
R/W-X
表 7-124. FLEXWIRE2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
OFAF
R
0h
Reserved
R/W
X
Output one-fail-all-fail setting register in fail-safe state
Load EEPROM data when reset
0h = OFAF Disabled
1h = OFAF Enabled
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表 7-124. FLEXWIRE2 Register Field Descriptions (continued)
Bit
Field
INITTIMER
Type
Reset
Description
3-0
R/W
X
Initialization timer setting register
Load EEPROM data when reset
0h = 0ms
1h = 50ms
2h = 20ms
3h = 10ms
4h = 5ms
5h = 2ms
6h = 1ms
7h = 500µs
8h = 200µs
9h = 100µs
Ah = 50µs
Bh = 50µs
Ch = 50µs
Dh = 50µs
Eh = 50µs
Fh = 50µs
7.6.3.24 CRC Register (Offset = 87h) [Reset = X]
CRC is shown in 图 7-121 and described in 表 7-125.
Return to the Summary Table.
图 7-121. CRC Register
7
6
5
4
3
2
1
0
EEPCRC
R/W-X
表 7-125. CRC Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPCRC
R/W
X
CRC reference for all EEPROM registers including RESERVED
registers, manufacture default CRC result is 81h
Load EEPROM data when reset
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7.6.4 CTRL Registers
表 7-126 lists the memory-mapped registers for the CTRL registers. All register offset addresses not listed in 表
7-126 should be considered as reserved locations and the register contents should not be modified.
Control Register
表 7-126. CTRL Registers
Offset
90h
91h
92h
93h
94h
95h
96h
97h
98h
Acronym
ADCCH
CLR
Register Name
Section
Go
ADC Channel Selection Setting
Control Register for Clear
Go
DEBUG
LOCK
Control Register for Debug
Control Register for Register Lock
Control Register for Clear Register
Control Register for NSTB
Gate Register for MISC and LOCK
Control Register for EEP Operation
Gate Register for EEP
Go
Go
CLRREG
NSTB
Go
Go
CTRLGATE
EEP
Go
Go
EEPGATE
Go
Complex bit access types are encoded to fit into small table cells. 表 7-127 shows the codes that are used for
access types in this section.
表 7-127. CTRL Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.6.4.1 ADCCH Register (Offset = 90h) [Reset = 00h]
ADCCH is shown in 图 7-122 and described in 表 7-128.
Return to the Summary Table.
图 7-122. ADCCH Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
ADCCHSEL
R/W-0h
表 7-128. ADCCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4-0
RESERVED
ADCCHSEL
R
0h
Reserved
R/W
0h
Channel selection setting for ADC voltage measurement, write this
register automatically initiates the ADC conversion
7.6.4.2 CLR Register (Offset = 91h) [Reset = 00h]
CLR is shown in 图 7-123 and described in 表 7-129.
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Return to the Summary Table.
图 7-123. CLR Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
CLRFS
R/W-0h
CLRFAULT
R/W-0h
CLRPOR
R/W-0h
表 7-129. CLR Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
CLRFS
R
0h
Reserved
R/W
0h
Write 1 to force device to exit fail-safe state to normal state,
automatically returns to 0
1
0
CLRFAULT
CLRPOR
R/W
R/W
0h
0h
Write 1 to clear all fault flags, automatically returns to 0
Write 1 to clear POR fault flag, automatically returns to 0
7.6.4.3 DEBUG Register (Offset = 92h) [Reset = 00h]
DEBUG is shown in 图 7-124 and described in 表 7-130.
Return to the Summary Table.
图 7-124. DEBUG Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FORCEFS
R/W-0h
FPRCEERR
R/W-0h
表 7-130. DEBUG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
1
RESERVED
FORCEFS
FPRCEERR
R
0h
Reserved
R/W
R/W
0h
Write 1 to force device to fail-safe state, automatically returns to 0
0
0h
Write 1 to set FLAG_ERR to 1 and ERR output pulled down for 50µs
in normal state, automatically returns to 0
7.6.4.4 LOCK Register (Offset = 93h) [Reset = 03h]
LOCK is shown in 图 7-125 and described in 表 7-131.
Return to the Summary Table.
图 7-125. LOCK Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
BRTLOCK
R/W-0h
CONFLOCK
R/W-1h
IOUTLOCK
R/W-1h
表 7-131. LOCK Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
BRTLOCK
R
0h
Reserved
R/W
0h
BRT register lock
0h = Write protection is disabled
1h = Write protection is enabled
1
CONFLOCK
R/W
1h
CONF register lock
0h = Write protection is disabled
1h = Write protection is enabled
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表 7-131. LOCK Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
IOUTLOCK
R/W
1h
IOUT register lock
0h = Write protection is disabled
1h = Write protection is enabled
7.6.4.5 CLRREG Register (Offset = 94h) [Reset = 00h]
CLRREG is shown in 图 7-126 and described in 表 7-132.
Return to the Summary Table.
图 7-126. CLRREG Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
SOFTRESET
R/W-0h
EEPLOAD
R/W-0h
REGDEFAULT
R/W-0h
表 7-132. CLRREG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
2
RESERVED
SOFTRESET
R
0h
Reserved
R/W
0h
Write 1 to reset all state machine and all registers, automatically
returns to 0
1
0
EEPLOAD
R/W
R/W
0h
0h
Write 1 to load EEP data to corresponding registers, automatically
returns to 0
REGDEFAULT
Write 1 to set all registers to default value, automatically returns to 0
7.6.4.6 NSTB Register (Offset = 95h) [Reset = 00h]
NSTB is shown in 图 7-127 and described in 表 7-133.
Return to the Summary Table.
图 7-127. NSTB Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
NSTB
R/W-0h
表 7-133. NSTB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
RESERVED
NSTB
R
0h
Reserved
R/W
0h
NSTB output internal pulling up control register
0h = Pulling up is enabled
1h = Pulling up is disabled
7.6.4.7 CTRLGATE Register (Offset = 96h) [Reset = 00h]
CTRLGATE is shown in 图 7-128 and described in 表 7-134.
Return to the Summary Table.
图 7-128. CTRLGATE Register
7
6
5
4
3
2
1
0
CTRLGATE
R/W-0h
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图 7-128. CTRLGATE Register (continued)
表 7-134. CTRLGATE Register Field Descriptions
Bit
Field
CTRLGATE
Type
Reset
Description
7-0
R/W
0h
Gate register for DEBUG, LOCK and CLRREG registers access,
write 43h, 4Fh, 44h and 45h one-byte by one-byte
7.6.4.8 EEP Register (Offset = 97h) [Reset = 00h]
EEP is shown in 图 7-129 and described in 表 7-135.
Return to the Summary Table.
图 7-129. EEP Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
EEPPROG
R/W-0h
EEPMODE
R/W-0h
表 7-135. EEP Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
1
RESERVED
EEPPROG
R
0h
Reserved
R/W
0h
EEPROM burning starts in EEPROM programming state only,
automatically returns to 0
0
EEPMODE
R/W
0h
EEPROM programming state setting
0h = Disabled
1h = Enabled
7.6.4.9 EEPGATE Register (Offset = 98h) [Reset = 00h]
EEPGATE is shown in 图 7-130 and described in 表 7-136.
Return to the Summary Table.
图 7-130. EEPGATE Register
7
6
5
4
3
2
1
0
EEPGATE
R/W-0h
表 7-136. EEPGATE Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
EEPGATE
R/W
0h
Gate register for EEP registers access, write 00h, 04h, 02h, 09h, 02h
and 09h one-byte by one-byte
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7.6.5 FLAG Registers
表 7-137 lists the memory-mapped registers for the FLAG registers. All register offset addresses not listed in 表
7-137 should be considered as reserved locations and the register contents should not be modified.
FLAG Register
表 7-137. FLAG Registers
Offset
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
Acronym
Register Name
Section
Go
FLAG_ERR
Device Error Flag Register
FLAG_STATUS
FLAG_ADC
Device Status Flag Register
Go
Selected Channel ADC Measurement Result
OUTAn, OUTBn Single-LED Short Error FLAG
OUTCn, OUTDn Single-LED Short Error FLAG
OUTEn, OUTFn Single-LED Short Error FLAG
OUTGn, OUTHn Single-LED Short Error FLAG
OUTAn, OUTBn LED Open Error FLAG
OUTCn, OUTDn LED Open Error FLAG
OUTEn, OUTFn LED Open Error FLAG
OUTGn, OUTHn LED Open Error FLAG
OUTAn, OUTBn Short-to-GND Error FLAG
OUTCn, OUTDn Short-to-GND Error FLAG
OUTEn, OUTFn Short-to-GND Error FLAG
OUTGn, OUTHn Short-to-GND Error FLAG
EEPROM Calculated CRC
Go
FLAG_SLS0
Go
FLAG_SLS1
Go
FLAG_SLS2
Go
FLAG_SLS3
Go
FLAG_OPEN0
FLAG_OPEN1
FLAG_OPEN2
FLAG_OPEN3
FLAG_SHORT0
FLAG_SHORT1
FLAG_SHORT2
FLAG_SHORT3
FLAG_EEPCRC
Go
Go
Go
Go
Go
Go
Go
Go
Go
Complex bit access types are encoded to fit into small table cells. 表 7-138 shows the codes that are used for
access types in this section.
表 7-138. FLAG Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Reset or Default Value
-n
Value after reset or the default
value
7.6.5.1 FLAG_ERR Register (Offset = A0h) [Reset = 01h]
FLAG_ERR is shown in 图 7-131 and described in 表 7-139.
Return to the Summary Table.
图 7-131. FLAG_ERR Register
7
6
5
4
3
2
1
0
FLAG_LOWSU FLAG_SUPUV
P
FLAG_REF
FLAG_PRETSD
FLAG_TSD
FLAG_EEPCR
C
FLAG_OUT
FLAG_ERR
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-1h
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表 7-139. FLAG_ERR Register Field Descriptions
Bit
Field
Type
Reset
Description
7
FLAG_LOWSUP
FLAG_SUPUV
FLAG_REF
R
0h
Supply voltage low flag
0h = Supply voltage is above preset threshold.
1h = Supply voltage is below preset threshold.
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
1h
Supply undervoltage fault flag
0h = No supply undervoltage fault is detected.
1h = Device has supply undervoltage fault detected.
REF pin fault flag
0h = No REF pin fault is detected.
1h = Device has REF pin fault detected.
FLAG_PRETSD
FLAG_TSD
Overtemperature Pre warning flag
0h = No overtemperature pre-warning is detected.
1h = Device has triggered overtemperature pre-warning threshold.
Thermal shutdown flag
0h = No thermal shutdown fault is triggered.
1h = Device has triggered thermal shutdown fault.
FLAG_EEPCRC
FLAG_OUT
EEPROM CRC failure flag
0h = EEPROM CRC passes.
1h = EEPROM CRC fails.
Output fault flag
0h = No output fault is detected.
1h = Device has at least one fault detected on output channels.
FLAG_ERR
Error flag
0h = No error flag.
1h = Device has at least one error flag.
7.6.5.2 FLAG_STATUS Register (Offset = A1h) [Reset = 01h]
FLAG_STATUS is shown in 图 7-132 and described in 表 7-140.
Return to the Summary Table.
图 7-132. FLAG_STATUS Register
7
6
5
4
3
2
1
0
FLAG_EEPPAR FLAG_EXTFS1 FLAG_EXTFS0 FLAG_PROGD
ONE
FLAG_FS
R-0h
FLAG_ADCDO FLAG_ADCER
FLAG_POR
NE
R
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-1h
表 7-140. FLAG_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
5
4
3
FLAG_EEPPAR
FLAG_EXTFS1
FLAG_EXTFS0
FLAG_PROGDONE
FLAG_FS
R
0h
EEPROM parity error flag
0h = No internal EEPROM parity error is triggered.
1h = Internal EEPROM parity error is triggered.
R
R
R
R
0h
0h
0h
0h
FS1 input status flag
0h = FS1 input is logic low.
1h = FS1 input is logic high.
FS0 input status flag
0h = FS0 input is logic low.
1h = FS0 input is logic high.
EEPROM program completition flag
0h = EEPROM burning is not completed or not started.
1h = EEPROM burning is completed.
FS state flag
0h = Device is not in Fail-safe state.
1h = Device is in Fail-safe state.
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表 7-140. FLAG_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
FLAG_ADCDONE
R
0h
ADC measurement completition flag
0h = ADC measurement result is not available.
1h = ADC measurement result is available, read ADC_OUT or write
ADCCHSEL to clear FLAG_ADCDONE.
1
0
FLAG_ADCERR
FLAG_POR
R
R
0h
1h
ADC error flag
0h = No ADC error is triggered.
1h = ADC error is triggered.
Power-On-Reset flag
0h = No POR is triggered.
1h = Device has triggered POR.
7.6.5.3 FLAG_ADC Register (Offset = A2h) [Reset = 00h]
FLAG_ADC is shown in 图 7-133 and described in 表 7-141.
Return to the Summary Table.
图 7-133. FLAG_ADC Register
7
6
5
4
3
2
1
0
ADC_OUT
R-0h
表 7-141. FLAG_ADC Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
ADC_OUT
R
0h
ADC measurement result for selected channel
7.6.5.4 FLAG_SLS0 Register (Offset = A3h) [Reset = 00h]
FLAG_SLS0 is shown in 图 7-134 and described in 表 7-142.
Return to the Summary Table.
图 7-134. FLAG_SLS0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_SLSOUT FLAG_SLSOUT
RESERVED
R-0h
FLAG_SLSOUT FLAG_SLSOUT
B1
B0
A1
A0
R-0h
R-0h
R-0h
R-0h
表 7-142. FLAG_SLS0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
FLAG_SLSOUTB1
R
0h
Single-LED short-circuit fault flag for OUTB1
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
4
FLAG_SLSOUTB0
R
0h
Single-LED short-circuit fault flag for OUTB0
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_SLSOUTA1
Single-LED short-circuit fault flag for OUTA1
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
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表 7-142. FLAG_SLS0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
FLAG_SLSOUTA0
R
0h
Single-LED short-circuit fault flag for OUTA0
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
7.6.5.5 FLAG_SLS1 Register (Offset = A4h) [Reset = 00h]
FLAG_SLS1 is shown in 图 7-135 and described in 表 7-143.
Return to the Summary Table.
图 7-135. FLAG_SLS1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_SLSOUT FLAG_SLSOUT
RESERVED
R-0h
FLAG_SLSOUT FLAG_SLSOUT
D1
D0
C1
C0
R-0h
R-0h
R-0h
R-0h
表 7-143. FLAG_SLS1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
FLAG_SLSOUTD1
R
0h
Single-LED short-circuit fault flag for OUTD1
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
4
FLAG_SLSOUTD0
R
0h
Single-LED short-circuit fault flag for OUTD0
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_SLSOUTC1
Single-LED short-circuit fault flag for OUTC1
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
0
FLAG_SLSOUTC0
R
0h
Single-LED short-circuit fault flag for OUTC0
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
7.6.5.6 FLAG_SLS2 Register (Offset = A5h) [Reset = 00h]
FLAG_SLS2 is shown in 图 7-136 and described in 表 7-144.
Return to the Summary Table.
图 7-136. FLAG_SLS2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_SLSOUT FLAG_SLSOUT
RESERVED
R-0h
FLAG_SLSOUT FLAG_SLSOUT
F1
F0
E1
E0
R-0h
R-0h
R-0h
R-0h
表 7-144. FLAG_SLS2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
FLAG_SLSOUTF1
R
0h
Single-LED short-circuit fault flag for OUTF1
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
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表 7-144. FLAG_SLS2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
FLAG_SLSOUTF0
R
0h
Single-LED short-circuit fault flag for OUTF0
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_SLSOUTE1
Single-LED short-circuit fault flag for OUTE1
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
0
FLAG_SLSOUTE0
R
0h
Single-LED short-circuit fault flag for OUTE0
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
7.6.5.7 FLAG_SLS3 Register (Offset = A6h) [Reset = 00h]
FLAG_SLS3 is shown in 图 7-137 and described in 表 7-145.
Return to the Summary Table.
图 7-137. FLAG_SLS3 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_SLSOUT FLAG_SLSOUT
RESERVED
R-0h
FLAG_SLSOUT FLAG_SLSOUT
H1
H0
G1
G0
R-0h
R-0h
R-0h
R-0h
表 7-145. FLAG_SLS3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
FLAG_SLSOUTH1
R
0h
Single-LED short-circuit fault flag for OUTH1
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
4
FLAG_SLSOUTH0
R
0h
Single-LED short-circuit fault flag for OUTH0
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_SLSOUTG1
Single-LED short-circuit fault flag for OUTG1
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
0
FLAG_SLSOUTG0
R
0h
Single-LED short-circuit fault flag for OUTG0
0h = Single-LED short-circuit fault is not detected.
1h = Single-LED short-circuit fault is detected.
7.6.5.8 FLAG_OPEN0 Register (Offset = A7h) [Reset = 00h]
FLAG_OPEN0 is shown in 图 7-138 and described in 表 7-146.
Return to the Summary Table.
图 7-138. FLAG_OPEN0 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_OPENO FLAG_OPENO
RESERVED
R-0h
FLAG_OPENO FLAG_OPENO
UTB1
UTB0
UTA1
UTA0
R-0h
R-0h
R-0h
R-0h
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表 7-146. FLAG_OPEN0 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
FLAG_OPENOUTB1
R
0h
Output open-circuit fault flag for OUTB1
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
4
FLAG_OPENOUTB0
R
0h
Output open-circuit fault flag for OUTB0
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_OPENOUTA1
Output open-circuit fault flag for OUTA1
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
0
FLAG_OPENOUTA0
R
0h
Output open-circuit fault flag for OUTA0
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
7.6.5.9 FLAG_OPEN1 Register (Offset = A8h) [Reset = 00h]
FLAG_OPEN1 is shown in 图 7-139 and described in 表 7-147.
Return to the Summary Table.
图 7-139. FLAG_OPEN1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_OPENO FLAG_OPENO
RESERVED
R-0h
FLAG_OPENO FLAG_OPENO
UTD1
UTD0
UTC1
UTC0
R-0h
R-0h
R-0h
R-0h
表 7-147. FLAG_OPEN1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
FLAG_OPENOUTD1
R
0h
Output open-circuit fault flag for OUTD1
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
4
FLAG_OPENOUTD0
R
0h
Output open-circuit fault flag for OUTD0
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_OPENOUTC1
Output open-circuit fault flag for OUTC1
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
0
FLAG_OPENOUTC0
R
0h
Output open-circuit fault flag for OUTC0
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
7.6.5.10 FLAG_OPEN2 Register (Offset = A9h) [Reset = 00h]
FLAG_OPEN2 is shown in 图 7-140 and described in 表 7-148.
Return to the Summary Table.
图 7-140. FLAG_OPEN2 Register
7
6
5
4
3
2
1
0
RESERVED
FLAG_OPENO FLAG_OPENO
RESERVED
FLAG_OPENO FLAG_OPENO
UTE1 UTE0
UTF1
UTF0
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图 7-140. FLAG_OPEN2 Register (continued)
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表 7-148. FLAG_OPEN2 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
FLAG_OPENOUTF1
R
0h
Reserved
R
0h
Output open-circuit fault flag for OUTF1
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
4
FLAG_OPENOUTF0
R
0h
Output open-circuit fault flag for OUTF0
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_OPENOUTE1
Output open-circuit fault flag for OUTE1
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
0
FLAG_OPENOUTE0
R
0h
Output open-circuit fault flag for OUTE0
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
7.6.5.11 FLAG_OPEN3 Register (Offset = AAh) [Reset = 00h]
FLAG_OPEN3 is shown in 图 7-141 and described in 表 7-149.
Return to the Summary Table.
图 7-141. FLAG_OPEN3 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_OPENO FLAG_OPENO
RESERVED
R-0h
FLAG_OPENO FLAG_OPENO
UTH1
UTH0
UTG1
UTG0
R-0h
R-0h
R-0h
R-0h
表 7-149. FLAG_OPEN3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
FLAG_OPENOUTH1
R
0h
Output open-circuit fault flag for OUTH1
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
4
FLAG_OPENOUTH0
R
0h
Output open-circuit fault flag for OUTH0
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_OPENOUTG1
Output open-circuit fault flag for OUTG1
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
0
FLAG_OPENOUTG0
R
0h
Output open-circuit fault flag for OUTG0
0h = Output open-circuit fault is not detected.
1h = Output open-circuit fault is detected.
7.6.5.12 FLAG_SHORT0 Register (Offset = ABh) [Reset = 00h]
FLAG_SHORT0 is shown in 图 7-142 and described in 表 7-150.
Return to the Summary Table.
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图 7-142. FLAG_SHORT0 Register
7
6
5
4
3
2
1
0
RESERVED
FLAG_SHORT FLAG_SHORT
RESERVED
R-0h
FLAG_SHORT FLAG_SHORT
OUTB1
OUTB0
OUTA1
OUTA0
R-0h
R-0h
R-0h
R-0h
R-0h
表 7-150. FLAG_SHORT0 Register Field Descriptions
Bit
7-6
5
Field
Type
Reset
Description
RESERVED
R
0h
Reserved
FLAG_SHORTOUTB1
R
0h
Output short-circuit fault flag for OUTB1
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
4
FLAG_SHORTOUTB0
R
0h
Output short-circuit fault flag for OUTB0
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_SHORTOUTA1
Output short-circuit fault flag for OUTA1
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
0
FLAG_SHORTOUTA0
R
0h
Output short-circuit fault flag for OUTA0
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
7.6.5.13 FLAG_SHORT1 Register (Offset = ACh) [Reset = 00h]
FLAG_SHORT1 is shown in 图 7-143 and described in 表 7-151.
Return to the Summary Table.
图 7-143. FLAG_SHORT1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_SHORT FLAG_SHORT
RESERVED
R-0h
FLAG_SHORT FLAG_SHORT
OUTD1
OUTD0
OUTC1
OUTC0
R-0h
R-0h
R-0h
R-0h
表 7-151. FLAG_SHORT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
FLAG_SHORTOUTD1
R
0h
Output short-circuit fault flag for OUTD1
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
4
FLAG_SHORTOUTD0
R
0h
Output short-circuit fault flag for OUTD0
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_SHORTOUTC1
Output short-circuit fault flag for OUTC1
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
0
FLAG_SHORTOUTC0
R
0h
Output short-circuit fault flag for OUTC0
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
7.6.5.14 FLAG_SHORT2 Register (Offset = ADh) [Reset = 00h]
FLAG_SHORT2 is shown in 图 7-144 and described in 表 7-152.
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Return to the Summary Table.
图 7-144. FLAG_SHORT2 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_SHORT FLAG_SHORT
RESERVED
R-0h
FLAG_SHORT FLAG_SHORT
OUTF1
OUTF0
OUTE1
OUTE0
R-0h
R-0h
R-0h
R-0h
表 7-152. FLAG_SHORT2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
FLAG_SHORTOUTF1
R
0h
Output short-circuit fault flag for OUTF1
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
4
FLAG_SHORTOUTF0
R
0h
Output short-circuit fault flag for OUTF0
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_SHORTOUTE1
Output short-circuit fault flag for OUTE1
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
0
FLAG_SHORTOUTE0
R
0h
Output short-circuit fault flag for OUTE0
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
7.6.5.15 FLAG_SHORT3 Register (Offset = AEh) [Reset = 00h]
FLAG_SHORT3 is shown in 图 7-145 and described in 表 7-153.
Return to the Summary Table.
图 7-145. FLAG_SHORT3 Register
7
6
5
4
3
2
1
0
RESERVED
R-0h
FLAG_SHORT FLAG_SHORT
RESERVED
R-0h
FLAG_SHORT FLAG_SHORT
OUTH1
OUTH0
OUTG1
OUTG0
R-0h
R-0h
R-0h
R-0h
表 7-153. FLAG_SHORT3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
5
RESERVED
R
0h
Reserved
FLAG_SHORTOUTH1
R
0h
Output short-circuit fault flag for OUTH1
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
4
FLAG_SHORTOUTH0
R
0h
Output short-circuit fault flag for OUTH0
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
3-2
1
RESERVED
R
R
0h
0h
Reserved
FLAG_SHORTOUTG1
Output short-circuit fault flag for OUTG1
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
0
FLAG_SHORTOUTG0
R
0h
Output short-circuit fault flag for OUTG0
0h = Output short-circuit fault is not detected.
1h = Output short-circuit fault is detected.
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7.6.5.16 FLAG_EEPCRC Register (Offset = AFh) [Reset = 00h]
FLAG_EEPCRC is shown in 图 7-146 and described in 表 7-154.
Return to the Summary Table.
图 7-146. FLAG_EEPCRC Register
7
6
5
4
3
2
1
0
CALC_EEPCRC
R-0h
表 7-154. FLAG_EEPCRC Register Field Descriptions
Bit
7-0
Field
CALC_EEPCRC
Type
Reset
Description
R
0h
Calculated CRC result for all EEPROM
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8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS929160-Q1 device with FlexWire interface easily generates independent brightness and ON and OFF
control for large amount LED units. The device allows each single LED as a pixel in large LED array or string to
display a complicated pattern or animation under accurate control. The FlexWire interface also supports to use
the CAN physical layer through external CAN transceiver for data transmission between master microcontroller
(MCU) and TPS929160-Q1, which allows the TPS929160-Q1 to be controlled by control module far away in
long distance. With these features, the single TPS929160-Q1 or multiple TPS929160-Q1 devices can drive
large volume LEDs with digital control interface for automotive lighting applications. The long distance, reliable
off-board communication with high EMC performance simplifies the system design in lower cost for automotive
application.
The TPS929160-Q1 can also operate as a standalone LED driver without master MCU. The FAIL-SAFE state
is designed to ensure the TPS929160-Q1 keeps operating in case the communication is lost or the master
MCU is damaged. TPS929160-Q1 can also use the FAIL-SAFE state without master MCU design for traditional
automotive lighting applications.
8.2 Typical Application
8.2.1 Smart Rear Lamp with Distributed LED Drivers
Use multiple TPS929160-Q1 devices to control large number of LED pixels for rear-lamp animation.
Power from
BCM
CAN from
BCM
16x
16x
16x
16x
16x
DC/DC
(optional)
CAN
XCVR
TPS929160-Q1
TX RX
TPS929160-Q1
TX RX
TPS929160-Q1
TX RX
TPS929160-Q1
TX RX
TPS929160-Q1
TX
RX
TX
RX
TX
RX
CAN
XCVR
MCU
CAN XCVR
CAN XCVR
PCB board
CAN XCVR
LED Driver
图 8-1. System Block Diagram
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VLDO1
*
*
RX
OUTA0
OUTA1
RX
RX
OUTA0
OUTA1
VLDO2
4.7µF
VLDO1
4.7µF
VLDO
GND
VLDO
GND
CAN
Transceiver
TX
CANH
CANL
TX
TX
TPS929160-Q1
TPS929160-Q1
VIO
NSTB
EN
NSTB
INH
NSTB
EN
OUTH0
OUTH1
4.7k
OUTH0
OUTH1
100k
ERR
ERR
SUPPLY
SUPPLY
VBAT
FS0
SUPPLY
SUPPLY
VBAT
FS0
VBAT
DC/DC
Converter
4.7µF
4.7µF
ADDR3
ADDR3
10k
FS1
FS2
4.7µF
ADDR2
ADDR1
ADDR0
4.7µF
ADDR2
ADDR1
ADDR0
10k
FS1
FS1
VLDO2
REF
REF
1nF
R(REF)
1nF
R(REF)
: 1nF ceramic capacitor is recommended for each output channel
*
LED Driver
LED
图 8-2. Typical Application Schematic
8.2.2 Design Requirements
Input voltage ranges from 9 V to 16 V, and a total of 80 LED strings with 3 LEDs in each string are required in
one rear-lamp housing. The 80 LED strings must be controlled independently to achieve the animation effect.
The maximum forward voltage of single LED V(F_MAX) = 2.6 V, minimum forward voltage V(F_MIN) = 2.3 V, and
each string current I(LED) = 50 mA. The 48 strings of LED, and 32 strings of LED and MCU must be placed in
three different boards due to the shape of the rear-lamp housing.
8.2.3 Detailed Design Procedure
STEP 1: Determine the architecture at system level.
Because MCU is located in a separate board, the CAN physical layer must be used for off-board long distance
communication between LED driver boards and MCU board. The overall system block diagram is shown in 图
8-1 and the typical schematic for 48 strings of LED board is shown in 图 8-2. The pullup resistors for RX and TX
interface can or cannot required, depending on the model of the CAN transceiver. Normally the pullup resistor
value for RX and TX must be about 10 kΩ. TI recommends putting a 4.7-µF ceramic capacitor on the VLDO
output to keep the voltage stable. Because only one CAN transceiver is required per one PCB board, the CAN
transceiver must only be powered by one LDO output of the TPS929160-Q1. Do not tie the LDO outputs for all
TPS929160-Q1 in one PCB board. TI also recommends placing a 4.7-µF decoupling ceramic capacitor close to
the VBAT and the SUPPLY pin of each TPS929160-Q1 to obtain good EMC performance.
STEP 2: Thermal analysis for the worst application conditions.
Normally the thermal analysis is necessary for linear LED-driver applications to ensure that the operation
junction temperature of TPS929160-Q1 is well managed. The total power consumption on the TPS929160-Q1
itself is one important factor determining operation junction temperature, and it can be calculated by using the
following equation.
P
= V
- V
ìI(CH) ìN(CH)
(MAX)
(SUPPLY _MAX)
(LED _MIN)
(9)
where
•
•
•
•
V(SPPLY_MAX) is maximum supply voltage.
V(LED_MIN) is minimum output voltage.
I(CH) is channel current.
N(CH) is number of used channels.
Based on the worst-case analysis for maximum power consumption on device, either optimizing PCB layout for
better power dissipation as Layout Example describes or implementing a DC-to-DC converter in previous stage
on MCU board can be considered. The DC-to-DC such as a buck converter or buck-boost converter can regulate
the battery voltage to be a stable supply for the TPS929160-Q1 with sufficient headroom. A properly designed
supply voltage is helpful to minimize the power consumption on the TPS929160-Q1 itself as well as the whole
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system. In this application, the DC-to-DC converter with 8.6-V output voltage can make sure current output on
each output channel of TPS929160-Q1 is stable. The calculated maximum power dissipation on the device is
1.36 W as show in the below equation.
(10)
where
•
•
•
•
V(SPPLY_MAX) is maximum supply voltage.
V(LED_MIN) is minimum output voltage.
I(CH) is channel current.
N(CH) is number of used channels.
STEP 3: Set up the slave address for individual TPS929160-Q1.
The slave address of TPS929160-Q1 can be configured by ADDR3/ADDR2/ADDR1/ADDR0 pins or
DEVADDR[3:0] selected by INTADDR. The detailed description is explained in UART Interface Address Setting.
STEP 4: DC current setup for each LED string.
The DC current for all output channel can be programmed by an external resistor, R(REF), and internal register
REFRANGE. The resistor value can be calculated by using 方程式 11. The manufacturer default value for K(REF)
is 512. If the other number rather than 512 is chosen for DC current setting, the selected code needs to be burnt
into EEPROM to change the default value for REFRANGE. A 1-nF ceramic capacitor is recommended to be
placed in parallel with R(REF) resistor to improve the noise immunity. The 6-bit register IOUTXn can be used to
program DC current for each output channel independently mainly for dot correction purpose. The code setting
for IOUTXn registers must be decided in the end of production line according to the LED calibration result. The
detailed calculation is described in 64-Step Programmable High-Side Constant-Current Output.
V
(REF)
R(REF)
=
ìK(REF)
I(FULL _RANGE)
(11)
where
•
•
V(REF) = 1.235 V typically.
K(REF) = 64, 128, 256 or 512 (default).
表 8-1. Reference Current Range Setting
CURRENT (mA)
REFRANGE
K(REF)
512
256
128
64
REF RESISTOR VALUE (kΩ)
11b
12.7
6.34
3.16
1.58
10b
50
01b
00b
TI recommends placing a 1-nF ceramic capacitor on each of output channels to achieve good EMC
performance.
STEP 5: Design the configuration for PWM generator. Basically, there are three main parameters for PWM
generator that must be considered, including:
•
•
PWM frequency is set by PWMFREQ. The detailed calculation and description is explained in PWM Dimming
Frequency. The default value of PWMFREQ can be changed by burning the target value to EEPROM.
PWM duty cycle is set by PWMOUTXn and PWMLOWOUTXn. The detailed calculation and description are
explained in Linear Brightness Control. The default value of PWMOUTXn and PWMLOWOUTXn can be
changed by burning the target value to EEPROM.
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•
PWM dimming method set by EXPEN. The detailed calculation and description are explained in Exponential
Brightness Control. The default value of EXPEN can be changed by burning the target value to EEPROM.
STEP 6: Design the diagnostics configuration. The diagnostics configuration for both NORMAL state and FAIL-
SAFE states must be set up properly based on the system requirements. The following configuration registers
must be designed:
•
•
•
Low-supply warning threshold set by LOWSUPTH. The detail calculation and description are explained in
Low-Supply Warning Diagnostics in NORMAL State. The default value of LOWSUPTH can be changed by
burning the target value to EEPROM.
Diagnostics enabling setup for each channel by CONF_DIAGENCHx. The diagnostics for each channel can
be enabled or disabled by DIAGENOUTXn register. The detailed description is explained in Fault Masking.
The default value of DIAGENOUTXn can be changed by burning the target value to EEPROM.
Single-LED short-circuit configuration by SLSEN, SLSTHOUTXn, SLSTH0 and SLSTH1. The detailed
calculation and description are explained in Single-LED Short-Circuit Detection in NORMAL state. The default
value of SLSEN, SLSTHOUTXn, SLSTH0 and SLSTH1 can be changed by burning the target value to
EEPROM.
•
•
FAIL-SAFE state access watchdog timer setup by WDTIMER. The detailed calculation and description are
explained in NORMAL state. The default value of WDTIMER can be changed by burning the target value to
EEPROM.
Channel setup in FAIL-SAFE state. In FAIL-SAFE state, the FS pin can be used as control signal to turn on
or turn off the corresponding channel. Each current output channel has its own register, FSOUTXn to set the
mapping to FS0 or FS1. When FSOUTXn is set to 0, the corresponding current output channel is controlled
by FS0 input, otherwise it is controlled by FS1 input. The detailed calculation and description are explained in
FAIL-SAFE State Operation.
•
•
One-fails-all-fail setup by OFAF. If the one-fails-all-fail can be enabled by burning 1 to OFAF according to
system requirements. Tie the ERR pins for all TPS929160-Q1 in the system together with a single 4.7-kΩ
pullup resistor to realize the one-fails-all-fail feature. The detailed calculation and description is explained in
OFAF Setup In FAIL-SAFE State.
CRC check reference calculation for EEPCRC. After all the EEPROM register values are designed, the CRC
reference value for all EEPROM register must be calculated and burnt into EEPCRC. The detailed calculation
and description are explained in EEPROM CRC Error in NORMAL state.
STEP 7: EEPROM burning solution design.
TI recommends that the EEPROM burning be done in the end of production line. The detailed flow is introduced
in EEPROM Register Access and Burn .
8.2.4 Application Curves
CH1 = RX
CH2 = TC
CH3 = CANH
CH1 = RX
CH2 = TX
CH3 = V(OUT0)
CH4 = CANL
CH4 = I(OUT0)
图 8-3. CAN Transceiver Operating
图 8-4. Output Control by FlexWire Interface
Copyright © 2023 Texas Instruments Incorporated
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119
Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
TPS929160-Q1
ZHCSNG0 – APRIL 2023
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8.3 Power Supply Recommendations
The TPS929160-Q1 is designed to operate from an automobile electrical power system within the range
specified in Power Supply (SUPPLY) and Power Bias (VBAT). The V(SUPPLY) input must be protected from
the reverse voltage and the voltage dump condition over 40 V. The impedance of the input supply voltage source
must be low enough that the input current transient does not cause the input voltage at the supply pin of device
to drop below LED string required forward voltage. If the input supply is connected with long wires, additional
bulk capacitance is required in addition to normal input capacitor.
8.4 Layout
8.4.1 Layout Guidelines
Thermal dissipation is the primary consideration for TPS929160-Q1 layout. TI recommends that a large thermal
dissipation area should be connected to the thermal pads with multiple thermal vias. Place the capacitor for
SUPPLY input, VBAT input and VLDO output as close as possible to the pins. The R(REF) resistor must also
be placed as close as possible to the REF pin together with 1-nF capacitor for enhanced noise immunity. A
1-nF ceramic capacitor is recommended to be put closely to each of output channels to achieve good EMC
performance.
8.4.2 Layout Example
GND
TPS929160-Q1
To µC or CAN Tranceiver
1
2
RX
ADDR3 38
ADDR2 37
ADDR1 36
ADDR0 35
VLDO
GND
TX
3
4
To µC or CAN Tranceiver
To CAN Tranceiver
OUTA0
5
NSTB
REF
34
6
OUTA1 33
OUTB0 32
OUTB1 31
NC 30
7
ERR
EN
GND
GND
8
9
VBAT
SUPPLY
VBAT
10
OUTC0
29
To Power Supply
11 SUPPLY
12 FS1
OUTC1 28
NC 27
13 FS0
OUTD0 26
OUTD1 25
NC 24
14 OUTH1
15 OUTH0
Exposed Pad
16
17
OUTE0 23
OUTE1 22
NC 21
OUTG1
OUTG0
18 NC
19 OUTF1
OUTF0 20
GND
图 8-5. TPS929160-Q1 Layout
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
120 Submit Document Feedback
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TPS929160-Q1
ZHCSNG0 – APRIL 2023
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9 Device and Documentation Support
9.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
9.3 Trademarks
FlexWire™ is a trademark of FlexRadio Systems.
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback 121
Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
PACKAGE OPTION ADDENDUM
www.ti.com
13-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS929160QDCPRQ1
ACTIVE
HTSSOP
DCP
38
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
929160Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
DCP 38
4.4 x 9.7, 0.5 mm pitch
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/B
www.ti.com
PACKAGE OUTLINE
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9
9.8
9.6
NOTE 3
19
20
0.27
0.17
0.08
38X
4.5
4.3
B
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
SYMM
38X (1.5)
38X (0.3)
SEE DETAILS
38
1
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(9.7)
NOTE 9
(0.6) TYP
SOLDER MASK
DEFINED PAD
(
0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
(4.7)
SYMM
39
BASED ON
0.125 THICK
STENCIL
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
0.125
0.15
0.175
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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