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TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

TPS92691/-Q1 具有轨到轨电流感测放大器的多拓扑 LED 驱动器

1 特性

3 说明

1

•

宽输入电压范围：4.5V 至 65V

宽输出电压范围：2V 至 65V

低输入偏移轨到轨电流感测放大器

TPS92691/-Q1 是一款通用 LED 控制器，支持一系列

升压或降压驱动器拓扑。该器件实现了固定频率峰值电

流模式控制技术，可编程开关频率、斜坡补偿和软启动

时序。其整合了高电压 (65V) 轨到轨电流感测放大

器，从而可使用高侧或低侧串联感测电阻直接测量

LED 电流。该放大器可用于实现低输入偏移电压且在

25°C 至 140°C 结温范围和 0 至 60V 输出共模电压范

围获得好于 ±3% 的 LED 电流精度。

•

–

在 25°C 至 140°C 结温范围内，好于 ±3% 的发

光二极管 (LED) 电流精度

–

与高侧和低侧电流感测元件兼容

•

高阻抗模拟 LED 电流调节输入 (IADJ)，对比度高

于 15:1

使用集成的串联 N 通道调光驱动器接口时，具有超

过 1000:1 串联场效应管 (FET) 脉宽调制 (PWM)

调光比率

可使用模拟或 PWM 调光技术单独调制 LED 电流。通

过在高阻抗模拟调整输入 (IADJ) 范围内将电压从

140mV 改变为 2.25V 可获得具有 15:1 范围的线性模

拟调光响应。通过将 PWM 输入引脚调制为所需的占

空比和频率实现 LED 电流的 PWM 调光。可使用可选

DDRV 栅极驱动器输出使串联 FET 调光功能获得高于

1000:1 的对比度。

•

具有 LED 电流持续监视输出用于系统故障检测和

诊断

•

可编程开关频率以实现与外部时钟同步

可编程软启动和斜坡补偿

综合故障保护电路，包括电源电压 (VCC) 欠压锁定

(UVLO)、输出过压保护 (OVP)、逐周期开关电流限

制和热保护

TPS92691/-Q1 支持通过电流监视输出连续检查 LED

状态。这样就可以实现 LED 短路或开路检测和保护。

其他故障保护特性包括 VCC UVLO、输出过压保护

(OVP)、开关逐周期电流限制和热保护。

•

TPS92691-Q1：符合汽车类 Q100 1 级标准

2 应用

•

TPS92691-Q1：汽车外部照明应用

建筑照明和通用照明应用

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

TPS92691-Q1

TPS92691

HTSSOP (16)

5.10mm x 6.60mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

典型升压 LED 驱动器应用原理图

效率与输出电压之间的关系

L

100

R_CS

VIN

D

LED+

C_IN

V_O= 60 V, I_LED= 300 mA

C_VCC

R_OV2

TPS92691-Q1

Q₁

C_OUT

95

90

85

80

75

C_SS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

R_ADJ2

VIN

VCC

SS

GATE

IS

R_T

R_OV1

RT/SYNC

PWM

COMP

IADJ

Q₂

R_IS

V_PWM

PGND

OVP

DDRV

CSP

C_OV

LEDÅ

C_COMP

IMON

R_ADJ1

C_IMON

AGND

PAD

CSN

8

9

10

11

12

13

14

15

16

17

18

V_IN(V)

D019

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSD68

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

7.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Applications ................................................ 26

Power Supply Recommendations...................... 37

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 12

8

9

10 Layout................................................................... 37

10.1 Layout Guidelines ................................................. 37

10.2 Layout Example .................................................... 38

11 器件和文档支持 ..................................................... 39

11.1 相关链接................................................................ 39

11.2 社区资源................................................................ 39

11.3 商标....................................................................... 39

11.4 静电放电警告......................................................... 39

11.5 Glossary................................................................ 39

12 机械、封装和可订购信息....................................... 39

7

4 修订历史记录

日期

修订版本

注释

2015 年 12 月

*

首次发布。

2

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

5 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP with PowerPAD™

Top View

VIN

SS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VCC

GATE

IS

RT/SYNC

PWM

PGND

OVP

DDRV

CSP

CSN

Thermal

Pad

COMP

IADJ

IMON

AGND

Pin Functions

NAME

I/O

DESCRIPTION

NO.

Input supply for the internal VCC regulator. Bypass with 100-nF capacitor to GND located close to the

controller.

1

VIN

SS

—

Soft-start programming pin. Connect a capacitor to AGND to extend the start-up time. Switching can

be disabled by shorting the pin to GND.

2

3

I/O

Oscillator frequency programming pin. Connect a resistor to AGND to set the switching frequency. The

internal oscillator can be synchronized by coupling an external clock pulse through 100-nF series

capacitor.

RT/SYNC

PWM

I/O

I

PWM dimming input. Driving the pin below 2.3 V (typ), turns off switching, idles the oscillator,

disconnects the COMP pin, and sets DDRV output to ground. The input signal duty cycle controls the

average LED current through PWM dimming operation. Connect to VCC when not used for PWM

dimming.

4

Transconductance error amplifier output. Connect compensation network to achieve desired closed-

loop response.

5

6

COMP

IADJ

I/O

I

LED current reference input. Connecting pin to VCC with 100-kΩ series resistor sets internal reference

voltage to 2.42 V and the current sense threshold, V_(CSP-CSN)to 172 mV. The pin can be modulated by

external voltage source from 0 V to 2.25 V to implement analog dimming.

LED current report pin. The LED current sensed by CSP/CSN input is reported as V_IMON= 14 × I_LED

R_cs. Bypass with a 1-nF ceramic capacitor to AGND.

×

7

8

IMON

AGND

CSN

O

—

I

Analog ground. Return for the internal voltage reference and analog circuit. Connect to circuit ground,

GND, to complete return path.

Current sense amplifier negative input (–). Connect directly to the negative node of LED current sense

resistor R_CS).

9

Current sense amplifier positive input (+). Connect directly to the positive node of LED current sense

resistor R_CS).

10

11

12

13

CSP

I

Series dimming FET gate driver output. Connect to gate of external N-channel MOSFET or a level-shift

circuit with P-channel MOSFET to implement series FET PWM dimming.

DDRV

OVP

O

I

Hysteretic overvoltage protection input. Connect resistor divider from output voltage to set OVP

threshold and hysteresis.

Power ground connection pin for internal N-channel MOSFET gate drivers. Connect to circuit ground,

GND, to complete return path.

PGND

—

Switch current sense input. Connected to the switch current sense resistor, R_IS, in the source of the N-

channel MOSFET.

14

15

16

IS

I

GATE

VCC

O

—

N-channel MOSFET gate driver output. Connect to gate of external switching N-channel MOSFET.

VCC bias supply pin. Locally decouple to PGND using a 2.2-µF to 4.7-µF ceramic capacitor located

close to the controller.

The AGND and PGND pin must be connected to the exposed PowerPAD for proper operation. This

PowerPAD must be connected to PCB ground plane using multiple vias for good thermal performance.

PowerPAD

—

3

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

—

MAX

65

UNIT

V

VIN, CSP, CSN

IADJ, IS, PWM, RT/SYNC

8.8

V

Input voltage

OVP, SS

CSP to CSN⁽³⁾, PGND

5.5

V

0.3

V

VCC, GATE, DDRV

8.8

V

Output voltage⁽⁴⁾

COMP

5.0

V

IMON

Source current

100

500

140

150

µA

mA

°C

GATE, DDRV (Pulsed <20 ns)

—

Sink current

GATE, DDRV (Pulsed <20 ns)

—

Operating junction temperature, T_J

Storage temperature, T_stg

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to AGND unless otherwise noted

(3) Continuous sustaining voltage

(4) All output pins are not specified to have an external voltage applied.

6.2 ESD Ratings

VALUE

UNIT

TPS92691-Q1 IN PWP (HTSSOP) PACKAGE

Human-body model (HBM), per AEC Q100-002, all pins⁽¹⁾

±2000

±500

±750

Electrostatic

discharge

All pins except 1, 8, 9, and

16

V_(ESD)

V

Charged-device model (CDM), per AEC Q100-011

Pins 1, 8, 9, and 16

TPS92691 IN PWP (HTSSOP) PACKAGE

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽²⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins⁽³⁾

±2000

±500

Electrostatic

discharge

V_(ESD)

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

6.5

NOM

MAX

UNIT

VIN

Supply input voltage

14

65

V

VIN, crank

V_CSP, V_CSN

ƒ_SW

Supply input, battery crank voltage

Current sense common mode

Switching frequency

4.5

0

60

700

V

80

kHz

V

ƒ_SYNC

V_IADJ

SYNC frequency

0.8 × ƒ_sw

0.14

–40

1.2 × ƒ_SW

V_IADJ(CLAMP)

125

Current reference voltage

Operating ambient temperature

T_A

°C

4

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

6.4 Thermal Information

TPS92691/-Q1

THERMAL METRIC⁽¹⁾

PWP (HTSSOP)

UNIT

16 PINS

40.8

26.1

22.2

0.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

22.0

2.3

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

T_J= –40°C to 140°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load

on GATE and DDRV (unless otherwise noted)⁽¹⁾

PARAMETER

INPUT VOLTAGE (VIN)

V_DOLDO dropout voltage

BIAS SUPPLY (VCC)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_CC= 20 mA, V_IN= 5 V

300

mV

V_CC(REG)

Regulation voltage

No load

7.0

3.75

26

7.5

4.1

4.0

100

38

8.0

V

VCC rising threshold, V_IN= 8 V

VCC falling threshold, V_IN= 8 V

Hysteresis

4.35

V

V_CC(UVLO)

Supply undervoltage protection

V

mV

mA

I_CC(LIMIT)

I_CC(STBY)

I_CC(SW)

Supply current limit

V_CC= 0 V

46

2.1

6.6

Supply stand-by current

Supply switching current

V_PWM= 0 V

1.8

5.1

V_CC= 7.5 V, C_GATE= 1 nF

OSCILLATOR (RT/SYNC)

R_T= 40 kΩ

R_T= 20 kΩ

165

327

200

390

1

230

448

kHz

V

ƒ_SW

Switching frequency

V_RT

RT output voltage

SYNC rising threshold

SYNC falling threshold

Minimum SYNC clock pulse width

V_RT/SYNCrising

V_RT/SYNCfalling

2.7

2

3.1

V

V_SYNC

t_SYNC(MIN)

1.8

V

100

ns

GATE DRIVER (GATE)

R_GH

R_GL

Gate driver high side resistance

Gate driver low side resistance

I_GATE= –10 mA

I_GATE= 10 mA

5.4

4.3

11.2

10.5

Ω

CURRENT SENSE (IS)

V_IS(LIMIT)

t_IS(BLANK)

t_IS(FAULT)

t_ILMT(DLY)

Current limit threshold

497

103

525

150

35

550

188

mV

ns

Leading edge blanking time

Current limit fault time

µs

ns

IS to GATE propagation delay

V_ISpulsed from 0 to 1 V

100

PWM COMPARATOR AND SLOPE COMPENSATION

D_MAX

V_LV

Maximum duty cycle

90.4%

1.17

93%

1.5

94.7%

1.8

IS to COMP level shift voltage

No slope compensation added

V

D = D_MAX(with max slope

compensation)

V_SL

I_LV

Slope compensation

200

25

mV

µA

IS level shift bias current

No slope compensation added

(1) All voltages are with respect to AGND unless otherwise noted

5

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

Electrical Characteristics (continued)

T_J= –40°C to 140°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load

on GATE and DDRV (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

D = D_MAX(with max slope

compensation)

I_LV+ I_SL

IS level shift source current

115

µA

CURRENT SENSE AMPLIFIER (CSP, CSN)

Cumulative offset voltage at V_CSP= 60 –40°C ≤ T_J≤ 140°C

–5.2

–4.4

–3.5

-2.8

–5.9

-4.7

–2.3

–1.7

5.9

4.6

5.0

4.0

6.7

5.0

3.2

2.6

mV

V and V_(CSP-CSN)= 150 mV, referred to

current sense input

25°C ≤ T_J≤ 140°C

Cumulative offset voltage at V_CSP= 60 –40°C ≤ T_J≤ 140°C

V and V_(CSP-CSN)= 10 mV, referred to

current sense input

25°C ≤ T_J≤ 140°C

V_CS(offset)

Cumulative offset voltage at V_CSN= 0

V and V_(CSP-CSN)= 150 mV, referred to

current sense input

–40°C ≤ T_J≤ 140°C

25°C ≤ T_J≤ 140°C

–40°C ≤ T_J≤ 140°C

25°C ≤ T_J≤ 140°C

Cumulative offset voltage at V_CSN= 0

V and V_(CSP-CSN)= 10 mV, referred to

current sense input

CS_(BW)

Current sense unity gain bandwidth

CSP, CSN bias current

500

4

kHz

µA

I_CS(BIAS)

V_{CSP, CSN}= 60 V

CURRENT MONITOR (IMON)

V_IMON(CLP)IMON output voltage clamp

V_IMON(OS)IMON buffer offset voltage

ANALOG ADJUST (IADJ)

3.2

3.7

4.2

7.3

V

–11.4

–1.6

mV

V_IADJ(CLP)

I_IADJ(BIAS)

R_IADJ(LMT)

IADJ internal clamp voltage

I_IADJ= 1 µA

V_IADJ< 2.2 V

V_IADJ> 2.6 V

2.27

2.42

12

2.55

90

V

IADJ input bias current

nA

kΩ

IADJ current limiting series resistor

ERROR AMPLIFIER (COMP)

g_M

Transconductance

121

130

5

µA/V

µA

I_COMP(SRC)

I_COMP(SINK)

EA_(BW)

COMP current source capacity

COMP current sink capacity

Error amplifier bandwidth

V_IADJ= 1.4 V, V_(CSP-CSN)= 0 V

V_IADJ= 0 V, V_(CSP-CSN)= 0.1 V

–3 dB

µA

MHz

mV

Ω

V_COMP(RST)COMP pin reset voltage

R_COMP(DCH)COMP discharge FET resistance

SOFT-START (SS)

100

246

I_SS

Soft-start source current

Soft-start pin reset voltage

SS discharge FET resistance

7

10

25

12.8

µA

mV

Ω

V_SS(RST)

R_SS(DCH)

260

OVERVOLTAGE PROTECTION (OVP)

V_OVP(THR)

I_OVP(HYS)

OVP detection threshold

OVP hysteresis current

1.18

12

1.24

20

1.31

27.5

V

µA

PWM INPUT (PWM)

Schmitt trigger logic level (high

V_PWM(HIGH)

2.5

2.3

2.7

V

threshold)

Schmitt trigger logic level (low

threshold)

V_PWM(LOW)

2.0

R_PWM(PD)

t_DLY(RISE)

t_DLY(FALL)

PWM pulldown resistance

PWM to DDRV rising delay

PWM to DDRV falling delay

1

54

72

MΩ

ns

PWM GATE DRIVE OUTPUT (DDRV)

R_DH

R_DL

DDRV high-side resistance

DDRV low-side resistance

6.1

5.2

12.8

11.4

Ω

6

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

Electrical Characteristics (continued)

T_J= –40°C to 140°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load

on GATE and DDRV (unless otherwise noted)⁽¹⁾

PARAMETER

THERMAL SHUTDOWN

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Thermal shutdown temperature

Thermal shutdown hysteresis

175

25

°C

6.6 Typical Characteristics

T_A= 25°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load on GATE

and DDRV (unless otherwise noted)

7.8

7.7

7.6

7.5

7.4

7.3

7.2

1.9

1.875

1.85

1.825

1.8

1.775

1.75

1.725

1.7

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

D001

D018

Figure 1. VCC Regulation Voltage vs Temperature

Figure 2. Standby Current vs Temperature

600

500

400

300

200

100

4.25

4.2

V_IN= 5V, I_VCC= 20mA

Rising Threshold

Falling Threshold

4.15

4.1

4.05

4

3.95

3.9

3.85

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

D002

D003

Figure 3. VCC Dropout Voltage vs Temperature

Figure 4. UVLO Threshold vs Temperature

7

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

Typical Characteristics (continued)

T_A= 25°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load on GATE

and DDRV (unless otherwise noted)

100

39.5

80

70

60

39

50

40

30

38.5

38

20

37.5

37

10

-40

-20

0

20

40

60

80

100 120 140

50

150

250

350

450

550

650

750

Temperature (°C)

Frequency (kHz)

D004

D005

Figure 5. VCC Current Limit vs Temperature

Figure 6. R_Tvs Switching Frequency

402

398

394

390

386

382

93.2

93.1

93

92.9

92.8

92.7

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

D006

D012

Figure 7. Switching Frequency vs Temperature

Figure 8. Maximum Duty Cycle vs Temperature

532

530

528

526

524

522

520

518

158

156

154

152

150

148

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

D007

D008

Figure 9. IS Current Limit Threshold vs Temperature

Figure 10. Leading Edge Blanking Period vs Temperature

8

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

Typical Characteristics (continued)

T_A= 25°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load on GATE

and DDRV (unless otherwise noted)

151

150.8

150.6

150.4

150.2

150

0.4

0.2

0

V_CSP= 60V

V_CSP= 0V

-0.2

-0.4

-0.6

-0.8

149.8

149.6

149.4

0

5

10 15 20 25 30 35 40 45 50 55 60 65

V_CSP(V)

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

D009

D010

V_IADJ= 2.1 V

Figure 11. V_(CSP-CSN)Threshold vs V_CSP

V_IADJ= 2.1 V

Figure 12. Current Sense Amplifier Offset vs Temperature

4

4.2

3.5

4.15

4.1

3

2.5

2

4.05

4

1.5

1

3.95

3.9

3.85

3.8

0.5

0

-40

-20

0

20

40

60

80

100 120 140

0

30

60

90 120 150 180 210 240 270 300

V_(CSP-CSN)(mV)

Temperature (°C)

D013

D011

Figure 13. CSP/CSN Input Bias Current vs Temperature

Figure 14. V_IMONvs V_(CSP-CSN)

200

2.44

180

160

140

120

100

80

2.435

2.43

2.425

2.42

2.415

2.41

60

40

2.405

2.4

20

0

0.28 0.56 0.84 1.12 1.4 1.68 1.96 2.24 2.52 2.8

V_IADJ(V)

3

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

D014

D015

Figure 15. V_(CSP-CSN)Threshold vs V_IADJ

Figure 16. V_IADJVoltage Clamp vs Temperature

9

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

Typical Characteristics (continued)

T_A= 25°C, V_IN= 14 V, V_IADJ= 2.2 V, C_VCC= 1 µF, C_COMP= 2.2 nF, R_CS= 100 mΩ, R_T= 20 kΩ, V_PWM= 5 V, no load on GATE

and DDRV (unless otherwise noted)

1.26

1.255

1.25

21

20.6

20.2

19.8

19.4

19

1.245

1.24

1.235

1.23

1.225

1.22

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

D016

D017

Figure 17. OVP Detection Threshold vs Temperature

Figure 18. OVP Hysteresis Current vs Temperature

10

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www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

7 Detailed Description

7.1 Overview

The TPS92691/-Q1 wide input range (4.5 V to 65 V) controller features all of the functions necessary to

implement a highly efficient and compact LED driver based on step-up or step-down converter topologies. The

device implements a fixed-frequency, peak current mode control technique to achieve a constant current output,

ideal for driving a single string of series-connected LEDs. The integrated low input offset, rail-to-rail current sense

amplifier supports a wide range of output voltages (0 V to 65 V) and is capable of powering an LED string

consisting of 1 to more than 20 white LEDs. The controller is compatible with either high- or low-side current

shunt sensing technique, based on the LED configuration and driver topology. The LED current sense threshold,

set by the analog adjust input, IADJ, provides the capability to analog (amplitude) dim over a linear range of 15:1

by varying the voltage, V_IADJ, from 140 mV to 2.25 V. The IADJ input provides the means to externally program

LED current and facilitates calibration, brightness correction, and thermal management of the LEDs. High

resolution and linear dimming response is achieved by varying the duty cycle of LED current based on the PWM

input. The PWM input directly controls the GATE and DDRV drive outputs, controls the internal oscillator, and

enables high-speed PWM dimming with over 1000:1 contrast ratio when using an external MOSFET placed in

series with the LED load. The current monitor output, IMON, reports the instantaneous status of LED current

measured by the rail-to-rail current sense amplifier. This feature is incorporated to indicate LED short and open-

circuit failures and enables cable harness fault detection independent of LED driver topology. Other fault

protection features include cycle-by-cycle current limiting, hysteresis-based overvoltage protection, VCC

undervoltage protection, thermal shutdown, and remote shutdown capability by pulling down the SS pin.

7.2 Functional Block Diagram

7.5V LDO

Regulator

VIN

VCC

2.42V

1.24V

525mV

INTERNAL

REFERENCES

THERMAL

LIMIT

UVLO

(4.1V)

STANDBY

LEB

CLOCK

RT/

SYNC

Q

S

R

GATE

PGND

MAX DUTY

SLOPE

OSCILLATOR

&

SLOPE

10ꢀA

SS

20ꢀA

OVP

PWM

+

PWM

COMP

1.24V

VCC

100mV

RESET

LOGIC

25mV

FAULT

SS

DDRV

FAULT

PGND

CSP

GAIN = 14

+

10ꢀA

CURRENT SENSE

AMPLIFIER

CSN

138k

SLOPE

+

IMON

2k

STANDBY

3.7V

+

IS

35 ꢀs

TIMER

525mV

IADJ

12k

LEB

+

AGND

2.42V

11

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

7.3 Feature Description

7.3.1 Internal Regulator and Undervoltage Lockout (UVLO)

The IC incorporates a 65-V input V_INrated linear regulator to generate the 7.5 V (typ) V_CCbias supply and other

internal reference voltages. The V_CCoutput is monitored to implement UVLO protection. The device is enabled

when V_CCexceeds the 4.1-V (typ) threshold and is disabled when V_CCdrops below the 4.0-V (typ) threshold. The

UVLO comparator provides 0.1 V of hysteresis to avoid chatter during transitions. The UVLO thresholds are

internally fixed and cannot be adjusted. The supply current, I_CC, is limited to 26 mA minimum to protect the

device under VCC pin short-circuit conditions. The V_CCsupply powers the internal circuitry and N-channel gate

driver outputs, GATE, and DDRV. Place a bypass capacitor in the range of 2.2 µF to 4.7 µF across the V_CC

output and PGND to ensure proper operation. The regulator operates in dropout when input voltage V_INfalls

below 7.5 V forcing V_CCto be lower than V_INby 300 mV for a 20-mA supply current. The V_CCis a regulated

output of the internal regulator and is not recommended to be driven from an external power supply.

7.3.2 Oscillator

The TPS92691/-Q1 switching frequency is programmable by a single external resistor connected between the

RT/SYNC pin and the AGND pin. To set a desired frequency, ƒ_SW(Hz), the resistor value can be calculated from

Equation 1.

1.432ì10¹⁰

R_T

=

W

(

)

1.047

f

(

)

SW

(1)

Figure 6 shows a graph of switching frequency versus resistance, R_T. TI recommends a switching frequency

setting between 80 kHz and 700 kHz for optimal performance over input and output voltage operating range and

for best efficiency. Operation at higher switching frequencies requires careful selection of N-channel MOSFET

characteristics and should take into consideration additional switching losses and junction temperature rise.

TPS92691

CLOCK

RT/SYNC

C_SYNC

OSCILLATOR

R_T

Figure 19. Oscillator Synchronization Through AC Coupling

The internal oscillator can be synchronized by AC coupling an external clock pulse to RT/SYNC pin as shown in

Figure 19. The positive going synchronization clock at the RT pin must exceed the RT sync threshold and the

negative going synchronization clock at the RT pin must exceed the RT sync falling threshold to trip the internal

synchronization pulse detector. TI recommends that the frequency of the external synchronization pulse is within

±20% of the internal oscillator frequency programmed by the R_Tresistor. TI recommends a minimum coupling

capacitor of 100 nF and typical pulse width of 100 ns for proper synchronization. In the case where external

synchronization clock is lost the internal oscillator takes control of the switching rate based on the R_Tresistor to

maintain output current regulation. The R_Tresistor is always required whether the oscillator is free running or

externally synchronized.

7.3.3 Gate Driver

The TPS92691/-Q1 contains a N-channel gate driver that switches the output V_GATEbetween V_CCand PGND. A

peak source and sink current of 500 mA allows controlled slew-rate of the MOSFET gate and drain node

voltages, limiting the conducted and radiated EMI generated by switching. The gate driver supply current

I_CC(GATE)depends on the total gate drive charge (Q_G) of the MOSFET and the operating frequency of the

I_CC(GATE)= Q_Gì f

converter, ƒ_SW

,

^SW. TI recommends a MOSFET with a low gate charge specification to limit the

junction temperature rise and switch transition losses.

12

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

Feature Description (continued)

While choosing the N-channel MOSFET device, consider the threshold voltage when operating in the dropout

region when V_INis below the V_CCregulation level. TI recommends a logic level device with a threshold voltage

below 5 V when the device is required to operate at an input voltage less than 7 V.

7.3.4 Rail-to-Rail Current Sense Amplifier

The internal rail-to-rail current sense amplifier measures the average LED current based on the differential

voltage drop between the CSP and CSN inputs over a common mode range of 0 V to 65 V. The differential

voltage, V_(CSP-CSN), is amplified by a voltage-gain factor of 14 and is connected to the negative input of the

transconductance error amplifier. Accurate LED current feedback is achieved by limiting the cumulative input

offset voltage, (represented by the sum of the voltage-gain error, the intrinsic current sense offset voltage, and

the transconductance error amplifier offset voltage) to less than 5 mV over the recommended common-mode

voltage, and temperature range.

Differential Mode

Filter Capacitors

R_FS

TPS92691

CSP

+

R_CS

C_FDM

œ

CSN

R_FS

Common Mode

Filter Capacitors

C_FCMC_FCM

Figure 20. Current Sense Amplifier Input Filter Options

An optional common-mode or differential mode low-pass filter implementation, as shown in Figure 20, can be

used to smooth out the effects of large output current ripple and switching current spikes caused by diode

reverse recovery. TI recommends a filter resistance in the range of 10 Ω to 100 Ω to limit the additional offset

caused by amplifier bias current and achieve best accuracy and line regulation.

7.3.5 Transconductance Error Amplifier

The internal transconductance amplifier generates an error signal proportional to the difference between the LED

current sense feedback voltage and the external IADJ input voltage. Closed-loop regulation is achieved by

connecting a compensation network to the output of the error amplifier. In most LED driver applications, a stable

response can be achieved by connecting a capacitor across the COMP output and ground to implement a simple

integral compensator. TI recommends a capacitor value between 10 nF and 100 nF as a good starting point.

Higher closed-loop bandwidth can be achieved by implementing a proportional-integral compensator consisting

of a series resistor and a capacitor network connected across the COMP output and ground. Based on the

converter topology, the compensation network should be tuned to achieve a minimum of 60° of phase margin

and 10 dB of gain margin. The Application and Implementation section presents detailed equations.

7.3.6 Switch Current Sense and Internal Slope Compensation

The main MOSFET current is monitored by the IS input pin to implement peak current mode control. The GATE

output duty cycle is derived by comparing the peak switch current, measured by the R_ISresistor, to the internal

COMP voltage threshold. An internal slope signal is added to the measured sense voltage, V_IS, to prevent

subharmonic oscillations for duty cycles greater than 50%. The linear slope voltage, V_SL, of fixed amplitude 200

mV, is derived from a 100-µA sawtooth ramp current synchronized to the internal oscillator frequency. An internal

blanking circuit prevents MOSFET switching current spike propagation and premature termination of duty cycle

by internally shunting the IS input for 150 ns after the beginning of the new switching period. TI recommends an

external low-pass RC filter with resistor values ranging from 100 Ω to 500 Ω for additional noise suppression

when operating in the dropout region (V_INless than 7 V).

13

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

Feature Description (continued)

Cycle-by-cycle current limit is accomplished by a redundant internal comparator, which immediately terminates

the GATE output when the IS input voltage, V_IS, exceeds 525-mV (typ) threshold. Upon a current limit event, the

SS and COMP pin are internally grounded to reset the state of the controller. The GATE output is enabled after

the expiration of the 35-µs internal fault timer and a new start-up sequence is initiated through the SS pin.

7.3.7 Analog Adjust Input

The voltage across the LED current sense resistor, V_(CSP–CSN), is regulated to the analog adjust input voltage,

V_IADJ, scaled by the current sense amplifier voltage gain of 14. The LED current can be linearly adjusted by

varying the voltage on IADJ from 140 mV to 2.25 V using either a resistor divider from V_CCor a voltage source.

The IADJ pin can be connected to V_CCthrough an external resistor to set LED current based on the 2.42-V

internal reference voltage. Figure 21 shows different methods to set the IADJ voltage. The IADJ input can be

used in conjunction with a NTC resistor to implement thermal foldback protection as shown in Figure 21(b). A

PWM signal in conjunction with first- or second-order low-pass filter can be used to program the IADJ voltage as

shown in Figure 21(c).

TPS92691

VCC

R_ADJ

R_ADJ2

R_ADJ

IADJ

PWM

SIGNAL

C_ADJ

Åt°

R_ADJ1

R_NTC

(a)

(b)

(c)

a. Static reference setting resistor divider from VCC

b. Thermal fold-back circuit using external NTC resistor

c. Analog dimming achieved by low-pass filtering external PWM signal

Figure 21. Setting Analog Adjust Input Voltage

7.3.8 PWM Input and Series Dimming FET Gate Driver Output

The TPS92691/-Q1 incorporates a dimming input (PWM) for pulse-width modulating the output LED current. The

brightness of the LEDs can be linearly varied by modulating the duty cycle of the pulsating voltage source

connected to the PWM input pin. Driving the PWM input below 2.3 V (typ) turns off switching, parks the oscillator,

disconnects the COMP pin, and sets the DDRV output to GND in order to maintain the charge on the

compensation network and output capacitors. On the rising edge of the PWM input voltage (V_PWM> 2.5 V), the

GATE and DDRV outputs are enabled to ramp the inductor current to the previous steady-state value. The

COMP pin is connected and the error amplifier and oscillator are enabled only when the switch current sense

voltage V_ISexceeds the COMP voltage, V_COMP, thus immediately forcing the converter into steady-state

operation with minimum LED current overshoot. The PWM pin should be connected to the V_CCif dimming is not

required. An internal pulldown resistor sets the input to logic-low and disables the part when the pin is

disconnected or left floating.

14

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

Feature Description (continued)

LED-

LED+

TPS92691

DDRV

Figure 22. Series Dimming FET Connections

The DDRV output follows the PWM input signal and is capable of sinking and sourcing up to 500 mA of peak

current to control a low-side series connected N-channel dimming FET. Alternatively, the DDRV output can be

translated with an external level-shift circuit to drive a high-side series P-channel dimming FET as shown in

Figure 22. The series dimming FET is required to achieve high contrast ratio as it ensures fast rise and fall times

of the LED current in response to the PWM input. Without any dimming FET, the rise and fall times are limited by

the inductor slew rate and the closed-loop bandwidth of the system. Leave the DDRV pin unconnected if not

used.

7.3.9 Soft-Start

The soft-start feature helps the regulator gradually reach the steady-state operating point, thus reducing startup

stresses and surges. The TPS92691/-Q1 clamps the COMP pin to the SS pin, separated by a diode, until LED

current nears the regulation threshold. The internal 10-µA soft-start current source gradually increases the

voltage on an external soft-start capacitor C_SSconnected to the SS pin. This results in a gradual rise of the

COMP voltage from GND.

The internal 10-µA current source turns on when VCC exceeds the UVLO threshold. At the beginning of the soft-

start sequence, the SS pulldown switch is active and is released when the voltage V_SSdrops below 25 mV. The

SS pin can also be pulled down by an external switch to stop switching. When the SS pin is externally driven to

enable switching, the slew-rate on the COMP pin should be controlled by choosing a compensation capacitor

that avoids large startup transients. The value of C_SSshould be large enough to charge the output capacitor

during the soft-start transition period.

7.3.10 Current Monitor Output

The IMON pin voltage represents the LED current measured by the rail-to-rail current sense amplifier across the

external current shunt resistor. The linear relationship between the IMON voltage and LED current includes the

amplifier gain-factor of 14 (see Figure 14). The IMON output can be connected to an external microcontroller or

comparator to facilitate LED open, short, or cable harness fault detection and mitigation based on programmable

threshold V_OCTH. The IMON voltage is internally clamped to 3.7 V.

TPS92691

SS

PWM

V_OCTH

+

IMON

Figure 23. LED Overcurrent Protection using IMON Output

15

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

Feature Description (continued)

7.3.11 Overvoltage Protection

The TPS92691/-Q1 device includes a dedicated OVP pin which can be used for either input or output

overvoltage protection. This pin features a precision 1.24 V (typ) threshold with 20-µA (typ) of hysteresis current.

The overvoltage threshold limit is set by a resistor divider network from the input or output terminal to GND.

When the OVP pin voltage exceeds the reference threshold, the GATE and DDRV pins are immediately pulled

low and the SS and COMP capacitors are discharged. The GATE is enabled and a new startup sequence is

initiated after the voltage drops below the hysteresis threshold set by the 20-µA source current and the external

resistor divider.

7.3.12 Thermal Protection

Internal thermal shutdown circuitry is implemented to protect the controller in the event the maximum junction

temperature is exceeded. When activated, typically at 175°C, the controller is forced into a shutdown mode,

disabling the internal regulator. This feature is designed to prevent overheating and damage to the device.

7.4 Device Functional Modes

This device has no additional functional modes.

16

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS92691/-Q1 controller is suitable for implementing step-up or step-down LED driver topologies including

Buck, Boost, Buck-Boost, SEPIC, Cuk, and Flyback. Use the following design procedure to select component

values for the TPS92691/-Q1 device. This section presents a simplified discussion of the design process for the

Buck, Boost, and Buck-Boost converter. The expressions derived for Buck-Boost can also be altered to select

components for a 1:1 coupled-inductor SEPIC converter. The design procedure can be easily adapted for

Flyback and Cuk converter topologies.

L

R_CS

VIN

D

LED+

C_IN

C_VCC

R_OV2

TPS92691-Q1

VCC

Q₁

C_OUT

C_SS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

R_ADJ2

VIN

SS

GATE

IS

R_T

R_OV1

RT/SYNC

PWM

COMP

IADJ

Q₂

R_IS

V_PWM

PGND

OVP

DDRV

CSP

C_OV

LEDÅ

C_COMP

IMON

R_ADJ1

C_IMON

AGND

PAD

CSN

Figure 24. Boost LED Driver

VIN

L₁

L₂

C_IN

C_S

C_VCC

TPS92691-Q1

R_CS

C_OUT

Q₂

LED+

D

R_OV2

C_SS

Q₁

1

16

R_ADJ2

VIN

SS

VCC

2

3

4

5

6

7

8

15

GATE

R_T

R_OV1

14

RT/SYNC

PWM

IS

PGND

OVP

R_IS

13

12

11

10

9

V_PWM

C_OV

LEDÅ

COMP

IADJ

C_COMP

DDRV

CSP

IMON

R_ADJ1

C_IMON

AGND

PAD

CSN

Figure 25. SEPIC LED Driver

17

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

Application Information (continued)

R_CS

Q₂

LEDÅ

C_OUT

L

LED+

D

VIN

C_IN

R_OV2

R_LS2

C_VCC

TPS92691-Q1

VCC

Q₁

Q₄

C_SS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

R_ADJ2

VIN

Q₃

SS

GATE

IS

R_T

RT/SYNC

PWM

COMP

IADJ

R_OV1

C_OV

R_LS1

R_IS

V_PWM

PGND

OVP

DDRV

CSP

C_COMP

IMON

R_ADJ1

C_IMON

AGND

PAD

CSN

Figure 26. Buck-Boost LED Driver

VIN

LED+

R_LS2

Q₂

D

R_OV2

C_OUT

C_IN

L

Q₁Q₄

C_VCC

R_CS

LEDÅ

TPS92691-Q1

VCC

C_SS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

R_ADJ2

VIN

Q₃

SS

GATE

IS

R_T

R_OV1

RT/SYNC

PWM

COMP

IADJ

R_LS1

R_IS

V_PWM

PGND

OVP

DDRV

CSP

C_OV

C_COMP

IMON

R_ADJ1

C_IMON

AGND

PAD

CSN

Figure 27. Buck LED Driver

18

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

Application Information (continued)

8.1.1 Duty Cycle Considerations

The switch duty cycle, D, defines the converter operation and is a function of the input and output voltages. In

steady state, the duty cycle is derived using expression:

Buck:

V_O

D =

V

IN

(2)

(3)

(4)

Boost:

D =

V_O- V

IN

V_O

Buck-Boost:

V_O

D =

V

+ V_O

IN

The minimum duty cycle, D_MIN, and maximum duty cycle, D_MAX, are calculated by substituting maximum input

voltage, V_IN(MAX), and the minimum input voltage, V_IN(MIN), respectively in the previous expressions. The minimum

duty cycle achievable by the device is determined by the leading edge blanking period and the switching

frequency. The maximum duty cycle is limited by the internal oscillator to 93% (typ) to allow for minimum off-time.

It is necessary for the operating duty cycle to be within the operating limits of the device to ensure closed-loop

LED current regulation over the specified input and output voltage range.

8.1.2 Inductor Selection

The inductor peak-to-peak ripple current, Δi_L-PP, is typically set between 10% and 80% of the maximum inductor

current, I_L, as a good compromise between core loss and copper loss of the inductor. Higher ripple inductor

current allows a smaller inductor size, but places more of a burden on the output capacitor to smooth the LED

current ripple. Knowing the desired ripple ratio RR, switching frequency ƒ_SW, maximum duty cycle D_MAX, and the

typical LED current I_LED, the inductor value can be calculated as follows:

Buck:

Di_L(PP)= RR ∂I_L= RR ∂I_LED

(5)

V

- V_OìD

(

)

IN(MIN)

MAX

L =

Di_L(PP)ì f_SW

(6)

Boost and Buck-Boost:

Di_L(PP)= RR ∂I_L= RR ∂

I_LED

1-D_MAX

(7)

(8)

V_IN(MIN)ìD_MAX

L =

Di_L(PP)ì f_SW

As an alternative, the inductor can be selected based on CCM-DCM boundary condition specified based on

output power, P_O(BDRY). The choice of inductor ensures CCM operation in battery-powered LED driver

applications that are designed to support different LED string configurations with a wide range of programmable

LED current setpoints. The output power should be calculated based on the lowest LED current and the lowest

output voltage requirements for a given application.

P_O(BDRY)Ç I_LED(MIN)ì V_O(MIN)

(9)

Buck:

V_O²_(MAX)

V_O(MAX)

≈

∆

«

’

L =

ì 1-

∆

÷

2ìP_O(BDRY)ì f_SW

V

IN

◊

(10)

19

Boost:

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

Application Information (continued)

V²

V

IN

≈

’

IN

L =

ì∆1-

÷

◊

∆

2ìP_O(BDRY)ì f_SW

V_O(MAX)

«

(11)

Buck-Boost:

1

L =

2

≈

’

1

2ìP_O(BDRY)ì f_SW

ì

+

∆

«

÷

◊

V_O(MAX)

V

IN

(12)

The saturation current rating of the inductor should be greater than the peak inductor current, I_L(PK), at the

maximum operating temperature.

V

_IN(MIN)ìD_MAX

I_L(PK)= I_L+

2ìL ì f_SW

(13)

8.1.3 Output Capacitor Selection

The output capacitors are required to attenuate the discontinuous or large ripple current generated by switching

and achieve the desired peak-to-peak LED current ripple, Δi_LED(PP). The capacitor value depends on the total

series resistance of the LED string, r_D, the switching frequency, ƒ_SW, and on the converter topology (that is, step-

up or step-down). For the Buck and Cuk topology, the inductor is in series with LED load and requires a smaller

capacitor than the Boost, Buck-Boost, and SEPIC topologies to achieve the same LED ripple current. The

capacitance required for the target LED ripple current can be calculated based on following equations.

Buck:

Di_L(PP)

C_OUT

=

8ì f_SWìr_Dì Di_LED(PP)

(14)

Boost and Buck-Boost:

I_LEDìD_MAX

f_SWìr_Dì Di_LED(PP)

C_OUT

=

(15)

When choosing the output capacitors, it is important to consider the ESR and the ESL characteristics as they

directly impact the LED current ripple. Ceramic capacitors are the best choice due to their low ESR, high ripple

current rating, long lifetime, and good temperature performance. When selecting ceramic capacitors, it is

important to consider the derating factors associated with higher temperature and DC bias operating conditions.

TI recommends an X7R dielectric with voltage rating greater than maximum LED stack voltage. An aluminum

electrolytic capacitor can be used in parallel with ceramic capacitors to provide bulk energy storage. The

aluminum capacitors must have necessary RMS current and temperature ratings to ensure prolonged operating

lifetime. The minimum allowable RMS output capacitor current rating, I_COUT(RMS), can be approximated:

Buck:

Di_LED(PP)

I_COUT(RMS)

=

12

Boost and Buck-Boost:

(16)

D_MAX

I_COUT(RMS)= I_LED

ì

1- D_MAX

(17)

The expressions (Equation 14 to Equation 17) are best suited for designs driving a fixed LED load, with known

output voltage and LED current. For applications that are required to support different LED string configurations

with a wide range of programmable LED current setpoints, the previous expressions are rearranged to reflect

output capacitance based on the maximum output power, P_O(MAX), to ensure that LED current ripple

specifications are met over the entire range of operation. Typical Buck-Boost LED Driver provides the details for

Buck-Boost LED driver.

20

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

Application Information (continued)

8.1.4 Input Capacitor Selection

The input capacitors, C_IN, smooth the input voltage ripple and store energy to supply input current during input

voltage or PWM dimming transients. The series inductor in the Boost, SEPIC, and Cuk topology provides

continuous input current and requires a smaller input capacitor to achieve desired input ripple voltage, Δv_IN(PP)

.

The Buck and Buck-Boost topology have discontinuous input current and require a larger capacitor to achieve

the same input voltage ripple. Based on the switching frequency, ƒ_SW, and the maximum duty cycle, D_MAX, the

input capacitor value can be calculated as follows:

Buck:

I_LEDìD_MAXì(1-D_MAX

f_SWì Dv_IN(PP)

)

C_IN

=

(18)

(19)

(20)

Boost:

C_IN

Di_L(PP)

=

8ì f_SWì Dv_IN(PP)

Buck-Boost:

I_LEDìD_MAX

f_SWì Dv_IN(PP)

C_IN

=

X7R dielectric-based ceramic capacitors are the best choice due to their low ESR, high ripple current rating, and

good temperature performance. For applications using PWM dimming, TI recommends an aluminum electrolytic

capacitor in addition to ceramic capacitors to minimize the voltage deviation due to large input current transients

generated in conjunction with the rising and falling edges of the LED current.

TPS92691

R_VIN

VIN

C_VIN

Figure 28. VIN Filter

For most applications, TI highly recommends to bypass the VIN pin with a 0.1-µF ceramic capacitor placed as

close as possible to the device and add a series 10-Ω resistor to create a 150-kHz low-pass filter and eliminate

undesired high-frequency noise.

8.1.5 Main Power MOSFET Selection

The power MOSFET should be able to sustain the maximum switch node voltage, V_SW, and switch RMS current

derived based on the converter topology. TI recommends a drain voltage V_DSrating of at least 20% greater than

the maximum switch node voltage to ensure safe operation. The MOSFET drain-to-source breakdown voltage,

V_DS, and RMS current ratings are calculated using the following expressions.

Buck:

V_DS= V_IN(MAX)ì1.2

(21)

I_Q(RMS)= I_LEDì D_MAX

(22)

Boost:

V_DS= V_O(OV)ì1.2

(23)

21

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

Application Information (continued)

D_MAX

I_Q(RMS)= I_LED

Buck-Boost:

ì

1- D_MAX

(24)

V_DS= V

+ V_O(OV)ì1.2

(

)

IN(MAX)

(25)

(26)

D_MAX

I_Q(RMS)= I_LED

ì

1- D_MAX

Where the voltage, V_O(OV), is the overvoltage protection threshold and the worst-case output voltage under fault

conditions.

Select a MOSFET with low total gate charge, Q_g, to minimize gate drive and switching losses. The MOSFET R_DS

resistance is usually a less critical parameter because the switch conduction losses are not a significant part of

the total converter losses at high operating frequencies. The switching and conduction losses are calculated as

follows:

P_COND= R_DSìI_Q²_(RMS)

(27)

I_Lì V_S²_WìC_RSSì f_SW

P_SW

=

I_GATE

(28)

C_RSSis the MOSFET reverse transfer capacitance. I_Lis the average inductor current. I_GATEis gate drive output

current, typically 500 mA. The MOSFET power rating and package should be selected based on the total

calculated loss, the ambient operating temperature, and maximum allowable temperature rise.

8.1.6 Rectifier Diode Selection

A Schottky diode (when used as a rectifier) provides the best efficiency due to low forward voltage drop and

near-zero reverse recovery time. TI recommends a diode with a reverse breakdown voltage, V_D(BR), greater than

or equal to MOSFET drain-to-source voltage, V_DS, for reliable performance. It is important to understand the

leakage current characteristics of the Schottky diode, especially at high operating temperatures because it

impacts the overall converter operation and efficiency.

The current through the diode, I_D, is given by:

I_D= I_Lì (1 - D _{M A X}

)

(29)

The diode should be sized to exceed the current rating, and the package should be able to dissipate power

without exceeding the maximum allowable temperature.

8.1.7 LED Current Programming

The LED current is set by the external current sense resistor, R_CS, and the analog adjust voltage, V_IADJ. The

current sense resistor is placed in series with the LED load and can be located either on the high side

(connected to the output, V_O), or on the low side (connected to ground, GND). The CSP and CSN inputs of the

internal rail-to-rail current sense amplifier are connected to the R_CSresistor to enable closed-loop regulation.

When V_IADJ> 2.5 V, the internal 2.42-V reference sets the V_(CSP-CSN)threshold to 172 mV and the LED current is

regulated to:

0.172

I_LED

=

R_CS

(30)

The LED current can be programmed by varying V_IADJbetween 140 mV to 2.25 V. The LED current can be

calculated using:

V

IADJ

I_LED

=

14ìR_CS

(31)

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TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

Application Information (continued)

The output voltage ripple should be limited to 50 mV for best performance. TI recommends a low-pass common-

mode filter consisting of 10-Ω resistors is series with CSP and CSN inputs and 0.01-µF capacitors to ground to

minimize the impact of voltage ripple and noise on LED current accuracy (see Figure 20). A 0.1-µF capacitor

across CSP and CSN is included to filter high-frequency differential noise.

8.1.8 Switch Current Sense Resistor and Slope Compensation

The switch current sense resistor, R_IS, is used to implement peak current mode control and to set the peak

switch current limit. The value of switch current sense R_ISis selected to achieve stable inner current loop

operation based on the magnitude of slope compensation ramp, V_SL, and to protect the main switching MOSFET

under fault conditions. The lower of the two values calculated using the following equations should be selected

for R_IS.

2ì V_SLìL ì f_SW

R_IS

=

V_O(MAX)

(32)

V

- V_SLìD_MAX

IS(LIMIT)

R_IS

=

I_L(PK)

(33)

The internal slope compensation voltage, V_SLis fixed at 200 mV (typ). A resistor can be placed in series with the

IS pin to increase slope compensation, if necessary. The peak switch current limit is set based on the internal

current limit threshold of 525 mV (typ) and adjusted based on slope compensation to ensure reliable operation

while PWM dimming.

VCC

TPS92691

GATE

100 O

R_IS

IS

1 nF

PGND

Figure 29. IS Input Filter

The use of a 1-nF and 100-Ω low-pass filter is optional. If used, the resistor value should be less than 500 Ω to

limit its influence on the internal slope compensation signal.

8.1.9 Feedback Compensation

The open-loop response is the product of the modulator transfer function (shown in Equation 34) and the

feedback transfer function. Using a first-order approximation, the modulator transfer function can be modeled as

a single pole created by the output capacitor, and in the boost and buck-boost topologies, a right half-plane zero

created by the inductor, where both have a dependence on the LED string dynamic resistance, r_D. Because TI

recommends a ceramic capacitor, the ESR of the output capacitor is neglected in the analysis. The small-signal

modulator model also includes a DC gain factor that is dependent on the duty cycle, output voltage, and LED

current.

≈

∆

«

≈

∆

«

’

÷

◊

’

÷

◊

s

1-

1+

Ù

w_Z

i

LED

= G₀

Ù

v_COMP

s

w_P

(34)

Table 1 summarizes the expression for the small-signal model parameters.

23

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

Application Information (continued)

The feedback transfer function includes the current sense resistor and the loop compensation of the

transconductance amplifier. A compensation network at the output of the error amplifier is used to configure loop

gain and phase characteristics. A simple capacitor, C_COMP, from COMP to GND (as shown in Figure 30) provides

integral compensation and creates a pole at the origin. Alternatively, a network of R_COMP, C_COMP, and C_HF, shown

in Figure 31, can be used to implement proportional and integral (PI) compensation and to create a pole at the

origin, a low-frequency zero, and a high-frequency pole.

Table 1. Small-Signal Model Parameters

DC GAIN (G₀)

POLE FREQUENCY (ω_P)

ZERO FREQUENCY (ω_Z)

1

Buck

1

—

r_Dì C_OUT

(1- D)ì V_O

V + r ìI

LED

(

)

V_Oì(1-D)²

L ìI_LED

O

D

Boost

R_ISì V + r ìI

(

)

(

)

V_Oìr_Dì C_OUT

O

D

LED

(1-D)ì V_O

V + Dìr ìI

(

)

V_Oì(1-D)²

DìL ìI_LED

O

D

LED

Buck-Boost

R_ISì V + Dìr ìI

(

)

(

)

V_Oìr_DìC_OUT

O

D

LED

The feedback transfer function is defined as follows.

Feedback transfer function with integral compensation:

Ù

v_COMP14ì g_MìR_CS

-

=

Ù

sì C_COMP

i

LED

(35)

(36)

Feedback transfer function with proportional integral compensation:

Ù

1+ sìR_COMPìC_COMP

v_COMP

14ì g_MìR_CS

sì C + C_HF

(

)

-

=

Ù

≈

’

(

)

i

≈

∆

«

’

÷

◊

C_COMPìC_HF

C_COMP+ C_HF

COMP

LED

1+ sìR

ì

∆

÷

COMP

«

◊

The pole at the origin minimizes output steady-state error. High bandwidth is achieved with the PI compensator

by placing the low-frequency zero an order of magnitude less than the crossover frequency. Use the following

expressions to calculate the compensation network.

TPS92691

COMP

R_COMP

C_COMP

C_HF

C_COMP

GAIN = 14

CSP

CSN

CSP

CSN

+

R_CS

I_LED

R_CS

I_LED

CURRENT SENSE

AMPLIFIER

CURRENT SENSE

AMPLIFIER

VCC

IADJ

+

2.42V

Figure 30. Integral Compensation

Buck with integral compensator:

Figure 31. Proportional-Integral Compensation

8.75ì10^-3ìR_CS

C_COMP

=

w_P

(37)

Boost and Buck-Boost with proportional integral compensator:

24

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

≈

∆

«

’

÷

◊

R_CSìG₀

C_COMP= 8.75ì10^-3ì

w_Z

(38)

(39)

C_COMP

100

C_HF

=

1

R_COMP

=

w_PìC_COMP

(40)

The loop response is verified by applying step input voltage transients. The goal is to minimize LED current

overshoot and undershoot with a damped response. Additional tuning of the compensation network may be

necessary to optimize PWM dimming performance.

8.1.10 Soft-Start

The soft-start time (t_SS) is the time required for the LED current to reach the target setpoint. The required soft-

start time, t_SS, is programmed using a capacitor, C_SS, from SS pin to GND, and is based on the LED current,

output capacitor, and output voltage.

≈

∆

«

’

÷

◊

C_OUTì V_OUT

C_SS= 12.5ì10^-6

t

-

SS

I_LED

(41)

8.1.11 Overvoltage Protection

The overvoltage threshold is programmed using a resistor divider, R_OV2and R_OV1, from the output voltage, V_O, to

ground for Boost and SEPIC topologies, as shown in Figure 24 and Figure 25. If the LEDs are referenced to a

potential other than ground, as in the Buck-Boost or Buck configuration, the output voltage is sensed and

translated to ground by using a PNP transistor and level-shift resistors, as shown in Figure 27 and Figure 26.

The overvoltage turn-off threshold, V_O(OV), is:

Boost:

≈

∆

«

’

÷

◊

R_OV1+ R_OV2

V_O(OV)= V_OVP(THR)

ì

R_OV1

(42)

Buck and Buck-Boost:

R_OV2

R_OV1

V_O(OV)= V_OVP(THR)

ì

+ 0.7

(43)

(44)

The overvoltage hysteresis, V_OV(HYS)is:

V_OV(HYS)= I_OVP(HYS)ìR_OV2

8.1.12 PWM Dimming Considerations

When PWM dimming, the TPS92691/-Q1 requires another MOSFET placed in series with the LED load. This

MOSFET should have a voltage rating greater than the output voltage, V_O, and a current rating at least 10%

higher than the nominal LED current, I_LED

.

It is important to control the slew-rate of the external FET to achieve a damped LED current response to PWM

rising-edge transitions. For a low-side, N-channel dimming FET, the slew-rate is controlled by placing a resistor

in series with the GATE pin. The rise and fall times depend on the value of the resistor and the gate-to-source

capacitance of the MOSFET. The series resistor can be bypassed with a diode for fast rise time and slow fall

times to achieve 100:1 or higher contrast ratios. If a high-side P-channel dimming FET is used, the rise and fall

times can be controlled by selecting appropriate resistors for the level-shift network, R_LS1and R_LS2, as shown in

Figure 26.

25

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

8.2.1.1 Design Requirements

Table 2 shows the design parameters for the boost LED driver application.

Table 2. Design Parameters

PARAMETER

INPUT CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input voltage range

Input UVLO setting

7

14

18

V

4.5

OUTPUT CHARACTERISTICS

LED forward voltage

3.2

12

V

Number of LEDs in series

V_O

I_LED

RR

r_D

Output voltage

LED+ to LED–

38.4

500

5%

4

V

Output current

mA

LED current ripple ratio

LED string resistance

Maximum output power

PWM dimming range

Ω

20

25

W

240-Hz PWM frequency

4%

100%

SYSTEMS CHARACTERISTICS

Δi_L(PP)

Δv_IN(PP)

V_O(OV)

V_OV(HYS)

t_ss

Inductor current ripple

20%

70

50

5

Input voltage ripple

mV

V

Output overvoltage protection threshold

Output overvoltage protection hysteresis

Soft-start period

V

8

ms

kHz

Switching frequency

390

8.2.1.2 Detailed Design Procedure

This procedure is for the boost LED driver application.

8.2.1.2.1 Calculating Duty Cycle

Solve for D, D_MAX, and D_MIN

:

38.4 -14

38.4

V_O- V

IN

D =

=

= 0.6354

V_O

V_O- V

(45)

38.4 - 7

IN(MIN)

D_MAX

=

= 0.8177

= 0.5312

V_O

38.4

(46)

(47)

V_O- V

38.4 -18

IN(MAX)

D_MIN

=

V_O

38.4

8.2.1.2.2 Setting Switching Frequency

Solve for R_T:

1.432ì10¹⁰

R_T

=

= 20.05ì10³

1.047

)

1.047

390ì10³

f

(

SW

(

)

(48)

The closest standard resistor of 20 kΩ is selected.

8.2.1.2.3 Inductor Selection

The inductor value should ensure continuous conduction mode (CCM) of operation and should achieve desired

ripple specification, Δi_L(PP)

.

27

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

I_LED

Di_L(PP)= RRì

1-D_MAX

0.5

= 0.2ì

= 0.5485

1- 0.8177

(49)

Solving for inductor:

V

_IN(MIN)ìD_MAX

7ì 0.8177

0.5485 ì390 ì10³

L =

=

= 26.76 ì10^-6

Di_L(PP)ì f_SW

(50)

(51)

(52)

The closest standard inductor is 27 µH. The expected inductor ripple based on the chosen inductor is:

V

_IN(MIN)ìD_MAX

7ì0.8177

27ì10^-6ì390ì10³

Di_L(PP)

=

= 0.5436

L ì f_SW

The inductor saturation current rating should be greater than the peak inductor current, I_L(PK)

.

V

_IN(MIN)ìD_MAX

I_LED

0.5

7ì0.8177

2ì 27ì10^-6ì390ì10³

I_L(PK)

=

+

=

+

= 3.01

1-D_MAX

2ìLì f_SW

1- 0.8177

8.2.1.2.4 Output Capacitor Selection

The specified peak-to-peak LED current ripple, Δi_LED(PP), is:

Di_LED(PP)= 0.05ìI_LED= 25 ì10^-3

(53)

(54)

The output capacitance required to achieve the target LED current ripple is:

I_LEDìD_MAX

f_SWìr_Dì Di_LED(PP)

0.5ì0.8177

390ì10³ì 4ì 25ì10^-3

C_OUT

=

= 10.48ì10^-6

Considering 40% derating factor under DC bias operation, four 4.7-µF, 100-V rated X7R ceramic capacitors are

used in parallel to achieve a combined output capacitance of 18.8 µF.

8.2.1.2.5 Input Capacitor Selection

The input capacitor is required to reduce switching noise conducted through the input wires and reduced the

input impedance of the LED driver. The capacitor required to limit peak-to-peak input ripple voltage ripple,

Δv_IN(PP), to 70 mV is given by:

Di_L(PP)

0.5436

8ì390ì10³ì70ì10^-3

C_IN

=

= 2.49ì10^-6

8ì f_SWì Dv_IN(PP)

(55)

A 4.7-µF, 50-V X7R ceramic capacitor is selected.

8.2.1.2.6 Main N-Channel MOSFET Selection

The MOSFET ratings should exceed the maximum output voltage and RMS switch current given by:

V_DS= V_O(OV)ì1.2 = 50ì1.2 = 60

(56)

(57)

D_MAX

0.8177

I_Q(RMS)= I_LED

ì

= 0.5ì

= 2.48

1-D_MAX

1- 0.8177

A 60-V or a 100-V N-channel MOSFET with current rating exceeding 3 A is required for this design.

8.2.1.2.7 Rectifying Diode Selection

The diode should be selected based on the following voltage and current ratings:

V_D(BR)= V_O(OV)ì1.2 = 50ì1.2 = 60

(58)

(59)

I_D= I_Lì(1-D_MAX) = I_LED= 0.5

A 60-V or a 100-V Schottky diode with low reverse leakage current is suitable for this design. The package must

be able to handle the power dissipation resulting from continuous forward current, I_D, of 0.5 A.

28

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

8.2.1.2.8 Programming LED Current

LED current is based on the current shunt resistor, R_CSand the V_(CSP-CSN)threshold set by the voltage on the

IADJ pin V_IADJ. By default, IADJ is tied to VCC via an external resistor to enable the internal reference voltage of

2.42 V that then sets the V_(CSP-CSN)threshold to 172 mV. The current shunt resistor value is calculated by:

0.172 0.172

R_CS

=

= 0.344

I_LED

0.5

(60)

Two 0.68-Ω resistors are connected in parallel to achieve R_CSof 0.34 Ω.

8.2.1.2.9 Setting Switch Current Limit and Slope Compensation

The switch current sense resistor, R_IS, is calculated by solving the following equations and choosing the lowest

value:

2ì0.2ì27ì10^-6ì390ì10³

2ì V_SLìLì f_SW

R_IS

=

= 0.11

V_O(MAX)

_IS(LIMIT)- V_SLìD_MAX

38.4

(61)

(62)

V

0.525 - 0.2ì0.8177

R_IS

=

= 0.12

I_L(PK)

3.01

A standard value of 0.1 Ω is selected.

8.2.1.2.10 Deriving Compensator Parameters

The modulator transfer function for the Boost converter is derived for nominal V_INvoltage and corresponding duty

cycle, D, and is given by the following equation. (See Table 1 for more information.)

≈

∆

«

≈

∆

«

’

÷

◊

’

÷

◊

s

≈

s

’

1-

1+

1-

∆

«

÷

◊

378.12ì10³

Ù

w_Z

i

LED

= G₀

= 3.466

Ù

v_COMP

≈

s

’

s

1+

∆

÷

◊

14ì10³

w_P

«

(63)

The proportional-integral compensator components C_COMPand R_COMPare obtained by solving the following

expressions:

≈

∆

«

’

÷

◊

R_CSìG₀

≈ 0.34ì3.466 ’

C_COMP= 8.75ì10^-3ì

= 8.75ì10^-3ì

= 27.27ì10^-9

∆

÷

378.12ì10³

w_Z

«

◊

(64)

(65)

1

R_COMP

=

= 2.165ì10³

14ì10³ì33ì10^-9

w_PìC_COMP

The closet standard capacitor of 33 nF and resistor of 2.15 kΩ is selected. The high frequency pole location is

set by a 100 pF C_HFcapacitor.

8.2.1.2.11 Setting Start-up Duration

The soft-start capacitor required to achieve start-up in 8 ms is given by:

18.8ì10^-6ì38.4

≈

∆

«

’

≈

∆

«

’

÷

◊

C_OUTì V_OUT

C_SS= 12.5ì10^-6

t

-

= 12.5 ì10^-68 ì10^-3

-

= 81.9 ì10^-9

∆

÷

◊

SS

I_LED

0.5

(66)

The closet standard capacitor of 100 nF is selected.

8.2.1.2.12 Setting Overvoltage Protection Threshold

The overvoltage protection threshold of 50 V and hysteresis of 5 V is set by the R_OV1and R_OV2resistor divider.

V_OV(HYS)

5

R_OV2

=

= 250ì10³

20ì10^-620ì10^-6

(67)

29

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

≈

’

1.24

≈

’

R_OV1= ∆

÷R_OV2

=

250ì10³= 6.36ì10³

∆

«

÷

◊

∆

÷

V_O(OV)-1.24

50 -1.24

«

◊

(68)

The standard resistor values of 249 kΩ and 6.34 kΩ are chosen.

8.2.1.2.13 PWM Dimming Considerations

A series dimming FET is required to meet PWM dimming specification from 100% to 4% duty cycle. A 60-V, 2-A

N-channel FET is suitable for this application.

As an alternative, a 60-V, 2-A P-channel FET could be used to achieve PWM dimming. An external level-shift

circuit is required to translate the DDRV signal to the gate of the P-channel dimming FET. The drive strength of 5

mA and gate-source voltage of 15 V are set by the 1-kΩ and 2-kΩ level-translator resistors and a small-signal N-

channel MOSFET, whose gate is connected to DDRV.

By default, the PWM pin is connected to VCC through a 100-kΩ resistor to enable the part upon start-up.

8.2.1.3 Application Curves

These curves are for the boost LED driver.

100

95

90

85

80

75

7

8

9

10 11 12 13 14 15 16 17 18

V_IN(V)

Ch1: Switch node voltage;

D021

Ch3: Switch sense current resistor voltage;

Ch4: LED current; Time: 1 µs/div

Figure 34. Normal Operation

Figure 33. Efficiency vs Input Voltage

Ch1: Input voltage; Ch2: Soft-start (SS) voltage;

Ch3: Input current;

Ch4: LED current; Time: 2 ms/div

Figure 35. Startup Transient

Ch1: Output voltage;

Ch2: Soft-start (SS) voltage;

Ch4: LED current; Time: 200 ms/div

Figure 36. Overvoltage Protection

30

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

Ch1: GATE voltage; Ch2: External CLK signal;

Ch1: DDRV voltage; Ch2: PWM input;

Ch3: Switch sense current resistor voltage;

Ch4: LED current; Time: 1 µs/div

Ch3: Switch sense current resistor voltage;

Ch4: LED current; Time: 2 ms/div

Figure 37. Clock Synchronization

Figure 38. PWM Dimming Transient

Ch1: DDRV voltage; Ch2: PWM input;

Ch3: Switch sense current resistor voltage;

Ch4: LED current; Time: 4 µs/div

Ch1: Input voltage;

Ch2: IMON voltage;

Ch4: LED current; Time: 2 ms/div

Figure 40. Step Input Voltage Transient and IMON

Behavior

Figure 39. PWM Dimming Transient (Zoomed)

31

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

8.2.2.1 Design Requirements

Buck-Boost LED drivers provide the flexibility needed in applications that support multiple LED load

configurations. For such applications, it is necessary to modify the design procedure presented in Application

Information to account for the wider range of output voltage and LED current specifications. This design is based

on the maximum output power P_O(MAX), set by the lumen output specified for the lighting application. The design

procedure for a battery connected application with 3 to 9 LEDs in series and maximum 15 W output power is

outlined in this section.

For applications that have a fixed number of LEDs and a narrow LED current range (for brightness correction),

design equations provided in the Application Information and simplified design procedure, similar to one outlined

in Typical Boost LED Driver for Boost LED driver, are recommended for developing an optimized circuit with

lower Bill of Material (BOM) cost.

Table 3. Design Parameters

PARAMETER

INPUT CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX UNIT

Input voltage range

Input UVLO setting

7

14

18

V

4.5

OUTPUT CHARACTERISTICS

LED forward voltage

3.2

6

V

Number of LEDs in series

3

9.6

9

28.8

1500

V_O

Output voltage

LED+ to LED–

19.2

750

5%

2

V

I_LED

Output current

500

mA

Δi_LED(PP)

r_D

LED current ripple

LED string resistance

Maximum output power

PWM dimming range

1

3

15

Ω

P_O(MAX)

W

240-Hz PWM frequency

4%

100%

SYSTEMS CHARACTERISTICS

P_O(BDRY)

Output power at CCM-DCM boundary

5

W

condition

Δv_IN(PP)

V_O(OV)

V_OV(HYS)

t_ss

Input voltage ripple

70

40

5

mV

V

Output overvoltage protection threshold

Output overvoltage protection hysteresis

Soft-start period

V

8

ms

kHz

Switching frequency

390

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Calculating Duty Cycle

Solving for D, D_MAX, and D_MIN

:

V_O

19.2

19.2 +14

D =

=

= 0.5783

V_O+ V

IN

(69)

V_O(MAX)

28.8

D_MAX

=

= 0.8045

V_O(MAX)+ V

28.8 + 7

IN(MIN)

(70)

(71)

V_O(MIN)

9.6

=

D_MIN

=

= 0.3478

V_O(MIN)+ V

9.6 +18

IN(MAX)

8.2.2.2.2 Setting Switching Frequency

Solving for R_Tresistor:

33

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

1.432ì10¹⁰

R_T

=

= 20.05ì10³

1.047

390ì10³

f

(

)

SW

(

)

(72)

8.2.2.2.3 Inductor Selection

The inductor is selected to meet the CCM-DCM boundary power requirement, P_O(BDRY). Typically, the boundary

condition is set to enable CCM operation at the lowest possible operating power based on minimum LED forward

voltage drop and LED current. In most applications, P_O(BDRY)is set to be 1/3 of the maximum output power,

P_O(MAX). The inductor value is calculated for maximum input voltage, V_IN(MAX), and output voltage, V_O(MAX)

:

1

L =

=

= 31.46ì10^-6

2

1

≈

’

≈

’

2ì5ì390ì10³ì

+

1

2ìP_O(BDRY)ì f_SW

ì

+

∆

«

÷

◊

∆

«

÷

◊

28.8 18

V_O(MAX)

V

IN(MAX)

(73)

(74)

The closest standard value of 33 µH is selected. The inductor ripple current is given by:

V_IN(MIN)ìD_MAX

7ì0.8045

Di_L(PP)

=

= 0.4376

33ì10^-6ì390ì10³

L ì f_SW

The inductor saturation rating should exceed the calculated peak current which is based on the maximum output

power using the following expression:

≈

’

V_O(MIN)ì V

1

IN(MIN)

I_L(PK)= P_O(MAX)ì∆

+

÷ +

÷

∆

V_O(MIN)

V

IN(MIN)

2ìL ì f_SWì V_O(MIN)+ V

(

)

IN(MIN)

«

◊

(75)

1

7

9.6 ì7

≈

’

I_L(PK)= 15ì

+

= 3.863

∆

«

÷

◊

2ì33ì10^-6ì390 ì10³ì 9.6 + 7

9.6

(

)

8.2.2.2.4 Output Capacitor Selection

The output capacitor should be selected to achieve the 5% peak-to-peak LED current ripple specification. Based

on the maximum power, the capacitor is calculated as follows:

P_O(MAX)

C_OUT

=

f_SWìr_D(MIN)ì Di_LED(PP)ì V_O(MIN)+ V

(

)

IN(MIN)

(76)

15

C_OUT

=

= 30.9 ì10^-6

390ì10³ì1ì0.075 ì 9.6 + 7

(

)

A minimum of four 10-µF, 50-V X7R ceramic capacitors in parallel are needed to meet the LED current ripple

specification over the entire range of output power. Additional capacitance may be required based on the

derating factor under DC bias operation.

8.2.2.2.5 Input Capacitor Selection

The input capacitor is calculated based on the peak-to-peak input ripple specifications, Δv_IN(PP). The capacitor

required to limit the ripple to 70 mV over range of operation is calculated using:

P_O(MAX)

15

C_IN

=

= 33.1ì10^-6

f_SWì Dv_IN(PP)ì V_O(MIN)+ V

390ì10³ì0.07ì 9.6 + 7

(

)

(

)

IN(MIN)

(77)

A parallel combination of four 10-µF, 50-V X7R ceramic capacitors are used for a combined capacitance of 40

µF. Additional capacitance may be required based on the derating factor under DC bias operation.

8.2.2.2.6 Main N-Channel MOSFET Selection

Calculating the minimum transistor voltage and current rating:

V_DS= 1.2ì V_O(OV)+ V

= 1.2ì(40 +18) = 69.6

(

)

IN(MAX)

(78)

34

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

≈

’

P_O(MAX)

V

15

7

≈

’

I_Q(RMS)

=

∆1+ ^IN(MIN)÷ =

1+

= 2.82

∆

«

÷

◊

∆

÷

V

V_O(MIN)

9.6

IN(MIN)

«

◊

(79)

This application requires a 60-V or 100-V N-channel MOSFET with a current rating exceeding 3 A.

8.2.2.2.7 Rectifier Diode Selection

Calculating the minimum Schottky diode voltage and current rating:

V_D(BR)= 1.2ì V

+ V

= 1.2ì(40 +18) = 69.6

(

)

O(OV)

IN(MAX)

(80)

(81)

I_D= I_LED(MAX)= 1.5

This application requires a 60-V or 100-V Schottky diode with a current rating exceeding 1.5 A. TI recommends a

single high-current diode instead of paralleling multiple lower-current-rated diodes to ensure reliable operation

over temperature.

8.2.2.2.8 Setting Switch Current Limit and Slope Compensation

Solving for R_IS:

2ì0.2ì33ì10^-6ì390ì10³

2ì V_SLìL ì f_SW

R_IS

=

= 0.179

V_O(MAX)

28.8

(82)

(83)

V

- V_SLìD_MAX

0.525 - 0.2ì0.8045

IS(LIMIT)

R_IS

=

= 0.094

I_L(PK)

3.863

A standard resistor of 0.1 Ω is selected based on the lower of the two calculated values. The resistor ensures

stable current loop operation with no subharmonic oscillations over the entire input and output voltage ranges.

8.2.2.2.9 Programming LED Current

The LED current can be programmed to match the LED string configuration by using a resistor divider, R_ADJ1and

R_ADJ2, from V_CCto GND for a given sense resistor, R_CS, as shown in Figure 21. To maximize the accuracy, the

IADJ pin voltage is set to 2.1 V for the specified LED current of 1.5 A. The current sense resistor, R_CS, is then

calculated as:

V

2.1

14ìI_LED(MAX)14ì1.5

IADJ

R_CS

=

= 0.1

(84)

A standard resistor of 0.1 Ω is selected. Table 4 summarizes the IADJ pin voltage and the choice of the R_ADJ1

and R_ADJ2resistors for different current settings.

Table 4. Design Requirements

LED CURRENT

500 mA

IADJ VOLTAGE (V_IADJ

)

R_ADJ1

R_ADJ2

100 kΩ

700 mV

1.05 V

2.1 V

10.2 kΩ

16.2 kΩ

39.2 kΩ

750 mA

1.5 A

8.2.2.2.10 Deriving Compensator Parameters

A simple integral compensator provides a good starting point to achieve stable operation across the wide

operating range. The modulator transfer function with the lowest frequency pole location is calculated based on

maximum output voltage, V_O(MAX), duty cycle, D_MAX, LED dynamic resistance, r_D(MAX), and minimum LED string

current, I_LED(MIN). (See Table 1 for more information.)

≈

∆

«

≈

∆

«

’

÷

◊

’

÷

◊

s

≈

s

’

1-

1+

1-

∆

÷

82.92ì10³

Ù

w_Z

i

«

◊

LED

= G₀

= 1.876

Ù

v_COMP

≈

s

’

s

1+

∆

÷

8.68ì10³

w_P

«

◊

(85)

35

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

The compensation capacitor needed to achieve stable response is:

8.75ì10^-3ìR_CS

8.75ì10^-3ì0.1

C_COMP

=

= 100.8ì10^-9

8.68ì10³

w_P

(86)

A 100 nF capacitor is selected.

A proportional integral compensator can be used to achieve higher bandwidth and improved transient

performance. However, it is necessary to experimentally tune the compensator parameters over the entire

operating range to ensure stable operation.

8.2.2.2.11 Setting Startup Duration

Solving for soft-start capacitor, C_SS, based on 8-ms startup duration:

40ì10^-6ì 28.8

≈

’

≈

’

C_OUTì V_OUT(MAX)

C_SS= 12.5ì10^-6∆t_SS

-

÷ = 12.5 ì10^-68 ì10^-3

-

= 71.2ì10^-9

∆

÷

◊

∆

÷

I_LED(MIN)

0.5

«

◊

(87)

A 100-nF soft-start capacitor is selected.

8.2.2.2.12 Setting Overvoltage Protection Threshold

Solving for resistors, R_OV1and R_OV2

:

V_OV(HYS)

20ì10^-620ì10^-6

5

R_OV2

=

= 250ì10³

(88)

(89)

1.24ì 250 ì10³

1.24ìR_OV2

V_O(OV)- 0.7

R_OV1

=

= 7.89ì10³

40 - 0.7

The closest standard values of 249 kΩ and 7.87 kΩ along with a 60-V PNP transistor are used to set the OVP

threshold to 40 V with 5 V of hysteresis.

8.2.2.2.13 PWM Dimming Consideration

A 60-V, 2-A P-channel FET is used in conjunction with an external level-shift circuit to achieve PWM dimming.

The drive strength of 5 mA and gate-source voltage of 15 V are set by the 1-kΩ and 2-kΩ level-translator

resistors and a small-signal N-channel MOSFET, whose gate is connected to DDRV.

8.2.2.3 Application Curves

These curves are for the buck-boost LED driver.

1600

1400

1200

1000

800

600

400

200

0

1504

1503

1502

1501

1500

1499

1498

1497

1496

508

506

504

502

500

498

496

494

492

LEDs = 3

LEDs = 9

LEDs = 3

8

9

10

11

12

13

V_IN(V)

14

15

16

17

18

0

0.28 0.56 0.84 1.12

V_IADJ(V)

1.4

1.68 1.96 2.24

D022

D023

V_IN= 14 V

Figure 43. LED Current vs IADJ Voltage

Figure 42. Line Regulation (3 LEDs at 1.5 A and 9 LEDs at

500 mA)

36

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

100

90

80

70

60

50

40

LEDs = 3

LEDs = 5

LEDs = 7

LEDs = 9

100

200

300 400 500 700 1000

I_LED(mA)

2000

D024

V_IN= 14 V

Figure 44. Efficiency from 100 mA to 1.5 A

9 Power Supply Recommendations

This device is designed to operate from an input voltage supply range between 4.5 V and 65 V. The input could

be a car battery or another preregulated power supply. If the input supply is located more than a few inches from

the TPS92691/-Q1 device, additional bulk capacitance or an input filter may be required in addition to the

ceramic bypass capacitors to address noise and EMI concerns.

10 Layout

10.1 Layout Guidelines

•

The performance of the switching regulator depends as much on the layout of the PCB as the component

selection. Following a few simple guidelines will maximize noise rejection and minimize the generation of EMI

within the circuit.

•

Discontinuous currents are the most likely to generate EMI. Therefore, take care when routing these paths.

The main path for discontinuous current in the TPS92691/-Q1 Buck regulator contains the input capacitor,

C_IN, the recirculating diode, D, the N-channel MOSFET, Q1, and the sense resistor, R_IS. In the TPS92691/-Q1

Boost regulator, the discontinuous current flows through the output capacitor C_OUT, diode, D, N-channel

MOSFET, Q1, and the current sense resistor, R_IS. In Buck-Boost regulator, both loops are discontinuous and

should be carefully laid out. These loops should be kept as small as possible and the connection between all

the components should be short and thick to minimize parasitic inductance. In particular, the switch node

(where L, D, and Q1 connect) should be just large enough to connect the components. To minimize

excessive heating, large copper pours can be placed adjacent to the short current path of the switch node.

•

CSP and CSN traces should be routed together with Kelvin connections to the current sense resistor as short

as possible. If needed, use common mode and differential mode noise filters to attenuate switching and diode

reverse recovery noise from affecting the internal current sense amplifier.

•

The COMP, IS, OVP, PWM, and IADJ pins are all high-impedance inputs that couple external noise easily;

therefore, the loops containing these nodes should be minimized whenever possible.

In some applications, the LED or LED array can be far away from the TPS92691/-Q1, or on a separate PCB

connected by a wiring harness. When an output capacitor is used and the LED array is large or separated

from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce the effects of

parasitic inductance on the AC impedance of the capacitor.

•

The TPS92691/-Q1 has an exposed thermal pad to aid power dissipation. Adding several vias under the

exposed pad helps conduct heat away from the device. The junction-to-ambient thermal resistance varies

with application. The most significant variables are the area of copper in the PCB and the number of vias

under the exposed pad. The integrity of the solder connection from the device exposed pad to the PCB is

critical. Excessive voids greatly decrease the thermal dissipation capacity.

37

TPS92691, TPS92691-Q1

ZHCSEM9 –DECEMBER 2015

www.ti.com.cn

10.2 Layout Example

VIA TO BOTTOM GROUND PLANE

VIN

LED+

GND

VCC

GATE

IS

VIN

SS

RT/SY

PWM

COMP

IADJ

PGND

OVP

DDRV

CSP

IMON

AGND

CSN

Figure 45. Layout Recommendation

38

TPS92691, TPS92691-Q1

www.ti.com.cn

ZHCSEM9 –DECEMBER 2015

11 器件和文档支持

11.1 相关链接

下面的表格列出了快速访问链接。范围包括技术文档、支持和社区资源、工具和软件，以及样片或购买的快速访

问。

表 5. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持与社区

请单击此处

TPS92691

TPS92691-Q1

11.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.3 商标

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对本

文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

39

PACKAGE OUTLINE

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

4

0

PLASTIC SMALL OUTLINE

C

6.6

6.2

TYP

SEATING PLANE

PIN 1 ID

AREA

A

0.1 C

14X 0.65

16

1

2X

5.1

4.9

4.55

NOTE 3

8

9

0.30

16X

0.19

4.5

4.3

B

0.1

C A B

(0.15) TYP

SEE DETAIL A

4X 0.166 MAX

NOTE 5

2X 1.34 MAX

NOTE 5

THERMAL

PAD

0.25

GAGE PLANE

3.3

2.7

17

1.2 MAX

0.15

0.05

0 - 8

0.75

0.50

DETAIL A

TYPICAL

(1)

3.3

2.7

4214868/A 02/2017

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

SOLDER MASK

DEFINED PAD

(3.3)

16X (1.5)

SYMM

SEE DETAILS

1

16

16X (0.45)

(1.1)

TYP

17

SYMM

(3.3)

(5)

NOTE 9

14X (0.65)

8

9

(

0.2) TYP

VIA

(1.1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-16

4214868/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.3)

BASED ON

0.125 THICK

STENCIL

16X (1.5)

(R0.05) TYP

1

16

16X (0.45)

(3.3)

17

SYMM

BASED ON

0.125 THICK

STENCIL

14X (0.65)

9

8

SYMM

(5.8)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.69 X 3.69

3.3 X 3.3 (SHOWN)

3.01 X 3.01

0.125

0.15

0.175

2.79 X 2.79

4214868/A 02/2017

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS92691-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有轨到轨电流感应放大器的汽车类多拓扑 LED 驱动器放大器驱动驱动器
文件：	总46页 (文件大小：1983K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS92691-Q1 [TI]

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