TPS92518PWPT [TI]
具有 SPI 接口、模拟和 PWM 调光功能的 42V 双路降压 LED 控制器 | PWP | 24 | -40 to 125;型号: | TPS92518PWPT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 SPI 接口、模拟和 PWM 调光功能的 42V 双路降压 LED 控制器 | PWP | 24 | -40 to 125 控制器 |
文件: | 总56页 (文件大小:1885K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS92518
SLUSCR7 –MAY 2017
TPS92518 Dual Channel Buck LED Controller with SPI Interface,
Analog and PWM Dimming
1 Features
3 Description
The TPS92518 family of parts are dual channel buck
LED current controllers with a SPI communications
interface. The serial communication interface
1
•
•
Wide Input Voltage Range 6.5 V to 65 V
Two independent Buck LED Controllers
–
–
–
–
High Bandwidth, Quasi-Hysteretic Control
Adjustable High-Side Sense
provides
a
singular communication path for
multichannel and platform lighting driver module
(LDM) applications.
Direct PWM Dimming Input
The TPS92518 uses
a quasi-hysteretic control
Cycle-by-Cycle Current Limit
method that supports switching frequencies ranging
from 1 kHz to 2 MHz. This control method enables
superior, high frequency shunt FET dimming and also
handles the demanding dynamic loads of adaptive
LED matrix based headlamp systems.
•
•
SPI Communications Interface
–
–
–
Software configurable Set Points (8-bit)
Digital Calibration and Binning
Fault Monitoring and Reporting
Software programmable SPI set points (Precision
Peak Current, Controlled Off-Time and Output
Voltage Sense) enables designers to develop a single
LED driver solution for multiple load configurations
that can be quickly reconfigured for future LED driver
design requirements.
Advanced, High Precision Dimming
–
–
–
10,000:1 PWM Dimming Range
255:1 Analog Dimming Range
High Frequency Shunt FET Dimming
2 Applications
The TPS92518 device has an input range up to 42 V.
The TPS92518HV is a high-voltage option with an
input range up to 65 V.
•
•
•
•
Color Mixing Applications
Aftermarket Lighting Applications
LED General Lighting
Device Information(1)
Projector Applications
PART NUMBER
TPS92518
PACKAGE
BODY SIZE (NOM)
HTSSOP (24)
7.7 mm x 4.4 mm
TPS92518HV
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Battery or Boost
Regulator
Input Voltage
EN/UV
VLED1
PWM1
PWM2
µC
TPS92518
Input Voltage
VLED2
ñ Peak
ñ Off time
ñ Enable
ñ Faults
ñ Temp
SPI
Copyright © 2017, Texas Instruments Incorporated
MCU
VCC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS92518
SLUSCR7 –MAY 2017
www.ti.com
Table of Contents
8.5 Registers................................................................. 29
8.6 Programming .......................................................... 41
Application and Implementation ........................ 43
9.1 Application Information............................................ 43
9.2 Typical Application ................................................. 43
9.3 Dos and Don'ts ....................................................... 45
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 9
7.1 CSN Pin Falling Delay (tDEL)..................................... 9
7.2 Off-Timer (tOFF) ........................................................ 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Serial Interface........................................................ 25
9
10 Power Supply Recommendations ..................... 46
10.1 Input Source Direct from Battery........................... 46
10.2 Input Source from a Boost Stage.......................... 46
11 Layout................................................................... 47
11.1 Layout Guidelines ................................................. 47
11.2 Layout Example .................................................... 47
12 Device and Documentation Support ................. 48
12.1 Receiving Notification of Documentation Updates 48
12.2 Community Resources.......................................... 48
12.3 Trademarks........................................................... 48
12.4 Electrostatic Discharge Caution............................ 48
12.5 Glossary................................................................ 48
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 48
4 Revision History
DATE
REVISION
NOTES
May 2017
*
Initial release.
2
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TPS92518
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SLUSCR7 –MAY 2017
5 Pin Configuration and Functions
PWP Package
24-Pin HTTSOP
Top View
EN/UV
CSP2
CSN2
GATE2
SW2
VIN
CSP1
CSN1
GATE1
SW1
1
24
23
22
21
20
19
18
17
16
15
14
13
2
3
4
5
BOOT2
VCC2
GND
BOOT1
VCC1
GND
6
7
8
VLED2
PWM2
MOSI
MISO
VLED1
PWM1
SSN
9
10
11
12
SCK
Pin Functions
PINS
NAME
BOOT1
I/O
DESCRIPTION
NO.
6
I
I
I
I
I
I
Channel 1 bootstrap voltage input
BOOT2
CSN1
CSN2
CSP1
CSP2
19
3
Channel 2 bootstrap voltage input
Channel 1 negative current sense input
Channel 2 negative current sense input
Channel 1 positive current sense input
Channel 2 positive current sense input
22
2
23
Device enable. If not configured as under voltage lock out or enable, tie to VCCx. Tie to >23.6V to bypass SPI
communication and enable default register values.
EN/UV
24
I
GATE1
GATE2
4
O
O
Channel 1 gate drive output. Connect to FET gate
Channel 2 gate drive output. Connect to FET gate
21
8
GND
G
System ground
17
13
14
10
15
12
11
5
MISO
MOSI
PWM1
PWM2
SCK
O
I
SPI data output
SPI data input
I
Channel 1 PWM dimming input. Tie to VCCx if PWM pin control is not required.
Channel 2 PWM dimming input. Tie to VCCx if PWM pin control is not required.
SPI clock input
I
I
SSN
I
SPI slave select input
SW1
I
Channel 1 switch node connection
SW2
20
I
Channel 2 switch node connection
Channel 1 supply voltage output. May be used to power low current external circuits. See Application and Implementation
section.
VCC1
VCC2
7
O
O
Channel 2 supply voltage output. May be used to power low current external circuits. See Application and Implementation
section.
18
VIN
1
9
I
I
Device power supply voltage input. May be common to CSP1, CSP2 or an independent supply.
Channel 1 output voltage sense.
VLED1
VLED2
16
I
Channel 2 output voltage sense.
Exposed thermal pad
G
Connect to ground. Add vias to improve thermal performance.
Copyright © 2017, Texas Instruments Incorporated
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SLUSCR7 –MAY 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
-0.3
–0.3
–0.3
–0.3
–0.3
-0.3
–0.3
–2
MAX
67
UNIT
TPS92518HV
TPS92518
VIN, EN/UV, CSPx, CSNx, SWx, VLEDx to GND
44
MOSI, MISO, SCK, SSN to GND
PWMx, VCCx to GND
5.5
8.8
8.8
75
GATEx, BOOTx to SWx
V
TPS92518HV
TPS92518
GATEx, BOOTx to GND
52
CSPx to CSNx
5.5
SWx to GND, 10ns transient
Junction temperature, TJ
Storage temperature , Tstg
–40
–65
150
165
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per V AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
65
UNIT
TPS92518HV
TPS92518
6.5
6.5
-40
-40
V
V
VIN
Input Voltage
42
(1)
TA
TJ
Operating ambient temperature
Operating junction temperature
125
150
°C
°C
(1) The TPS92518-Q1 can operate at an ambient temperature of up to +125ºC as long as the junction temperature maximum of +150ºC is
not exceeded.
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6.4 Thermal Information
TPS92518
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
24 PINS
32.5
17.9
15.7
0.4
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
15.5
1.8
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VVIN = 14 V, -40 °C ≤ TJ ≤ 150 °C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCCx, VIN
VVIN = 40 V or VVIN = 65 V, 0 A ≤
External Load ≤ 500 µA
VCCx
VCCx Voltage
6.9
7.5
8.25
V
VCCx2
VCCx Voltage with External Load
VCCx undervoltage lockout
VCCx undervoltage lockout Hysteresis
VCCx regulator current limit
Operating Current
External Load = 500 µA
6.9
7.5
5.9
0.25
38
8.25
6.1
V
V
VCCx_UVLO
VCCx_UVHYS
IVCCx-LIM
IVIN
Falling threshold, VVIN = 10 V
5.65
V
VCC shorted to GND.
Not Switching
25
48
4
mA
mA
mV
3
VDO
LDO drop-out voltage
IVCC = 5 mA, VVIN = 5 V
90
225
Peak Current Comparator (CSPx, CSNx)
LEDx_PKTH_DAC = 255
LEDx_PKTH_DAC = 127
LEDx_PKTH_DAC = 10
245
255
127
10
265
mV
mV
mV
µA
VCSTx
VCSPx-VCSNx peak current threshold
118.5
135.5
ICSN
tDEL
CSN input bias current
CSN pin falling delay
0.4
1.5
CSNx fall to GATEx fall (1V/us
stimulus)
58
110
ns
ns
Leading edge blanking (minimum on-
time)
tLEB
Minimum Pulse Width
165
200
235
CSPUVLO
CSPx UVLO Falling Threshold
CSPx UVLO Hysteresis
4.65
4.90
520
5.15
V
CSPUVLO-H
mV
Gate Drivers (GATEx, SWx and BOOTx)
RDSP
GATEx PFET ( RDS High
GATEx NFET ( RDS Low
)
7.3
2.8
4.4
200
Ω
Ω
RDSN
)
VBOOT-UVLO
VBOOT-UVLO-HYS
Voltage where gate drive is disabled
Hysteresis on BOOTx UVLO
VBOOT to VSW , VBOOT falling
VBOOTx to VSWx
3.6
5.2
V
mV
PWMx low, (BOOTx to SWx) = 5V,
VSWx= 8V
IPD PWMx
IPD BOOTx
IBOOT_Q
Pull down from SWx when PWMx Low
VBOOTx -VSWx < VBOOT-UVLO
200
5
260
7
µA
mA
µA
PWMx high, (BOOTx to SWx) <
BOOT_UVLO, VSWx = 8 V
(BOOTx to SWx) = 5.5 V, 0 V ≤ VSWx
≤ 65 V
BOOTx quiescent current
100
200
OFF-TIMER
tOFF
Off-time
VLEDx = 30 V, tOFFXDAC = 255
Specified by design
3.2
4.1
50
65
4.8
µs
ns
µs
tD-OFF
COFF threshold to gate rising delay
Maximum off-time
tOFF-MAX
tOFF-MAXDAC = 255
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Electrical Characteristics (continued)
VVIN = 14 V, -40 °C ≤ TJ ≤ 150 °C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Enable and Input UVLO
VEN/UV1
EN/UV pin threshold
EN/UV pin hysteresis
EN/UV pin rising
1.18
1.24
100
1.30
V
Difference between rising and falling
threshold
VEN/UV-HYS1
mV
EN/UV pin rising to GATEx pin rising.
LEDx_MAXOFF_DAC = 0
300
ns
tEN/UV1
EN/UV pin delay
EN/UV pin falling to GATEx pin falling
EN/UV = 2 V
470
16
ns
IEN/UV-HYST1
VEN/UV2
VEN/UV-HYS2
tEN/UV2
EN/UV Hysteresis Current
12
28
µA
EN/UV LED1_EN and LED2_EN
override threshold
EN/UV pin rising writes LED1_EN and
LED2_EN = 1
23.4
3
V
V
Difference between rising and falling
threshold
EN/UV pin hysteresis
EN/UV pin delay 2
EN/UV pin rising to GATEx pin rising.
LEDx_MAXOFF_DAC = 0
520
ns
PWM, MOSI, SCK, SSN
ILKG
VIL
Leakage current
1
µA
V
Low level input voltage threshold
High level input voltage threshold
0.8
VIH
1.8
105
100
V
PWM pin rising to GATE pin rising
PWM pin falling to GATE pin falling
68
55
ns
ns
tPWM
PWM pin delay
MISO
VOL
MISO low, IMISO applied
IMISO = 10 mA
IMISO = 10 mA
0.26
26
0.51
V
RDS
MISO Pull-down resistance
Ω
ADC
ADC Reading T = –40°C
ADC Reading T = 25°C
ADC Reading T= 150°C
ADC Reading VLEDx= 60 V
ADC Reading VLEDx = 10 V
ADC Reading VLEDx = 1 V
104
130
171
230
38
Code
Code
Code
Code
Code
Code
ADCTEMP
226
37
2
240
39
4
ADCLEDx
3
SPI Interface
Falling edge of SSN to 1st SCK rising
edge
tSS_SU
SSN Setup Time
SSN Hold Time
500
250
ns
ns
Falling edge of 16th SCK to SSN
rising edge
tSS_H
tSCK
DSCK
tSU
SCK Period
Clock period
500
40
ns
%
SCK Duty Cycle
MOSI Setup Time
MOSI Hold Time
Clock duty cycle
60
MOSI valid to rising edge SCK
MOSI valid after rising edge SCK
250
275
ns
ns
tH
Time to tri-state (deactivate low-side
switch) MISO after SSN rising edge
tHI_Z
MISO Tri-State Time
110
320
320
ns
ns
Time to place valid "0" on MISO after
falling SCK edge
tMISO_HL
MISO Valid High-to-Low
Time to tri-state (deactivate the
internal low-side switch) MISO after
falling SCK edge. tRC is the time
added by the application total
capacitance and resistance.
tMISO_LH
MISO Valid Low-to-High
320+tRC
320
ns
tZO_HL
tSS
MISO Drive Time High-to-Low
SSN High Time
SSN Falling Edge to MISO Falling
ns
ns
How long SSN must remain high
between transactions
1000
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
Thermal shutdown hysteresis
175
10
°C
TSD HYST
6
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6.6 Typical Characteristics
VVIN = 14 V unless otherwise specified. Temperature = Junction Temperature. Note: Any difference between channels does
not necessarily illustrate a systematic difference between them.
127
126.9
126.8
126.7
126.6
126.5
126.4
126.3
126.2
126.1
126
5.1
4.95
4.8
-0.36
-0.39
-0.42
-0.45
-0.48
-0.51
-0.54
CSP1 UVLO Falling Threshold
CSP2 UVLO Falling Threshold
CSP1 UVLO Hysteresis
4.65
4.5
CSP2 UVLO Hysteresis
VCST1 (CSP1-CSN1)
VCST2 (CSP2-CSN2)
4.35
4.2
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
Temperature (èC)
D002
D001
VVIN = 42 V
LEDx_PKTH_DAC = 127
Figure 2. Current Sense Threshold Voltage
Figure 1. CSPx UVLO Falling Level and Hysteresis
11
256
255.5
255
10.8
10.6
10.4
10.2
10
254.5
254
253.5
253
9.8
9.6
9.4
9.2
9
252.5
252
VCST1 (CSP1-CSN1) VVIN=42
VCST2 (CSP2-CSN2) VVIN=42
VCST1 (CSP1-CSN1) VVIN=65
VCST2 (CSP2-CSN2) VVIN=65
251.5
251
VCST2 (CSP2-CSN2)
VCST1 (CSP1-CSN1)
-40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
D004
-40 -20
0
20
40
60
80 100 120 140
VVIN = 42 V and 65 V
LEDx_PKTH_DAC = 255
Temperature (èC)
D003
VVIN = 42 V
LEDx_PKTH_DAC = 10
Figure 4. Current Sense Threshold Voltage
Figure 3. Current Sense Threshold Voltage
80
4.8
4.72
4.64
4.56
4.48
4.4
0.6
BOOT1 UV FALL
BOOT2 UV FALL
BOOT1 HYST
76
72
68
64
60
56
52
48
44
40
0.55
0.5
BOOT2 HYST
0.45
0.4
0.35
0.3
4.32
4.24
4.16
4.08
4
0.25
0.2
0.15
0.1
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
Temperature (èC)
D005
D006
VVIN = 42 V
Figure 5. CSN Pin Falling Delay (tDEL
)
Figure 6. BOOT Undervoltage Lock-out Falling Threshold
and Hysteresis
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Typical Characteristics (continued)
VVIN = 14 V unless otherwise specified. Temperature = Junction Temperature. Note: Any difference between channels does
not necessarily illustrate a systematic difference between them.
1.244
1.243
1.242
1.241
1.24
0.108
64.6
64.4
64.2
64
MAXOFF_TIME1
MAXOFF_TIME2
EN_THRES1_RISING
EN_THRES1_HYS
0.1065
0.105
0.1035
0.102
63.8
63.6
63.4
63.2
63
1.239
1.238
1.237
1.236
1.235
1.234
0.1005
0.099
0.0975
0.096
0.0945
0.093
62.8
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
Temperature (èC)
D008
D007
LEDx_MAXOFF_DAC = 255
Figure 8. Enable/UV Threshold
Figure 7. Maximum Off-Time
160
40
39
38
37
36
35
34
33
32
31
30
90
80
70
60
50
40
2.8
2.4
2
PWM RISE DELAY
PWM FALL DELAY
PWM FALL THRESH
PWM RISE THRESH
159
158
157
156
155
154
153
152
151
150
1.6
1.2
0.8
ADC LED1 40V
ADC LED1 10V
-40 -20
0
20
40
60
80 100 120 140
-40 -21
-2
17
36
55
74
93 112 131 150
Temperature (èC)
Temperature (èC)
D009
D010
Readings shown are TPS92518 register values
Figure 9. ADC (Analog to Digital) LED Readings
Figure 10. PWM Input Characteristics
27
24
21
18
15
12
9
27
24
21
18
15
12
9
6
6
3
3
0
0
102
103
104
105
106
107
108
109
110
128
129
130
131
132
133
134
135
136
D022
VTHERM Register Value (Decimal)
VTHERM Register Value (Decimal)
D024
TJ = -40°C
TJ = 25°C
Figure 11. VTHERM Performance
Figure 12. VTHERM Performance
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Typical Characteristics (continued)
VVIN = 14 V unless otherwise specified. Temperature = Junction Temperature. Note: Any difference between channels does
not necessarily illustrate a systematic difference between them.
25
22.5
20
25
22.5
20
17.5
15
17.5
15
12.5
10
12.5
10
7.5
5
7.5
5
2.5
0
2.5
0
7
8
9
0
1
2
3
4
5
7
8
9
0
1
2
3
4
5
8
6
6
6
7
7
7
7
7
7
7
7
7
8
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VTHERM Register Value
VTHERM Register Value (Decimal)
D025
D021
TJ = 125°C
TJ = 150°C
Figure 13. VTHERM Performance
Figure 14. VTHERM Performance
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
1
3
6
9
2
5
8
1
4
7
9
91.
91.
91.
92.
92.
92.
93.
93.
EVM - Two Channel Efficiency9(3%. )
D017
25 x TPS92518EVM-878 EVM's Tested
LEDx_PKTH_DAC = 88
VVIN= VCSPx= 50 V
22.3 V <= VVLED1= VVLED2 <= 25.1 V
ILED1= ILED2 = 425 mA
LEDx_TOFF_DAC=70
Figure 15. Efficiency Performance
7 Parameter Measurement Information
7.1 CSN Pin Falling Delay (tDEL
)
A voltage is applied between CSP to CSN to trip the Peak Current threshold. The difference in time between the
peak current activation and the Gate signal turning off is measured.
7.2 Off-Timer (tOFF
)
A voltage is applied to the VLEDx pin. The peak current comparator is tripped and the time between the gate
falling and rising is measured.
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8 Detailed Description
8.1 Overview
The TPS92518 is a Dual Channel Buck LED controller with SPI Interface. Quasi-hysteretic operation allows a
high control bandwidth and is ideal for Shunt FET and Matrix applications (series LED switched network). Internal
DACs control the high-side differential peak current sense threshold, the peak-to-peak ripple (off-time) and the
maximum off-time.
The high-side differential peak current sense threshold trip voltage is set via a 10:1 divider. The divider allows a
lower sense voltage for improved efficiency while still allowing a practical control voltage. The device uses a
controlled off-time (COFT) architecture to allow the converter to operate in both continuous conduction mode
(CCM) and discontinuous conduction mode (DCM) with no external control loop compensation, and provides an
inherent cycle-by-cycle current limit because of the peak current detection each cycle. Once an off-time (us·V)
target is digitally programmed, analog circuitry adjusts the off-time to maintain a constant peak-to-peak ripple.
Since the peak and ripple are fixed, regulation is maintained. The programmable off-time also controls the
switching frequency target.
The digitally controlled analog peak current sense threshold allows analog dimming of the LED current over the
full output range. The PWM dimming input allows for high-frequency PWM dimming control requiring no external
components. An internal configurable maximum off-timer allows for easy implementation of external shunt FET
dimming. Refer to shunt FET dimming information.This simple regulator contains all the features necessary to
implement a high-efficiency, versatile, digitally controlled, high-performance LED driver.
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8.2 Functional Block Diagram
SPI
CSP1 CSN1
CSN2 CSP2
VIN
VIN
R
R
R
VCC1 UV
VCC2 UV
VCC1 Output
VCC
Regulator
VCC
Regulator
VCC2 Output
VCC2
VCC1
+
+
R
VIADJ1‰
„ VIADJ2
+
+
10R
10R
SPI
Logic
EN/UV
EN/UV
20ꢀA
Boot UVerr‰
Boot UVerr‰
LEB
LEB
+
EN/UV
Power Cycle‰
ThermalWarning‰
SPI Error‰
1.24V
EN/UV
BOOT_UV
BOOT_UV
-LED2_EN‰
„ LED1_EN-
LED1_EN„
LED2_EN„
SMPL_x CNTRL„
BOOT
UVLO
BOOT
UVLO
Thermal
Shutdown
Thermal
Shutdown
Control
Logic
PWM2
PWM1
Control
Logic
VCC2_UV
CSP2_UV
VCC1_UV
CSP1_UV
-VIADJ2‰
„VIADJ1-
DAC1
DAC3
DAC5
DAC2
0.5uA
0.5uA
DAC4
DAC6
„VCOFF1-
-VCOFF2‰
+
+
12.6pF
12.6pF
„ VMaxCOFF1-
-VMaxCOFF2‰
„VMaxOFF1
-VMaxOFF2‰
Mirror
ADC
5mA
200uA
200uA
5mA
Mirror
X1
X1
X1
X1
VLED1
VLED2
VLED1
VLED2
1M
1M
+
+
DIE Temp
+
+
SMPL
Control
12.6p
12.6p
40k
40k
„VCOFF1
VCOFF2‰
150k
150k
PWM1
PWM2
GND
GND
SW1 BOOT1 GATE1
GATE2 BOOT2 SW2
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8.3 Feature Description
8.3.1 General Operation
The TPS92518 operates using a peak-current, constant off-time control as described in Figure 16. Two states
dictate the high-side FET control. The switch turns on and stays on until the programmed peak current is
reached. The peak current is controlled by monitoring the voltage across the sense resistor. When the voltage
drop is higher than the programmed threshold, the peak current is reached. The switch is then turned OFF,
which initiates an off-time period. An internal capacitor is then charged by a current source which varies in
relation to the VLEDx pin voltage. When the capacitor voltage reaches the DAC controlled threshold, the off-time
ends. The off-time capacitor resets and the main switch turns ON, starting the next ON cycle.
1
2
3
The average output current =
the peak œ ½ the peak to peak
inductor ripple
[LEDx_PKTH_DAC]
and RSENSE adjust
the peak inductor
current
The Inductance (L)
and tOFF define DI
L-PP
DIL-PP
2
IL = ILED = IL(pk)
-
AVE
VLED * tOFF
DIL-PP
=
L
[LEDx _PKTH_DAC]
IL(pk)
=
1000 * RSENSE
t
t
t
OFF
ON
Figure 16. Hysteretic Operation
8.3.1.1 Constant Off-Time vs. Constant µs×V operation
Although commonly referred to as constant off-time, the off-time does vary with the output voltage in the standard
TPS92518 configuration. This relation ensures constant peak-to-peak inductor current ripple (ΔIL-PP). Although
not common, the VLEDx pin can be set to a fixed value to generate a truly constant off-time and limit changes in
frequency, however current regulation degrades. To maintain regulation and a constant ripple over various output
voltages, the converter off-time must become shorter or longer as VLEDx pin voltage changes. This results in a
change in frequency. In this regard, the off-time register can be considered as a seconds-times-volts setting (s ×
V) for the converter. The TPS92518 Electrical Characteristics table specification for off-time specifies a certain off
time duration for a certain register value. The time is also dependent on the VLEDx pin voltage. For example, the
off-time is specified at 4 µs for a VVLEDx= 30 V and LEDx_TOFF_DAC = 255. The internal analog circuitry
operates to keep the ripple and µs·V (micro-second volt) product constant. If the LEDx voltage changes to 15 V,
the off time adjusts to 8 µs. If the LEDx voltage changes to 60 V the off time adjusts to 2 µs, and so on.
Two general cases can be examined: If the input voltage and output voltage are relatively constant, the
frequency also remains constant. If either the input voltage or the output voltage changes, the frequency
changes. For a fixed input voltage, the device operates at the maximum frequency at 50% duty cycle and the
frequency reduces as the duty cycle becomes shorter or longer. A graphical representation is shown in
Figure 17.
For a fixed output voltage (VVLEDx), the off-time stays fixed. The frequency then increases as the duty cycle
becomes smaller with an increasing VIN voltage. This relation is shown in Figure 18.
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Feature Description (continued)
0
V /2
IN
Maximum
65
Output Voltage (V)
Input Voltage (V)
Figure 18. Frequency vs. Input Voltage. Fixed LED Voltage
Figure 17. Frequency vs. LED Output Voltage. Fixed Input
Voltage
8.3.1.2 Output Equation
By maintaining the off-time proportional to the output voltage (constant µs·V), it is possible to illustrate how the
LED voltage (VLEDx) can be removed from the output current equation.
Starting with the inductor ripple derived from:
di
V = L
dt
(1)
(2)
and the equation for the off-time:
LEDx _ TOFF_DAC[7 : 0]
tOFF
=
2.136ì106 ì VLEDx
the VLEDx term is then eliminated and the peak-to-peak inductor current ripple is defined by:
LEDx _ TOFF_DAC[7 : 0]
VLEDx ì
2.136 ì106 ì VLEDx
VLEDx ì tOFF
Vdt
L
LEDx _ TOFF_DAC[7 : 0]
DIL-PP
=
=
=
=
L ì 2.136ì106
L
L
(3)
(4)
The final equation for the average LED current is then:
»
…
ÿ
Ÿ
⁄
LEDx _PKTH_DAC[7 :0]
LEDx _ TOFF_DAC[7 :0]
»
…
ÿ
ILED
=
-
Ÿ
2ìL ì2.136ì106
1000ìRSENSE
⁄
Because the control method relies on thresholds to control the main switch, offsets and delays must also be
considered when examining the output accuracy. The ILED equation can be expanded to include these error
sources as shown in Equation 5. ILED equations include several passive components, so it is important to
consider the tolerance of each component. In this case the components are the main inductor and the sense
resistor. The VCSTx-OFFSET parameter is the variation in the VCSTx threshold between the typical and maximum or
minimum values as defined in the Electrical Characteristics. The peak current threshold delay (tDEL) and off timer
trip point delay (tD-OFF) specifications are also shown in the Electrical Characteristics.
≈
∆
∆
∆
’
÷
÷
÷
»
…
ÿ
LEDx _ TOFF _DAC[7 : 0]
2.136 ì106 ì VLEDx
2ìL
»
…
ÿ
≈
∆
∆
∆
’
÷
÷
÷
LEDx _PKTH_DAC[7 : 0]
»
…
ÿ
ê tD-OFF Ÿ ì VLEDx
ê VCSTx-OFFSET
Ÿ
Ÿ
(VIN - VLEDx)ì tDEL
1000
⁄
⁄
⁄
ILED
=
ê
-
RSENSE
L
∆
∆
÷
÷
∆
÷
«
◊
«
◊
(5)
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Feature Description (continued)
8.3.1.3 OFF Timer
The converter Off-time is controlled via the LEDx_TOFF_DAC[7:0] register and VLEDx pin. The VLEDx pin
voltage is converted to a current that charges an internal capacitor to a voltage set by the LEDx_TOFF_DAC
creating a delay. Details of this circuit are shown in the Functional Block Diagram. Deriving the off-time from the
output voltage creates a ramp representing the inductor current.
When the TPS92518 is first enabled (All UVLO levels are cleared) both timer capacitor pull-downs are disabled
allowing voltage to increase on the internal timer capacitors. When either capacitor reaches the matching DAC
control voltage, the high-side FET is turned on, starting a switching cycle. The maximum off-time timer is always
dominant at start-up when the output is completely discharged or when shunt FET dimming and the shunt FET
shunts the output for the required period.
TPS92518x
+
GATE
LEDx_MAXOFF_DAC[7:0]
DAC
END OFF TIME,
TURN ON GATE
OFF
Time
VLED1
Circuit
+
GATE
LEDx_TOFF_DAC[7:0]
DAC
Figure 19. TPS92518 Simplified Internal Off-Timers Detail
8.3.1.3.1 Off-time and Maximum Off-time Calculations
Circuitry in the TPS92518 adjusts the off-time to ensure a constant peak-to-peak ripple. The off-time follows the
relationship defined by Equation 6
LEDx _ TOFF_DAC[7 : 0]
tOFF
=
2.136ì106 ì VLEDx
(6)
Or
LEDx _ TOFF_DAC[7 : 0]
tOFF ì VLEDx =
2.136ì106
(7)
The maximum off-time circuit operates from its own independent current source that is not related to the VLEDx
pin voltage. The equation for the maximum off-time is defined by Equation 8
Maximum Off-time(s) = LEDx _MAXOFF_DAC[7 : 0] ì 251ì10-9
(8)
8.3.2 Important System Considerations: Off-Timer and Maximum Peak Threshold Values
To allow full application flexibility, controls have not been implemented to limit values written to any SPI register.
The system firmware must ensure control of all register values, but these two in particular must have safeguards
in place.
Two potential application architectures that may allow a register modification after system engineering is
complete are:
•
A system has been engineered to allow firmware updates at a later time creating a situation where the Peak
Current Threshold [LEDx_PKTH_DAC] value may be modified. The system LEDs can not support any higher
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Feature Description (continued)
than the designed current.
•
A system has been engineered to allow fine tuning of the register values during a calibration step in
manufacturing.
Section Peak Current Sense Comparator and Off-Time Thresholds
-
LEDx_TOFF_DAC and
LEDx_MAXOFF_DAC discuss a few of many system approaches to ensure values remain correct.
8.3.2.1 Peak Current Sense Comparator
A comparator, two resistors and a current source create a peak current detection circuit block. See the
Functional Block Diagram for details. A current source controlled by LEDx _PKTH_DAC[7:0] draws a current
across a resistor in series with the comparator, forcing a proportional offset. The resistor in the current source
(10 R) and in series with the comparator ( R ) are sized with a 10:1 ratio. This ratio allows for a practical voltage
range of operation for the IADJ pin and maintains a small current sense voltage for low losses and less impact
on efficiency. The ON cycle begins with the offset in place via IADJ across the resistor R at the VIN pin. When
the current rises enough to create a voltage across the sense resistor to match the offset, the comparator trips.
The end of the on-time period starts an off-time cycle.
Trace resistance can have an impact on accuracy, so care must be used when routing the traces to CSPx and
CSNx from the sense resistor. Because the sense resistor value is typically in milli-ohms, use a short kelvin
connection if possible.
8.3.2.2 Peak Current Threshold - LEDx _PKTH_DAC
•
Always use a current sense resistor sized so the full scale current occurs at or close to the maximum value of
255. This is also a good practice for accuracy.
•
Impose a limit in firmware. Monitor the LEDxPKTH_DAC variable before each write and ensure a maximum
value is maintained.
8.3.2.3 Off-Time Thresholds - LEDx_TOFF_DAC and LEDx_MAXOFF_DAC
•
Do not write '0' to the LEDx_TOFF_DAC or LEDx_MAXOFF_DAC registers. Writing a '0' to the
LEDx_TOFF_DAC or LEDx_MAXOFF_DAC registers is the equivalent to: do not turn the FET off. Damage
occurs to the device when a value of 0 is written to this register.
•
Do not write an off-time value that causes the TPS92518 to operate beyond the maximum frequency possible
for the conversion voltage ranges. For example: for a given application switching frequency and VIN to VLED
conversion, there is a required duty cycle. If the duty cycle requirement is shorter than the TPS92518
minimum on-time ( tLEB ) current can not regulate. If the Off-time is made sufficiently short such that the
inductor current is not able to reset given the V-s reached during the leading edge blanking time, the inductor
current continues to increase until the inductor is saturated and the system may be damaged. The maximum
frequency can be estimated, starting with Equation 9
VLED tON
=
= tON x fSW
V
T
IN
(9)
Then the maximum frequency can be derived using the minimum on-time (tLEB leading edge blanking)
VLED-MIN tLEB
=
= tLEB x fSW-MAX
V
TMIN
IN-MAX
(10)
Using an example condition: VIN= 65 V, VLED= 6 V, tLEB= 250 ns, ΔIL-PP= 250 mA, we can find the maximum
switching frequency and an Off-time minimum value.
VLED-MIN
6V
=
= 250ns x fSW-MAX then fSW-MAX = 369 kHz
V
65V
IN-MAX
(11)
DIL-PP x L
0.25 x 100mH
tOFF-MIN
=
=
= 4.17ms then
VLED
6
LEDx _ TOFF_DAC[7 : 0]MIN = tOFF-MIN x VLED x 2.136x106 = 53
(12)
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Feature Description (continued)
The system controller must be programmed with a minimum LEDx_TOFF_DAC value of 55 allowing for some
margin above the computed value of 53. (a smaller value = higher switching frequency) Note this is the correct
value for this example. Each application is different. All register values, minimums and maximums must be
considered for each application separately.
8.3.3 Shunt FET or Matrix dimming: Maximum Off-timer Calculation
Shunt FET or Matrix dimming is typically used where precise control of the LED current is required. For the LED
current and light output to most accurately match the control signal, the current source supplying the LEDs must
be as close to ideal as possible. With the TPS92518 hysteretic control and maximum off-time setting, the LED
current can approach ideal. Two waveforms show the result during shunt FET dimming with and without
optimized maximum off-time control. The result with maximum off-time control is superior and approaches an
ideal current source.
CH4 (Green) :
Inductor Current
(200 mA per
division)
CH2 (Cyan) :
VVLEDx (10 V per
division)
CH1 (Blue) : Shunt
FET Control Signal
CH4 (Green) :
Inductor Current
(200 mA per
division)
CH2 (Cyan) :
VVLEDx (10 V per
division)
CH1 (Blue) : Shunt
FET Control Signal
Figure 21. Shunt FET Dimming: Optimized Maximum Off-
time.
Figure 20. Shunt FET Dimming: Non-Optimized Maximum
Off-time
To ensure the correct maximum off-time when shunt dimming it is necessary to calculate the off-time required
when the output is in the shunted condition. The following procedure may be used:
1. Estimate or measure the output voltage during the shunted condition.
VSHUNT = FET
ìILED
RDS-ONMAX
(13)
(14)
Or for the Matrix approach:
VSHUNT = RALL(on) ìILED
2. Compute the off-time required (tOFF-Shunt) when the output is shunted.
DILpk-pk ìL
tOFF-Shunt
=
VSHUNT + (0.7)
(15)
(16)
3. Compute the Maximum Off-time Register Value.
Maximum Off-time(s)
LEDx _MAXOFF_DAC[7 :0] =
251ì10-9
8.3.3.1 Output Ringing and TPS92518 Protection
During shunt dimming, ringing may occur at the channel output due to PCB and device parasitic capacitances
and inductances. This should be checked as part of the design process. If the ringing approaches the absolute
maximum of any pin, a clamping diode must be added to the design. Connect the diode anode to the output at
VLEDx and the cathode to the input voltage. This protection must also be used if the LED load is ever to be
connected or removed while the output is enabled.
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Feature Description (continued)
8.3.3.2 Live Peak and Off-Time Threshold Changes
All TPS92518 thresholds may be changed at any time. Once the SPI transaction completes, the change is seen
in operation in ~100ns.
8.3.4 VIN and the VCC Internal Regulators
The device incorporates a linear regulator for each channel to generate the 7.5-V (typ) VCC voltage. Both VCC
rails are powered from the VIN pin. VIN may be connected to the input of either channel or to a separate external
supply. The VCC output voltages are internally monitored to implement undervoltage lockout (UVLO) protection
for the respective channel. For example, if UVLO is reached on CH1, CH2 remains active. The VCC
undervoltage lockout thresholds are fixed and cannot be adjusted.
The device has been designed to supply current for the device operation as well as additional power for external
circuitry. If a 7.5-V rail is required in an application, the device can allow up to 500 μA to be drawn in addition to
the device load. A capacitance of 1 μF or ≥ 10× the BOOT capacitance to a maximum of 10 μF is recommended.
The device requires adequate input decoupling in order to lower ΔVIN-PP ripple for the best VCC supply voltage
performance. ΔVIN-PP must not exceed 10% of the input voltage or 3V, whichever is lower.
8.3.5 Output Enable Control Logic
Several safeguards and control states must be satisfied before switching can begin as shown in Figure 22. VCC,
BOOT and the CSP input must not be in under voltage lock-out. The device must not be in thermal shut-down
and the EN/UV pin must be high. The PWM pin for the channel must also be high. It is not possible to override
the PWM pin logic via the SPI interface. If PWM dimming is not required, tie the pins to VCC.
BOOT
TPS92518x
VCCx UVLO
BOOT_UV_CHx
CSPx UVLO
Thermal Shut Down
EN/UV1
PWM
One Shot
Gate
Driver
S
R
Q
Q
GATEx
SWx
OFF Timer
Peak Detect
CHx Go
PWMx
LEDxEN Register
EN/UV2
(SPI Bypass)
Figure 22. TPS92518 Output Enable Control
8.3.5.1 EN/UV2 - SPI Control Bypass
Note that the TPS92518 does allow a means to enable the part without SPI communication. By applying a
voltage above the second threshold level, EN/UV2 (23.6 V typical), the state of the LEDxEN register is bypassed.
This allows a TPS92518 to be powered and operated using the default register values (see Registers. A quick
summary is that peak and off-time thresholds are set to 127 out of 255) without SPI communication. All other
required operation points must still be satisfied as shown in Figure 22.
This could be useful in a manufacturing flow or during system troubleshooting. The logic path is highlighted again
in Figure 23.
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Feature Description (continued)
LEDxEN Register
EN/UV2
(SPI Bypass)
Figure 23. Output Enable Control Logic
8.3.6 BOOT Capacitor and BOOT UVLO
The BOOT capacitor provides the power for the high-side gate drive circuitry. The capacitor is charged each
cycle from VCC during the off-time phase of the switching cycle. During the off-time, the free-wheeling diode
conducts, pulling the switchnode (SW) low and providing a conduction path to charge the capacitor. During the
on-time, the current required to charge the high-side FET gate and power the driver are supplied by the
capacitor.
A minimum boot capacitor can be calculated by considering: the MOSFET Qg, the driver quiescent current, and
the desired nominal maximum on-time. Other factors include: the BOOT diode Vf, the minimum BOOT operation
voltage, and the level of the switchnode (SWx) during the off-time. A rough estimate can be calculated using
Equation 17: or just use 0.1µF.
Qg + (IQ x TON)
CBOOT
í
VCC - Vf(bd) - VBOOT-UVLO(MAX) - VSW(OFF)
(17)
The variables are defined by:
Table 1. CBOOT Variables
Variable
Description
Qg
High-side FET total gate charge (Qg) as shown in the FET datasheet.
VCC
7.5 V
VSW(off)
VBOOT-UVLO(MAX)
IBOOT-Q
tON
The switchnode voltage when the high-side FET is off. Use 0 V.
5.2 V
200 µA
Estimate your worst case on-time or use 500 µs
Forward drop of the boot diode
Vf(bd)
A typical solution calculates a minimum CBOOT of approximately 60 nF, justifying the 100 nF selection.
If conditions are created which cause the boot capacitor to become depleted (see Drop-out Operation) and reach
VBOOT-UVLO, switching is disabled until VBOOT increases by VBOOT-UVLO-HYST
.
8.3.7 Drop-out Operation
If the input or output voltage change such that they become close to the same value, a condition known as drop-
out is created. During drop-out conditions the output LED current may fall out of regulation. If the input reaches
the target output voltage or below, the LED current can drop to zero. There are two stages of drop-out when
operating with a hysteretic device like the TPS92518. The two stages are described in Early Drop-Out (Boot
Capacitor Voltage >> VBOOT-UVLO) and Full Drop-Out (Boot Capacitor Voltage reaching VBOOT-UVLO) .
8.3.7.1 Early Drop-Out (Boot Capacitor Voltage >> VBOOT-UVLO
)
the first effects of drop-out can be seen when the input voltage approaches a few volts above the output voltage.
Unless there is sufficient output capacitance, the change in the LED voltage during the ramp up of the inductor
and output current can cause a non-linearity in the ramp.
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( 1 )
( 2 )
(VIN - VLED)* tOFF
(VIN - DVLED)* tOFF
DIL-PP
=
DIL-PP =
L
L
ILED
A
VLED
t
t
t
t
t
OFF
ON
OFF
ON
Figure 24. Inductor on-time Current Non-linearity
In case (1) shown in , VIN-VLED is sufficiently large that variations in VLED are not relevant and/or not present
because of sufficient output capacitance.
In case (2), VIN and VLED are closer in value making the difference lower and more easily affected by variations in
VLED. ΔVLED is the total variation in the voltage across the inductor and includes the ILED x RL-DCR voltage drop
which also changes with IL and impacts the inductor current linearity. The combination of factors leads to an
inductor current on-time non-linearity which increases the average value of the inductor current, and hence the
LED current. This means the first affect of approaching drop-out is always an increase in LED current.
It is important to note that the output current is always limited to the peak limit set by the internal programmed
reference and the sense resistor. (The peak current threshold) This means a design having a smaller overall
inductor current ripple (smaller ΔIL-PP) will have less error when a drop-out condition occurs.
8.3.7.2 Full Drop-Out (Boot Capacitor Voltage reaching VBOOT-UVLO
)
If VIN and VLED are sufficiently close the duty cycle demand increases. Because of the TPS92518 hysteretic
control method, the high-side FET attempts to remain ON until the programmed peak current is reached.
Keeping the high-side FET ON requires energy from the BOOT capacitor which depletes the BOOT capacitor
voltage. If the high-side FET is ON for sufficient duration, the BOOT capacitor voltage eventually reaches VBOOT-
level at which point the high-side FET is turned off. This allows for long on-times and duty cycles >99.5%,
UVLO
since the time the high-side FET can remain ON is long (>1 ms) compared to the time required the recharge the
BOOT capacitor (approximately 100 ns). The typical maximum on-time can be estimated by Equation 18
CBOOT x (VCC - VBOOT-UVLO
)
C dv
i
0.1mF x (7.5 - 4.6)
tON-MAX
=
=
ö
ö 2.9ms
(TYP)
IBOOT-Q
100mA
(18)
8.3.7.3 Minimum BOOT Voltage and FET Control
The minimum VBOOT-UVLO is also the minimum voltage available to drive the external FET. Check the FET Output
Characteristics (ID versus VDS) at the minimum BOOT voltage and ensure the FET is sufficiently enhanced under
this condition. If the turn-on is marginal, the FET may operate in the linear region causing increased losses and
possibly damage the device.
8.3.7.4 BOOT Controlled internal Pull-Down
Each time VBOOT ≤ VBOOT-UVLO an internal pull-down (IPD BOOTx = 5 mA typical) from the SWx pin to ground is
enabled. This behavior occurs during drop-out conditions such as Full Drop-Out (Boot Capacitor Voltage
reaching VBOOT-UVLO) . This behavior also occurs at Start-Up if the output is pre-charged.
If the TPS92518 application uses an output capacitor and the output is disabled and re-enabled before the output
voltage reduces (or is otherwise pre-charged) a condition can be created where the SWx pin voltage is not low
enough for the BOOT capacitor to charge. (VSWx << VCC) BOOT-UV is then activated and the internal pull-down
circuitry enabled. The pull-down circuitry reduces the time required to deplete the output voltage to allow the
BOOT capacitor to be charged. Note that the internal pull-down circuitry can not act as a synchronous FET.
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8.3.8 Analog and PWM Dimming
8.3.8.1 Dimming Methods
The TPS92518 has been designed to support three dimming methods. Analog, PWM and Shunt-FET or Matrix
(TPS92661/TPS92662 device family) dimming. Analog dimming is still accomplished via the SPI interface
through adjustment of the LEDx_PKTH_DAC register. PWM dimming is accomplished by using the PWMx pin.
Shunt-FET or Matrix Dimming is optimized by using the LEDx_MAXOFF_DAC register. One or more dimming
methods may also be combined to obtain extreme contrast ratios. To obtain an ultra-fine adjustment, the
LEDxTOFF_DAC register may be also adjusted allowing average output current modifications in the range of
100 µA per LSB.
8.3.8.2 PWMx Pin Operation
PWM dimming can be used to adjust the output brightness by changing the applied PWM duty cycle to a
channels’ corresponding PWM pin. Each channel can be controlled with an independent frequency and duty
cycle.
When the PWM pin signal is < 0.8 V, the corresponding channel's gate logic is disabled. When PWM rises above
1.6 V the rising edge sets the gate drive latch and turns on the FET. If PWM dimming is not required, PWMx be
tied to VCC.
Treat the PWM pin as a digital input. Avoid slow transitions of the pin voltage level around the logic thresholds.
Ensure the signal edge rate is adequate (<100ns) when measured at the device PWMx pin to prevent false level
interpretations. If the edge is too slow, a small capacitor may be required. If the PWM pin edge rate is too slow
and is not adequately decoupled, the TPS92518 PWM pin logic may interpret one transition as multiple ON-OFF
transitions. This can cause the output current to ratchet beyond the desired set-point and possibly cause the
system to be damaged.
BOOT
TPS92518x
One Shot
PWMx
Gate
Driver
S
R
Q
Q
GATEx
SWx
OFF Timer
Peak Detect
CHx Go
Figure 25. Gate Control Logic
8.3.8.3 PWM Dimming - Current Rise Performance
A unique feature of the TPS92518 hysteretic control allows the first switching pulse of a PWM dimming on-time
to rise completely to the correct peak current in one switching cycle. An example is shown in Figure 26. When
the rising edge of the PWM signal is seen by the PWMx pin the main FET is turned on. The FET remains ON
until the programmed peak current threshold is reached. Once reached, switching continues until the PWMx pin
voltage goes low. The TPS92518 can also operate when using pulse widths that are sufficiently narrow that the
programmed peak is not reached. The on-time is terminated at the end of the PWM pulse and another on-time
initiated when the PWMx pin goes high again.
!~
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CH4: Inductor Current CH3: PWMx Pin CH2: SWNx
CH4: Inductor Current CH3: PWMx Pin CH2: SWNx
Figure 27. PWM Dimming, Two Periods
Figure 26. PWM Dimming, Pulse after Rising Edge
8.3.8.4 PWM and Analog Dimming - Linearity Limitations and Buck Converters
8.3.8.4.1 PWM:
A linearity limitation occurs at very small PWM duty cycles; the PWM dimming on-time becomes short enough
that it contains only one or a few switching cycles. If the PWMx pulse falls during an off-time (see Figure 28), the
pulse length is not able to change because the switch is already off. This can lead to a small 'stair-case' dimming
curve in this region as the duty cycle affects the average current during on-times and then not during off-times.
This situation can be improved by increasing the switching frequency. This limitation is common to all Buck
converters during very small PWM dimming duty cycles.
Shunt FET PWM dimming avoids this issue as the average current is affected during switching ON and OFF
times. Shunt FET PWM dimming can out-perform PWM dimming, but is more complicated to implement.
IL
PWM
t
Figure 28. PWM Dimming Limitation
8.3.8.4.2 ANALOG:
Another impact on linearity can occur when analog dimming (LEDx_PKTH_DAC threshold adjustment) and the
inductor current becomes discontinuous. Discontinuous conduction mode (DCM) occurs when the inductor
current reaches 0 A each off-time. When the device enters DCM, the output current is no longer the peak current
minus half the ripple current (as shown in Figure 16) and is no longer a linear relationship between the
LEDx_PKTH_DAC value and the average output current. The linear range can be extended by lowering the
ripple, ΔIL-PP to extend the natural linear region of operation.
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CCM
Peak TH1
IL
DCM
Peak TH2
t
Figure 29. Analog Dimming Limitation
Another approach can be used by first analyzing the system operation. The point at which DCM is entered can
be calculated as well as the average current value when in DCM. The micro-controller writing the
LEDx_PKTH_DAC values can simply write alternate values in the DCM area to ensure net linear response to the
LED average current. See DCM Current Calculation for information on calculating the average current when in
DCM.
8.3.8.5 DCM Current Calculation
The converter is considered to be operating in DCM (Discontinuous conduction mode) when the peak current is
less than the peak-to-peak inductor current ripple. (IL(pk) < ΔIL-PP). Equations Equation 20 through Equation 25
define the calculation described by Equation 19. Note that the value of the LED voltage is different when
operating in DCM.
Starting with the basic equation for a buck converter in DCM:
D1 x T
ILED
=
x D + D
x (VIN - VLEDx)
(
)
1
2
DCM
2 x L
(19)
followed by: (η is the estimated converter efficiency):
1
D1 =
»
…
…
ÿ
Ÿ
tOFF x ((V x
h
) - VLEDx)
IN
1+
L x ILx-peak
Ÿ
⁄
(20)
(21)
(22)
ILx-peak x L
D2 =
TDCM x VLEDx
Where T defines the switching converter period.
TDCM = tON-DCM + tOFF
ILx-peak x L
tON-DCM
=
VIN - VLEDx
(23)
(24)
(25)
LEDx _ TOFF_DAC[7 : 0]
tOFF
=
2.136ì106 ì VLEDx
LEDx _PKTH_DAC[7 : 0]
ILx-peak
=
1000ìRSENSE
See Equation 4 for the CCM (continuous current mode) equation.
8.3.8.6 Current Sharing
The TPS92518 can be configured to operate as a Two Channel, Single Output converter by configuring each
channel identically and connecting the outputs together. Figure 30 illustrates the current sharing capability with
each channel handling approximately the equal share of the output current load. Statistics are enabled and the
average inductor current of each channel is also shown. The total output current for this configuration is 438 mA.
Note that both channels must be enabled at the same time to allow charging of the boot capacitors. When a
channel is paralleled, it may not be enabled after the first channel is enabled.
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TPS92518 Channel 1 and 2 Outputs Connected in Parallel.
CH4 (Green) : Inductor Current (100 mA per division)
CH2 (Cyan) : Inductor Current (100 mA per division)
CH1 (Blue) : SW1 Node (50 V per division)
Figure 30. TPS92518 Channels Connected to Current Share
8.3.9 VIN and CSPx Pin Configuration
The TPS92518 has been designed to support single or dual input voltage sources. The VIN pin connection is
also flexible and may be connected to the input supply of either channel or from a third independent channel.
The Electrical Characteristics table defines CSPUVLO as the minimum voltage required by a channel to continue
operating. This limit is set regardless of the VIN and VCCx voltages. The VIN pin does not have an under voltage
lock-out level, but must support the VCCx voltage for the channel. The minimum VIN pin voltage is limited to 6.5
V because two items depend on the voltage level for operation that have their own UVLO (under voltage lock-
out) levels: VCCx and BOOTx. The 6.5-V level is derived from the maximum VCCx_UVLO level with some added
margin. Alternately the maximum VBOOT-UVLO level may be used. If we consider this level and add the drop of the
boot diode, we obtain the same value and with some margin obtain the same VIN pin minimum level of 6.5 V.
8.3.10 Enable and Undervoltage Lock-out Configuration
If drop-out operation is not desired, configure a resistor divider to disable switching of both channels at the
desired input voltage.
The value of resistors R2 and R3 establish the undervoltage lockout level as shown in Figure 31. Include a small
level of capacitance (approximately 0.1 μF) at the UVLO pin for noise immunity. If the application does not
require drop-out operation (operation when VVIN approximates VVLEDx) program a UVLO level that allows no
switching to occur until there is adequate input voltage available.
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TPS92518x
VIN
R2
IEN/UV-HYST1
+
EN/UV
R3
4kΩ
950kΩ
1.24V
Figure 31. EN/UV Programming Resistors
Select the desired amount of voltage hysteresis and the desired turn-ON threshold (VIN-RISE_THRESHOLD). Because
of the small amount of fixed-voltage hysteresis and fixed-hysteresis current, some combinations of turn-ON and
turn-OFF thresholds are not possible. If the calculation results in values that are zero or negative, the
combinations selected are not possible. After selecting a turn-ON point and desired amount of voltage hysteresis
(VHYST) use Equation 26 and Equation 27 to calculate R3 and R2.
0.1x V
- 0.124
»
…
ÿ
IN-RISE_ THRESHOLD
VHYST
-
- 0.1
Ÿ
⁄
1.24
18 x 10-6
R2 =
R3 =
(26)
(27)
1.24 (R2)
IN-RISE_ THRESHOLD -1.24
V
8.3.11 Voltage Sampling and DAC Operation
The TPS92518 integrates an ADC (analog to digital converter) and 6 DACs (digital to analog converters). The
single ADC is multiplexed to provide the VLEDx pin voltages (starting with: LED1 Voltage) and the TPS92518 die
temperature (Die Temperature Reading). A simplified diagram is shown in Figure 32.
-LED2_PKTH_DAC‰
-LED2_TOFF_DAC‰
„LED1_PKTH_DAC-
„LED1_TOFF_DAC-
DAC1
DAC3
DAC5
DAC2
DAC4
DAC6
„LED1_MAXOFF_DAC-
-LED2_MAXOFF_DAC‰
-ADC OUTPUT‰
ADC
Result
Routing
‰
-PWMx‰
MUX
VLED1
VLED2
DIE Temp
CONTROL Register (0h)
Figure 32. TPS92518 Internal Digital Blocks
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8.3.11.1 ADC Control and LED Voltage Updating
Each of the analog outputs are controlled via their own individual DAC. The DAC's operate asynchronously and
changes to controlling register values are updated immediately (~1 µs).
The ADC (analog to digital converter) sampling intervals are asynchronous to the incoming PWM1 and PWM2
signals. The TPS92518 logic determines which register(s) to update based on the state of the corresponding
PWM signal at the time of ADC sampling. There are three LED voltage registers per channel:
•
•
•
LEDx_MOST_RECENT
LEDx_LAST_ON
LEDx_LAST_OFF
The LEDx_MOST_RECENT registers are updated periodically every time the ADC has a new sample. Sampling
a single input increases the sampling frequency. For example: an ADC sample and conversion requires ~100us.
If one item is selected it is sampled at roughly 10 kHz. If all three inputs are selected each is sampled at ~3.3
kHz.
The LEDx_LAST_ON registers are only updated when the corresponding PWM input has toggled from high to
low, and the LEDx_LAST_OFF registers are only updated when the corresponding PWM input has toggled from
low to high. This allows the last sample before the falling edge of PWM to be saved as the LAST_ON value, and
the last sample before the rising edge of PWM to be saved as the LAST_OFF value ensuring the most consistent
LED voltage reading.
8.3.12 Device Functional Modes
8.3.12.1 Analog Dimming
Analog dimming refers to the method of controlling the peak inductor current as the method to set the continuous
average output current. Analog dimming is controlled digitally via the SPI interface. The register control value is
converted via a digital to analog converter and the peak inductor current is compared to this analog voltage level.
The level can be updated at any time during operation.
8.3.12.2 PWM Dimming
PWM Dimming is accomplished via a channel's corresponding PWM pin. A 1.6-V (typical) rising threshold and a
0.8-V (typical) falling threshold are required.
8.4 Serial Interface
The 4-wire control interface is compatible with the Serial Peripheral Interface (SPI) bus. The control bus consists
of four signals: SSN, SCK, MOSI, and MISO. The SSN, SCK, and MOSI pins are TTL inputs into the TPS92518
while the MISO pin is an open-drain output. The SPI bus can be configured for both star-connect and daisy chain
hardware connections.
A bus transaction is initiated by a MCU on a falling edge of SSN. While SSN is low, the input data present on the
MOSI pin is sampled on the rising edge of SCK, MSbit first. The output data is asserted on the MISO pin at the
falling edge of SCK. The figure below shows the data transition and sampling edges of SCK.
A valid transfer requires a non-zero integer multiple of 16 SCK cycles (i.e., 16, 32, 48, etc.). If SSN is pulsed low
and no SCK pulses are issued before SSN rises, a SPI error is reported. Similarly, if SSN is raised before the
16th rising edge of SCK, the transfer is aborted and a SPI error is reported. If SSN is held low after the 16th
falling edge of SCK and additional SCK edges occur, the data continues to flow through the TPS92518 shift
register and out the MISO pin. When SSN transitions from low-to-high, the internal digital block decodes the most
recent 16 bits that were received prior to the SSN rising edge.
SSN must transition high only after a multiple of 16 SCK cycles for a transaction to be valid and not set the SPI
error bit. In the case of a write transaction, the TPS92518 logic performs the requested operation when SSN
transitions high. In the case of a read transaction, the read data is transferred during the next frame, regardless
of whether a SPI error has occurred.
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Serial Interface (continued)
SSN
SCK
1
2
3
4
15
16
D15
D15
D14
D14
D13
D13
D12
D12
D1
D0
MOSI
MISO
D1
D0
Figure 33. SPI Data Format
The data bit on MOSI is shifted into an internal 16-bit shift register (MSbit first) while data is simultaneously
shifted out the MISO pin. While SSN is high (bus idle), MISO is tri-stated by the open-drain driver. While SSN is
low, MISO is driven according to the 16-bit data pattern being shifted out based on the prior received command.
At the falling edge of SSN to begin a new transaction, MISO is driven to the MSbit of the outbound data, and is
updated on each subsequent falling edge of SCK.
NOTE
The first MISO transition happens on the first falling edge AFTER the first rising edge of
SCK.
8.4.1 Command Frame
There is only one defined format for frames coming in on MOSI from the master. These are called Command
frames. A Command frame can be either a read command or a write command.
A Command frame consists of a CMD bit, five bits of ADDRESS, a PARITY bit (odd parity), and nine bits of
DATA. The format of the Command frame is shown in Figure 34. The bit sequence is as follows:
1. The COMMAND bit (CMD). CMD = 1 means the transfer is a write command; CMD = 0 means it is a read
command.
2. The five-bit read or write ADDRESS (A4..A0).
3. The PARITY bit (PAR). This bit is set by the following equation: PARITY = XNOR(CMD, A4..A0, D8..D0).
4. Nine bits of read or write DATA (D8..D0). For a read, all data bits must be 0.
Both the Read Command and the Write Command follow the Command frame format as shown in Figure 34.
SSN
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
C
M
D
P
A
R
A
4
A
3
A
2
A
1
A
0
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
MOSI
Figure 34. Command Frame Format
8.4.2 Response Frame Formats
There are three possible response frame formats: Read Response, Write Response and Write Error/POR. These
formats are further described below.
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Serial Interface (continued)
8.4.2.1 Read Response Frame Format
The Read Response frame has the following format. The read response frame contains the state of the four fault
bits. A special command is not required to poll the status of the bits, they are returned in every read response.!~
1. The SPI Error bit (SPE).
2. Two reserved bits (always 1).
3. The POWER CYCLED bit PC).
4. The LED2 BOOTUV ERROR bit (UV2).
5. The LED1 BOOTUV ERROR bit “UV1).
6. The THERMAL WARNING bit (TW).
7. Nine bits of DATA (D8..D0).
This is shown in Figure 35 below. This frame is sent out by the TPS92518 following a read command.
SSN
SCK
1
2
1
3
1
4
5
6
7
8
9
10 11 12 13 14 15 16
S
P
E
U
V
2
U
V
1
P
C
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
T
W
MISO
Figure 35. Read Response Frame Format
8.4.2.2 Write Response Frame Format
The Write Response frame has the following format:
1. The SPI Error bit (SPE).
2. The COMMAND bit (CMD).
3. Five bits of ADDRESS (A4..A0).
4. Nine bits of DATA (D8..D0).
This is shown in Figure 36. This frame is sent out following a write command if the previously received frame
was a write command and no SPI Error occurred during that frame.
SSN
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
S
P
E
C
M
D
A
4
A
3
A
2
A
1
A
0
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
MISO
Figure 36. Write Response Frame Format
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Serial Interface (continued)
8.4.2.3 Write Error/POR Frame Format
The Write Error/POR frame is simply a ‘1’ in the MSB, followed by all zeroes (see Figure 37) This frame is sent
out by the TPS92518 Internal digital block during the first SPI transfer following power-on reset, or following a
write command with a SPI Error.
SSN
SCK
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MISO
Figure 37. Write Error/POR
8.4.2.4 SPI Error
The TPS92518 records a SPI Error if any of the following conditions occur:
• The SPI command has a non-integer multiple of 16 SCK pulses.
• Any of the DATA bits during a read command are non-zero.
• There is a parity error in the previously received command.
If any of these conditions are true, the TPS92518 sets the SPI_ERROR bit in the Status Register. This is
reported by setting the SPE (MSbit) in the next response frame. A write command with a SPI Error (not 16-bit
aligned or bad parity) does NOT write to the register being addressed. The bad write is ignored and discarded.
The TPS92518 attempts to respond to read requests regardless of SPI Error status since there is no danger to
the system.
The SPI_ERROR bit can be cleared by reading the STATUS register.
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8.5 Registers
Table 2 lists the memory-mapped registers. All register offset addresses not listed in Table 2 are considered as
reserved locations and the register contents should not be modified.
Table 2. Registers
Address
0h
Acronym
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
CONTROL
Control Register
1h
STATUS
Status Register
2h
THERM_WARN_LMT
LED1_PKTH_DAC
LED2_PKTH_DAC
LED1_TOFF_DAC
LED2_TOFF_DAC
LED1_MAXOFF_DAC
LED2_MAXOFF_DAC
VTHERM
Thermal Warning Limit Register
LED1 Peak Threshold DAC Register
LED2 Peak Threshold DAC Register
LED1 Off Time DAC Register
LED2 Off Time DAC Register
LED1 Maximum Off Time DAC Register
LED2 Maximum Off Time DAC Register
VTHERM Register
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
LED1_MOST_RECENT
LED1_LAST_ON
LED1_LAST_OFF
LED2_MOST_RECENT
LED2_LAST_ON
LED2_LAST_OFF
RESET
LED1 Most Recent Register
LED1 Last ADC On Register
LED1 Last ADC Off Register
LED2 Most Recent ADC Register
LED2 Last On ADC Register
LED2 Last Off ADC Register
Reset Register
10h
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8.5.1 CONTROL Register (Address = 00h) [reset = 00h]
CONTROL is shown in Figure 38 and described in Table 3.
Return to Summary Table.
Figure 38. CONTROL Register
8
7
6
5
4
3
2
1
0
RESERVED
R-0h
THERM
SMPL
EN
VLED2
SMPL
EN
VLED1
SMPL
EN
LED2
EN
LED1
EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
(1) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 3. CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
8-5
RESERVED
R
0
Reserved
4
3
2
1
0
THERM_SMPL_EN
VLED2_SMPL_EN
VLED1_SMPL_EN
LED2_EN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Thermal sample enable
0 = Disable sampling
1 = Enable sampling
VLED2 sample enable
0 = Disable sampling
1 = Enable sampling
VLED1 sample enable
0 = Disable sampling
1 = Enable sampling
LED2 enable. This bit controls the operation state of channel 2.
0 = Disable LED channel 2
1 = Enable LED channel 2
LED1_EN
LED1 enable. This bit controls the operation state of channel 1.
0 = Disable LED channel 1
1 = Enable LED channel 1
xSMPL_EN: The TPS92518 Analog to Digital Converter (ADC) input is multiplexed between 3 inputs: the
thermal sensor and the two output voltages. Each input is sampled consecutively. Sampling a single input
increases the sampling frequency. For example: an ADC sample and conversion requires ~100us. If one
item is selected it is sampled at roughly 10 kHz. If all three inputs are selected each is sampled at ~3.3 kHz.
LEDx_EN: The TPS92518 PWMx pin AND the corresponding LEDxEN bit must be high for a channel to be
enabled. If not using the external PWM input, tie the pin to VCC. The use of the LEDxEN register also
enables the corresponding channel SWx pin internal pull-down to ensure no current flows to the LED load. A
sample of the timing and waveforms around a SPI enable write are shown in Figure 39.
LEDxEN control may be bypassed using an analog activated override via the EN/UV pin. By applying a
voltage >VEN/UV2 (23.6 V Typical) the contents of LEDxEN are ignored and the TPS92518 operates without
SPI communication using the default register values. This is discussed in EN/UV2 - SPI Control Bypass
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Figure 39. SPI Enable Write Waveform Example
8.5.2 STATUS (FAULT) Register (Address = 01h) [reset = 10h]
STATUS is shown in Figure 40 and described in Table 4.
Return to Summary Table.
Figure 40. STATUS Register
8
7
6
5
4
3
2
1
0
RESERVED
R-0h
POWER
CYCLED
LED2BOOTUV LED1BOOTUV
THERMAL
_ WARNING
SPI
_ERROR
ERROR
_ERROR
RtoCl-1h
RtoCl-0h
RtoCl-0h
RtoCl-0h
RtoCl-0h
(1) R/W = Read/Write; R = Read Only RtoCl = Read to clear bit; -n = value after reset
Table 4. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
8-5
RESERVED
R
0
Reserved
4
POWER_CYCLED
RtoCl
1
Power cycled. This bit indicates that a power-on reset has
occurred since the last STATUS register read.
0h = No power cycle has occurred since the last STATUS read.
1h = A power cycle has occurred since the last STATUS read.
3
2
1
LED2_BOOTUV_ERROR RtoCl
LED1_BOOTUV_ERROR RtoCl
0
0
0
Latched LED2 BOOTUV error. This bit is cleared by reading the
STATUS register if the condition is no longer present.
Latched LED1 BOOTUV error. This bit is cleared by reading the
STATUS register if the condition is no longer present.
THERMAL_WARNING
RtoCl
Latched thermal warning flag: This bit is cleared by reading the
STATUS register if the condition is no longer present.
0h = No thermal warning has occurred since the last STATUS
read.
1h = A thermal warning has occurred since the last STATUS
read.
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Table 4. STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
SPI_ERROR
RtoCl
0
Latched SPI error flag
0h = No SPI error occurred since the last STATUS read.
1h = A SPI error has occurred since the last STATUS read.
POWER_CYCLED: This bit is set each time the input power is cycled to the TPS92518, including the first time
the TPS92518 is powered on. To utilize this feature, read the bit as part of the start-up routine.
x_BOOTUV_ERROR: Set any time the high-side FET ‘BOOT’ drive circuit falls below VBOOT-UVLO (4.6 V typical).
Note: This can be used to detect that the LED load is open, or that a drop-out condition is occurring. (any time
VVIN ~= VVLEDx) For example: the LED load is removed from the output. There is no path for current flow and no
increase of voltage on the sense resistor. The high-side FET remains ON requiring some current draw from the
BOOT capacitor. After some time (milli-second magnitude) the capacitor is depleted, and reaches VBOOT-UVLO. At
this point the high-side FET is turned off and the LEDx_BOOTUV_ERROR flag set. The boot capacitor is then be
re-charged. See BOOT Capacitor and BOOT UVLO for more information.
SPI_ERROR: This error is cleared by reading the STATUS register. A SPI error is caused by any of the following
conditions:
•
•
•
A non-integer-multiple of 16 clocks received during a SPI transfer
Any of the DATA bits are non-zero during a SPI read command
SPI parity error during a SPI read or write command.
The TPS92518 detects and reports certain communication and system conditions. The SPI Error status is
reported with every response frame. This is useful to quickly diagnose a communication problem and attempt to
fix it. On a read response frame, the TPS92518 reports the Power Cycled, Boot UV and Thermal Warning status
bits, as reflected in the STATUS register. Any power and/or system faults are immediately reported on ANY read
response which allows the controlling MCU to more quickly respond to system problems. (See Read Response
Frame Format)
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8.5.3 THERM_WARN_LMT Register (Address = 02h) [reset = 80h]
THERM_WARN_LMT is shown in Figure 41 and described in Table 5.
Return to Summary Table.
Figure 41. THERM_WARN_LMT Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
THERM_WARN_LMT
R/W-80h
(2) R/W = Read/Write; R = Read Only; RtoCl = Read to clear bit; -n = value after reset
Table 5. THERM_WARN_LMT Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
THERM_WARN_LMT
R/W
80h
Thermal warning voltage limit. If the ADC value of VTHERM (
Register 9h ) exceeds this limit, the THERMAL_ERROR bit in
the STATUS register is set.
THERM_WARN_LMT : The Thermal Warning status register is controlled by the content of this register.
Use Equation 28 to calculate the value for the register for the desired Thermal Warning Limit.
Thermal Warning Limit (o C) = 2.439 x VTHERM_ WARN_LMT[7 : 0] - 293.5
»
ÿ
⁄
(28)
8.5.4 LED1_PKTH_DAC Register (Address = 03h) [reset = 80h]
LED1_PKTH_DAC is shown in Figure 42 and described in Table 6.
Return to Summary Table.
Figure 42. LED1_PKTH_DAC Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED1_PKTH_DAC
R/W-80h
(3) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 6. LED1_PKTH_DAC Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
LED1_PKTH_DAC
R/W
80h
Channel 1 peak threshold DAC value.
The content of the register is used to set the peak inductor current (ILx-peak). The register value sets the voltage
across the sense resistor (VCSPx-VCSNx) that ends the converter on-time.
The register value can be modified at any time during operation and the DAC analog value is then updated in
~1us. Always use the highest value that the application allows to reduce accuracy error. For example, the
amount of variation in the actual peak threshold for LEDx_PKTH_DAC = 255 is less than for LEDx_PKTH_DAC
= 127.
The Peak Current Threshold Voltage in volts (the voltage measured across the sense resistor that trips the peak
current comparator) is simply the register value divided by 1000. (Consider the decimal register value to be in
milli-volts)
The Peak Current Threshold in Amps can be calculated using Equation 29
LEDx _PKTH_DAC[7 : 0]
ILx-peak
=
1000ìRSENSE
(29)
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8.5.5 LED2_PKTH_DAC Register (Address = 04h) [reset = 80h]
LED2_PKTH_DAC is shown in Figure 43 and described in Table 7.
Return to Summary Table.
Figure 43. LED2_PKTH_DAC Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED2_PKTH_DAC
R/W-80h
(4) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 7. LED2_PKTH_DAC Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
LED2_PKTH_DAC[7:0]
R/W
80h
Channel 2 peak threshold DAC value.
The content of the register is used to set the peak inductor current (ILx-peak). The register value sets the voltage
across the sense resistor (VCSPx-VCSNx) that ends the converter on-time.
The register value can be modified at any time during operation and the DAC analog value is then updated in
~1us. Always use the highest value that the application allows to reduce accuracy error. For example, the
amount of variation in the actual peak threshold for LEDx_PKTH_DAC = 255 is less than for LEDx_PKTH_DAC
= 10.
The Peak Current Threshold Voltage in volts (the voltage measured across the sense resistor that trips the peak
current comparator) is simply the register value divided by 1000. (Consider the decimal register value to be in
milli-volts)
The Peak Current Threshold in Amps can be calculated using Equation 30
LEDx _PKTH_DAC[7 : 0]
ILx-peak
=
1000ìRSENSE
(30)
8.5.6 LED1_TOFF_DAC Register (Address = 05h) [reset = 80h]
LED1_TOFF_DAC is shown in Figure 44 and described in Table 8.
Return to Summary Table.
Figure 44. LED1_TOFF_DAC Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED1_TOFF_DAC
R/W-80h
(5) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 8. LED1_TOFF_DAC Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
LED1_TOFF_DAC[7:0]
R/W
80h
Channel 1 off time DAC value.
See LED2_TOFF_DAC Register (Address = 06h) [reset = 80h] for information on setting LED1_TOFF_DAC.
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8.5.7 LED2_TOFF_DAC Register (Address = 06h) [reset = 80h]
LED2_TOFF_DAC is shown in Figure 45 and described in Table 9.
Return to Summary Table.
Figure 45. LED2_TOFF_DAC Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED2_TOFF_DAC
R/W-80h
(6) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 9. LED2_TOFF_DAC Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
LED2_TOFF_DAC[7:0]
R/W
80h
Channel 2 off time DAC value.
LEDx_TOFF_DAC: The content of this register AND corresponding VLEDx pin set the corresponding channel off-
time.
Important: →Ensure code controlling the TOFF register for both channels maintains limits on this register value.
It is possible to write a value that is too low that may damage the application. See Off-Time Thresholds -
LEDx_TOFF_DAC and LEDx_MAXOFF_DAC for more details about controlling this register value.
LEDx _ TOFF_DAC[7 : 0]
tOFF
=
2.136ì106 ì VLEDx
(31)
Where tOFF is in seconds. It can also be described as a setting for the channel V·µs product. The V·µs relation
ensures the converter peak-peak ripple is constant and maintains the converter regulation.
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8.5.8 LED1_MAXOFF_DAC Register (Address = 07h) [reset = 80h]
LED1_MAXOFF_DAC is shown in Figure 46 and described in Table 10.
Return to Summary Table.
Figure 46. LED1_MAXOFF_DAC Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED1_MAXOFF_DAC
R/W-80h
(7) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 10. LED1_MAXOFF_DAC Register Field Descriptions
Bit
8
Field
Type
Reset
0
Description
RSVD
R
Reserved
7-0
LED1_MAXOFF_DAC[7:0] R/W
80h
Channel 1 maximum off time DAC value.
See LED2_MAXOFF_DAC Register (Address
LED1_MAXOFF_DAC register.
=
08h) [reset = 80h] for information on setting the
8.5.9 LED2_MAXOFF_DAC Register (Address = 08h) [reset = 80h]
LED2_MAXOFF_DAC is shown in Figure 47 and described in Table 11.
Return to Summary Table.
Figure 47. LED2_MAXOFF_DAC Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED2_MAXOFF_DAC
R/W-80h
(8) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 11. LED2_MAXOFF_DAC Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
LED2_MAXOFF_DAC[7:0]
R/W
80h
Channel 2 maximum off time DAC value.
LEDx_MAXOFF_DAC: the content of this register sets the maximum off-time for the corresponding channel,
regardless of output voltage. LEDxMAXOFF and LEDx_TOFF operate in parallel. In normal operation,
LEDxMAXOFF must always be longer in time than LEDxTOFF so as not to interfere with the normal operation of
the converter.
Maximum Off Time (s) = LEDx _MAXOFF_DAC[7:0] x (251x 10-9)
(32)
The MaxOffTime value is most useful in LED Matrix or shunt-FET dimming applications. When the output LED
voltage is sufficiently low (<2V), regular operation of the off-timer is not possible. This parallel timer does not rely
on the output voltage and can be set to maintain consistent inductor current peak-to-peak ripple. Refer to the
application section Off-Time Thresholds - LEDx_TOFF_DAC and LEDx_MAXOFF_DAC for equations to properly
set the maximum off time under shunted conditions.
The Maximum off-time is also the time that must expire before the first cycle is initiated at start-up, or after a
POR.
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8.5.10 VTHERM Register (Address = 09h) [reset = 0h]
VTHERM is shown in Figure 48 and described in Table 12.
Return to Summary Table.
Figure 48. VTHERM Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
VTHERM
R-0h
(9) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 12. VTHERM Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
VTHERM[7:0]
R
0h
Most recent ADC value of voltage on internal thermal sensor
(based on a DeltaVBE).
The content of the VTHERM register represents the TPS92518 die temperature. Use Equation 33 to convert to
degrees Celsius. The conversion is approximately 2.5ºC per LSB. The part-to-part temperature reading variation
is ±10ºC or ±4lsb. This is the maximum variation a population of parts will have at a given temperature. If a single
part temperature is read and then the temperature changes and returns to the same temperature, the reading will
vary ±1 lsb from the original reading.
Die Temperature (èC) = 2.439 x VTHERM[7 : 0] - 293.5
(33)
8.5.11 LED1_MOST_RECENT Register (Address = 0Ah) [reset = 0h]
LED1_MOST_RECENT is shown in Figure 49 and described in Table 13.
Return to Summary Table.
Figure 49. LED1_MOST_RECENT Register
8
7
6
5
4
3
2
1
0
PWM1
R-0h
LED1_MOST_RECENT
R-0h
(10) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 13. LED1_MOST_RECENT Register Field Descriptions
Bit
Field
Type
Reset
Description
8
PWM1
R
0
State of PWM1 when most recent ADC conversion of VLED1
voltage was started.
7-0
LED1_MOST_RECENT[7:0]
R
0h
Most recent ADC value of voltage on the VLED1 pin.
This register contains the last LEDx reading recorded by the internal ADC along with the state of the
corresponding PWM pin state at the time the value was recorded. See Voltage Sampling and DAC Operation for
more detailed information about LED voltage sampling control. This sample occurs at anytime and is not co-
ordinated with the PWMx input pin.
LEDx_MOST_RECENT (Volts) =LEDx_MOST_RECENT[7:0] x 0.26
(34)
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8.5.12 LED1_LAST_ON Register (Address = 0Bh) [reset = 0h]
LED1_LAST_ON is shown in Figure 50 and described in Table 14.
Return to Summary Table.
Figure 50. LED1_LAST_ON Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED1_LAST_ON
R-0h
(11) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 14. LED1_LAST_ON Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
LED1_LAST_ON[7:0]
R
0h
Last ADC value of voltage on VLED1 pin before falling edge of
PWM1
Contains the last ADC recorded value of the LED1 voltage before the falling edge of PWM1. This ensures the
most stable and consistent recorded value of the output voltage.
LEDx _LAST_ON(Volts) = LEDx _LAST_ON[7:0] x 0.26
(35)
See Voltage Sampling and DAC Operation for more information on LED voltage sampling.
8.5.13 LED1_LAST_OFF Register (Address = 0Ch) [reset = 0h]
LED1_LAST_OFF is shown in Figure 51 and described in Table 15.
Return to Summary Table.
Figure 51. LED1_LAST_OFF Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED1_LAST_OFF
R-0h
(12) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 15. LED1_LAST_OFF Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
LED1_LAST_OFF[7:0]
R
0h
!~ Last ADC value of voltage on VLED1 pin before rising edge of
PWM1 !~ Last ADC value of voltage on VLED1 pin before rising
edge of PWM1
Contains the last ADC recorded value of the LED1 voltage before the rising edge of PWM1. This ensures the
most stable and consistent recorded value of the output voltage when the PWM signal was low.
LEDx _LAST_OFF(Volts) = LEDx _LAST_OFF[7:0] x 0.26
(36)
See Voltage Sampling and DAC Operation for more information on LED voltage sampling.
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8.5.14 LED2_MOST_RECENT Register (Address = 0Dh) [reset = 0h]
LED2_MOST_RECENT is shown in Figure 52 and described in Table 16.
Return to Summary Table.
Figure 52. LED2_MOST_RECENT Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED2_MOST_RECENT
R-0h
(13) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 16. LED2_MOST_RECENT Register Field Descriptions
Bit
Field
Type
Reset
Description
8
PWM2
R
0
State of PWM2 when most recent ADC conversion of VLED2 pin
voltage was started.
7-0
LED2_MOST_RECENT[
7:0]
R
0h
Most recent ADC value of voltage on the VLED2 pin.
See section LED1_MOST_RECENT Register. Information on LED1_MOST_RECENT Register (Address = 0Ah)
[reset = 0h] is the same as LED2_MOST_RECENT Register
8.5.15 LED2_LAST_ON Register (Address = 0Eh) [reset = 0h]
LED2_LAST_ON is shown in Figure 53 and described in Table 17.
Return to Summary Table.
Figure 53. LED2_LAST_ON Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED2_LAST_ON
R-80h
(14) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 17. LED2_LAST_ON Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
LED2_LAST_ON[7:0]
R
0h
Last ADC value of voltage on VLED2 pin before falling edge of
PWM2
See section LED1_LAST_ON Register (Address = 0Bh) [reset = 0h] for more information on LED2_LAST_ON.
Operation of each of the LAST_ONx registers is the same.
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8.5.16 LED2_LAST_OFF Register (Address = 0Fh) [reset = 0h]
LED2_LAST_OFF is shown in Figure 54 and described in Table 18.
Return to Summary Table.
Figure 54. LED2_LAST_OFF Register
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LED2_LAST_OFF
R-0h
(15) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 18. LED2_LAST_OFF Register Field Descriptions
Bit
8
Field
Type
R
Reset
0
Description
RSVD
Reserved
7-0
LED2_LAST_OFF[7:0]
R
0h
Last ADC value of voltage on the VLED2 pin before rising edge
of PWM2
See section LED1_LAST_OFF Register (Address = 0Ch) [reset = 0h] for more information on LED2_LAST_OFF.
Operation of each of the LAST_OFFx registers is the same.
8.5.17 Reset Register (Address = 10h) [reset = 0h]
Reset is shown in Figure 55 and described in Table 19.
Return to Summary Table.
Figure 55. Reset Register
8
7
6
5
4
3
2
1
0
Reset
R/W-0h
(16) R/W = Read/Write; R = Read Only ; RtoCl = Read to clear bit; -n = value after reset
Table 19. Reset Register Field Descriptions
Bit
Field
Type
Reset
Description
8
Reset[8:0]
R/W
0h
Write 0x0C3 to the RESET register to reset all writable registers
to their default values.
This register is write-only. Reads of this register return 0.
The RESET register provides a means to reset all the writable registers to their default values.
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8.6 Programming
Coding examples outline common TPS92518 tasks.
8.6.1 TPS92518 Register Typedef - Sample Code
// TPS92518 Registers
typedef enum
{
CONTROL = 0x00,
STATUS = 0x01,
THERM_WARN_LMT = 0x02,
LED1_PKTH_DAC = 0x03,
LED2_PKTH_DAC = 0x04,
LED1_TOFF_DAC = 0x05,
LED2_TOFF_DAC = 0x06,
LED1_MAXOFF_DAC = 0x07,
LED2_MAXOFF_DAC = 0x08,
VTHERM = 0x09,
LED1_MOST_RECENT = 0x0A,
LED1_LAST_ON = 0x0B,
LED1_LAST_OFF = 0x0C,
LED2_MOST_RECENT = 0x0D,
LED2_LAST_ON = 0x0E,
LED2_LAST_OFF = 0x0F,
RESET = 0x10
}Registers518;
8.6.2 Command Frame - Sample Code
The Command Frame can be constructed using the following code:
//assemble the 16-bit command
uint_t AssembleSPICmd(bool write, Registers518 regAddr, uint16_t data)
{
uint16_t assembledCmd = 0; // Build this to shift through parity calc
uint16_t parity = 0;
uint16_t packet = 0;
// Parity bit calculated here
// This will be what we send
// Set the CMD bit high if this is a write
if(write)
{
assembledCmd |= 0x8000; // Set CMD = 1
}
// Move the register address into the correct position
assembledCmd |= (( regAddr << 10) & 0x7C00);
// Append the data for a write
if(write)
{
assembledCmd |= (data & 0x01FF);
}
// Save this off into the returned variable
packet = assembledCmd;
// Calculate the parity bit
while(assembledCmd > 0)
{
// Count the number of 1s in the LSb
if(assembledCmd & 0x0001)
{
parity++;
}
// Shift right
assembledCmd >>= 1;
}
// If the LSb is a 0 (even # of 1s), we need to add the odd parity bit
if(!(parity & 0x0001))
{
packet |= (1 << 9);
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Programming (continued)
}
return(packet);
}
8.6.3 SPI Read/Write - Sample Code
Perform a SPI read/write; with assumption that the buffer holding write data has been filled using the
AssembleSPICmd function, Then send the 16-bit characters. Lower numbered array elements are nearer the
MCU in the daisy-chain.
/* Perform the SPI read/write; assumed that the buffer holding write data has been filled
* using the AssembleSPICmd function. */
void SendSPIPacket(uint16_t chainID, uint16_t *writeBuf_ptr, uint16_t *readBuf_ptr)
{
uint16_t i;
// Which SSN to take low; SSx_LOW is a macro for GPO manipulation switch(chainID)
{
case 0:
SS0_LOW();
break;
case 1:
SS1_LOW();
break;
case 2:
SS2_LOW();
break;
default:
break;
}
// Send the 16-bit characters; lower numbered array elements are nearer the MCU in the daisy-chain
for(i = NUM_DEVICES_PER_CHAIN; i >= 1; i--)
{
SpibRegs.SPITXBUF = *(writeBuf_ptr + (i-1));
while(SpibRegs.SPISTS.bit.INT_FLAG == 0);
*(readBuf_ptr + (i-1)) = SpibRegs.SPIRXBUF;
// Send each 16-bit piece of the packet
// Wait for buffer to empty
// Grab the TPS92518 response
}
// Small delay to ensure all data is shifted out
DELAY_US(5);
// Make sure all SSN#s are high (SSx_HIGH is a macro)
SS0_HIGH();
SS1_HIGH();
SS2_HIGH();
}
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS92518 buck current controller is suitable for implementing step-down LED drivers. This section presents
a simplified design process for an LED driver with the specifications shown in Design Requirements:
Use the following design procedure to select component values for this and similar buck applications.
9.2 Typical Application
VIN
R2
CIN
TPS92518
EN/UV
CSP2
CSN2
GATE2
SW2
VIN
24
23
R3
CSP1
CSN1
GATE1
SW1
Rsense
Rsense
22
21
20
19
18
17
3
4
5
L
L
VLED1
VLED2
6
7
BOOT2
VCC2
GND
BOOT1
VCC1
GND
CBOOT
CBOOT
CVCC
CVCC
8
DAP
9
VLED1
PWM1
VLED2
PWM2
MOSI
16
15
14
13
10
11
12
SSN
SCK
10k ꢀ
µC VCC
MISO
SPI BUS
Figure 56. Typical Application Schematic
Table 20. Design Requirements
9.2.1 Design Requirements
Buck converter topology.
PARAMETER
Input voltage
VALUE
UNIT
VIN
50
1.6
V
A
V
ILED
LED current
VLED
LED voltage
9.4
ΔIL-PP
Ripple voltage change
Target switching frequency
12.5%
550
40
LEDx_PK_DAC[7:0]
VEN/UV
kHz
V
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Typical Application (continued)
Table 20. Design Requirements (continued)
PARAMETER
VALUE
UNIT
VEN/UV-HYST
5
V
9.2.2 Detailed Design Procedure
TPS92518 Design Equations and sample Calculations.
Start by calculating the converter Duty Cycle
1. Calculate D:
VLEDx
9.4
D =
=
= 0.209
V
x
h
50 x 0.9
IN
(37)
(38)
2. Calculate Off Time Estimate:
1. Using Switching Period (T)
1. T = tOFF + tON = tOFF + (D x T), and T = 1/fSW
then:
1
1
tOFF
=
x (1-D) =
x (1- 0.209) = 1.44ms
fSW
550kHz
3. Compute the off-time register value:
[LEDx_TOFF_DAC] = tOFF x (2.136x106) x VLEDx =1.44 s x 2.136x106 x 9.4 = 29 =1Dh
m
(39)
(40)
(41)
4. Calculate the inductance: Where ΔIL-PP is in Amps.
DIL-PP(Amps) = DIL-PP% x ILED = 0.125 x 1.6 = 200mA
tOFF x VLEDx
1.44ms x 9.4
L =
=
= 67.68mH
DIL-PP
0.2
The user has the option of choosing a value of 68µH, however, this design uses the next common value of
100 µH in order to meet the ripple requirements. When selecting an inductor, ensure both the average and
peak current values are met with adequate margin.
5. Calculate the sense resistor:For the highest current set-point, set the peak threshold register to be as high
as possible. Use [LEDx_PKTH_DAC] = 255 (the maximum value) if possible to increase the converter
accuracy. Only use something lower if it is possible the average current level requires adjustment after the
design is complete and the BOM is complete. For example, if the production flow includes a trimming step.
DIL-PP
0.2
2
ILx-peak = ILED
+
= 1.6 +
= 1.7A
2
(42)
[LEDx _PKTH_DAC]
1000 x ILx-peak
255
RSENSE
=
=
= 0.15W
1000 x 1.7
(43)
6. Calculate the UVLO Resistors: Considering the turn-on point of 40 V and a 5 V hysteresis values for the
UVLO resistors can be selected. ( Refer to Figure 31 for configuration details.)
0.1x V
- 0.124
»
…
ÿ
IN-RISE_ THRESHOLD
(0.1x 40) - 0.124
1.24
»
…
ÿ
VHYST
-
- 0.1
5 -
- 0.1
Ÿ
⁄
Ÿ
⁄
1.24
18 x 10-6
R2 =
R3 =
=
= 98.6 kW
18 x 10-6
(44)
(45)
1.24 (R2)
IN-RISE_ THRESHOLD -1.24
1.24 (98.6k)
=
= 3.15 kW
V
40 -1.24
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9.2.3 Application Curves
CH4 (Green) :
Inductor Current
(500 mA per
division)
CH1 (Blue) : SWx
Node (20 V per
division)
Time Base: 4µs
per division
CH4 (Green) :
Inductor Current
(500 mA per
division)
CH1 (Blue) : SWx
Node (20 V per
division)
Time Base: 2µs
per division
Figure 57. TPS92518 Start-Up
Figure 58. TPS92518 Normal Steady-State Operation
TPS92518 Useful Equations:
Converter Output Equation (A) (Ideal)
»
…
ÿ
Ÿ
⁄
LEDx _PKTH_DAC[7 :0]
LEDx _ TOFF_DAC[7 :0]
»
…
ÿ
ILED
=
-
Ÿ
2ìL ì2.136ì106
1000ìRSENSE
⁄
(46)
Converter Output Equation (A) (With error sources)
≈
∆
∆
∆
’
»
…
ÿ
LEDx _ TOFF _DAC[7 : 0]
2.136 ì106 ì VLEDx
2ìL
»
…
ÿ
≈
∆
∆
∆
’
LEDx _PKTH_DAC[7 : 0]
»
…
ÿ
ê tD-OFF Ÿ ì VLEDx
ê VCSTx-OFFSET
÷
÷
÷
÷
÷
÷
Ÿ
Ÿ
(VIN - VLEDx)ì tDEL
1000
⁄
⁄
⁄
ILED
=
ê
-
RSENSE
L
∆
∆
÷
÷
∆
÷
«
◊
«
◊
(47)
9.3 Dos and Don'ts
Do:
•
•
Check the TPS92518 case and junction temperature during and after prototyping of any solution.
Check the soldering of the device thermal pad (DAP) in production
Don't:
•
Don't write 0 (zero) to any of the off-time registers ([LEDx_TOFF_DAC] or LEDxMAXOFF_DAC] unless the
use case is well understood and tested.
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10 Power Supply Recommendations
The TPS92518 was designed with the consideration of two main input source possibilities: direct from battery or
from the output of a boost stage. For either application, ensure input voltage ripple requirements are met. The
input ripple must go no higher than 10% of the input voltage to a maximum of 3 V.
10.1 Input Source Direct from Battery
Operation direct from battery has been considered when designing the TPS92518. The device ratings are such
that load dump and other battery voltage excursions should not exceed the ratings of the device. When the
battery voltage drops, the device's ability to run in to drop-out and various UVLO controls ensure a controlled
recovery and no device damage. The BOOT UVLO protection allows duty cycles over 99%.
10.2 Input Source from a Boost Stage
The TPS92518 maximum input voltage of 65 V makes it a suitable second stage buck regulator(s) for a variety of
applications and LED output configurations. For an average LED forward voltage of 3.5 V, and allowing for some
headroom below the 65-V maximum input, the TPS92518 can successfully control up to 17 LEDs connected in
series.
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11 Layout
11.1 Layout Guidelines
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. Following a few simple guidelines maximizes noise rejection and minimizes the generation of EMI
within the circuit. Figure 59 shows a sample layout and the associated current loops.
•
Discontinuous currents are the type of current most likely to generate EMI, therefore care should be taken
when routing these paths. – The main path for discontinuous current contains the input capacitor, the
recirculating diode, the MOSFET (CSN pin to SW pin), and the sense resistor (RSENSE) shown as LOOP2.
Make LOOP2 as small as possible. – Make the connections between all three components short and thick to
minimize parasitic inductance. In particular, the switchnode (where L1, D1 and the SW pin connect, shown as
LOOP1) should be only large enough to connect the components without excessive heating from the current
it carries.
•
In some applications the LED load can be far away (several inches or more) from the device, or on a
separate PCB connected by a wiring harness. When an output capacitor is used and the LED load is large or
separated from the main converter, the output capacitor must be placed close to the LEDs to reduce the
effects of parasitic inductance on the AC impedance of the capacitor.
11.2 Layout Example
VIAs - Connection to
Ground plane, Layer
2
Input +
CONN
INPUT
=
||||
Input -
LED-
LED-
LOOP2
LOOP2
LED-
LED-
||||
||||
||||
||||
||||
D
D
LED+
LED+
LOOP1
LOOP1
SW1
SW2
L
L
To PWM and SPI
Connections
Figure 59. TPS92518 Layout Guideline
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
PWP0024B
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC SMALL OUTLINE
6.6
6.2
SEATING PLANE
C
TYP
PIN 1 ID
AREA
A
0.1 C
22X 0.65
24
1
2X
7.9
7.7
7.15
NOTE 3
12
13
0.30
24X
4.5
4.3
0.19
B
0.1
C A
B
(0.15) TYP
SEE DETAIL A
4X (0.2) MAX
NOTE 5
2X (0.95) MAX
NOTE 5
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
5.16
4.12
1.2 MAX
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
2.40
1.65
4222709/A 02/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present and may vary.
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EXAMPLE BOARD LAYOUT
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.4)
24X (1.5)
SYMM
SEE DETAILS
1
24
24X (0.45)
(R0.05)
TYP
(7.8)
NOTE 9
(1.1)
TYP
SYMM
(5.16)
22X (0.65)
(
0.2) TYP
VIA
12
13
(1) TYP
METAL COVERED
BY SOLDER MASK
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-24
4222709/A 02/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
PWP0024B
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.4)
BASED ON
0.125 THICK
STENCIL
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
(5.16)
SYMM
BASED ON
0.125 THICK
STENCIL
22X (0.65)
13
12
SYMM
(5.8)
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.68 X 5.77
2.4 X 5.16 (SHOWN)
2.19 X 4.71
0.125
0.15
0.175
2.03 X 4.36
4222709/A 02/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS92518HVPWPR
TPS92518HVPWPT
TPS92518PWPR
TPS92518PWPT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
PWP
24
24
24
24
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
92518HV
NIPDAU
NIPDAU
NIPDAU
92518HV
92518
92518
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS92518, TPS92518HV :
Automotive: TPS92518-Q1, TPS92518HV-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS92518HVPWPR
TPS92518PWPR
HTSSOP PWP
HTSSOP PWP
24
24
2000
2000
330.0
330.0
16.4
16.4
6.95
6.95
8.3
8.3
1.6
1.6
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS92518HVPWPR
TPS92518PWPR
HTSSOP
HTSSOP
PWP
PWP
24
24
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
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