TPS92513HVDGQR [TI]
65V 1.5A 模拟电流可调节降压 LED 驱动器 | DGQ | 10 | -40 to 125;
| 型号： | TPS92513HVDGQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 65V 1.5A 模拟电流可调节降压 LED 驱动器 | DGQ | 10 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总29页 (文件大小：1592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS92513, TPS92513HV
ZHCSDR0 –APRIL 2015
TPS92513 具有集成模拟电流调节功能的 1.5A 降压发光二极管 (LED) 驱动
器
1 特性
3 说明
1
•
集成型 220mΩ 高侧金属氧化物半导体场效应晶体
管 (MOSFET)
TPS92513/HV 为 1.5A 降压电流稳压器，其集成有
MOSFET，用于驱动高电流 LED。 这两款 LED 驱动
器的输入电压上限分别为 42V 和 60V (HV)，并且可在
峰值电流模式控制下以用户选择的固定频率工作，同时
可提供出色的线路和负载调节性能。
•
4.5V 至 42V 输入电压范围
（TPS92513HV 为 4.5V 至 60V）
•
•
•
•
•
•
•
•
0V 至 300mV 可调基准电压
±5% LED 电流精度
TPS92513/HV LED 驱动器特有分别用于模拟调光和脉
宽调制 (PWM) 调光的独立输入，并且不会影响到亮度
控制，对比度分别高达 10:1 和 100:1 以上。 PWM 输
入符合低压逻辑标准，可轻松连接各类微控制器。 通
过 IADJ 输入，可使用 0V 至 1.8V 的外部信号在 0V
至 300mV 范围内调整模拟 LED 电流设定值。
100kHz 至 2MHz 开关频率范围
专用脉宽调制 (PWM) 调光输入
可调节欠压闭锁
过流保护
过热保护
MSOP-10 封装，采用 PowerPAD™
对于使用两个或两个以上 TPS92513/HV LED 驱动器
的多灯串应用，可通过外部时钟来过驱动内部振荡器，
以确保所有转换器工作在同一频率下，从而降低出现拍
频的几率并简化系统电磁干扰 (EMI) 滤波设计。 该器
件具有一个带滞后功能的可调节输入欠压闭锁 (UVLO)
引脚，可根据具体的电源电压条件灵活设置起始/停止
电压。
2 应用范围
•
•
•
•
•
•
•
•
街道照明
紧急/出口照明
一般工业和商业用照明
零售照明
电器照明
运输照明
TPS92513 具有逐周期过流保护和热关断保护。 该器
件采用 10 引脚 HVSSOP PowerPAD™ 封装。
立体发光字
光条
器件信息(1)
器件型号
TPS92513
TPS92513HV
封装
封装尺寸（标称值）
HVSSOP (10)
5.00mm x 3.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
4 简化电路原理图
0.18V ± 1.8V
6
1
效率与输入电压间的关系
1.5A 电流下的 7 个白色 LED (VOUT = 23V)
IADJ
BOOT
2
4
VIN
100
97.5
95
PH 10
PDIM
TPS92513
3
8
5
UVLO
COMP
RT/CLK
ISENSE
7
92.5
90
GND
9
Pad
87.5
85
25
30
35
40
45
50
55
60
Input Voltage (V)
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCX6
TPS92513, TPS92513HV
ZHCSDR0 –APRIL 2015
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 17
9.3 Design Requirements.............................................. 17
9.4 Detailed Design Procedure ..................................... 18
9.5 Application Curves .................................................. 20
1
2
3
4
5
6
7
特性.......................................................................... 1
9
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 器件和文档支持 ..................................................... 22
12.1 相关链接................................................................ 22
12.2 商标....................................................................... 22
12.3 静电放电警告......................................................... 22
12.4 术语表 ................................................................... 22
13 机械、封装和可订购信息....................................... 22
8
5 修订历史记录
日期
修订版本
注释
2015 年 4 月
*
首次发布。
2
Copyright © 2015, Texas Instruments Incorporated
TPS92513, TPS92513HV
www.ti.com.cn
ZHCSDR0 –APRIL 2015
6 Pin Configuration and Functions
DGQ (HVSSOP) Package
Top View
BOOT
VIN
1
2
3
4
5
10
9
PH
GND
COMP
ISENSE
IADJ
UVLO
PDIM
RT/CLK
8
7
6
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is recharged.
BOOT
1
O
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
COMP
GND
8
9
O
G
Ground.
Analog current adjust pin. The voltage applied to this pin will set the current sense (ISENSE pin) voltage.
The range of the ADJ pin is 180 mV to 1.8 V and the corresponding ISENSE pin voltage is the IADJ pin
voltage divided by 6.
IADJ
6
I
ISENSE
PDIM
PH
7
4
I
Inverting node of the transconductance (gM) error amplifier.
PWM dimming input pin. The duty cycle of the PWM signal linearly controls the average output current of the
converter.
I
10
O
G
The source of the internal high-side MOSFET.
GND pin must be electrically connected to the exposed pad directly beneath the device on the printed circuit
board for proper operation.
PowerPAD PAD
Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to program the switching frequency. If the pin is pulled above the PLL upper
threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is
disabled and the pin becomes a high impedance clock input to the internal PLL. If the clocking edges stop,
the internal amplifier is re-enabled and the mode returns to the resistor-programmed function.
RT/CLK
5
I
UVLO
VIN
3
2
I
Adjustable undervoltage lockout. Set with resistor divider from VIN.
Input supply voltage, 4.5V to 42V or 4.5V to 60V for the HV version.
P
(1) I = Input, O = Output, P = Supply, G = Ground
Copyright © 2015, Texas Instruments Incorporated
3
TPS92513, TPS92513HV
ZHCSDR0 –APRIL 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
MAX
65
UNIT
VIN (TPS92513HV)
VIN (TPS92513)
45
PDIM, UVLO
5
Input voltage
BOOT
V
(PH + 8)
ISENSE, IADJ, COMP
RT/CLK
–0.3
–0.3
–0.6
–0.6
–2
3
3.6
65
45
PH (TPS92513HV)
Output voltage
PH (TPS92513)
PH, 10-ns Transient
PAD to GND
PH
V
Voltage Difference
Source Current
±200
Current Limit
Current Limit
1
mV
A
VIN
A
Sink current
BOOT
mA
°C
°C
TJ
Operating junction temperature
Storage temperature
–40
–65
150
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human-body model (HBM),ESD stress voltage(1)
Charged-device model (CDM), ESD stress voltage(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2 kV may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
MAX
60
UNIT
Input voltage (TPS92513HV)
VIN
fSW
V
Input voltage (TPS92513)
4.5
42
Switching frequency range using RT mode
Switching frequency range using CLK mode
100
300
2000
2000
kHz
tMIN(RT
/CLK)
TJ
Minimum RT/CLK input pulse width for switching frequency synchronization
Operating junction temperature
51
ns
°C
–40
125
4
Copyright © 2015, Texas Instruments Incorporated
TPS92513, TPS92513HV
www.ti.com.cn
ZHCSDR0 –APRIL 2015
7.4 Thermal Information
TPS92513
TPS92513HV
THERMAL METRIC(1)
UNIT
DGQ (10 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
66.7
45.8
37.5
1.8
RθJC(top)
RθJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
37.1
15.4
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
–40°C ≤ TJ ≤ 125°C, VVIN = 12V (unless otherwise noted)
PARAMETER
SUPPLY VOLTAGE (VIN)
TEST CONDITIONS
MIN
TYP
MAX UNIT
VINUVLO
IVINSD
VIN undervoltage lockout threshold
Shutdown supply current
No voltage hysteresis, rising and falling
2.94
V
VUVLO = 0 V, 4.5 V ≤ VVIN ≤ 42 V (60 V for HV)
11.5
407
µA
VISENSE = 220 mV, 4.5V ≤ VVIN ≤ 42 V (60 V
for HV)
IVIN
Non-switching supply current
337
µA
UNDER VOLTAGE LOCKOUT (UVLO)
VUVLO
UVLO threshold voltage
Rising threshold
1.12
1.22
3.97
1.05
1.30
V
VUVLO = 1.5 V (device enabled)
VUVLO = 1 V (device disabled)
UVLO pin source current
µA
ANALOG CURRENT ADJUST (VIADJ, VISENSE
)
IIADJ = 1 µA
1.8
2.77
VIADJ
IADJ clamp voltage
V
IIADJ = 100 µA
VIADJ = 1.2 V, TJ = 25°C to 125°C
VIADJ = 0.18 V, TJ = 25°C to 125°C
IIADJ = 1 µA, TJ = 25°C to 125°C
IIADJ = 100 µA, TJ = 25°C to 125°C
180 mV ≤ VIADJ ≤ 1.8V
191
21.4
285
286
200
210
40.0
309
309
30.0
Current sense voltage
VISENSE
300
mV
300
Current sense voltage level
VIADJ/6
HIGH-SIDE MOSFET (BOOT, PH)
VVIN = 4.5 V, (VBOOT – VPH) = 3.5 V
(VBOOT – VPH) = 6 V
VPDIM = 3V
255
220
6
RDS(on)
On-resistance
mΩ
375
VBOOT
IBOOT
BOOT-PH voltage
BOOT-PH current
V
VPDIM = 0V, (VBOOT – VPH) = 5V
Rising threshold
93.9
2.25
1.99
140
µA
2.81
VBOOTUV
tON(min)
BOOT-PH under voltage lockout
Minimum on time
V
Falling threshold
1.42
VCOMP = 0
ns
ERROR AMPLIFIER (ISENSE, COMP)
Input bias current
VISENSE = 200 mV
20
nA
VIADJ = 1.2 V, 180 mV < VISENSE < 220 mV,
VCOMP = 1 V
gM(ea)
Transconductance gain
331
µA/V
DC gain
VIADJ = 1.2 V , VISENSE = 0.2 V
10
kV/V
MHz
Bandwidth
2.7
VIADJ = 1.2 V , VCOMP = 1 V,
VISENSE = 200 mV ± 100 mV
Source/sink current
±28
6
µA
CURRENT LIMIT
Current limit threshold
A
Copyright © 2015, Texas Instruments Incorporated
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TPS92513, TPS92513HV
ZHCSDR0 –APRIL 2015
www.ti.com.cn
Electrical Characteristics (continued)
–40°C ≤ TJ ≤ 125°C, VVIN = 12V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
THERMAL SHUTDOWN
TSD
Thermal shutdown
165
20
°C
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK)
VRT
fSW
RT/CLK regulated voltage
Switching frequency
RRT = 200 kΩ
474
447
500
557
513
648
mV
kHz
V
VVIN = 6 V, RRT = 200 kΩ
VVIN = 6 V
RT/CLK high threshold
RT/CLK low threshold
1.49
1.02
1.81
VVIN = 6 V
0.63
V
PWM DIMMING (PDIM)
IPDIM PDIM source current
VIH
VPDIM = 0
1.04
1.34
0.88
µA
V
High-level input voltage
Low-level input voltage
1.45
VIL
0.79
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK)
RT/CLK falling edge to PH rising
edge delay
Measured at 500 kHz with RT
resistor in series, VVIN = 6 V
92.1
100
ns
µs
Phase loop (PLL) lock-in time
fSW = 500 kHz
PWM DIMMING (PDIM)
tRISE
tFALL
Rising propagation delay
Falling propagation delay
305
535
ns
6
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TPS92513, TPS92513HV
www.ti.com.cn
ZHCSDR0 –APRIL 2015
7.7 Typical Characteristics
VIN = 24V, Unless otherwise specified
1.53
1.52
1.51
1.5
100
98
96
94
92
90
88
86
84
82
80
1.49
1.48
1.47
15
20
25
30
35
40
45
50
55
60
10
15
20
25
30
35
40
45
50
55
60
Input Voltage (V)
Input Voltage (V)
3 LEDs in Series
VOUT = 9.9 V
D001
D001
1.5 A LED Current
fSW = 570 kHz
4 LEDs in Series
VOUT = 13.1 V
VIADJ = 1.8 V
1.5 A LED Current
VIADJ = 1.8 V
图 1. Efficiency vs Input Voltage
图 2. Line Regulation
2200
2000
1800
1600
1400
1200
1000
800
600
550
500
450
400
350
300
250
200
150
100
600
400
40
60
80
100
120
140
160
180
200
200 300 400 500 600 700 800 900 1000 1100 1200
Resistor, RT (k:)
Resistor, RT (k:)
D001
D001
图 3. Switching Frequency vs RT Resistor
图 4. Switching Frequency vs RT Resistor
1.5
1.25
1
1.6
1.4
1.2
1
0.75
0.5
0.25
0
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
10
20
30
40
50
60
70
80
90 100
IADJ Voltage (V)
PDIM Duty Cycle (%)
D001
D001
1.5 A LED Current
3 LEDs in Series
VOUT = 9.9 V
1.5 A LED Current
3 LEDs in Series
VOUT = 9.9 V
VIADJ = 1.8 V
250 Hz PWM Frequency
图 5. LED Current vs IADJ Voltage
图 6. LED Current vs PDIM Duty Cycle
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TPS92513, TPS92513HV
ZHCSDR0 –APRIL 2015
www.ti.com.cn
Typical Characteristics (接下页)
VIN = 24V, Unless otherwise specified
310
307.5
305
340
320
300
280
260
240
220
200
180
160
140
302.5
300
297.5
295
292.5
290
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Junction Temperature (qC)
Junction Temperature (qC)
D001
D001
VIN = 12 V
VIADJ = 1.8 V
图 7. PH Switch RDS(on) vs Junction Temperature
图 8. VISENSE vs Junction Temperature
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
-40
-20
0
20
40
60
80
100 120 140
0
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
Junction Temperature (qC)
D001
D001
VVIN = 12 V
TJ = 25°C
图 9. Shutdown Input Current vs Junction Temperature
图 10. Shutdown Input Current vs Input Voltage
8
版权 © 2015, Texas Instruments Incorporated
TPS92513, TPS92513HV
www.ti.com.cn
ZHCSDR0 –APRIL 2015
8 Detailed Description
8.1 Overview
The TPS92513 is a high voltage, up to 1.5-A, step-down (buck) regulator with an integrated high-side N-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
peak-current mode control which reduces output capacitance and simplifies external frequency compensation
design. The wide switching frequency of 100 kHz to 2000 kHz allows for efficiency and size optimization when
selecting the output filter components.
8.2 Functional Block Diagram
1µA 2.9µ A
Thermal
Shutdown
VIN
UVLO
2
VIN
BOOT
Charge
3
UVLO
Shutdown
Logic
+
1. 22V
1
BOOT
BOOT
UVLO
8
7
COMP
ISENSE
Error
Amplifier
PWM
Comparator
COMP S /H
R
R
+
S
Logic and
PWM Latch
R
Q
+
-
+
10k
S
Current
Sense
6
1/6
IADJ
COMP
Clamp
1µA
10
9
PH
1.8V
Oscillator
with PLL
Slope
Compensation
GND
4
PDIM
1.34 V
+
5
RT /CLK
8.3 Feature Description
8.3.1 Undervoltage Lockout and Low Power Shutdown (UVLO Pin)
The TPS92513 contains an internal under-voltage lockout circuit on the VIN pin of the device. However, this
internal UVLO is for device protection only and does not contain hysteresis. The UVLO pin of the device should
always be used to set the minimum VIN voltage that the circuit operates at. This level should be set using the
minimum input voltage expected for the application with a minimum setting of 4.5 V.
The UVLO pin has an internal pull-up current source of 1 µA (I1) that will provide a default ON state in the event
the UVLO pin is left floating (not recommended). When the UVLO pin voltage exceeds 1.22 V (VEN), an
additional 2.9 µA of hysteresis current is added (see 图 11). This additional current provides the input voltage
hysteresis. Use 公式 1 to set the external hysteresis (VHYS) for the input voltage. Use 公式 2 to set the input
rising start voltage, VSTART. When the UVLO pin is pulled low, the internal regulators are shut down, the device
enters a low-power shutdown mode and the compensation capacitor on the COMP pin, CCOMP, is discharged.
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TPS92513, TPS92513HV
ZHCSDR0 –APRIL 2015
www.ti.com.cn
Feature Description (接下页)
TPS92513
VIN
2
3
I1
IHYS
R1
1µA
2.9µA
UVLO
+
RESD
1.22V
VEN
R2
图 11. Adjustable Undervoltage Lockout (UVLO)
-IHYS ´RESD ´ VSTART
ESD
VHYS ´ V - I1´R
(
)
)
(
EN
R1=
IHYS ´ VEN
(1)
R1´ V - R
(
´ I1+ I
(
)
)
(
- VEN + I1+ I
)
EN
ESD
HYS
R2 =
V
´ R1+ R
(
VHYS = VSTART - VSTOP
) ( HYS ) (
)
STOP
ESD
(2)
(3)
(4)
RESD = 10 kW
8.3.2 Adjustable Switching Frequency (RT/CLK Pin)
The switching frequency of the TPS92513 is adjustable over a wide range from 100 kHz to 2 MHz by placing a
resistor, RRT, on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to
set the switching frequency. To determine the timing resistance for a given switching frequency, use 公式 5 or
the curves in 图 3 or 图 4. To reduce the solution size one typically sets the switching frequency as high as
possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should
be considered. The minimum controllable on time, tON(min), limits the maximum operating input voltage.
206033
RRT kW =
( )
1.092
(SW ) ( )
f
kHz
(5)
(6)
1
( )
1.092
æ
ç
è
ö
÷
ø
206033
fSW
=
RRT(kW)
8.3.3 Synchronizing the Switching Frequency to an External Clock (RT/CLK Pin)
The RT/CLK pin can be used to synchronize the regulator to an external system clock by connecting a square
wave to the RT/CLK pin through the circuit network as shown in 图 12. The square wave amplitude must
transition lower than 0.63 V and higher than 1.81 V on the RT/CLK pin and have an on-time greater than 51 ns
and an off-time greater than 100 ns. The synchronization frequency range is 300 kHz to 2 MHz. The rising edge
of the PH is synchronized to the falling edge of RT/CLK pin signal. The internal oscillator provides default
switching frequency set by connecting the resistor from the RT/CLK pin to ground should the synchronization
signal turn off.
10
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Feature Description (接下页)
It is required to AC couple the synchronization signal through a 470 pF ceramic capacitor and a 4 kΩ series
resistor to the RT/CLK pin. The series resistor reduces PH jitter in heavy load applications when synchronizing to
an external clock and in applications which transition from synchronizing to RT mode. The first time the RT/CLK
pin is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The
internal 0.5 V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock
onto the external signal. Since there is a PLL on the regulator, the switching frequency can be higher or lower
than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode
and then increases or decreases the switching frequency until the PLL locks onto the CLK frequency within 100
microseconds.
When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK
frequency to 150 kHz, then reapplies the 0.5 V voltage and the resistor then sets the switching frequency. It is
not recommended that a system transition from PLL mode to resistor mode repeatedly during operation. When
the PLL loses the external clock input the default 150 kHz switching frequency creates long on-times, which
result in higher inductor ripple currents. This can lead to inductor saturation if the system is not designed to
operate at this frequency.
TPS92513
470 pF 4 k RT/CLK
Phase-Lock
Loop (PLL)
5
RRT
图 12. Frequency Synchronization
8.3.4 Adjustable LED Current (IADJ and ISENSE Pins)
The LED current can be set, and controlled dynamically, by using the IADJ pin of the TPS92513. 公式 7 shows
the relationship between the voltage applied to IADJ (VIADJ) and the regulation setpoint at the ISENSE pin. 公式 8
shows how to calculate the value of the current setting resistor (RISENSE) from the ISENSE pin to ground for the
desired LED current.
V
IADJ
V
=
ISENSE
6
(7)
V
ISENSE
RISENSE
=
ILED
(8)
The IADJ pin voltage range is 0 V to 1.8 V and is internally clamped at 1.8 V. If analog current adjustment will
not be used, the IADJ pin can be connected to VIN through a resistor for a default ISENSE voltage of 300 mV.
This resistor should be sized so that the current into the IADJ pin is limited to 100 µA or less at the maximum
input voltage. A precision reference between 0 V and 1.8 V can also be used on IADJ to control the ISENSE
voltage. If no external voltage source is available, the IADJ pin can be tied to the RT/CLK pin either directly or
using a resistor divider to generate a voltage between 0 V and 500 mV. If a resistor divider is used off the
RT/CLK pin to generate the IADJ voltage it will introduce a parallel resistance with the RT resistor. High value
resistors are recommended in that case and the parallel combination must be used to calculate the switching
frequency. The current sense voltage is most accurate with IADJ voltages between 180 mV and 1.8 V for a
dimming range of 10:1. Below 180 mV the TPS92513 dims well but may have more variation between circuits.
Due to internal offsets pulling IADJ to 0 V will not result in a current sense voltage of 0 V. Some small current will
continue to run unless the PDIM pin is pulled low or the device is disabled using the UVLO pin. Analog dimming
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Feature Description (接下页)
is also most accurate when the device is in continuous conduction mode (CCM). If the highest accuracy possible
is desired during analog dimming, size the inductor so that 1/2 the peak-to-peak inductor ripple is less than the
minimum LED current to remain in CCM. The IADJ pin should be decoupled with a 10 nF capacitor to ground. A
1 kΩ resistor should be used between the ISENSE pin and RISENSE to protect the pin in the event RISENSE opens
or there is a transient due to one or more LEDs shorting.
8.3.5 PWM Dimming (PDIM Pin)
The TPS92513 incorporates a PWM dimming input pin, which directly controls the enable/disable state of the
internal gate driver. When PDIM is low, the gate driver is disabled. The PDIM pin has a 1 µA pull-up current
source, which creates a default ON state when the PDIM pin is floating. When PDIM goes low, the gate driver
shuts off and the LED current quickly reduces to zero. A square wave of variable duty cycle should be used and
should have a low level below 0.79 V and a high level of 1.45 V or above.
The TPS92513 uses a sample-and-hold switch on the error amplifier output. During the PDIM off-time the COMP
voltage remains unchanged. Also, the error amplifier output is internally clamped low. These techniques help the
system recover to its regulation duty cycle quickly. The dimming frequency range is 100 Hz to 1 kHz and the
minimum duty cycle is only limited in cases where the BOOT capacitor can discharge below its under-voltage
threshold of 2 V (VIN is within 2 V of the total output voltage).
8.3.6 External Compensation (COMP Pin)
The TPS92513 error amplifier output is connected to the COMP pin. The TPS92513 is a simple device to
stabilize and only requires a capacitor from the COMP pin to ground (CCOMP). A 0.1 µF capacitor is
recommended and will work well for most all applications. If an application requires faster response to input
voltage transients, a capacitor as small as 0.01 µF will work for most applications if needed. The overall system
bandwidth can be approximated using 公式 9.
gM(ea)
BW =
2p´ CCOMP
(9)
8.3.7 Overcurrent Protection
Overcurrent can be the result of a shorted sense resistor or a direct short from VOUT to GND. In either case, the
voltage at the ISENSE pin is zero and this causes the COMP pin voltage to rise. When VCOMP reaches
approximately 2.2 V, it is internally clamped and functions as a MOSFET current limit. The TPS92513 limits the
MOSFET current to 6 A (typical). If the shorted condition persists, the TPS92513 junction temperature increases.
If it increases above 165°C, the thermal shutdown protection is activated.
8.3.8 Overtemperature Protection
The TPS92513 includes a thermal shutdown circuit to protect the device from over-temperature conditions. The
device can overheat due to high ambient temperatures, high internal power dissipation, or both. In the event the
die temperature reaches 165°C the device will shut down until the die temperature falls 20°C at which point it will
turn back on.
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8.4 Device Functional Modes
8.4.1 Start-Up
To reduce inrush current and to keep the regulator in control during all startup conditions the TPS92513 employs
a startup mode that behaves differently than during normal operation (regulation mode). The UVLO conditions
must be satisfied before the TPS92513 is allowed to switch. When the UVLO pin is held low the device enters a
low-power shutdown mode, and some internal circuits are deactivated to conserve power. When UVLO returns
high these circuits are enabled, which results in a delay of approximately 50 µs (typical) before switching starts.
During start-up the TPS92513 operates in a minimum pulse width mode which is an open-loop control. At the
start of each switching cycle the internal oscillator initiates a SET pulse. The high-side MOSFET turns on with a
minimum pulse width of 140 ns (typical), independent of the COMP voltage. The device does not pulse skip.
While operating in minimum pulse width mode, the LED bypass capacitor is being charged causing an in-rush
current. Also, the COMP voltage begins to rise as the error amplifier output current charges the compensation
capacitor. When the COMP voltage reaches approximately 0.7 V, the error amplifier is ensured to be out of
saturation and to have sufficient gain to regulate the loop. The TPS92513 then transitions from minimum pulse
width mode to regulation mode. During regulation mode the error amplifier is now in closed-loop control of the
system. The gain of the error amplifier quickly increases the duty cycle, which causes the output voltage to
increase. Once the output voltage approaches the forward voltage of the LED string, the LED current quickly
begins to increase until it reaches regulation.
There is a slight delay from the time the VIN and EN UVLO conditions are satisfied until the time the error
amplifier has control of the feedback loop. This delay is a result of the time it takes COMP to charge the
compensation capacitor to 0.7 V. This delay can be approximated as shown in 公式 10.
0.7 V
tDELAY = CCOMP
´
28 mA
(10)
The peak inrush current, IPEAK, can be calculated to a first order approximation using 公式 11 and the value of
the output capacitor, COUT
V ´ tON(min) ´ fSW
.
IN
IPEAK
=
L
+ RISENSE
COUT
(11)
8.4.2 Minimum Pulse Width and Limitations
The TPS92513 is designed to output a minimum pulse width during each switching cycle of 140 ns (typical). The
control loop cannot regulate the system to an on-time less than this amount, and it does not skip pulses. When
attempting to operate below the minimum on-time the system loses regulation and the LED current increases.
This puts a practical limitation on the system operating conditions, as shown in 公式 12.
VOUT
V
=
IN
fSW ´ tON(min)
(12)
Where VOUT equals the forward voltage of the LED string plus the reference voltage VISENSE
.
The system can avoid this operating condition by limiting the maximum input voltage as shown in 公式 12. If the
input voltage cannot be limited due to application, then the switching frequency can be lowered, or the output
voltage increased. This region of operation typically occurs with high input voltages, high operating frequencies,
and low output voltages.
8.4.3 Maximum Duty Cycle and Bootstrap Voltage (BOOT)
The TPS92513 requires a small 0.1 µF ceramic capacitor between the BOOT and PH pins to provide the gate
drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET turns
off, and the freewheeling rectifier diode conducts. A ceramic capacitor with an X7R or X5R dielectric and a
minimum voltage rating of 10 V is recommended.
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Device Functional Modes (接下页)
The TPS92513 is designed to operate up to 100% duty cycle as long as the BOOT to PH voltage is greater than
at least 2 V. If the BOOT capacitor voltage drops below 2 V, then the BOOT UVLO circuit turns off the MOSFET,
which allows the BOOT capacitor to be recharged. The current required from the BOOT capacitor to keep the
MOSFET on is quite low. Therefore, many switching cycles occur before the BOOT capacitor is refreshed. In this
way, the effective duty cycle of the converter is quite high.
Attention must be taken in maximum duty cycle applications which experience extended time periods with little or
no load current such as during PWM dimming. When the voltage across the BOOT capacitor falls below the 2 V
UVLO threshold, the high-side MOSFET is turned off, but there may not be enough inductor current to pull the
PH pin down to recharge the BOOT capacitor. The high-side MOSFET of the regulator stops switching because
the voltage across the BOOT capacitor is less than 2 V. The output capacitor then decays until the difference
between the input voltage and output voltage is greater than 2 V, at which point the BOOT UVLO threshold is
exceeded, and the device starts switching again until the desired output current is reached. This operating
condition persists until the input voltage and/or the load current increases. It is recommended to adjust the VIN
stop voltage, VSTOP, to be greater than the BOOT UVLO trigger condition at the minimum load of the application
using the adjustable UVLO feature.
8.4.4 Thermal Shutdown and Thermal Limitations
The TPS92513 is a high current density device in a small package. Therefore; it is not capable of providing the
full 1.5 A of output current under all conditions without the die reaching the thermal shutdown temperature. To
ensure the device will not get too hot the package power dissipation should be calculated and used in
conjunction with the device Thermal Information to estimate the maximum die temperature for a given
application. The total device power dissipation can be closely approximated using the following equations:
VOUT
D =
VIN
(13)
(14)
2
PD(sw) = D´RDS(on) ´ILED
2 mA ´ fSW
æ
ö
PD(IQ) = VIN ´ 400 mA +
ç
÷
1 MHz
è
ø
(15)
PD(AC) = 0.73´10-9 ´ fSW ´ VIN2 ´ILED
(16)
(17)
PTOT = PD(SW) + PD(IQ) + PD(AC)
Where each are in Watts and
•
•
•
•
•
•
D is the maximum duty cycle (at minimum input voltage)
VOUT is the LED stack voltage plus the reference voltage VISENSE
PD(SW) is the power dissipated in the MOSFET
PD(IQ) is the power dissipated by the internal circuitry
PD(AC) are the approximate AC losses due to the MOSFET transitions
PTOT is the total device dissipation
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This section describes power component selection not discussed in the Feature Description section.
9.1.1 Inductor Selection
The value of the buck inductor impacts the peak-to-peak ripple-current amplitude. The peak inductor current is
used in current mode control and to maintain a good signal to noise ratio it is recommended that the peak-to-
peak ripple current (IR 公式 18) is greater than 75 mA for dependable operation. This allows the control system to
have an adequate current signal even at the lowest input voltage. 公式 18 calculates the value for the buck
inductance given the minimum ripple current of IR = 75 mA. Enter the lowest input voltage and the highest output
voltage to yield the maximum inductance value.
VOUT ´ VIN - V
(
IR ´ VIN´ fSW
)
OUT
L =
(18)
Calculate the maximum inductor value for the particular application and choose the next lowest standard value
for applications requiring low ripple current. Choose a lower value for size sensitive applications that can tolerate
higher LED current ripple or use larger output capacitors. With the chosen value the user can calculate the actual
inductor current ripple using 公式 19.
VOUT ´ VIN - V
(
L ´ VIN´ fSW
)
OUT
IRIPPLE
=
(19)
The inductor RMS current and saturation current ratings must be greater than those seen in the application. This
ensures that the inductor does not overheat or saturate. During power-up, transient conditions, or fault
conditions, the inductor current can exceed its normal operating current. For this reason, the most conservative
approach is to specify an inductor with a saturation current rating equal to or greater than the converter current
limit. This is not always possible due to application size limitations. The peak inductor current and the RMS
current equations are shown in 公式 20 and 公式 21.
IRIPPLE
IL _PEAK =ILED
+
2
(20)
(21)
2
IRIPPLE
+
12
2
IL _RMS = ILED
9.1.2 Input Capacitor Selection
The TPS92513 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 2 µF of
effective capacitance per 1 A of output current. Ceramic capacitance tends to decrease as the applied dc voltage
increases. This depreciation must be accounted for to ensure that the minimum input capacitance is satisfied. In
some applications, additional capacitance is needed to provide bulk energy storage such as high current PWM
dimming applications. The input capacitor voltage rating must be greater than the maximum input voltage and
have a ripple current rating greater than the maximum input current ripple of the converter. The RMS input ripple
current is calculated in 公式 22, where D is the duty cycle (output voltage divided by input voltage). The
maximum RMS input ripple current can be calculated by using the minimum input voltage for the application.
IIN_RMS = ILED ´ D´ 1- D
(
)
(22)
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Application Information (接下页)
The input capacitance (CIN) is inversely proportional to the input ripple voltage of the converter. The peak-to-peak
input ripple voltage can be calculated as shown in 公式 23. Additionally, this equation can be used to solve for
the required input capacitance to keep the input ripple voltage to a defined limit.
ILED ´D´ 1-D
(
CIN ´ fSW
)
ΔVIN=
(23)
9.1.3 Output Capacitor Selection
During start-up, the TPS92513 uses the discharged output capacitor as a charging path for the BOOT capacitor.
In order to ensure that the BOOT capacitor charges and that the converter begins switching immediately, the
value of the output capacitor should be 10 times larger than the BOOT capacitor. If the BOOT capacitor is 0.1
µF, then the minimum output capacitor should be 1 µF for the fastest startup time. If the output capacitor is
chosen to be a smaller value or none at all, then the BOOT capacitor can charge through the LED string itself.
However, this method of charging the BOOT capacitor will result in longer startup times.
The output capacitor also reduces the high-frequency ripple current through the LED string. Various guidelines
disclose how much high-frequency ripple current is acceptable in the LED string. Excessive ripple current in the
LED string increases the RMS current in the LED string, and therefore the LED temperature also increases. First,
calculate the total dynamic resistance of the LED string (RLED) using the LED manufacturer’s data sheet. Second,
calculate the required impedance of the output capacitor (ZOUT) given the acceptable peak-to-peak ripple current
through the LED string, ΔILED. IRIPPLE is the peak-to-peak inductor ripple current as calculated previously in
Inductor Selection. Third, calculate the minimum effective output capacitance required. Finally, increase the
output capacitance appropriately due to the derating effect of applied dc voltage. See 公式 24, 公式 25, and 公式
26.
DVF
RLED
=
´ # of LEDs
DIF
(24)
(25)
(26)
R
LED ´DILED
ZCOUT
=
IRIPPLE - DILED
1
COUT
=
2´ p´ fSW ´ ZCOUT
9.1.4 Rectifier Diode Selection
The rectifier diode conducts the inductor current only during the high-side MOSFET off-time. The rectifier diode
must have a reverse voltage rating greater than the maximum input voltage and a current rating greater than the
peak inductor current. A Schottky diode is recommended for highest efficiency and optimal performance. The
package size chosen for the rectifier diode must be capable of handling the power dissipation of the diode. The
diode power dissipation is equal to the average diode current times the diode forward voltage, VF. See 公式 27
and 公式 28.
ID _ AVE = ILED(1- D)
(27)
PDIODE = ID _ AVE ´ VF
(28)
When calculating the diode average current, the worst case duty cycle, D, for the diode should be used. D should
be calculated using the maximum input voltage for the application in this case.
9.1.5 Output Protection Clamp (Optional)
In the event of an output open circuit during normal operation the output voltage will rise up to the input voltage.
This is a safe operating mode provided the output capacitor can sustain the voltage without damage. However,
the inductor will still have energy stored at the moment of the event. This can cause significant ringing between
the inductor and output capacitor that can shoot higher than VIN. To prevent this, a single Schottky diode from
VOUT to VIN can be used to clamp the ringing. This diode should be rated for at least 500 mA and have a voltage
rating greater than or equal to the voltage rating of the rectifier diode. A zener diode across the output capacitor
can also be used to clamp the output voltage to a lower level. The output will clamp at the zener voltage plus the
ISENSE voltage since when the zener begins to conduct it will pull the ISENSE pin up and reduce the duty cycle.
16
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9.2 Typical Application
The TPS92513 is a switching regulator designed to provide tight current regulation and high performance over a
wide range of conditions. The following application is a design example for a wide input voltage range, high
current regulator.
图 13 shows the schematic for the wide input voltage range converter with the design requirements below. A
detailed design procedure to calculate various component values follows.
CBOOT
6
1
0.1 PF
0.01 PF
10 0ꢀ
IADJ
BOOT
L
U1
TPS92513
33 µH
VIN
2
4
3
8
5
VIN
PH 10
R1
176 Nꢀ
PDIM
UVLO
COMP
D
COUT
4.7 PF
CIN
10 PF
1 Nꢀ
RT/CLK ISENSE
7
R2
19.3 Nꢀ
GND
9
RISENSE
0.2
0.5 W
CCOMP
0.1 µF
RRT
200 Nꢀ
图 13. High Current, Low LED Current Ripple Buck Converter
9.3 Design Requirements
•
•
•
•
•
•
VIN range of 12 V to 48 V
UVLO set to 12 V with 0.8 V hysteresis
3 LED output, 9.7 V stack, VOUT = 10 V
1.5A LED current (at VISENSE = 300 mV for best accuracy)
Switching frequency of 570 kHz
LED current ripple of 10 mA or less
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9.4 Detailed Design Procedure
This section provides a detailed design procedure for selecting the component values for the application with the
given design requirements.
9.4.1 Standard Component Selection
Choose a 0.1 µF ceramic capacitor with a 10 V or greater rating for CCOMP and CBOOT. Connect IADJ to VIN
through a 10 MΩ resistor to clamp it at 1.8 V and provide an ISENSE voltage regulation point of 300 mV.
Connect a 10 nF capacitor from IADJ to ground. Connect ISENSE to R(ISENSE) through a 1 kΩ resistor.
9.4.2 Calculate UVLO Resistor Values
Using 公式 1 and 公式 2 the UVLO resistors R1 and R2 can be calculated using 公式 29, 公式 30, and the
following parameters:
•
•
•
VSTART = 12 V
VSTOP = 11.2 V
VHYS = 0.8 V
0.8´ 1.22 V - 1 µA ´10 kW - 2.9 µA ´10 kW´12 V
(
)
)
(
R1=
= 175 kW
2.9 µA ´1.22 V
(29)
Choose the closest standard 1% value of 176 kΩ for R1. This value can then be used to calculate the value of
R2 as shown in 公式 30.
174 kW´ 1.22 V - 10 kW ´ 1 µA + 2.9 µA
(
)
)
)
(
(
R2=
= 19.2 kW
11.2 V -1.22 V + 1 µA + 2.9 µA ´ 174 kW +10 kW
) (
(
) (
)
(30)
Choose the closest standard 1% value of 19.3 kΩ for R2.
9.4.3 Calculate the RT Resistor Value (RRT
)
The desired switching frequency is 570 kHz, so the value of RRT can be calculated using 公式 5 as shown in 公
式 31.
206033
RRT kW =
= 201.6 kW
( )
1.092
570
( )
(31)
Choose the closest standard 1% value of 200 kΩ for RRT
.
9.4.4 Calculate the ISENSE Resistor Value (R(ISENSE)
)
This design uses a VISENSE voltage of 300 mV and the desired LED current (ILED) is 1.5 A. Given these values the
sense resistor value can be calculated using 公式 8 as shown in 公式 32.
300 mV
RISENSE
=
= 0.2 W
1.5 A
(32)
0.2 Ω is a standard 1% resistor value. The power dissipation is VISENSE multiplied by ILED, in this case 0.45 W.
Choose a 0.5 W or greater resistor.
9.4.5 Calculate the Inductor Value and Operating Parameters (L)
For this application, low LED ripple current is important. One way to reduce LED ripple current is to reduce
inductor ripple current. For this low ripple current application, the maximum inductor value (minimum 75 mA
current ripple IR) will be calculated and the next lower value will be used. The maximum inductor value can be
calculated using 公式 18 as shown in 公式 33.
10 V ´ 12 V -10 V
(
)
75 mA ´12 V ´570 kHz
L =
= 39 mH
(33)
Choose the next lowest standard value of 33 µH. Now the actual inductor current ripple, the peak inductor
current, and the RMS inductor current can be calculated using 公式 19, 公式 20, and 公式 21 as shown in 公式
34, 公式 35, and 公式 36.
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Detailed Design Procedure (接下页)
10 V ´ 12 V -10 V
(
)
33 mH´12 V ´570 kHz
IRIPPLE
=
= 89 mA
(34)
(35)
88mA
IL _PEAK =1.5A +
= 1.544A
2
88mA2
12
I
L _RMS = 1.5A2 +
= 1.5002A
(36)
The inductor chosen should have a saturation current rating higher than IL_PEAK and a DC current rating higher
than IL_RMS
.
9.4.6 Calculate the Minimum Input Capacitance and the Required RMS Current Rating (CIN)
Given a minimum of 2 µF of capacitance for every 1 A of LED current, a 1.5 A design would require a minimum
of 3 µF. To account for ceramic capacitor tolerances and capacitance drops due to bias voltage this capacitance
should be at least doubled. Higher values will also give better overall performance. Choose a 10 µF capacitor
with a voltage rating of 50 V or greater. Using 公式 13, 公式 22, and 公式 23 the user can calculate the RMS
current rating required for the capacitor and the resulting input voltage ripple as shown in 公式 38 and 公式 39.
10V
D=
= 0.83
12V
(37)
(38)
I
=1.5A ´ 0.83´ 1- 0.83 = 0.56A
)
(
IN_RMS
1.5 A ´0.83´ 1-10.83
(
10 mF´570 kHz
)
DVIN =
= 37 mV
(39)
9.4.7 Calculate the Output Capacitor Value (COUT
)
The required output capacitor value to get the required LED ripple current can be calculated by first determining
the dynamic resistance of the LEDs used, RLED, by using the forward voltage versus forward current graph in the
manufacturer’s datasheet. Place a tangent line on the curve at the forward current required to get the slope and
the corresponding ΔV and ΔF. For this design example, the RLED is 0.22 Ω per LED. So the total RLED is 0.22 Ω
X 3, or 0.66 Ω. Then find the required output impedance, ZCOUT, using 公式 25 as shown in 公式 40. Using the
required ZCOUT calculate the minimum output capacitance using 公式 26 as shown in 公式 41.
0.66W ´10mA
ZCOUT
=
= 0.0835W
89mA -10mA
(40)
(41)
1
COUT
=
= 3.34mF
2´ p´ 570kHz ´ 0.0835W
Choose a 4.7 µF ceramic capacitor with a X5R or X7R dielectric and 16 V or greater voltage rating.
9.4.8 Calculate the Diode Power Dissipation (D)
The maximum input voltage is 48 V, so a 60 V or greater Schottky diode should be used for this application.
Calculate the required current rating and power dissipation to size the diode correctly. This should be done at the
maximum input voltage since that is where the diode conducts for the most time and will have the highest power
dissipation. The duty cycle, D, at the maximum input voltage is 10 V/48 V, or 0.208. Using this duty cycle and 公
式 27 calculate the average diode current, ID_AVE, as shown in 公式 42. Then calculate the diode power
dissipation, PDIODE, using 公式 28 as shown in 公式 43.
ID _ AVE = 1.5 A ´ 1- 0.208 = 1.19 A
)
(
(42)
(43)
PDIODE = 1.19 A ´0.7 V = 0.833 W
The power dissipation calculation is assuming a diode forward voltage drop, VF, of 0.7 V. If a diode with a
different forward drop is chosen the calculation should be re-done. Choose a Schottky diode with a 1.5 A or
greater current rating that can dissipate at least 1 W of power.
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9.5 Application Curves
PDIM
PDIM
LED Current
LED Current
Time = 40 ms/div
Time = 1 ms/div
,
图 15. 50% Duty Cycle, 250 Hz PWM Dimming
图 14. 1% Duty Cycle, 250 Hz PWM Dimming
PDIM
LED Current
Time = 1 ms/div
图 16. 99% Duty Cycle, 250 Hz PWM Dimming
10 Power Supply Recommendations
Use any DC output power supply with a maximum voltage high enough for the application. The power supply
should have a current limit of at least 3A.
20
版权 © 2015, Texas Instruments Incorporated
TPS92513, TPS92513HV
www.ti.com.cn
ZHCSDR0 –APRIL 2015
11 Layout
The TPS92513 requires a proper layout for optimal performance. The following section gives some guidelines to
ensure a proper layout.
11.1 Layout Guidelines
An example of a proper layout for the TPS92513 is shown in 图 17. Creating a large GND plane under the
integrated circuit (IC) for good electrical and thermal performance is important.
•
•
The GND pin of the device must connect to the GND plane directly beneath the IC.
Thermal vias can be used to connect the topside GND plane to additional printed-circuit board (PCB) layers
for heat spreading and more solid grounding.
•
•
The input capacitors must be located as close as possible to the VIN pin and the GND plane and should be
tied to a solid backside ground plane using multiple vias.
The compensation components must be located as close as possible to the COMP and GND pins in order to
minimize noise sensitivity.
•
•
•
•
The PH trace must be kept as short as possible to reduce the possibility of radiated noise/EMI.
The ISENSE node should be kept as short as possible and shielded from noise.
The RT/CLK pin is sensitive and its routing must be kept as short as possible.
In higher current applications, routing the load current of the current-sense resistor to the junction of the input
capacitor and rectifier diode GND node may be necessary. The easiest way to accomplish this is to use a
backside ground plane and arrays of vias to connect the top side ground connections solidly to the backside
plane. This steers the high current away from the sensitive RT/CLK to GND connection.
•
If possible, the current loop created when the internal MOSFET is on should be in the same direction as the
current loop when the internal MOSFET is off and the schottky diode is conducting. This will prevent magnetic
field reversal, reduce radiated noise, and simplify EMI filtering.
11.2 Layout Example
L
GND
LED+
+
D
CBOOT
COUT
CIN
BOOT
PH
VIN
RISENSE
-
CCOMP
VIN
GND
LED-
UVLO
COMP
RUVLO
PDIM
ISENSE
IADJ
RP
RT/CLK
RUVLO
RRT
RIADJ
GND
THERMAL/POWER VIA
图 17. Layout Example
版权 © 2015, Texas Instruments Incorporated
21
TPS92513, TPS92513HV
ZHCSDR0 –APRIL 2015
www.ti.com.cn
12 器件和文档支持
12.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TPS92513
TPS92513HV
12.2 商标
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS92513DGQR
TPS92513DGQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HVSSOP
HVSSOP
HVSSOP
HVSSOP
DGQ
DGQ
DGQ
DGQ
10
10
10
10
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
92513
92513
513H
513H
NIPDAUAG
NIPDAUAG
NIPDAUAG
TPS92513HVDGQR
TPS92513HVDGQT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
DGQ 10
3 x 3, 0.5 mm pitch
PowerPADTM HVSSOP - 1.1 mm max height
PLASTIC SMALL OUTLINE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224775/A
www.ti.com
PACKAGE OUTLINE
DGQ0010D
PowerPADTM - 1.1 mm max height
S
C
A
L
E
3
.
7
0
0
PLASTIC SMALL OUTLINE
C
5.05
4.75
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.08
C A B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
EXPOSED
THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.69
0.15
0.05
0.7
0.4
8
0 - 8
1
DETAIL A
TYPICAL
1.83
1.63
4218842/A 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA-T.
www.ti.com
EXAMPLE BOARD LAYOUT
DGQ0010D
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(2.2)
NOTE 9
(1.83)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED PAD
SEE DETAILS
10X (1.45)
10X (0.3)
1
10
(1.3)
TYP
(1.89)
SOLDER MASK
OPENING
SYMM
(3.1)
NOTE 9
8X (0.5)
6
5
(R0.05) TYP
SYMM
METAL COVERED
BY SOLDER MASK
(
0.2) TYP
VIA
(1.3) TYP
(4.4)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218842/A 01/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGQ0010D
PowerPADTM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(1.83)
BASED ON
0.125 THICK
STENCIL
10X (1.45)
10X (0.3)
1
10
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
8X (0.5)
5
6
(R0.05) TYP
SEE TABLE FOR
SYMM
(4.4)
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
METAL COVERED
BY SOLDER MASK
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.05 X 2.11
1.83 X 1.89 (SHOWN)
1.67 X 1.73
0.125
0.150
0.175
1.55 X 1.60
4218842/A 01/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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