TPS82130SILR [TI]
具有集成电感器的 17V 输入电压、3A 降压转换器模块 | SIL | 8 | -40 to 125;
| 型号： | TPS82130SILR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电感器的 17V 输入电压、3A 降压转换器模块 | SIL | 8 | -40 to 125 开关 电感器 转换器 |
| 文件： | 总28页 (文件大小：1587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS82130
ZHCSEM3F –FEBRUARY 2016 –REVISED JANUARY 2023
TPS82130 具有集成电感器的17V 输入3A 降压转换器MicroSiP™ 电源模块
1 特性
3 说明
• 3mm × 2.8mm × 1.5mm MicroSiP 封装
• 3V 至17V 输入范围
• 3A 持续输出电流
• DCS-Control 拓扑
• 可实现轻负载效率的省电模式
• 20µA 工作静态电流
TPS82130 是一款 17V 输入 3A 降压转换器 MicroSiP
电源模块，经优化具有小解决方案尺寸和高效率等特
性。该模块集成了一个同步降压转换器和一个电感器，
以简化设计、减少外部元件数量并缩小 PCB 面积。该
模块采用紧凑的薄型封装，适合通过标准表面贴装设备
进行自动组装。
• 0.9V 至6V 可调节输出电压
• 可实现最低压降的100% 占空比
• 电源正常状态输出
• 具有跟踪功能的可编程软启动
• 热关断保护
为了更大限度地提高效率，该转换器以 2MHz 的标称
开关频率在PWM 模式下工作，
并且会在轻负载电流条件下自动进入省电模式。在省电
模式下，该器件以 20µA（典型值）的静态电流运行。
通过使用 DCS-Control 拓扑，该器件可实现出色的负
载瞬态性能和精确的输出稳压。
• –40°C 至125°C 工作温度范围
• 提供普通话数据表
• 使用TPS82130 并借助WEBENCH® Power
封装信息
封装(1)
Designer 创建定制设计
封装尺寸（标称值）
器件型号
TPS82130
SIL（µSiL，8）
3.00mm × 2.80mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 工业应用
• 电信和网络应用
• 固态硬盘
100
90
TPS82130
VIN
VOUT
VIN
VOUT
1.8 V / 3 A
12 V
C1
10 µF
C2
22 µF
R1
R3
124 kΩ 100 kΩ
EN
SS/TR
FB
C3
3.3 nF
R2
100 kΩ
PG
80
GND
POWER GOOD
70
1.8V 输出应用简化原理图
VOUT = 1.0 V
VOUT = 1.8 V
60
VOUT = 2.5 V
VOUT = 3.3 V
50
1m
10m
100m
Load (A)
1
5
D017
12V 输入电压效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSCY5
TPS82130
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ZHCSEM3F –FEBRUARY 2016 –REVISED JANUARY 2023
内容
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 规格................................................................................... 4
6.1 绝对最大额定值...........................................................4
6.2 ESD 等级.................................................................... 4
6.3 建议运行条件.............................................................. 4
6.4 热性能信息..................................................................4
6.5 电气特性......................................................................5
6.6 典型特性......................................................................6
7 Detailed Description........................................................7
7.1 概述.............................................................................7
7.2 Functional Block Diagram...........................................7
7.3 特性说明......................................................................7
7.4 器件功能模式.............................................................. 8
8 应用和实现.......................................................................11
8.1 应用信息....................................................................11
8.2 Typical Applications...................................................11
8.3 电源建议....................................................................17
8.4 布局...........................................................................17
9 器件和文档支持............................................................... 18
9.1 器件支持....................................................................18
9.2 Documentation Support............................................ 18
9.3 接收文档更新通知..................................................... 18
9.4 支持资源....................................................................18
9.5 商标...........................................................................18
9.6 术语表....................................................................... 18
9.7 静电放电警告............................................................ 19
10 机械、封装和可订购信息...............................................20
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (October 2021) to Revision F (January 2023)
Page
• 添加了指向翻译后普通话数据表的超链接...........................................................................................................1
• 更新的商标信息...................................................................................................................................................1
• Added Documentation Support section............................................................................................................ 18
Changes from Revision D (November 2018) to Revision E (October 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
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5 Pin Configuration and Functions
EN
VIN
1
2
3
4
8
7
6
5
SS/TR
PG
Thermal
Pad
GND
VOUT
FB
VOUT
Not to scale
图5-1. SIL 8-Pin µSiL Package (SIL0008C Top View)
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Enable pin. Pull High to enable the device. Pull Low to disable the device. This pin has an
internal pulldown resistor of typically 400 kΩwhen the device is disabled.
EN
1
I
VIN
2
3
PWR
Input pin
GND
VOUT
Ground pin
Output pin
4, 5
PWR
I
Feedback reference pin. An external resistor divider connected to this pin programs the
output voltage.
FB
6
7
8
Power-good open-drain output pin. A pullup resistor can be connected to any voltage less
than 6 V. Leave this pin open if it is not used.
PG
O
I
Soft start-up and voltage tracking pin. An external capacitor connected to this pin sets the
internal reference voltage rising time.
SS/TR
The exposed thermal pad must be connected to the GND pin. Must be soldered to
achieve appropriate power dissipation and mechanical reliability.
Exposed Thermal Pad
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6 规格
6.1 绝对最大额定值
最小值
-0.3
最大值
20
单位
VIN
-0.3
VIN + 0.3
EN、SS/TR
引脚处的电压(1) (2)
V
7
7
PG、FB
–0.3
VOUT
0
灌电流(1)
PG
10
125
125
mA
°C
模块工作温度(1)
贮存温度(1)
-40
°C
–55
(1) 超出那些最大绝对额定值下列出的压力可能会对器件造成永久损坏。这些仅为在压力额定值，并不表明器件在这些额定值下或者任何其
它超过建议工作条件所标明的条件下可正常工作。长时间处于最大绝对额定情况下可影响设备的可靠性。
(2) 所有电压值都是相对于网络接地引脚的值。
6.2 ESD 等级
值
单位
人体放电模式（HBM），符合ANSI/ESDA/JEDEC JS-001(1)
充电器件模式（CDM），符合JEDEC 规范JESD22-C101(2)
±2000
V(ESD)
V
静电放电
±1000
(1) JEDEC 文件JEP155 规定：500V HBM 可实现在标准ESD 控制流程下安全生产。
(2) JEDEC 文件JEP157 规定：250V CDM 可实现在标准ESD 控制流程下安全生产。
6.3 建议运行条件
在自然通风温度范围内测得，除非另有说明。
最小值
最大值
单位
V
VIN
3
17
6
输入电压
VPG
VOUT
IOUT
TJ
V
电源正常上拉电阻器电压
0.9
0
6
V
输出电压
3
A
输出电流
可实现100,000 小时寿命的模块工作温度范围(1)
-40
110
°C
(1) 模块工作温度范围包含模块自温升和IC 结温升。在存在高功率耗散的应用中，必须降低最高工作温度或最大输出电流。对于模块在125
°C 温度下连续运行的应用，最长寿命减少至50,000 小时。
6.4 热性能信息
TPS82130
（JEDEC 51-5）
热指标(1)
TPS82130EVM-720
单位
°C/W
°C/W
RθJA
58.2
46.1
9.4
结至环境热阻
Rθ
9.4
结至外壳（顶部）热阻
JC(top)
RθJB
ψJT
14.4
0.9
14.4
0.9
°C/W
°C/W
°C/W
结至电路板热阻
结至顶部特征参数
结至电路板特征参数
14.2
14.0
ψJB
Rθ
21.3
21.3
°C/W
结至外壳（底部）热阻
JC(bot)
(1) 有关新旧热指标的更多信息，请参阅《半导体和IC 封装热指标》应用报告。可以使用包含散热过孔的定制PCB 设计（如可能）来改善
θJA。
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6.5 电气特性
TJ = –40°C 至125°C 且VIN = 3.0V 至17V。除非另有说明，否则典型值是TJ = 25°C 且VIN = 12V 条件下的典型值。
参数
测试条件
最小 典型 最大 单位
值
值
值
电源
IQ
20
35
µA
µA
V
流入VIN 的静态电流
流入VIN 的关断电流
无负载，器件未进行开关
EN = 低电平
VIN 下降
ISD
1.5 7.4
2.7 2.8
2.9 3.0
160
2.6
2.8
VUVLO
欠压闭锁阈值
热关断阈值
V
VIN 上升
°C
°C
TJ 上升
TJSD
140
TJ 下降
逻辑接口（EN）
VIH
0.9 0.65
0.45 0.3
0.01
V
V
高电平输入电压
VIL
低电平输入电压
Ilkg(EN)
1
µA
流入EN 引脚的输入泄漏电流
EN = 高电平
控制（SS/TR、PG）
ISS/TR
VPG
VPG,OL
2.1
2.5 2.8
µA
SS/TR 引脚拉电流
92% 95% 99%
87% 90% 94%
0.1 0.3
V
V
OUT 上升，以VOUT 标称值为基准
OUT 下降，以VOUT 标称值为基准
电源正常阈值
Isink = 2 mA
VPG = 1.8V
V
电源正常低电平电压
Ilkg(PG)
1
400
nA
流入PG 引脚的输入泄漏电流
输出
VFB
785 800 815
788 800 812
785 800 823
788 800 815
PWM 模式
TJ = 0°C 至85°C
mV
反馈调节电压
COUT = 22µF
PSM
COUT = 2 × 22µF，TJ = 0°C 至85°C
Ilkg(FB)
VFB = 0.8 V
1
0.002
0.12
100
nA
反馈输入泄漏电流
线调节
IOUT = 1A，VOUT = 1.8V
%/V
%/A
IOUT = 0.5A 至3A，VOUT = 1.8V
负载调节
电源开关
90 170
120
40
ISW = 500mA，VIN ≥6V
ISW = 500mA，VIN = 3V
ISW = 500mA，VIN ≥6V
ISW = 500mA，VIN = 3V
100% 模式，VIN ≥6V
100% 模式，VIN = 3V
VIN = 6V，TA = 25°C
高侧FET 导通电阻
RDS(on
mΩ
mΩ
)
70
低侧FET 导通电阻
50
125
160
RDP
压降电阻
ILIMF
fSW
3.6
4.2 4.9
2.0
A
高侧FET 开关电流限制
PWM 开关频率
IOUT = 1A，VOUT = 1.8V
MHz
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6.6 典型特性
250
50
40
30
20
10
0
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
200
150
100
VIN = 3.0 V
VIN = 6.0 V
50
-40
-20
0
20
40
60
Module Temperature (°C)
80
100
120
3
5
7
9
11
Input Voltage (V)
13
15
17
D014
D025
图6-1. 压降电阻
图6-2. 静态电流
8
6
4
2
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0
3
5
7
9
11
Input Voltage (V)
13
15
17
D026
图6-3. 关断电流
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7 Detailed Description
7.1 概述
TPS82130 同步降压转换器 MicroSiP 电源模块基于 DCS-Control（可无缝转换到省电模式的直接控制）。DCS-
Control 是一种高级调节拓扑，兼具磁滞和电压模式控制的优势。
DCS-Control 拓扑可以在中等负载至重负载条件下以 PWM（脉宽调制）模式运行，也可以在轻负载电流下以
PSM（省电模式）运行。在 PWM 模式下，该转换器以其 2.0MHz 的标称开关频率运行，并且在输入电压范围内
的频率变化可控。随着负载电流的降低，转换器进入省电模式、降低开关频率并最大限度地降低IC 的静态电流，
可在整个负载电流范围内实现高效率。DCS-Control 使用单个构建块支持两种运行模式，因此可以从 PWM 无缝
转换到 PSM，而不会影响输出电压。TPS82130 提供出色的直流电压调节和负载瞬态调节，并具有低输出电压纹
波，可最大限度地减少对射频电路的干扰。
7.2 Functional Block Diagram
PG
EN
VIN
VFB
High Side
Current Sense
VREF
Bandgap
Undervoltage Lockout
Thermal Shutdown
L(2)
400 kΩ(1)
MOSFET Driver
Control Logic
VIN
Ramp
Direct Control
and
Compensation
VOUT
Voltage
Clamp
VREF
22 pF
SS/TR
Timer
ton
FB
Comparator
VREF
Error Amplifier
GND
Note:
(1) When the device is enabled, the 400 kΩ resistor is disconnected.
(2) The integrated inductor of 1 µH in the module.
7.3 特性说明
7.3.1 PWM 和PSM 运行
TPS82130 包含导通时间（tON）电路。在PWM 和PSM 模式下稳态运行时，可通过以下公式来估算tON
：
VOUT
tON = 500ns´
V
IN
(1)
在 PWM 模式下，TPS82130 在连续导通模式（CCM）以及中高负载电流下以脉宽调制模式运行，其 tON 如方程
式 1 所示。该 tON 电路可实现典型值为 2.0MHz 的 PWM 开关频率。只要输出电流高于电感器纹波电流（可通过
方程式2 进行估算）的一半，器件就会以PWM 模式运行。
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VIN - VOUT
DIL = tON
´
L
(2)
为了在轻负载时保持高效率，器件会在负载电流降低时无缝进入省电模式。当负载电流小于电感器纹波电流的一
半时，就会发生这种情况。在 PSM 模式下，转换器以更低的开关频率和最小静态电流运行来保持高效率。PSM
也基于tON 电路。可通过以下公式来估算PSM 模式下的开关频率：
2´IOUT
fPSM
=
V
VIN - VOUT
2
IN
´
tON
´
VOUT
L
(3)
在PSM 模式下，输出电压略高于 PWM 模式下的标称输出电压。可通过增大输出电容来降低该影响。节6.5 反映
了PSM 运行模式下的输出电压精度，针对22µF 输出电容器提供。
对于非常小的输出电压，会保持大约 80ns 的绝对最小导通时间，以便限制开关损耗。工作频率因此低于其标称
值，从而保持高效率。此外，在高占空比下，关断时间可以达到其最小值。在这种情况下，输出电压保持稳定。
当VIN 降低至比VOUT 高15%（典型值）时，无论负载电流如何，TPS82130 都无法进入省电模式。器件在PWM
模式下保持输出稳压状态。
7.3.2 低压降运行（100% 占空比）
TPS82130 通过进入100% 占空比模式提供低输入到输出电压差动。在该模式下，高侧MOSFET 开关始终开启。
该特性在电池供电应用中特别有用，可通过充分利用整个电池电压范围来实现最长的运行时间。可通过以下公式
来计算用于维持最小输出电压的最小输入电压：
V
= VOUT(min) + IOUT ´RDP
IN(min)
(4)
其中
• RDP = VIN 和VOUT 之间的电阻，包括高侧FET 导通电阻和电感器的直流电阻
• VOUT(min) = 负载可以接受的最低输出电压
7.3.3 开关电流限值
开关电流限值可防止器件出现高电感器电流和从电池或输入电压轨汲取过大的电流。在重负载/输出电路短路的情
况下可能会出现过大的电流。如果电感器峰值电流在30ns（典型值）的传播延迟后达到开关电流限值，高侧FET
将关闭，低侧FET 则会开启，从而减小电感器电流。
7.3.4 欠压锁定
为了避免器件在低输入电压下误操作，可进行欠压锁定，从而在电压低于VUVLO 时以200mV 的迟滞关闭器件。
7.3.5 Thermal Shutdown
The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. After
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
7.4 器件功能模式
7.4.1 启用和禁用（EN）
可以通过将 EN 引脚设置为逻辑高电平来启用器件。因此，如果 EN 引脚以典型值为1.5μA 的关断电流拉低，则
会强制实现关断模式。
当EN 引脚为低电平时，内部400kΩ下拉电阻器连接到EN 引脚。当EN 引脚为高电平时，下拉电阻器断开。
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7.4.2 软启动（SS/TR）
内部电压钳位控制启动期间的输出电压斜率。这可以避免过大的浪涌电流并确保受控的输出电压上升时间。当EN
引脚被拉高时，器件会在 55μs（典型值）的延迟后开始开关，并且输出电压以由连接到 SS/TR 引脚的外部电容
器控制的斜率上升。通过使用非常小的电容器或使SS/TR 引脚悬空，可实现最快的启动时间。
TPS82130 能够启动至预偏置输出电容器。在预偏置启动期间，在内部电压钳位将输出电压设置为高于预偏置电
压之前，两个功率MOSFET 无法开启。
当器件处于关断、欠压锁定或热关断状态时，连接到 SS/TR 引脚的电容器由内部电阻器放电。从这些状态返回会
导致新的启动序列。
7.4.3 电压跟踪（SS/TR）
SS/TR 引脚由另一个电压源从外部进行驱动，以实现输出电压跟踪。图7-1 显示了应用电路。
VOUT1
VOUT2
TPS82130
R1
R3
SS/TR
FB
R2
R4
Copyright © 2016, Texas Instruments Incorporated
图7-1. 输出电压跟踪
当SS/TR 引脚电压介于50mV 和1.2V 之间时，VOUT2 会跟踪VOUT1，如方程式5 所示。
VOUT2
R2
R3 + R4
» 0.64 ´
´
VOUT1
R1+ R2
R4
(5)
当SS/TR 引脚电压高于 1.2V 时，禁用电压跟踪，FB 引脚电压被调节为0.8V。为了降低 SS/TR 引脚电压，器件
不会从输出端灌入电流，因此，如果负载较轻，则导致的输出电压下降速度可能比 SS/TR 引脚电压慢。在使用外
部电压驱动SS/TR 引脚时，不要超过SS/TR 引脚的额定电压，即VIN + 0.3V。
有关跟踪和时序控制电路的详细信息，请参阅《使用 TPS621 系列和 TPS821 系列进行时序控制和跟踪应用报
告》。
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7.4.4 电源正常输出（PG）
该器件具有电源正常（PG） 输出输出高于标称电压的 95% 时，PG 引脚会变为高阻抗；输出电压低于标称电压
的 90%（典型值）时，PG 引脚会被驱动为低电平。PG 引脚是开漏输出，其额定灌电流不超过 2mA。电源正常
输出需要使用一个连接到任何低于6V 的电压轨的上拉电阻器。
通过将 PG 信号连接到其他转换器的 EN 引脚，可以使用 PG 信号对多个电源轨进行时序控制。未使用 PG 引脚
时，应将其保持悬空状态。表7-1 显示了PG 引脚逻辑。
表7-1. 电源正常引脚逻辑
PG 逻辑状态
器件状态
高阻抗
√
低电平
VFB ≥VTH_PG
VFB ≤VTH_PG
启用（EN = 高电平）
√
√
√
√
关断（EN = 低电平）
UVLO
0.7V < VIN < VUVLO
TJ > TSD
热关断
VIN < 0.7V
电源移除
√
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8 应用和实现
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 应用信息
可通过元件选择来调节 TPS82130 的输出电压。以下部分介绍了外部元件的设计，通过使用典型应用作为参考来
完成多个输入和输出电压选项的电源设计。
8.2 Typical Applications
8.2.1 1.8-V Output Application
TPS82130
VIN
VOUT
VIN
VOUT
1.8 V / 3 A
12 V
C1
10 µF
C2
22 µF
R1
R3
124 kΩ 100 kΩ
EN
SS/TR
FB
C3
3.3 nF
R2
100 kΩ
PG
GND
POWER GOOD
图8-1. 1.8-V Output Application
表8-1. 设计参数
8.2.1.1 设计要求
本设计示例使用以下参数作为输入参数。
设计参数
输入电压范围
示例值
12V
1.8V
< 20mV
3A
输出电压
输出纹波电压
输出电流额定值
下表提供了用于测量的元件。
表8-2. 元件列表
说明
基准
制造商
10µF，25V，X7R，±20%，尺寸1206，
C1
C2
TDK
TDK
C3216X7R1E106M160AE
22µF，10V，±20%，X7S，尺寸0805，
C2012X7S1A226M125AC
3300pF，50V，±5%，C0G/NP0，尺寸0603，
GRM1885C1H332JA01D
C3
Murata
R1，R2，R3
标准
8.2.1.2 详细设计过程
8.2.1.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS82130 device with the WEBENCH Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
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2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand the thermal performance of your board
• Export your customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Setting the Output Voltage
The output voltage is set by an external resistor divider according to 方程式6:
R1
R2
R1
R2
æ
ö
æ
ö
VOUT = VFB
´
1 +
= 0.8 V ´ 1 +
ç
÷
ç
÷
è
ø
è
ø
(6)
R2 must not be higher than 100 kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity. Larger currents through R2 improve noise sensitivity and output voltage accuracy. 图 8-1 shows the
external resistor divider value for a 1.8-V output. Choose appropriate resistor values for other outputs.
In case the FB pin gets opened, the device clamps the output voltage at the VOUT pin internally to
approximately 7 V.
8.2.1.2.3 Input and Output Capacitor Selection
For the best output and input voltage filtering, low-ESR ceramic capacitors are required. The input capacitor
minimizes input voltage ripple, suppresses input voltage spikes, and provides a stable system rail for the device.
A 10-µF or larger input capacitor is required. The output capacitor value can range from 22 μF up to more than
400 μF. Higher values are possible as well and can be evaluated through the transient response. TI
recommends larger soft start times for higher output capacitances.
High capacitance ceramic capacitors have a DC bias effect, which have a strong influence on the final effective
capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in
combination with dielectric material are responsible for differences between the rated capacitor value and the
effective capacitance.
8.2.1.2.4 软启动电容器选型
SS/TR 引脚和 GND 之间连接的电容可实现对输出电压的启动斜率进行编程。2.5μA 的恒定电流为外部电容器充
电。可通过以下公式来计算实现输出电压的给定软启动时间所需的电容：
ISS/ TR
CSS/ TR = tSS/ TR
´
1.25V
(7)
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8.2.1.3 应用性能曲线
TA = 25°C，VIN = 12V，VOUT = 1.8V（除非另有说明）。
100
100
90
80
70
60
50
90
80
70
60
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
50
1m
3
3
3
5
7
9
11
Input Voltage (V)
13
15
15
15
17
10m
100m
Load (A)
1
5
D019
D001
图8-3. 效率（VOUT = 1.0V）
图8-2. 效率（VOUT = 1V）
100
100
90
80
70
60
50
90
80
70
60
50
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
1m
10m
100m
Load (A)
1
5
5
7
9 11
Input Voltage (V)
13
17
D002
D020
图8-4. 效率（VOUT = 1.8V）
图8-5. 效率（VOUT = 1.8V）
100
90
80
70
60
50
100
90
80
70
60
50
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
1m
10m
100m
Load (A)
1
5
5
7
9
11
Input Voltage (V)
13
17
D003
D021
图8-6. 效率（VOUT = 2.5V）
图8-7. 效率（VOUT = 2.5V）
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100
90
80
70
60
100
90
80
70
60
50
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
VIN = 5.0 V
VIN = 12 V
50
1m
10m
100m
Load (A)
1
5
5
7
9
11
Input Voltage (V)
13
15
17
D004
D022
图8-8. 效率（VOUT = 3.3V）
图8-9. 效率（VOUT = 3.3V）
100
90
80
70
60
50
100
90
80
70
60
50
IOUT = 0.1 A
IOUT = 1.0 A
IOUT = 3.0 A
VIN = 12 V
1
1m
10m
100m
Load (A)
5
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
D023
D024
图8-10. 效率（VOUT = 5.0V）
图8-11. 效率（VOUT = 5V）
4
3
2
1
0
4
3
2
1
0
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
VIN = 5.0 V
VIN = 12 V
45
55
65
75
Ambient Temperature (°C)
85
95
105
115
125
45
55
65
75
Ambient Temperature (°C)
85
95
105
115
125
D015
D016
VOUT = 1.8 V
VOUT = 3.3V
θJA = 46.1°C/W
θJA = 46.1°C/W
图8-12. 热降额（VOUT = 1.8V）
图8-13. 热降额（VOUT = 3.3V）
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4
1.0
0.5
3
2
1
0.0
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
VIN = 3.3 V
VIN = 5.0 V
VIN = 12 V
-1.0
0
45
1m
10m
100m
Load (A)
1
5
55
65
75
85
95
Ambient Temperature (°C)
105
115
125
D005
D027
VIN = 12V
图8-14. 热降额（VOUT = 1.0V）
图8-15. 负载调节
5x106
106
1.0
0.5
105
104
103
0.0
-0.5
TA = 25°C
TA = -40°C
TA = 85°C
TA = -40°C
TA = 25°C
TA = 85°C
-1.0
3
1m
10m
100m
Load (A)
1
5
5
7
9
11
Input Voltage (V)
13
15
17
D009
D006
VOUT = 1.8 V
VIN = 12V
IOUT = 1A
图8-17. 开关频率
图8-16. 线路调节
3x106
2x106
1x106
VIN
50mV/DIV
AC
VOUT
10mV/DIV
AC
VOUT = 1.0 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
0x100
3
Time - 500ns/DIV
5
7
9
11
Input Voltage (V)
13
15
17
D007
D018
IOUT = 3A
IOUT = 1A
图8-19. PWM 模式下的输入和输出纹波
图8-18. 开关频率
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VIN
20mV/DIV
AC
IOUT
2A/DIV
VOUT
50mV/DIV
AC
VOUT
10mV/DIV
AC
Time - 500ꢀs/DIV
Time - 20ꢀs/DIV
D008
D010
空载
IOUT = 0A 至3A，1A/µs
图8-20. PSM 模式下的输入和输出纹波
图8-21. 负载瞬态
VEN
5V/DIV
IOUT
2A/DIV
VPG
5V/DIV
VOUT
50mV/DIV
AC
VOUT
1V/DIV
IOUT
2A/DIV
Time - 20ꢀs/DIV
Time - 500ꢀs/DIV
D011
D012
IOUT = 0.5A 至3A，1A/µs
空载
图8-22. 负载瞬态
图8-23. 在空载条件下启动
VEN
5V/DIV
VPG
5V/DIV
VOUT
1V/DIV
IOUT
2A/DIV
Time - 500ꢀs/DIV
ROUT = 0.68Ω
D013
图8-24. 电阻负载下的启动/关断
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8.3 电源建议
这些器件可在3V 至17V 的输入电源电压范围内工作。可通过以下公式来计算TPS82130 的平均输入电流：
VOUT ´IOUT
1
IIN
=
´
h
V
IN
(8)
请确保电源的额定电流足以满足应用需求。
8.4 布局
8.4.1 Layout Guidelines
• TI recommends placing all components as close as possible to the IC. The input capacitor placement
specifically must be closest to the VIN and GND pins of the device.
• Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
• To enhance heat dissipation of the device, the exposed thermal pad must be connected to bottom or internal
layer ground planes using vias.
• Refer to 图8-25 for an example of component placement, routing, and thermal design.
8.4.2 布局示例
C3
VIN
C1
R2
SS/TR
EN
PG
VIN
GND
FB
VOUT
VOUT
R1
VOUT
GND
C2
图8-25. TPS82130 PCB 布局
8.4.3 Thermal Consideration
The output current of the TPS82130 must be derated when the device operates in a high ambient temperature
or delivers high output power. The amount of current derating is dependent upon the input voltage, output power,
PCB layout design, and environmental thermal condition. Care must especially be taken in applications where
the localized PCB temperature exceeds 65°C.
The TPS82130 module temperature must be kept less than the maximum rating of 125°C. Three basic
approaches for enhancing thermal performance are below:
• Improve the power dissipation capability of the PCB design.
• Improve the thermal coupling of the TPS82130 to the PCB.
• Introduce airflow into the system.
To estimate approximate module temperature of TPS82130, apply the typical efficiency stated in this data sheet
to the desired application condition to find the power dissipation of the module. Then, calculate the module
temperature rise by multiplying the power dissipation by its thermal resistance. For more details on how to use
the thermal parameters in real applications, see the Thermal Characteristics of Linear and Logic Packages Using
JEDEC PCB Designs application report and Semiconductor and IC Package Thermal Metrics application report.
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9 器件和文档支持
9.1 器件支持
9.1.1 开发支持
9.1.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.1.1.2 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS82130 device with the WEBENCH Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand the thermal performance of your board
• Export your customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
application report
• Texas Instruments, Sequencing and Tracking With the TPS621-Family and TPS821-Family application report
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 商标
MicroSiP™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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9.7 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
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10 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，
且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OUTLINE
SIL0008D
MicroSiPTM - 1.53 mm max height
S
C
A
L
E
4
.
0
0
0
MICRO SYSTEM IN PACKAGE
2.9
2.7
A
B
PIN 1 INDEX
AREA
(2.5)
3.1
2.9
PICK AREA
NOTE 3
(2)
1.53 MAX
C
0.08 C
1.1 0.1
SYMM
EXPOSED
THERMAL PAD
(0.1)
TYP
5
4
SYMM
2X
1.9 0.1
1.95
1
8
0.42
0.38
6X 0.65
8X
(45 X0.25)
PIN 1 ID
0.1
C A
C
B
0.05
0.52
0.48
8X
4221520/A 07/2015
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.3 mm or smaller recommended.
4. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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ZHCSEM3F –FEBRUARY 2016 –REVISED JANUARY 2023
EXAMPLE BOARD LAYOUT
SIL0008D
MicroSiP TM - 1.53 mm max height
MICRO SYSTEM IN PACKAGE
(1.1)
8X (0.5)
8
1
8X (0.4)
SYMM
(1.9)
(0.75)
6X (0.65)
5
4
SYMM
(2.1)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:20X
0.05 MIN
ALL SIDES
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(R0.05) TYP
DETAIL
NOT TO SCALE
4221520/A 07/2015
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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ZHCSEM3F –FEBRUARY 2016 –REVISED JANUARY 2023
EXAMPLE STENCIL DESIGN
SIL0008D
MicroSiP TM - 1.53 mm max height
MICRO SYSTEM IN PACKAGE
SOLDER MASK EDGE
(R0.05) TYP
8X (0.5)
8X (0.4)
1
(1.04)
8
METAL
TYP
(0.85)
SYMM
(1.05)
6X (0.65)
5
4
SYMM
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED SOLDER COVERAGE BY AREA
SCALE:30X
4221520/A 07/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS82130SILR
TPS82130SILT
ACTIVE
ACTIVE
uSiP
uSiP
SIL
SIL
8
8
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
H6
H6
Samples
Samples
NIAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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11-Jan-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS82130SILR
uSiP
SIL
8
3000
330.0
12.4
3.05
3.25
1.68
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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7-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
uSiP SIL
SPQ
Length (mm) Width (mm) Height (mm)
383.0 353.0 58.0
TPS82130SILR
8
3000
Pack Materials-Page 2
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