TPS7A94 [TI]
1A 超低噪声、超高 PSRR RF 稳压器;型号: | TPS7A94 |
厂家: | TEXAS INSTRUMENTS |
描述: | 1A 超低噪声、超高 PSRR RF 稳压器 稳压器 |
文件: | 总63页 (文件大小:4324K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS7A94
ZHCSOO0C –SEPTEMBER 2021 –REVISED JUNE 2023
TPS7A94 1A 超低噪声、超高PSRR 低压降稳压器
1 特性
3 说明
• 超低输出噪声:
– 0.46μVRMS(典型值10Hz 至100kHz)
• 高电源纹波抑制(PSRR):
TPS7A94 是一款超低噪声 (0.46µVRMS)、低压降
(LDO) 稳压器,能够以仅 150mV 的压降提供 1A 电
流。低压降与宽带宽误差放大器相结合,可在低工作裕
量 (500mV) 和高输出电流 (750mA) 下实现非常高的
PSRR(1kHz 时为110dB,1MHz 时为50dB)。
– 100Hz 时为102dB
– 1 kHz 时为110 dB
– 10 kHz 时为95 dB
– 100 kHz 时为78 dB
– 在1MHz 时为50dB
该器件的输出可通过外部电阻进行调节,范围为 0V 至
5.5 V。该器件凭借宽输入电压范围,支持低至1.7V 和
高达 5.7V 的操作。该器件具有可编程电流限制、可编
程PG 阈值和精密使能功能,从而能够在应用中进行更
好的控制。
• 整个线路、负载和温度范围内的精度:1%
• 低压降:150 mV (1 A)
• 宽输入电压范围:1.7 V 至5.7 V
• 宽输出电压范围:0 V 至5.5 V
• 并行通道,可实现更低的噪声和更高的电流
• 快速瞬态响应
该器件凭借高精度基准和宽带宽拓扑,可以轻松并联以
实现更低的噪声和更高的电流。
该器件具有1% 的输出电压精度(在线路、负载和温度
范围内)和软启动功能以降低浪涌电流,是为敏感模拟
低压器件供电的理想选择。
• 精密使能和UVLO
• 可编程电流限制
• 可编程PG 阈值
• 可调启动浪涌控制
• 开漏电源正常状态(PG) 输出
• 封装:3.00mm × 3.00mm 10 引脚WSON:
封装信息
封装(1)
封装尺寸(2)
器件型号
TPS7A94
DSC(WSON,10) 3.00mm × 3.00mm
– JEDEC RθJA:46.1°C/W
– EVM RθJA:25.6°C/W
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
(2) 封装尺寸(长× 宽)为标称值,并包括引脚(如适用)。
2 应用
• 宏远程无线电单元(RRU)
• 室外回程单元
• 有源天线系统mMIMO (AAS)
• 超声波扫描仪
• 实验室和现场仪表
• 传感器、成像和雷达
ENABLE
RPG
RFB_PG(BOTTOM)
RFB_PG(TOP)
Clock
Clock
PG
FB_PG
VIN
IN
CIN
OUT
SNS
VDD_VCO
COUT
GND
GND
TPS7A94
VEN_UV
EN_UV
NR/SS
GND
GND
VDD
SCLK
ADC
RNR/SS
CNR/SS
ADC
GND
典型应用电路
与输出电压无关的超低输出噪声(10Hz –100kHz)
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBVS336
TPS7A94
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ZHCSOO0C –SEPTEMBER 2021 –REVISED JUNE 2023
Table of Contents
8 Application and Implementation..................................33
8.1 Application Information............................................. 33
8.2 Typical Application.................................................... 51
8.3 Power Supply Recommendations.............................53
8.4 Layout....................................................................... 53
9 Device and Documentation Support............................55
9.1 Device Support......................................................... 55
9.2 Documentation Support............................................ 55
9.3 接收文档更新通知..................................................... 55
9.4 支持资源....................................................................55
9.5 Trademarks...............................................................56
9.6 静电放电警告............................................................ 56
9.7 术语表....................................................................... 56
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................8
7 Detailed Description......................................................28
7.1 Overview...................................................................28
7.2 Functional Block Diagram.........................................29
7.3 Feature Description...................................................30
7.4 Device Functional Modes..........................................32
Information.................................................................... 56
10.1 Mechanical Data..................................................... 57
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision B (February 2023) to Revision C (June 2023)
Page
• Deleted note regarding output current range from Optimizing Noise and PSRR section.................................42
Changes from Revision A (May 2022) to Revision B (February 2023)
Page
• Changed GND Pin Current vs IOUT and Temperature for VOUT = 3.3 V to 100% Current Limit vs Temperature
for VOUT = 1.8 V curves in Typical Characteristics section................................................................................. 8
• Changed 方程式1, 方程式2, and the discussion of these equations in Precision Enable (External UVLO)
section.............................................................................................................................................................. 34
• Changed parallel impedance value from 10 kΩ to 12.5 kΩ in Power-Good Feedback (FB_PG Pin) and Power-
Good Threshold (PG Pin) section.....................................................................................................................36
• Added Relationship Between Threshold Voltage, Output Voltage, IFAST_SS, and INR/SS During Start-Up figure
to Programmable Soft-Start and Noise-Reduction (NR/SS Pin) section.......................................................... 39
• Changed discussion of VON and VOFF in Detailed Design Procedure section..................................................52
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBVS336
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5 Pin Configuration and Functions
IN
IN
1
2
3
4
5
10
9
OUT
OUT
SNS
Thermal
Pad
EN_UV
PG
8
7
NR/SS
GND
FB_PG
6
Not to scale
图5-1. DSC Package, 10-Pin WSON (Top View)
Pin Functions
PIN
WSON
I/O(1)
DESCRIPTION
NAME
EN_UV
Precision enable and undervoltage lockout pin; see the Precision Enable (External UVLO)
3
I
section for details.
Power-good feedback pin. This pin has a dual function: this pin programs the PG pin output
threshold and scales the factory-programmed current limit value specified in the Electrical
Characteristics table to either 100%, 80%, or 60%. See the Power-Good Feedback (FB_PG Pin)
and Power-Good Threshold (PG Pin) section for details.
FB_PG
5
I
GND
IN
6
G
P
Ground pin; see the Board Layout section for details.
Input voltage supply pin; see the Recommended Capacitor Types section and the Recommended
Operating Conditions table for additional information.
1, 2
Output voltage set and noise-reduction pin; see the Programmable Soft-Start and Noise-
Reduction (NR/SS Pin) section for details.
NR/SS
OUT
PG
7
9, 10
4
I
O
O
Regulated output pin; see the Load Transient Response section for additional information.
Open-drain, power-good indicator pin for the LDO output voltage. See the Power-Good Feedback
(FB_PG Pin) and Power-Good Threshold (PG Pin) section for additional information.
Output sense pin. This pin is the input to the noninverting terminal of the error amplifier; see the
Board Layout section for details.
SNS
8
I
The thermal pad is electrically connected to the GND pin; see the Board Layout section for
details.
Thermal pad
G
(1) I = input, O = output, I/O = input or output, G = ground, P = power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range and all voltages with respect to GND(unless otherwise noted)(1)
MIN
MAX
UNIT
IN, PG, EN_UV
FB_PG
6.0
1.5
–0.3
–0.3
–0.3
–0.3
Voltage
V
OUT
VIN + 0.3
6.0
NR/SS, SNS
OUT
Internally limited
A
Current
PG (sink current into the device)
Operating junction, TJ
Storage, Tstg
5
150
150
mA
–55
–55
Temperature
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per per ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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English Data Sheet: SBVS336
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6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.7
0.4
0
TYP
MAX
5.7
UNIT
V
VIN
Input supply voltage range
Output voltage range
Output current
VOUT
IOUT
VIN - VDO
1
V
A
CIN
Input capacitor
4.7
4.7
1
10
10
1000
1000
20
µF
µF
mΩ
nH
µF
kΩ
°C
COUT
COUT_ESR
ZOUT_ESL
CNR/SS
RPG
Output capacitor
Output capacitor ESR
Total output loop impedance
Noise-reduction capacitor
Power-good pull-up resistance
Junction temperature
2
1
10
4.7
100
100
TJ
125
–40
6.4 Thermal Information
TPS7A94
DSC
DSC
THERMAL METRIC(1)
UNIT
(WSON)(2)
10 PINS
46.1
(WSON)(3)
10 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
25.6
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
35.2
-
-
19.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
0.3
11.5
-
ψJT
19
ψJB
RθJC(bot)
3.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
(2) JEDEC standard. (2s2p)
(3) EVM thermal model using JEDEC measurement methodology, see TPS7A94EVM-046 thermal analysis.
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6.5 Electrical Characteristics
over operating temperature range (TJ = –40°C to +125°C), VIN(NOM) = VOUT(NOM) + 0.5 V, VOUT(NOM) = 3.3 V, IOUT = 1 mA,
VEN = 1.8 V, CIN = COUT = 10 μF, CNR/SS = 0 nF, and PG pin pulled up to VIN with 100 kΩ (4) (unless otherwise noted); typical
values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input supply voltage range
Input supply UVLO
1.7
5.7
V
VUVLO
VHYS(UVLO)
VIN rising, no load
No load
1.6
53
1.7
V
Input supply UVLO hysteresis
40
mV
µA
VIN = 1.7 V, IOUT = 1 mA, VOUT = 1.2 V
150
1.7 V ≤VIN ≤5.5 V, 0.4 V ≤VOUT < 1.2 V, 1 mA ≤
1.5
1
%
%
–1.5
–1
INR/SS
NR/SS pin current
I
OUT ≤1A
1.7 V ≤VIN ≤5.5 V, 1.2 V ≤VOUT ≤5.1 V, 1 mA ≤
OUT ≤1A
I
2.1
1.5
VNR/SS = GND, VIN ≥2.5 V, VFB_PG < 0.2 V, IOUT = 0 mA
NR/SS fast start-up charging
current
IFAST_SS
VOUT
mA
V
VNR/SS = GND, VIN = 1.7 V, VFB_PG < 0.2 V, IOUT = 0 mA
Output voltage range
0
5.5
2
1.7 V ≤VIN ≤5.7 V, 1.2 V ≤VOUT ≤5.1 V,
1 mA ≤IOUT ≤1 A
±0.1
±0.2
–2
Output offset voltage (VNR/SS
VOUT
–
VOS
mV
)
1.7 V ≤VIN ≤5.7 V, 0.4 V ≤VOUT < 1.2 V,
1 mA ≤IOUT ≤1 A
5
–5
0.4 V ≤VOUT < 1.2 V, IOUT = 1 mA,
VIN = (VOUT + 0.5 V) to 5.7 V
–0.9
2
nA/V
µV/V
Line regulation: ΔINR/SS
VOUT = 1.2 V and VOUT = 3.3 V, IOUT = 1mA,
VIN = (VOUT + 0.5V) to 5.7 V
ΔVOUT(ΔVIN)
0.4 V ≤VOUT < 1.2 V, IOUT = 1 mA,
VIN = (VOUT + 0.5 V) to 5.7 V
–4.5
2.1
Line regulation: ΔVOS
VOUT = 1.2 V & VOUT = 3.3 V, IOUT = 1 mA,
VIN = (VOUT + 0.5 V) to 5.7 V
2.3
–3.6
–21
VIN = 1.7 V, VOUT = 1.2 V, 1 mA ≤IOUT ≤1 A
VIN = 3.8 V, VOUT = 3.3 V, 1 mA ≤IOUT ≤1 A
VIN = 5.6 V, VOUT = 5.1 V, 1 mA ≤IOUT ≤1 A
VIN = VOUT(NOM) + 0.5 V, 1.2V ≤VOUT ≤5.1 V, 1 mA ≤
(1)
nA
Load regulation: ΔINR/SS
ΔVOUT(ΔIOUT)
(1)
0.03
mV
Load regulation: ΔVOS
IOUT ≤1 A
6.3
–3.3
0.033
0.013
nA
nA
0.4 V ≤VNR/SS ≤1.5 V, VIN = 5.7 V, IOUT = 1 mA
1.5 V ≤VNR/SS ≤5 V, VIN = 5.7 V, IOUT = 1 mA
0.4 V ≤VNR/SS ≤1.5 V, VIN = 5.7 V, IOUT = 1 mA
1.5 V ≤VNR/SS ≤5 V, VIN = 5.7 V, IOUT = 1 mA
ΔINR/
Change in INR/SS vs VNR/SS
Change in VOS vs VNR/SS
SS(ΔVNR/SS)
mV
mV
ΔVOS(ΔVNR/SS)
1.7 V ≤VIN < 2.0 V, IOUT = 1 mA,
VOUT = 99% x VOUT(NOM)
160
165
140
150
1.7 V ≤VIN < 2.0 V, IOUT = 1 A,
VOUT = 99% x VOUT(NOM)
220
VDO
Dropout voltage(2)
mV
VIN ≥2.0 V, IOUT = 1 mA,
VOUT = 99% x VOUT(NOM)
VIN ≥2.0 V, IOUT = 1 A,
VOUT = 99% x VOUT(NOM)
240
1.4
VOUT forced at 90% of VOUT(NOM)
,
VIN = VOUT(NOM) + 200 mV or VIN = 1.7 V whichever is
greater, VOUT(NOM) ≥1.2 V, RPGFB-to-GND ≤12.5 kΩ
(±1%)
1.2
1.3
A
A
VOUT forced at 90% of VOUT(NOM)
VIN = VOUT(NOM) + 200 mV or VIN = 1.7 V whichever is
greater, VOUT(NOM) ≥1.2 V, RPGFB-to-GND = 50 kΩ (±1%)
,
ICL
Output current limit
0.96
0.72
1.04
1.12
0.84
VOUT forced at 90% of VOUT(NOM)
VIN = VOUT(NOM) + 200 mV or VIN = 1.7 V whichever is
greater, VOUT(NOM) ≥1.2 V, RPGFB-to-GND = 100 kΩ (±1%)
,
0.78
5
A
VIN = VOUT(NOM) + 200 mV or VIN = 1.7 V whichever is
greater, VOUT = 0 V
Output current limit variation (3)
%
ΔISC
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English Data Sheet: SBVS336
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6.5 Electrical Characteristics (continued)
over operating temperature range (TJ = –40°C to +125°C), VIN(NOM) = VOUT(NOM) + 0.5 V, VOUT(NOM) = 3.3 V, IOUT = 1 mA,
VEN = 1.8 V, CIN = COUT = 10 μF, CNR/SS = 0 nF, and PG pin pulled up to VIN with 100 kΩ (4) (unless otherwise noted); typical
values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
VIN = 5.7 V, VOUT = 5.1 V, IOUT = 0.1 mA
VIN = 1.7 V, IOUT = 1 A, VOUT = 1.2 V
PG = (open), VIN = 5.7 V, VEN_UV = 0.4 V
VIN = 5.7 V, 0 V ≤VEN_UV ≤5.5 V
MIN
TYP
MAX
UNIT
8
15
22
IGND
GND pin current
mA
34
41
51
ISDN
Shutdown GND pin current
EN_UV pin current
0.1
30
µA
µA
V
IEN_UV
1
–1
VIH(EN_UV)
VHYS(EN_UV)
EN_UV trip point rising (turn-on) VIN = 1.7 V, no load
1.20
1.22
150
1.25
EN_UV trip point hysteresis
PG delay time rising
VIN = 1.7 V, no load
mV
Time from VOUT crossing PG threshold% to PG reaching
20% of the value
tPGDH
1.1
ms
tPGDL
PG delay time falling
Time from 90% of VOUT to 80% of PG
1.7 V ≤VIN ≤5.7 V
3
0.2
6
µs
V
VFB_PG
FB_PG pin trip point (rising)
FB_PG pin hysteresis
0.19
0.21
0.4
VHYS(FB_PG)
mV
1.7 V ≤VIN ≤5.7 V
VIN = 1.7 V, VOUT < VFB_PG(threshold), IPG = –1 mA
(current into device)
VOL(PG)
PG pin low-level output voltage
V
IPG(LKG)
IFB_PG
PG pin leakage current
VIN = 5.7 V, VOUT > VFB_PG(threshold), VPG = 5.5 V
VIN = 5.7 V, VFB_PG = 0.2 V
1
µA
nA
FB_PG pin leakage current
100
–100
f = 1 MHz, VIN = 3.8 V, VOUT(NOM) = 3.3 V,
IOUT = 750 mA, CNR/SS = 4.7 µF
PSRR
Power-supply ripple rejection
Output noise voltage
51
0.46
0.835
6.6
dB
BW = 10 Hz to 100 kHz, 1.7 V ≤VIN ≤5.7 V,
VOUT(NOM) = 1.2 V, IOUT = 1.0 A, CNR/SS = 4.7 µF
Vn
µVRMS
BW = 10 Hz to 100 kHz, VIN = 1.8 V, VOUT(NOM) = 0.8 V,
IOUT = 1.0 A, CNR/SS = 4.7 µF
f = 100 Hz, 1.7 V ≤VIN ≤5.7 V, VOUT(NOM) = 1.2 V,
IOUT = 1.0 A, CNR/SS = 4.7 µF
f = 1 kHz, 1.7 V ≤VIN ≤5.7 V, VOUT(NOM) = 1.2 V,
IOUT = 1.0 A, CNR/SS = 4.7 µF
Noise spectral density
1.3
nV/√Hz
f = 10 kHz, 1.7 V ≤VIN ≤5.7 V, VOUT(NOM) = 1.2 V,
IOUT = 1.0 A, CNR/SS = 4.7 µF
1.1
NRSS active discharge
resistance
RPULLDOWN_NRSS
VIN = 1.7 V, VEN_UV = GND
VIN = 1.7 V, VEN_UV = GND
15
Ω
Ω
Output active discharge
resistance
RPULLDOWN
195
175
160
TSD(shutdown) Thermal shutdown temperature Shutdown, temperature increasing
Thermal shutdown reset
°C
TSD(reset)
Reset, temperature decreasing
temperature
(1) The device is not tested under conditions where VIN > VOUT(NOM) + 2.5 V and IOUT = 1 A because the junction temperature is higher
than +125°C. Also, this accuracy specification does not apply on any application condition that exceeds the maximum junction
temperature.
(2) Measured when output voltage drops 1% below targeted value.
(3) Brickwall current limit: ICL_% = (ISC - ICL_@0.9xVOUT) / ICL_@0.9xVOUT x 100.
(4) Additional information on setting the PG pullup resistor can be found in the application section.
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6.6 Typical Characteristics
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CNR/SS = 4.7 μF, COUT = 10 μF, VIN = 1.7 V
CNR/SS = 4.7 μF, COUT = 10 μF, VIN = 2.3 V
图6-1. PSRR vs Frequency and IOUT for VOUT = 1.2 V
图6-2. PSRR vs Frequency and IOUT for VOUT = 1.8 V
CNR/SS = 4.7 μF, COUT = 10 μF, VIN = 3.8 V
CNR/SS = 4.7 μF, COUT = 10 μF, VIN = 5.5 V
图6-3. PSRR vs Frequency and IOUT for VOUT = 3.3 V
图6-4. PSRR vs Frequency and IOUT for VOUT = 5.0 V
CNR/SS = 4.7 μF, COUT = 10 μF, VIN = VOUT + 0.5 V,
CNR/SS = 4.7 μF, COUT = 10 μF, VIN = VOUT + VOpHr,
IOUT = 750 mA
VOUT = 3.3 V, IOUT = 750 mA
图6-5. PSRR vs Frequency and Input Pairs
图6-6. PSRR vs Frequency for Operating Headroom (VOpHr)
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
VOUT = 3.3 V, CNR/SS = 4.7 μF, COUT = 10 μF
VOUT = 3.3 V, CNR/SS = 4.7 μF, COUT = 10 μF
图6-7. PSRR vs Frequency for Operating Headroom (VOpHr) and 图6-8. PSRR vs Frequency for Operating Headroom (VOpHr) and
IOUT
IOUT
VOUT = 3.3 V, CNR/SS = 4.7 μF, COUT = 10 μF
VOUT = 3.3 V, CNR/SS = 4.7 μF, COUT = 10 μF
图6-9. PSRR vs Frequency for Operating Headroom (VOpHr) and
图6-10. PSRR vs Frequency for Operating Headroom (VOpHr)
IOUT
and IOUT
COUT = 10 μF, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 250 mA
图6-11. PSRR vs Frequency and CNR/SS
CNR/SS = 4.7 μF, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 750 mA
图6-12. PSRR vs Frequency and COUT
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = VOUT + 0.5 V,
VOUT = 3.3 V, IOUT = 750 mA (10 Hz–100 kHz)
CIN = COUT = 10 μF, IOUT = 750 mA (10 Hz–100 kHz)
图6-14. Output Voltage Noise (RMS) vs CNR/SS
图6-13. Output Voltage Noise (RMS) vs Output Voltage
CIN = COUT = 10 μF, CNR/SS = 4.7 μF (10 Hz–100 kHz)
CIN = COUT = 10 μF, CNR/SS = 4.7 μF (10 Hz–100 kHz)
图6-15. Output Voltage Noise Density vs Frequency for IOUT and 图6-16. Output Voltage Noise Density vs Frequency for IOUT and
VOUT = 1.2 V
VOUT = 1.8 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF (10 Hz–100 kHz)
CIN = COUT = 10 μF, CNR/SS = 4.7 μF (10 Hz–100 kHz)
图6-17. Output Voltage Noise Density vs Frequency for IOUT and 图6-18. Output Voltage Noise Density vs Frequency for IOUT and
VOUT = 3.3 V
VOUT = 5.0 V
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, IOUT = 500 mA (10 Hz–100 kHz)
图6-19. Output Noise vs CNR/SS for VOUT = 3.3 V
CIN = COUT = 10 μF, IOUT = 750 mA (10 Hz–100 kHz)
图6-20. Output Voltage Noise (RMS) vs CNR/SS for
VOUT = 3.3 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
(10 Hz–100 kHz)
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 750 mA
(10 Hz–100 kHz)
图6-21. Output Voltage Noise Density vs Frequency and COUT
图6-22. Output Voltage Noise Density vs Frequency and Input
for VOUT = 3.3 V
Pairs
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 1.7 V,
SR = 1 A/μs
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 1.7 V,
SR = 1 A/μs
图6-23. Load Transient Response for
图6-24. Load Transient Response for
VOUT = 1.2 V, IOUT = 100 mA to 500 mA
VOUT = 1.2 V, IOUT = 100 mA to 1 A
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 3.8 V,
SR = 1 A/μs
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 3.8 V,
SR = 1 A/μs
图6-25. Load Transient Response for
图6-26. Load Transient Response for
VOUT = 3.3 V, IOUT = 100 mA to 500 mA
VOUT = 3.3 V, IOUT = 100 mA to 1 A
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 5.7 V,
SR = 1 A/μs
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 5.7 V,
SR = 1 A/μs
图6-27. Load Transient Response for
图6-28. Load Transient Response for
VOUT = 5.2 V, IOUT = 100 mA to 500 mA
VOUT = 5.2 V, IOUT = 100 mA to 1 A
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-29. Line Transient Response for VOUT = 1.2 V, IOUT = 500 mA
图6-30. Line Transient Response for VOUT = 1.2 V, IOUT = 1 A
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-31. Line Transient Response for VOUT = 3.3 V, IOUT = 500 mA
图6-32. Line Transient Response for VOUT = 3.3 V, IOUT = 1 A
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOUT = 3.3 V
图6-33. Start-Up Waveform for IOUT = 500 mA
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOUT = 3.3 V
图6-34. Start-Up Waveform for IOUT = 1 A
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOUT = 3.3 V
图6-35. Shutdown Waveform for UVLO(IN)
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOUT = 3.3 V
图6-36. Shutdown Waveform With EN
CIN = COUT = 10 μF, IOUT = 0 mA, VIN = 3.8 V,
CIN = COUT = 10 μF, IOUT = 0 mA, VIN = 3.8 V,
VOUT = 3.3 V
VOUT = 3.3 V
图6-37. Inrush Current for CNR/SS = 1.0 μF
图6-38. Inrush Current for CNR/SS = 2.2 μF
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, IOUT = 0 mA, VIN = 3.8 V,
CIN = COUT = 10 μF, IOUT = 0 mA, VIN = 3.8 V,
VOUT = 3.3 V
VOUT = 3.3 V
图6-39. Inrush Current for CNR/SS = 4.7 μF
图6-40. Inrush Current for CNR/SS = 10 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 A
图6-41. Dropout Voltage vs VIN for IOUT = 1 A
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-42. Dropout Voltage vs IOUT for VOUT = 1.8 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-43. Dropout Voltage vs IOUT for VOUT = 3.3 V
图6-44. Dropout Voltage vs IOUT for VOUT = 5.1 V
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 5.7 V,
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 5.7 V,
VOUT = 5.1 V, IOUT = 1 mA
IOUT = 1 mA
图6-46. VOS Distribution
图6-45. INR/SS Distribution
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-47. INR/SS Load Regulation
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-48. VOS Load Regulation
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
图6-49. INR/SS Line Regulation
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
图6-50. VOS Line Regulation
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
图6-51. INR/SS vs VNR/SS and Temperature
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-52. VOS vs VNR/SS and Temperature
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOUT = 0.7 V
图6-53. INR/SS vs IOUT and Temperature for VIN = 1.2 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOUT = 0.7 V
图6-54. VOS vs IOUT and Temperature for VIN = 1.2 V
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOpHr = 500 mV
图6-55. INR/SS vs IOUT and Temperature for VIN = 1.8 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOpHr = 500 mV
图6-56. VOS vs IOUT and Temperature for VIN = 1.8 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOpHr = 500 mV
图6-57. INR/SS vs IOUT and Temperature for VIN = 3.3 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOpHr = 500 mV
图6-58. VOS vs IOUT and Temperature for VIN = 3.3 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOpHr = 500 mV
图6-59. INR/SS vs IOUT and Temperature for VIN = 5.1 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOpHr = 500 mV
图6-60. VOS vs IOUT and Temperature for VIN = 5.1 V
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
图6-62. VOS vs VIN and Temperature for VOUT = 1.2 V
图6-61. INR/SS vs VIN and Temperature for VOUT = 1.2 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
图6-64. VOS vs VIN and Temperature for VOUT = 1.8 V
图6-63. INR/SS vs VIN and Temperature for VOUT = 1.8 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
图6-66. VOS vs VIN and Temperature for VOUT = 3.3 V
图6-65. INR/SS vs VIN and Temperature for VOUT = 3.3 V
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
图6-68. VOS vs VIN and Temperature for VOUT = 5.1 V
图6-67. INR/SS vs VIN and Temperature for VOUT = 5.1 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
图6-70. VOS vs Temperature for VIN_Min, VOpHr = 0.2 V
图6-69. INR/SS vs Temperature for VIN_Min, VOpHr = 0.2 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 1 mA
图6-71. INR/SS Fast-Start vs VIN and Temperature
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 1.7 V
图6-72. GND Pin Current vs IOUT and Temperature for
VOUT = 1.2 V
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 3.8 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 5.6 V
图6-73. GND Pin Current vs IOUT and Temperature for
图6-74. GND Pin Current vs IOUT and Temperature for
VOUT = 3.3 V
VOUT = 5.1 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VIN = 5.7 V,
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, VOpHr = 500 mV
IOUT = 1 mA
图6-75. GND Pin Current vs VNR/SS and Temperature
图6-76. GND Pin Current vs VIN and Temperature for
IOUT = 1 mA
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF,
VOUT = VIN –0.5 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF,
VOUT = VIN –0.5 V
图6-77. GND Pin Current vs VIN and Temperature for
图6-78. GND Pin Current vs VIN and Temperature for
IOUT = 500 mA
IOUT = 1 A
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA,
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA,
VOUT = 3.3 V
VOUT = 3.3 V
图6-79. GND Pin Current vs VEN and Temperature for
图6-80. GND Pin Current vs VEN and Temperature for
VIN = 1.7 V (Dropout Operation)
VIN = 5.7 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-81. 100% Current Limit vs Temperature for VOUT = 0.4 V
图6-82. 100% Current Limit vs Temperature for VOUT = 0.8 V
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-83. 100% Current Limit vs Temperature for VOUT = 1.2 V
图6-84. 100% Current Limit vs Temperature for VOUT = 1.8 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-85. 100% Current Limit vs Temperature for VOUT = 3.3 V
图6-86. 100% Current Limit vs Temperature for VOUT = 5.1 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-87. 80% Current Limit vs Temperature for VOUT = 1.2 V
图6-88. 80% Current Limit vs Temperature for VOUT = 1.8 V
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-89. 80% Current Limit vs Temperature for VOUT = 3.3 V
图6-90. 80% Current Limit vs Temperature for VOUT = 5.1 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-91. 60% Current Limit vs Temperature for VOUT = 1.2 V
图6-92. 60% Current Limit vs Temperature for VOUT = 1.8 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
CIN = COUT = 10 μF, CNR/SS = 4.7 μF
图6-93. 60% Current Limit vs Temperature for VOUT = 3.3 V
图6-94. 60% Current Limit vs Temperature for VOUT = 5.1 V
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
图6-95. UVLOIN vs Temperature
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
图6-96. VEN Hysteresis and Threshold vs Temperature
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
图6-97. EN Pin Current vs Enable Voltage and Temperature for
图6-98. EN Pin Current vs Enable Voltage and Temperature for
VIN = 1.7 V
VIN = 5.7 V
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
图6-100. FB_PG Pin Current vs VIN and Temperature
图6-99. VFB_PG Hysteresis and Threshold vs Temperature
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IPG = –1 mA, VIN
1.7 V, IOUT = –1 mA
=
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
图6-102. PG Pin Current vs VIN and Temperature
图6-101. VPG Low-Level Output Voltage vs Temperature
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
图6-103. FB_PG to PG Pin Rising and Falling Delay vs
图6-104. NR/SS and OUT Pulldown Resistors vs Temperature
Temperature
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6.6 Typical Characteristics (continued)
VIN = VOUT(NOM) + 0.5 V, VEN = 1.8 V, CIN = 10 µF, CNR/SS = 4.7 μF, COUT = 10 μF, and IOUT = 1 mA (unless otherwise
noted); typical values are at TJ = 25°C
CIN = COUT = 10 μF, CNR/SS = 4.7 μF, IOUT = 0 mA
图6-105. Shutdown Current vs VIN and Temperature
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7 Detailed Description
7.1 Overview
The TPS7A94 is an ultra-low-noise (0.46 μVRMS over 10-Hz to 100-kHz bandwidth), ultra-high PSRR (> 50 dB
to 2 MHz), high-accuracy (1%), low-dropout (LDO) linear voltage regulator with an input range of 1.7 V to 5.7 V
and an output voltage range from 0 V to VIN – VDO and is fully specified above 0.4 VOUT. This LDO regulator
uses innovative circuitry to achieve wide bandwidth and high loop gain, resulting in ultra-high PSRR even when
operating under very low operational headroom (VIN – VOUT). At a high level, the device has two main blocks
(the current reference and the unity-gain LDO buffer) and a few secondary features (such as the precision
enable, current limit, and PG pin).
The current reference is controlled by the NR/SS pin. This pin sets the output voltage with a single resistor, sets
the start-up time, and filters the noise generated by the reference and external set resistor.
The unity-gain LDO buffer is controlled by the OUT pin. The ultra-low-noise does not increase with output
voltage and provides wideband PSRR. As such, the SNS pin is only used for remote sensing of the load.
The EN_UV pin sets the precision enable feature. Select the optimal input voltage at which the LDO starts at.
There are two independent UVLO voltages in this device: the internal IN rail UVLO and the EN_UV pin.
The FB_PG pin sets the current limit and power-good (PG) features. A voltage divider on this pin programs both
the current limit and the PG trip point.
An ultra-low-noise current reference (150 μA, typical) is used in conjunction with an external resistor (RNR/SS) to
set the output voltage. This process allows the output voltage range to be set from 0.4 V to (VIN – VDO). To
achieve this ultra-low noise, an external capacitor CNR/SS (typically 4.7 μF) is placed in parallel to the RNR/SS
resistor used to set the output voltage. The unity-gain architecture provides ultra-high PSRR over a wide
frequency range without compromising load and line transients.
This regulator offers programmable current-limit, thermal protection, is fully specified from –40°C to +125°C
above 0.4 VOUT, and is offered in a thermally efficient 10-pin, 3-mm × 3-mm WSON package.
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7.2 Functional Block Diagram
Thermal
Shutdown
UVLO
Output
overshoot
recovery
Current
Limit
IN
OUT
Prog.
Current Limit
150µA
(A)
RPULLDOWN
Logic
Logic
œ
+
UVLO
NR/SS
Dropout
Current Limit
VNR/SS
Logic
Output discharge
Thermal Shutdown
Logic
SNS
NR/SS discharge
Precision
EN
EN
Band Gap
{60%, 80%, 100%} . ICL_NO M
Prog. Current
Limit
FB_PG
PG
Programmable Power Good
œ
Delay(B)
+
200mV
V
GND
A. See the RPULLDOWN output active discharge resistance value in the Electrical Characteristics table.
B. See the delay value in the Electrical Characteristics table.
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7.3 Feature Description
7.3.1 Output Voltage Setting and Regulation
图 7-1 shows a simplified regulation circuit, where the input signal (VNR/SS) is generated by the internal current
source (INR/SS) and the external resistor (RNR/SS). Because the error amplifier is always operating in unity-gain
configuration, the LDO output voltage is directly programmed by the VNR/SS voltage. The VNR/SS reference
voltage is generated by an internal low-noise current source driving the RNR/SS resistor and is designed to have
very low bandwidth at the input to the error amplifier through the use of a low-pass filter (CNR/SS || RNR/SS).
VOUT
VIN
IFAST_SS
INR/SS = 150µA
Error Amplifier
driving passFET
œ
+
VSNS
VNR/SS
RPULLDOWN_NR/SS
CNR/SS
RNR/SS
NR/SS discharge
GND
Logic
GND
VOUT = INR/SS × RNR/SS
.
图7-1. Simplified Regulation Circuit
This unity-gain configuration, along with the highly accurate INR/SS reference current, enables the device to
achieve excellent output voltage accuracy; though, the RNR/SS accuracy can become the limiting factor when
operating at low output voltage. The low dropout voltage (VDO) enables reduced thermal dissipation and
achieves robust performance. This combination of features makes this device an excellent voltage source for
powering sensitive analog low-voltage devices.
7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
The architecture features a highly accurate, high-precision, low-noise current reference followed by a state-of-
the-art error amplifier (1.1 nV/√Hz at 10-kHz noise for VOUT ≥ 1.2 V) comparable to, if not better than, that of a
precision amplifier. The unity-gain configuration ensures ultra-low noise over the entire output voltage range.
Additional noise reduction and higher output current can be achieved by placing multiple TPS7A94 LDOs in
parallel.
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7.3.3 Programmable Current Limit and Power-Good Threshold
The brick-wall current limit can be programmed to either 100%, 80%, or 60% of the nominal factory-programmed
value by setting the input impedance for the FB_PG pin. Similarly, the power-good indication threshold can also
be adjusted between 85% and 95% of the nominal output voltage by changing the FB_PG resistor divider ratio;
see the Adjusting the Factory-Programmed Current Limit section for details.
7.3.4 Programmable Soft Start (NR/SS Pin)
The device features a programmable, monotonic, voltage-controlled, soft-start circuit that uses the CNR/SS
capacitor to minimize inrush current into the output capacitor and load during start up. This circuitry can also
reduce the start-up time for some applications that require the output voltage to reach at least 90% of the set
value for fast system start up. See the Programmable Soft-Start and Noise-Reduction (NR/SS Pin) section for
more details.
7.3.5 Precision Enable and UVLO
Two independent UVLO (undervoltage lockout) voltage circuits are present. An internally set UVLO on the input
supply (IN pin) automatically disables the LDO when the input voltage reaches the minimum threshold. A
precision EN function (EN_UV pin) can also be used as a user-programmable UVLO.
1. The input supply voltage undervoltage lockout (UVLO) circuit prevents the regulator from turning on when
the input voltage is not high enough, see the Electrical Characteristics table for more details.
2. The precision enable circuit allows a simple sequencing of multiple power supplies with a resistor divider
from another supply. This enable circuit can be used to set an external UVLO voltage at which the device is
enabled using a resistor divider on the EN_UV pin; see the Precision Enable (External UVLO) section for
more details.
7.3.6 Active Discharge
The device incorporates two internal pulldown metal-oxide semiconductor field effect transistors (MOSFETs).
The first pulldown MOSFET connects a resistor (RPULLDOWN) from OUT to ground when the device is disabled to
actively discharge the output capacitor. The second pulldown MOSFET connects a resistor (RPULLDOWN_NR/SS
)
from NR/SS to ground when the device is disabled and discharges the NR/SS capacitor. Both pulldown
MOSFETs are activated by any one or more of the following:
1. Driving the EN_UV pin below the VEN(LOW) threshold
2. The IN pin voltage falling below the undervoltage lockout VUVLO threshold
3. Having the output voltage greater than the input voltage
7.3.7 Thermal Shutdown Protection (TSD
)
A thermal shutdown protection circuit disables the LDO when the junction temperature (TJ ) of the pass transistor
rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device resets (turns on) when the
temperature falls to TSD(reset) (typical). The thermal time constant of the semiconductor die is fairly short, thus the
device can cycle off and on when thermal shutdown is reached until power dissipation is reduced. Power
dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high
inrush currents charging large output capacitors.
Under some conditions, the thermal shutdown protection can disable the device before start up completes. For
reliable operation, limit the junction temperature to the maximum listed in the Electrical Characteristics table.
Operation above this maximum temperature causes the device to exceed operational specifications. Although
the internal protection circuitry of the device is designed to protect against thermal overload conditions, this
circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or
above the maximum recommended junction temperature reduces long-term reliability.
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7.4 Device Functional Modes
表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table
for parameter values.
表7-1. Device Functional Mode Comparison
OPERATING MODE
PARAMETER
VIN
VEN_UV
IOUT
TJ
VIN > VOUT(nom) + VDO and VIN
VIN(min)
>
Normal operation
Dropout operation
VEN_UV > VIH(EN_UV)
VEN_UV > VIH(EN_UV)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
VIN(min) < VIN < VOUT(nom) + VDO
VIN < VUVLO or
Disabled (any true
condition disables the
device)
VIN < VOUT + 90 mV or
VIN < VNR/SS + 20 mV
VEN_UV < VIL(EN_UV)
Not applicable
TJ > TSD(shutdown)
VIN > VOUT(nom) + VDO and VIN
VIN(min)
>
Current-limit operation
VEN_UV > VIH(EN_UV)
TJ < TSD(shutdown)
IOUT ≥ICL(min)
7.4.1 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO
• The output current is less than the current limit (IOUT < ICL)
)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD(shutdown)
)
• The voltage on the EN_UV pin has previously exceeded the VIH(EN_UV) threshold voltage and has not yet
decreased to less than the VIL(EN_UV) falling threshold
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
备注
While in dropout, if a heavy load transient event forces VIN < VOUT(NOM) + 90 mV or VIN < VNR/SS
+
20 mV, the device restarts to prevent the output voltage from overshooting to protect the device and
load.
When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout
voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the
pass transistor back into the linear region.
For additional information, see the Output Voltage Restart (Overshoot Prevention Circuit) section.
7.4.3 Disabled
The output of the device can be shutdown by forcing the voltage of the EN_UV pin to less than the VIL(EN_UV)
threshold (see the Electrical Characteristics table). When disabled, the pass transistor is turned off, internal
circuits are shutdown, and both the NR/SS pin and OUT pin voltages are actively discharged to ground by
internal discharge circuits to ground when the IN pin voltage is higher than or equal to a diode-drop voltage.
7.4.4 Current-Limit Operation
If the output current is greater than or equal to the minimum current limit, (ICL(Min)), then the device is operating in
current-limit mode. The current limit is brick-wall and is programmable with the PG_FB pin. For additional
information, see the Adjusting the Factory-Programmed Current Limit section.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
8.1 Application Information
Successfully implementing a low-dropout regulator (LDO) in an application depends on the application
requirements. This section discusses key device features and how to best implement them to achieve a reliable
design.
8.1.1 Output Voltage Restart (Overshoot Prevention Circuit)
Wide bandwidth linear regulators suffer from an undesirable excessive overshooting of the output voltage during
restart events that occur when the CNR/SS and COUT capacitors are not fully discharged. In this device, and as
shown in 图 8-1, this undesirable behavior is mitigated by implementing low hysteresis circuitry consisting of two
ORed comparators to detect when the input voltage is either 20 mV (typical) lower than the VNR/SS reference
voltage or 300 mV (typical) lower than VOUT
.
Detects if VNR/SS > VIN
+
VNR/SS
Logic
œ
+
VOUT
+
Offset = 20 mV
œ
œ
+
VIN
Offset = 90 mV
VIN
œ
Detects if VOUT > VIN
图8-1. Overshoot Prevention Circuit
When the device is operating in dropout, transient events (such as an input voltage brownout, heavy load
transient, or short-circuit event) can force the device in a reversed bias condition where the input voltage is either
20 mV (typical) lower than the VNR/SS reference voltage or 300 mV (typical) lower than VOUT. The output
overshoot prevention circuit can be triggered, as shown in 图 8-2, thus forcing the device to shutdown and
restart, thereby preventing output voltage overshoot. If the device is still operating in dropout and the error
condition that triggered this circuit is still present, an additional restart can occur until these conditions are
removed or the device is no longer in dropout. The restart always occurs from a discharged state and always
has the same characteristics as the initial LDO power-up, so the start-up time, VOUT ramp rate, and VOUT
monotonicity are all predictable.
tbrownout
tbrownout
tbrownout ≥ 1.5µs
tbrownout ≥ 1.5µs will force LDO to restart
VIN
VIN
VNR/SS
VOUT
VNR/SS
VOUT
V(UVLO)
V(UVLO)
Time
图8-2. Device Behavior in Dropout
图8-3 and 图8-4 show examples of a soft brownout and a brownout event, respectively.
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The brownout overshoot is present with higher VIN slew rates. A 1-V/μs slew rate was used in 图8-5.
图8-3. Example: Soft Brownout to VNR/SS
图8-4. Example: Brownout
图8-5. Example: Brownout With Overshoot Recovery
The overshoot prevention circuit is implemented to provide a predictable start-up and shutdown of the device
without output overshoot if the EN_UV external UVLO is not used as described in this section. This circuit can be
prevented from triggering by:
1. Using an input supply capable of handling heavy load transients or a larger value input capacitor
2. Increasing the operating headroom between VIN and VOUT (for example, when using a battery as an input
supply to make sure that VIN stays higher than VOUT even when the battery is near the full discharge state)
3. Using an input supply with a ramp rate faster than the set output voltage time constant formed by CNR/SS ||
RNR/SS
4. Discharging the input supply slower than the discharge time formed by COUT || (Load || RPULLDOWN) or by the
CNR/SS || (RNR/SS || RPULLDOWN_NR/SS
)
8.1.2 Precision Enable (External UVLO)
The precision enable circuit is used to turn the device on and off. This circuit can be used to set an external
undervoltage lockout (UVLO) voltage (see 图 8-6) to turn on and off the device using a resistor divider between
IN, EN_UV, and GND.
If VEN_UV ≥ VIH(EN_UV), the regulator is enabled. If VEN_UV ≤ VIL(EN_UV), the regulator is disabled. The EN_UV
pin does not incorporate an internal pulldown resistor to GND and must not be left floating. Use the precision
enable circuit for this pin to set an external undervoltage lockout (UVLO) input supply voltage to turn on and off
the device using a resistor divider between IN, EN_UV, and GND.
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VIN
IN
CIN
R(TOP)
GND
EN_UV
TPS7A94
R(BOTTOM)
GND
图8-6. Precision EN Used as External UVLO
This external UVLO configuration prevents the LDO from turning on when the input supply voltage is insufficient
and places the device in dropout operation.
Using the EN_UV pin as an externally set UVLO allows simple sequencing of cascaded power supplies. An
additional benefit is that the EN_UV pin is never left floating. The EN_UV pin does not have an internal pulldown
resistor. In addition to the resistor divider, a zener diode can be needed between the EN_UV pin and ground to
comply with the absolute maximum ratings on this pin.
When VIN exceeds the targeted VON voltage and the R(BOTTOM) resistor is set, 方程式1 and 方程式2 provide the
R(TOP) resistor value and the VOFF voltage at which the input voltage must drop below to disable the LDO.
R
(TOP) ≤R(BOTTOM) × (VON / VIH(EN_UV) - 1)
(1)
(2)
VOFF < [1 + R(TOP) / R(BOTTOM)] × (VIH(EN_UV) - VHYS(EN_UV)
)
where:
• VOFF is the input voltage where the regulator shuts off
• VON is the voltage where the regulator turns on
Consider the EN_UV current pin when selecting the R(TOP) and R(BOTTOM) values.
8.1.3 Undervoltage Lockout (UVLO) Operation
The UVLO circuit, present on the IN pin, ensures that the device remains disabled before the input supply
reaches the minimum operational voltage range, and that the device shuts down when the input supply falls too
low.
The UVLOIN circuit has a minimum response time of several microseconds to fully assert. During this time, a
downward line transient below approximately 1.6 V causes the input supply UVLO to assert for a short time.
However, the UVLOIN circuit can possibly not have enough stored energy to fully discharge the internal circuits
inside of the device. When the UVLOIN circuit does not fully discharge, internal circuitry is not fully disabled.
The effect of the downward line transient can trigger the overshoot prevention circuit and can be easily mitigated
by using the solution proposed in the Precision Enable (External UVLO) section.
图 8-7 illustrates the UVLOIN circuit response to various input voltage events. This diagram can be separated
into the following regions:
• Region A: The device does not turn on until the input reaches the UVLO rising threshold.
• Region B: Normal operation with a regulated output.
• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold –UVLO hysteresis).
The output can fall out of regulation but the device is still enabled.
• Region D: Normal operation with a regulated output.
• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is re-enabled when the UVLO rising
threshold is reached by the input voltage and a normal start up then follows.
• Region F: Normal operation followed by the input falling to the UVLO falling threshold.
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• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
图8-7. Typical UVLO Operation
8.1.4 Dropout Voltage (VDO
)
The dropout voltage refers to the minimum voltage difference between the input and output voltage (VDO = VIN
– VOUT) that is required for regulation. When the input voltage (VIN) drops to or below the maximum dropout
voltage (VDO(Max)) for the given load current, see the Electrical Characteristics table, the device functions as a
resistive switch and does not regulate the output voltage. When the device is operating in dropout, the output
voltage tracks the input voltage. For high current, the dropout voltage (VDO) is proportional to the output current
because the device is operating as a resistive switch. For low current, internal nodes are saturating and the
dropout plateaus to the minimum value. As mentioned in the Output Voltage Restart (Overshoot Prevention
Circuit) section, transient events such as an input voltage brownout, heavy load transient, or short-circuit event
can trigger the overshoot prevention circuit. Operating the device at or near dropout significantly degrades both
transient performance and PSRR, and can also trigger the overshoot prevention circuit. Maintaining sufficient
operating headroom (VOpHr = VIN – VOUT) significantly improves the device transient performance and PSRR,
and prevents triggering the overshoot prevention circuit.
备注
For this device, the pass element is not the limiting dropout voltage factor. Because the reference
voltage is generated by a current source and the NR/SS resistor, and because the operating
headroom is reducing (even at low load), the internal current source (INR/SS) saturates faster than the
pass transistor. This behavior is described in the dropout voltage plot (图 6-43). Notice that the
dropout does not go to 0 V at light loads.
8.1.5 Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
For proper device operation, the resistor divider network input to the FB_PG pin must be connected. The FB_PG
pin must not be left floating because this pin represents an analog input to the device internal logic and the input
impedance is sampled during device start up.
The PG pin is an output indicating whether the LDO is ready to provide power. This pin is implemented using an
open-drain architecture. The FB_PG pin is used to program the PG pin and serves a dual purpose of
programming the PG threshold assert voltage and adjusting the current limit, ICL.
The PG pin must use the minimum value or larger pullup resistor from PG to IN, see 图 8-8, or the external rail
as listed in the Electrical Characteristics table. If PG functionality is not used, leave this pin floating or connected
to GND.
The FB_PG pin uses the parallel impedance formed by the resistor divider RFB_PG(TOP) and RFB_PG(BOTTOM) to
program the current limit value during LDO initialization. If this impedance is less than 12.5 kΩ, then the nominal
factory-programmed, current-limit value is selected. If the input impedance is less than 50 kΩ, but greater than
12.5 kΩ, then 80% of the nominal factory-programmed current limit is selected. If the input impedance is less
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than 100 kΩ, but greater than 50 kΩ, then 60% of the nominal factory-programmed current limit is selected.
Connect the RFB_PG(TOP) and RFB_PG(BOTTOM) resistors as indicated in this section for proper operation of the
LDO. Do not float this pin.
When initialization is complete, the voltage divider provides the necessary feedback to the PG pin by setting the
PG assert threshold voltage.
To properly select the values of the RFB_PG(TOP) and RFB_PG(BOTTOM) resistors, see the Adjusting the Factory-
Programmed Current Limit section for detailed explanation and calculation.
备注
The RFB_PG(TOP) and RFB_PG(BOTTOM) resistor divider ratio sets the power-good assert threshold
voltage between 85% to 95% of the VFB_PG voltage for 60% and 80% of the nominal factory-
programmed current limit.
If the current limit is set for 100% of the nominal factory-programmed current limit, the PG threshold
range is not limited. A PG threshold greater than 80% is common for system where start-up inrush
current must be minimized. Lower PG thresholds can be needed in systems with fast start-up time
constraints.
Setting the PG threshold based off the VFB_PG voltage sets the PG to assert when the output voltage
reaches the corresponding percentage level of VFB_PG because VFB_PG is a scaled version of the
output voltage. 图8-8 shows the internal circuitry for both the FB_PG and PG pins.
VOUT
VIN
{60%, 80%, 100%} . ICL(NO M)
Prog. Current
Limit
Logic
RFB_PG(TOP)
RPG
FB_PG
PG
œ
VPG
Delay
+
RFB_PG(BOTTOM)
Ref. = 200 mV
V
GND
GND
GND
图8-8. Programmable Power-Good Threshold Simplified Schematic
The PG pin pullup resistor value must be between 10 kΩand 100 kΩ. The lower limit of 10 kΩresults from the
maximum pulldown strength of the power-good transistor, and the upper limit of 100 kΩ results from the
maximum leakage current at the power-good node. If the pullup resistor is outside of this range, then the power-
good signal can possibly not read a valid digital logic level.
The state of the PG signal is only valid when the FB_PG pin resistor divider network is set properly and the
device is in normal operating mode.
8.1.6 Adjusting the Factory-Programmed Current Limit
The current limit is a brick-wall scheme and the factory-programmed current limit value can be programmed to a
set of discrete value (100%, 80%, or 60% of the default value), as specified in the Electrical Characteristics
table. This adjustment can be done by changing the input impedance of the FB_PG pin represented by the
parallel resistance of RFB_PG(TOP) || RFB_PG(BOTTOM). The FB_PG pin has dual functionality: adjusting the ICL
value and setting the power-good (PG) assert threshold.
Prior to start up, the input impedance of the FB_PG pin is sampled and the ICL value is adjusted based on the
input impedance.
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备注
The current limit programmability is dependent on the output voltage. For voltages below 0.4 V, the
current limit cannot be programmed. For voltages between 0.4 V and 1.2 V, the current limit cannot be
adjusted and is always set to 100%. Programmable Current Limit vs Output Voltage describes this
behavior.
Programmable Current Limit vs Output Voltage
NOMINAL OUTPUT
VOLTAGE (V)
ICL SETTING
RFB_PG(BOTTOM) (kΩ)
RFB_PG(BOTTOM) = 0.2 V / 16 μA
RFB_PG(BOTTOM) = 0.2 V / 4 μA
RFB_PG(BOTTOM) = 0.2 V / 2 μA
RFB_PG(TOP) (kΩ)
(%)
100
80
60
V
OUT(nom) ≥1.2 V
RFB_PG(TOP) = RFB_PG(BOTTOM)
( VOUT(nom) / 0.2 V × K – 1)
×
with K = PG threshold (%VOUT
)
100
N/A
0.4 V ≤VOUT(nom) < 1.2 V
RFB_PG(BOTTOM) = 0.2 V / 6 μA
VOUT(nom) < 0.4 V
N/A
N/A
表8-1 provides values for various output voltages using 1% resistors.
表8-1. Programmable Current Limit Voltage-Divider Current Settings
NOMINAL OUTPUT VOLTAGE (V)
ICL SETTING (%)
PG THRESHOLD (%)
RFB_PG(BOTTOM) (kΩ)
RFB_PG(TOP) (kΩ)
12.4
49.9
100
51.1
205
100
80
85
85
85
95
95
95
95
95
95
VOUT(nom) = 1.2 V
412
60
12.4
49.9
100
187
100
80
VOUT(nom) = 3.3 V
732
1470
287
60
12.4
49.9
100
100
80
VOUT(nom) = 5.1 V
1150
2320
60
图8-9 shows the different ICL settings for a nominal 3.3-V output voltage.
3.5
3
2.5
2
1.5
1
100% Current Limit
0.5
80% Current Limit
60% Current Limit
0
0
0.2
0.4
0.6
0.8
Current Limit Threshold (A)
1
1.2
1.4
图8-9. Programmable Current Limit Behavior (Typical) for a 3.3-VOUT(nom)
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8.1.7 Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
The NR/SS pin is the input to the inverting terminal of the error amplifier, see the Functional Block Diagram. A
resistor connected from this pin to GND sets the output voltage by the pin internal reference current INR/SS, VOUT
= INR/SS × RNR/SS . Connecting a capacitor from this pin to GND significantly reduces the output noise, limits the
input inrush-current, and soft-starts the output voltage. Use the minimum value or larger capacitor from NR/SS to
ground as listed in the Electrical Characteristics table and place the NR/SS capacitor as close to the NR/SS and
GND pins of the device as possible.
The device features a programmable, monotonic, voltage-controlled, soft-start circuit that is set to work with an
external capacitor (CNR/SS). In addition to the soft-start feature, the CNR/SS capacitor also lowers the output
voltage noise of the LDO. The soft-start feature can be used to eliminate power-up initialization problems. The
controlled output voltage ramp also reduces peak inrush current during start up, minimizing start-up transients to
the input power bus.
To achieve a monotonic start up, the device output voltage tracks the VNR/SS reference voltage until this
reference reaches the set value (the set output voltage). The VNR/SS reference voltage is set by the RNR/SS
resistor and, during start up, using a fast charging current (IFAST_SS) in addition to the INR/SS current, as shown in
图8-10, to charge the CNR/SS capacitor.
VOUT
VIN
IFAST_SS
INR/SS = 150µA
Error Amplifier
driving passFET
œ
+
VSNS
VNR/SS
RPULLDOWN_NR/SS
CNR/SS
RNR/SS
NR/SS discharge
GND
Logic
GND
图8-10. Simplified Soft-Start Circuit
The 2.1-mA (typical) IFAST_SS current and 150 μA (typical) INR/SS current quickly charge CNR/SS until the voltage
reaches approximately 93% of the set output voltage, then the IFAST_SS current disengages and only the INR/SS
current continues to charge CNR/SS to the set output voltage level. If there is any error during start up or the
output overshoot prevention circuit is triggered, the NR/SS discharge FET turns on, thus discharging the CNR/SS
capacitor to protect both the LDO and the load.
The soft-start ramp time depends on the fast start-up (IFAST_SS) charging current, the reference current (INR/SS),
CNR/SS capacitor value, and the set (targeted) output voltage (VOUT(target)). 方程式3 calculates the soft-start ramp
time.
Soft-Start Time (tSS) = (VOUT(target) × CNR/SS) / (INR/SS + IFAST_SS
)
(3)
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The INR/SS current is provided in the Electrical Characteristics table and has a value of 150 μA (typical). The
IFAST_SS current has a value of 2 mA (typical) for VIN > 2.5 V. 图 8-11 and 图 8-12 depict the INR/SS and IFAST_SS
current versus VIN and temperature.
图8-11. INR/SS Reference vs Input Voltage and
图8-12. IFAST_SS Reference vs Input Voltage and
Temperature for VOUT = 3.3 V
Temperature for VOUT = 3.3 V
Because the error amplifier is always operating in unity-gain configuration, the output voltage noise can only be
adjusted by increasing the CNR/SS capacitor. The CNR/SS capacitor and RNR/SS resistor form a low-pass filter
(LPF) that filters out the noise from the VNR/SS voltage reference, thereby reducing the device noise floor. The
LPF is a single-pole filter and 方程式 4 calculates the LPF cutoff frequency. Increasing the CNR/SS capacitor can
significantly lower output voltage noise; however, doing so greatly lengthens start-up time. For low-noise
applications, use a 4.7-μF CNR/SS for optimal noise and start-up time trade off.
Cutoff Frequency (fcutoff) = 1 / (2 × π× RNR/SS × CNR/SS
)
(4)
The Typical Characteristics section illustrates the impact of the CNR/SS capacitor on the LDO output voltage
noise.
图8-13 illustrates the relationship, timing, and output voltage value during the start-up phase.
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t2
t1
DV ∂CNR_SS
=
V
∂CNR_SS
OUT
PG_threshold
(
DVOUT ∂CNR/SS
=
VOUT_target -VPG_Threshold ∂CNR/SS
)
t1
=
t2
=
IFAST_SS
IFAST_SS
INR/SS
INR/SS
ISS = 2 mA
t1: CNR/SS charges with
constant current
(IFAS T_SS = 2 mA)
INR/SS = 150 mA
Threshold voltage
programmable
using PG_FB pin
time
图8-13. Relationship Between Threshold Voltage, Output Voltage, IFAST_SS, and INR/SS During Start-Up
8.1.8 Inrush Current
Inrush current is defined as the current into the LDO at the IN pin during start up. Inrush current then consists
primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to
measure because the input capacitor must be removed. Operating without an input capacitor is not
recommended because this capacitor is required for stability. However, 方程式 5 can be used to estimate this
current.
C
OUT ´ dVOUT(t)
VOUT(t)
RLOAD
IOUT(t)
=
+
dt
(5)
where:
• VOUT(t) is the instantaneous output voltage of the turn-on ramp
• dVOUT(t) / dt is the slope of the VOUT ramp
• RLOAD is the resistive load impedance
As illustrated in 图 8-10, the external capacitor at the NR/SS pin (CNR/SS) sets the output start-up time by setting
the rise time of the VNR/SS reference voltage.
Inrush current for a no-load condition is given in 图6-37 to 图6-40.
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8.1.9 Optimizing Noise and PSRR
Noise can be generally defined as any unwanted signal combining with the desired signal (such as the regulated
LDO output). Noise can easily be noticed in audio as a hissing or popping sound. Noise produced from an
external circuit or the 50- to 60-hertz power-line noise (spikes), along with the harmonics, is an excellent
representative of extrinsic noise. Intrinsic noise is produced by components within the device circuitry, such as
resistors and transistors. The two dominating sources of intrinsic noise are the error amplifier and the internal
reference voltage (VNR/SS). Extrinsic noise, including the switching mode power-supply ac ripple voltage, coupled
onto the input supply of the LDO is attenuated by the LDO power-supply rejection ratio, or PSRR. PSRR is a
measurement of the noise attenuation from the input to the output of the LDO.
Optimize the intrinsic noise and PSRR by carefully selecting:
• CNR/SS for the low-frequency range up to the device bandwidth
• COUT for the high-frequency range close to and higher than the device bandwidth
• Operating headroom, VIN –VOUT (VDO), mainly for the low-frequency range up to the device bandwidth, but
also for higher frequencies to a lesser effect
These behaviors are described in the Typical Characteristics curves.
图 8-14 and 图 8-15 show the measured 10-Hz to 100-kHz RMS noise for a 3.3-V device output voltage with a
0.5-V headroom for different CNR/SS and COUT capacitors and a 1-A load current. 表 8-2 lists the typical output
noise for these capacitors.
图8-14. PSRR vs Frequency and IOUT for VOUT = 3.3 图8-15. PSRR vs Frequency and IOUT for VOUT = 3.3
V, COUT = 10 μF
V, COUT = 4.7 μF || 4.7 μF|| 1.0 μF
表8-2. Typical Output Noise for 3.3-VOUT vs CNR/SS, COUT, and Typical Start-Up Time
CNR/SS (µF)
COUT (µF)
START-UP TIME (ms)
Vn (μVRMS), 10-Hz to 100-kHz BW
0.98
0.62
0.46
0.42
1
10
10
10
10
3.73
6.21
2.2
4.7
10
13.97
28.21
PSRR can be viewed as being simply the ratio of the output capacitor impedance by the LDO output impedance.
At low frequency, the output impedance is very low whereas the output impedance of the capacitor is high,
resulting in high PSRR. As the frequency increases, the output capacitor impedance reduces and reaches a
minima set by the ESR.
As shown in 图 8-14 and 图 8-15, and in order to achieve high PSRR at high frequencies, ensure that the output
capacitor ESR and ESL are minimal. These figures compare the use of a single 10-μF output capacitor with a
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4.7-μF || 4.7-μF || 1.0-μF implementation. Notice that below 200 kHz, there is no impact on performance but
above 200 kHz, the PSRR improves by 5 dB to 7 dB.
Minimizing the ESR, ESL generated resonance point in the output capacitance allows for a smoother transition
between the LDO active PSRR component to the passive PSRR of the capacitors.
8.1.10 Adjustable Operation
As shown in 图8-16, the output voltage of the device can be set using a single external resistor (RNR/SS). 方程式
6 calculates the output voltage.
VOUT = INR/SS(NOM) × RNR/SS
(6)
VIN
VOUT
COUT
IN
OUT
SNS
CIN
R(TOP)
VIN
EN_UV
GND
GND
RPG
TPS7A94
R(BOTTOM)
VPG
PG
GND
NR/SS
RFB_PG(TOP)
RNR/SS
CNR/SS
FB_PG
GND
GND
RFB_PG(BOTTOM)
GND
GND
图8-16. Typical Circuit
表 8-3 shows the recommended RNR/SS resistor values to achieve several common rails using a standard 1%-
tolerance resistor.
表8-3. Recommended RNR/SS Values
TARGETED OUTPUT VOLTAGE
(V)
CALCULATED OUTPUT VOLTAGE
(V)
RNR/SS (kΩ)
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.5
2.5
3.0
3.3
3.6
4.7
5.0
2.67
3.32
4.02
4.64
5.36
6.04
6.65
8.06
10.0
16.5
20.0
22.1
24.3
31.6
33.2
0.4005
0.498
0.603
0.696
0.804
0.906
0.9975
1.209
1.5
2.475
3.0
3.315
3.645
4.74
4.98
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备注
To avoid engaging the current limit during start-up with a large COUT capacitor, make sure that:
1. A minimum NR/SS capacitor of 1 μF is used
2. When the output capacitor is greater than 100 μF, maintain a COUT to CNR/SS ratio < 100
Because the set resistor is also placed on the NR/SS pin, consider using a thin-film resistor and
provide enough resistor temperature drift to ensure the targeted accuracy.
8.1.11 Paralleling for Higher Output Current and Lower Noise
Achieving higher output current and lower noise is achievable by paralleling two or more LDOs. Implementation
must be carefully planned out to optimize performance and minimize output current imbalance.
Because the TPS7A94 output voltage is set by a resistor driven by a current source, the NR/SS resistor and
capacitor must be adjusted as per the following:
RNR/SS_parallel = VOUT_TARGET / (n × INR/SS
CNR/SS_parallel = n × CNR/SS_single
)
(7)
(8)
where:
• n is the number of LDOs in parallel
• INR/SS is the NR/SS current as provided in the data sheet Electrical Characteristics table
• CNR/SS_single is the NR/SS capacitor for a single LDO
When connecting the input and NR/SS pin together, and with the LDO being a buffer, the current imbalance is
only affected by the error offset voltage of the error amplifier. As such, the current imbalance can be expressed
as:
2
εI = VOS × 2 × RBALLAST / (RBALLAST 2 –ΔRBALLAST
)
(9)
where:
• εI is the current imbalance
• VOS is the LDO error offset voltage
• RBALLAST is the ballast resistor
• ΔRBALLAST is the deviation of the ballast resistor value from the nominal value
With the typical offset voltage of 200 μV, considering no error from the design of the PCB ballast resistor
(ΔRBALLAST = 0) and a 100-mA maximum current imbalance, the ballast resistor must be 4 mΩ or greater; see
图8-17.
Using the configuration described, the LDO output noise is reduced by:
eO_parallel = (1 / √n) × eO_single
(10)
where:
• n is the numbers of LDOs in parallel
• eO_single is the output noise density from a single LDO
• eO_parallel is the output noise density for the resulting parallel LDO
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In 图8-17, the noise is reduced by 1 / √2.
VIN
PG
FB_PG
IN
RBALLAST = 4 mꢀ
OUT
SNS
TPS7A94
VEN_UV
EN_UV
NR/SS
GND
VOUT = 3.3V
NR/SS
EN_UV
TPS7A94
GND
RBALLAST = 4 mꢀ
OUT
SNS
IN
COUT = 10 µF
CIN = 10 µF
FB_PG
PG
图8-17. Paralleling Multiple TPS7A94 Devices
8.1.12 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) and low equivalent series
inductance (ESL) ceramic capacitors at the input, output, and noise-reduction pin. Multilayer ceramic capacitors
have become the industry standard for these applications and are recommended, but must be used with good
judgment. Ceramic capacitors that employ X7R-, X5R-rated, or better dielectric materials provide relatively good
capacitive stability across temperature. The use of Y5V-rated capacitors is discouraged because of large
variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature. The input and output capacitors recommended herein account for a capacitance derating of
approximately 50%, but at high VIN and VOUT conditions (VIN = 5.5 V to VOUT = 5.0 V), the derating can be
greater than 50%, which must be taken into consideration.
The device requires input, output, and noise-reduction capacitors for proper operation of the LDO. Use the
nominal or larger than the nominal input, and output capacitors as specified in the Recommended Operating
Conditions table. Place input and output capacitors as close as possible to the corresponding pin and make the
capacitor GND connections as close as possible to the device GND pin to minimize PCB loop inductance, thus
reducing transient voltage spikes during a load step.
As illustrated in 图 8-15, multiple parallel capacitors can be used to lower the impedance present on the line.
This capacitor counteracts input trace inductance, improves transient response, and reduces input ripple and
noise. Using an output capacitor larger than the typical value can also improve the transient response.
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8.1.13 Load Transient Response
备注
For best transient response, use the nominal value or larger capacitor from OUT to ground as listed in
the Recommended Operating Conditions table. Place the output capacitor as close to the OUT and
GND pins of the device as possible.
For best transient response and to minimize input impedance, use the nominal value or larger
capacitor from IN to ground as listed in the Recommended Operating Conditions table. Place the input
capacitor as close to the IN and GND pins of the device as possible.
The load-step transient response is the LDO output voltage response to load current changes. There are two
key transitions during a load transient response: the transition from a light to a heavy load, and the transition
from a heavy to a light load. The regions shown in 图 8-18 are broken down in this section. Regions A, E, and H
are where the output voltage is in steady-state regulation.
A
C
D
E
G
H
VOUT
B
F
Time (µs)
Current slew rate (rise = fall)
Max output current
Minimum output current
IOUT
Time (µs)
图8-18. Load Transient Waveform
During transitions from a light load to a heavy load:
• The initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to
the output capacitor (region B)
• Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load:
• The initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge
to increase (region F)
• Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load
discharging the output capacitor (region G)
Transitions between current levels changes the internal power dissipation because the device is a high-current
device (region D). The change in power dissipation changes the die temperature during these transitions, and
leads to a slightly different voltage level. This temperature-dependent output voltage level shows up in the
various load transient responses.
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
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8.1.14 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. 方程式11 calculates PD:
PD = (VOUT - VIN) ´ IOUT
(11)
备注
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the
system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be
obtained. The low dropout of the device allows for maximum efficiency across a wide range of output
voltages.
The primary heat conduction path for the package is through the thermal pad to the PCB. Solder the thermal pad
to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any
inner plane areas or to a bottom-side copper plane.
The power dissipation by the device determines the junction temperature (TJ) for the device. Power dissipation
and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the
combined PCB and device package and the temperature of the ambient air (TA), according to 方程式 12. This
equation is rearranged for output current in 方程式13.
TJ = TA = (RθJA × PD)
(12)
(13)
IOUT = (TJ –TA) / [RθJA × (VIN –VOUT)]
This thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and copper-
spreading area, and is only used as a relative measure of package thermal performance. For a well-designed
thermal layout, RθJA is actually the sum of the DSC package junction-to-case (bottom) thermal resistance
(RθJCbot) plus the thermal resistance contribution by the PCB copper.
8.1.15 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with 方程式14 and are given in the Thermal Information table.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
(14)
where:
• PD is the power dissipated as explained in the Power Dissipation (PD) section
• TT is the temperature at the center-top of the device package
• TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
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8.1.16 TPS7A94EVM-046 Thermal Analysis
The TPS7A94EVM-046 EVM was used to develop the TPS7A9401DRC thermal model. The DRC package is a
3-mm × 3-mm, 10-pin VQFN with 25-µm plating on each via. The EVM is a 2.85-inch × 3.35-inch (72.39 mm ×
85.09 mm) PCB comprised of four layers. 表 8-4 lists the layer stackup for the EVM. 图 8-19 to 图 8-23 illustrate
the various layer details for the EVM.
表8-4. TPS7A94EVM-046 PCB Stackup
LAYER
NAME
Top overlay
Top solder
Top layer
MATERIAL
THICKNESS (mil)
1
2
—
—
0.4
2.8
10
Solder resist
Copper
3
4
Dielectric 1
Mid layer 1
Dielectric 2
Mid layer 2
Dielectric 3
Bottom layer
Bottom solder
FR-4 high Tg
Copper
5
2.8
30
6
FR-4 high Tg
Copper
7
2.8
10
8
FR-4 high Tg
Copper
9
2.8
0.4
10
Solder resist
图8-19. Top Composite View
图8-20. Top Layer Routing
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图8-21. Mid Layer 1 Routing
图8-22. Mid Layer 2 Routing
图8-23. Bottom Layer Routing
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图 8-24 to 图 8-26 show the thermal gradient on the PCB and device that results when a 1-W power dissipation
is used through the pass transistor with a 25°C ambient temperature. 表 8-5 shows thermal simulation data for
the TPS7A94EVM-046.
表8-5. TPS7A94EVM-046 Thermal Simulation Data
DUT
RθJA (°C/W)
⍦
JB (°C/W)
⍦JT (°C/W)
TPS7A94EVM-046
25.6
11.5
0.3
图8-24. TPS7A94EVM-046 3D View
图8-25. TPS7A94EVM-046 PCB Thermal Gradient
图8-26. TPS7A94EVM-046 Device Thermal Gradient
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8.2 Typical Application
RFB_PG(BOTTOM) = 100 kꢀ
RFB_PG(TOP) = 1467 kꢀ
VIN
PG
FB_PG
IN
CIN = 10 µF
OUT
SNS
RTOP = 226 kꢀ
COUT = 10 µF
GND
TPS7A94
GND
DC/DC
RBOTTOM = 100 kꢀ
Load
EN_UV
NR/SS
Converter
VEN_UV
GND
GND
GND
CNR/SS = 4.7 µF
RNR/SS = 22.1 kꢀ
GND
GND
GND
图8-27. Typical Application Circuit
RFB_PG(BOTTOM) = 100 kꢀ
RFB_PG(TOP) = 1467 kꢀ
Ferrite-bead Impedance = 49 ꢀ @ 1MHz
VIN
PG
FB_PG
IN
CIN = 10 µF
OUT
SNS
RTOP = 226 kꢀ
C = 1 µF
GND
COUT = 10 µF
GND
TPS7A94
GND
DC/DC
RBOTTOM = 100 kꢀ
Load
EN_UV
NR/SS
Converter
VEN_UV
GND
GND
GND
CNR/SS = 4.7 µF
RNR/SS = 22.1 kꢀ
GND
GND
GND
图8-28. Typical Application Circuit With Added Pi-Filter
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8.2.1 Design Requirements
表8-6 lists the required application parameters for this design example.
表8-6. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
Output voltage
Output current
Current limit
VIN ≥5 V, ±3%, provided by the dc/dc converter switching at 1 MHz
3.3 V, ±1%
500 mA (maximum), 300 mA (minimum)
750 mA
95%
PG threshold
Targeted noise compliance mask
Zone 1 (10 Hz to 100 Hz): Spectral noise ≤100 nV/√Hz
Targeted spectral noise
Zone 2 (100 Hz to 1 kHz): Spectral noise ≤10 nV/√Hz
Zone 3 (> 1 kHz): Spectral noise ≤3 nV/√Hz
PSRR at 1 MHz
> 50 dB at max load current
Device to be enabled when VIN ≥80% × VIN_Target
Start-up environment
Device to be disabled when VIN < 80% × VIN_Target
Start-up time < 25 ms
8.2.2 Detailed Design Procedure
In this design example, the device is powered by a dc/dc convertor switching at 1 MHz. The load requires a 3.3-
V clean rail with the spectral noise mask versus frequency shown in 图 8-29 and a maximum load of 500 mA.
The typical 10-μF input and output capacitors and 4.7-μF NR/SS capacitors are used to achieve a good
balance between fast start-up time and excellent noise and PSRR performance.
Zone 3
Frequency (Hz)
图8-29. Noise Compliance Mask
The output voltage is set using a 22.1-kΩ, thin-film resistor value calculated as described in the Adjustable
Operation section. To set the current limit to a value close to the 750 mA required by the application, and to set
the PG threshold to 95%, use 表 8-1 to set the RFB_PG top and bottom resistors values at 1.47 MΩ and 100 kΩ,
respectively.
Setting RB to 100 kΩ and using a 4-V VON and 方程式 1 provide the RT value of 226 kΩ. VOFF is calculated with
方程式2 to be 3.5 V.
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图 8-30 shows that the device meets all design noise requirements except for the noise peaking at 900 kHz.
However, this noise peaking can be easily attenuated to the required noise level by means of a pi-filter
positioned after the LDO. 图 8-31 shows that this design is very close to the PSRR level at 1 MHz and can
require more margin. Fortunately, both requirements are easily achieved by inserting a pi-filter consisting of a
ferrite bead and a small capacitor beyond the LDO and before the load; see 图8-28.
The ferrite bead was selected to have a very small dc resistance of less than 50 mΩ, 1 A of current rating, and a
relatively small footprint. The added pi-filter components have almost no impact on the LDO accuracy
performance and no significant increase in the design total cost.
200
100
50
140
120
100
80
20
10
5
60
2
1
40
0.5
20
0.2
0.1
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
图8-30. Output Noise vs Frequency
图8-31. PSRR vs Frequency
8.2.3 Application Curves
图8-32 and 图8-33 show the design noise and PSRR performance after inserting the pi-filter.
200
100
50
140
120
100
80
Non-Filtered (nV/vHz)
Filtered (nV/vHz)
Filtered
Non-Filtered
20
10
5
60
2
1
40
0.5
20
0.2
0.1
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
图8-32. Noise vs Frequency
图8-33. PSRR vs Frequency
8.3 Power Supply Recommendations
The device is designed to operate from an input voltage supply ranging from 1.7 V to 5.7 V. Ensure that the input
voltage range provides adequate operational headroom for the device to have a regulated output. This input
supply must be well regulated. If the input supply is noisy, use additional input capacitors with low ESR and
increase the operating headroom to achieve the desired output noise, PSRR, and load transient performance.
8.4 Layout
8.4.1 Layout Guidelines
8.4.1.1 Board Layout
For good thermal performance, connect the thermal pad to a large-area GND plane.
Kelvin connects the SNS pin through a low-impedance connection to the output capacitor and load for optimal
transient performance. Do not float this pin.
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Connect the GND pin to the device thermal pad and connect both this pin and the thermal pad to the ground on
the board through a low-impedance connection.
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,
copper surface. To avoid negative system performance, do not use vias or long traces to the input and output
capacitors. The grounding and layout scheme described in 图 8-34 minimizes inductive parasitics, and thereby
reduces load-current transients, minimizes noise, and increases circuit stability.
To improve performance, use a ground reference plane, either embedded in the printed circuit board (PCB) or
placed on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy
of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO
device when connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal
requirements.
8.4.1.2 Layout Example
TOP View
CIN
COUT
GND Plane
IN
OUT
IN
OUT
OUT
IN
EN_UV
PG
SNS
RPG
Thermal vias
GND Plane
NR/SS
PG
CNR/SS
RNR/SS
FB_PG
GND
R
FB_PG(TOP)
R
FB_PG(BOTTOM)
OUT
图8-34. Example Layout
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS7A94. 表9-1 shows the summary information for this fixture.
表9-1. Design Kits and Evaluation Modules
NAME
LITERATURE NUMBER
TPS7A94EVM-046 evaluation module
SBVU070
The EVM can be requested at the Texas Instruments web site through the TPS7A94 product folder.
9.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS7A94 is available through the TPS7A94 product folder
under simulation models.
9.1.2 Device Nomenclature
表9-2. Ordering Information(1)
PRODUCT
DESCRIPTION
yyy is the package designator.
z is the package quantity.
TPS7A9401 yyy z
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS3702 High-Accuracy, Overvoltage and Undervoltage Monitor data sheet
• Texas Instruments, TPS7A94EVM-046 Evaluation Module user guide
• Texas Instruments, High-Current, Low-Noise Parallel LDO reference design
9.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
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9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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10.1 Mechanical Data
PACKAGE OUTLINE
DSC0010J
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.15
2.85
A
B
PIN 1 INDEX AREA
3.15
2.85
0.8 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
4X (0.23)
EXPOSED
THERMAL PAD
5
6
2X
2
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
0.5
0.3
PIN 1 ID
(OPTIONAL)
0.1
C A
C
B
10X
0.05
4221826/A 12/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSC0010J
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
10X (0.6)
1
10
10X (0.24)
SYMM
(2.4)
(0.95)
8X (0.5)
5
6
(0.575)
(2.8)
( 0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221826/A 12/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
DSC0010J
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
SYMM
METAL
TYP
10X (0.6)
1
10
2X
(1.06)
10X (0.24)
SYMM
(0.63)
8X (0.5)
6
5
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4221826/A 12/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A9401DSCR
ACTIVE
WSON
DSC
10
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
7A9401
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A9401DSCR
WSON
DSC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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3-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DSC 10
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TPS7A9401DSCR
3000
Pack Materials-Page 2
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