TPS7A57_技术文档

TPS7A57

ZHCSQT5 –JULY 2022

TPS7A57 5A、低V_IN(0.7V)、低噪声(2.1μV_RMS)、高精度(1%)、

超低压降(LDO) 稳压器

1 特性

3 说明

• 输入电压范围：

TPS7A57 是一款低噪声 (2.45µV_RMS)、低压降线性稳

压器 (LDO)，可提供 5A 电流，压降仅为 75mV（独立

于输出电压）。该器件的输出电压可通过一个外部电阻

进行调节，范围为 0.5V 至 5.2V。TPS7A57 集低噪

声、高 PSRR（1MHz 时为 36dB）和高输出电流能力

等特性一体，专为雷达电源、通信和成像应用中的噪声

敏感型组件（例如射频放大器、雷达传感器、

SERDES 和模拟芯片组）供电而设计。

– 无偏置：1.1V 至6.0V

– 有偏置：0.7V 至6.0V

• 输出电压噪声：2.45μV_RMS

• 整个线路、负载和温度范围内为1%（最高）精度

• 低压降：75mV (5A)

• 电源抑制比(5A)：

– 1kHz 时为100dB

– 10kHz 时为78dB

– 100kHz 时为60dB

– 在1MHz 时为36dB

• 出色负载瞬态响应：

– ±2mV，负载阶跃为100mA 至5A

• 可调输出电压范围：0.5V 至5.2V

• 可调软启动浪涌控制

需要以低输入和低输出 (LILO) 电压运行的数字负载

（例如应用特定集成电路 (ASIC)、现场可编程门阵列

(FPGA) 和数字信号处理器 (DSP)）还能够从出色精度

（在负载、线路和温度范围内可达 1%）、遥感功能、

出色的瞬态性能和软启动功能中受益，以提供出色的系

统性能。凭借多功能性、高性能和小尺寸解决方案，该

LDO 成为模数转换器 (ADC)、数模转换器 (DAC) 和成

像传感器等高电流模拟负载以及串行器/ 解串器

(SerDes)、FPGA 和DSP 等数字负载的理想选择。

• BIAS 电源轨：

– 内部电荷泵或3V 至11V 外部电源轨

– 可禁用内部电荷泵

• 开漏电源正常状态(PG) 输出

• 封装：3mm × 3mm 16 引脚WQFN

封装信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

TPS7A57

WQFN (16)

3.00mm × 3.00mm

– EVM R_θJA：21.9°C/W

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 宏远程无线电单元(RRU)

• 室外回程单元

• 有源天线系统mMIMO (AAS)

• 超声波扫描仪

• 实验室和现场仪表

• 传感器、成像和雷达

TPS7A57

0.9 V

IN

OUT

SNS

0.65 V

C_OUT

C_IN

V_OUT

EN

5 V

BIAS

REF

R_PG

C_BIAS

PG

R_REF

5 V

CP_EN

NR/SS

GND

C_NR/SS

典型应用电路

5A、1.2V_IN、0.9V_OUTPSRR，已启用CP

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS395

TPS7A57

ZHCSQT5 –JULY 2022

www.ti.com.cn

内容

7.4 Device Functional Modes..........................................58

8 Application and Implementation..................................60

8.1 Application Information............................................. 60

8.2 Typical Application.................................................... 81

8.3 Power Supply Recommendations.............................82

8.4 Layout....................................................................... 82

9 Device and Documentation Support............................84

9.1 Documentation Support............................................ 84

9.2 接收文档更新通知..................................................... 84

9.3 支持资源....................................................................84

9.4 商标...........................................................................84

9.5 Electrostatic Discharge Caution................................84

9.6 术语表....................................................................... 84

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Typical Characteristics................................................9

7 Detailed Description......................................................54

7.1 Overview...................................................................54

7.2 Functional Block Diagram.........................................55

7.3 Feature Description...................................................56

Information.................................................................... 84

10.1 Mechanical Data..................................................... 85

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

July 2022

*

Initial release

2

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5 Pin Configuration and Functions

IN

1

2

3

4

12

11

10

9

OUT

Thermal

Pad

Not to scale

图5-1. RTE Package, 16-Pin WQFN (Top View)

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

BIAS supply voltage pin. See the Charge Pump Enable and BIAS Rail section for

BIAS

5

I

additional information.

Charge pump enable pin. See the Charge Pump Enable and BIAS Rail section for

additional information.

CP_EN

15

I

EN

16

6

Enable pin. See the Precision Enable and UVLO section for additional information.

Ground pin. See the Layout Guidelines section for additional information.

GND

I

Input supply voltage pin. See the Input and Output Capacitor Requirements (C_INand

C_OUT) section for more details.

IN

1, 2, 3, 4

8

Noise-reduction pin. See the Programmable Soft-Start (NR/SS Pin) and Soft-Start, Noise

Reduction (NR/SS Pin), and Power-Good (PG Pin) sections for additional information.

NR/SS

I/O

Regulated output pin. See the Output Voltage Setting and Regulation and Input and

Output Capacitor Requirements (C_INand C_OUT) sections for more details.

OUT

9, 10, 11, 12

O

Open-drain, power-good indicator pin for the low-dropout regulator (LDO) output voltage.

See the Power-Good Pin (PG Pin) section for additional information.

PG

14

7

O

Reference pin. See the Output Voltage Setting and Regulation section for additional

information.

REF

I/O

I

Output sense pin. See the Output Voltage Setting and Regulation section for additional

information.

SNS

13

—

Connect the pad to GND for best possible thermal performance. See the Layout section for

more information.

Thermal Pad

GND

(1) I = input, O = output, I/O = input or output, G = ground.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range and all voltages with respect to GND (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

BIAS

11.2

–0.3

IN, PG, EN, CP_EN

REF, NR/SS, SNS

OUT

6.5

6

Voltage

V

V_IN+ 0.3 ⁽²⁾

OUT

Internally limited

A

Current

PG (sink current into the device)

Operating junction, T_J

Storage, T_stg

5

150

mA

–40

–55

Temperature

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) The absolute maximum rating is V_IN+ 0.3 V or 6.0 V, whichever is smaller.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

4

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6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

MIN

0.7

0.5

3

TYP

MAX

UNIT

V

V_IN

Input supply voltage range

Reference voltage range

Output voltage range

Bias voltage range

6

5.3

5.2

11

V_REF

V_OUT

V_BIAS

I_OUT

V

Output current

0

5

A

C_IN

Input capacitor

4.7

22

2

10

22

1000

3000

20

µF

mΩ

nH

µF

kΩ

°C

C_OUT

C_{OUT_ESL}

Z_{OUT_ESL}

C_BIAS

C_NR/SS

R_PG

Output capacitor ⁽¹⁾

Output capacitor ESR

Total impedance ESL

Bias pin capacitor

0.2

0

1

100

10

Noise-reduction capacitor

Power-good pull-up resistance

Junction temperature

0.1

10

4.7

100

125

T_J

–40

(1) Effective output capacitance of 15 µF minimum required for stability

6.4 Thermal Information

TPS7A57

RTE (WQFN) RTE (WQFN)

THERMAL METRIC ⁽¹⁾

UNIT

(2)

(3)

16 PINS

40.3

39.3

14

16 PINS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

21.9

°C/W

R_θJC(top)

R_θJB

–

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

0.4

ψ_JT

14.0

1.8

11.9

ψ_JB

R_θJC(bot)

–

(1) For more information about traditional and new thermal metrics, see the Using New Thermal Metric application report.

(2) Evaluated using JEDEC standard (2s2p).

(3) Evaluated using EVM.

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6.5 Electrical Characteristics

over operating temperature range (T_J= –40 °C to +125 °C), V_IN(NOM)= V_OUT(NOM)+ 0.4 V, V_{CP_EN}= 1.8 V, V_BIAS= 0 V, I_OUT

= 0 A, V_EN= 1.8 V, C_IN= 10 µF, C_OUT= 22 μF, C_BIAS= 0 nF, C_NR/SS= 100 nF, SNS pin shorted to OUT pin, and PG pin

pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_INrising, V_{CP_EN}= 1.8 V (3 V ≤V_BIAS≤11 V) and

V_{CP_EN}= 0 V (V_OUT+ 3.2 V ≤V_BIAS≤11 V)

V_UVLO(IN)

Input supply UVLO with BIAS

0.67

0.7

V

Input supply UVLO hysteresis

with BIAS

V_{CP_EN}= 1.8 V (3 V ≤V_BIAS≤11 V) and V_{CP_EN}= 0 V

(V_OUT+ 3.2 V ≤V_BIAS≤11 V)

V_{HYS(UVLO_IN)}

V_UVLO(IN)

50

1.07

50

mV

V

Input supply UVLO without BIAS V_INrising, V_{CP_EN}= 1.8 V

1.1

2.95

Input supply UVLO hysteresis

V_{CP_EN}= 1.8 V

V_{HYS(UVLO_IN)}

mV

without BIAS

BIAS UVLO relative to V_REF

without CP

V_UVLO(BIAS)

V_REF

–

2.1

V

V_BIASrising, V_{CP_EN}= 0 V, 1.4 V ≤V_REF≤5.2 V

V_{HYS(UVLO_BIAS -}BIAS UVLO relative to V_REF

240

mV

V_{CP_EN}= 0 V, 1.4 V ≤V_REF≤5.2 V

hysteresis without CP

REF)

V_UVLO(BIAS)

BIAS UVLO with CP

2.8

V

V_BIASrising, V_{CP_EN}= 1.8 V, 0.7 V ≤V_IN< 1.1 V

V_{CP_EN}= 1.8 V, 0.7 V ≤V_IN< 1.1 V

V_{HYS(UVLO_BIAS)}BIAS UVLO hysteresis with CP

115

mV

NR/SS fast start-up charging

current

I_NR/SS

V_NR/SS= GND, V_IN= 1.1 V

0.2

mA

0.5 V ≤V_OUT≤5.2 V,

0 A ≤I_OUT≤5 A,

V_{CP_EN}= 0 V, V_OUT+ 3.2 V ≤V_BIAS≤11 V; 0.7 V ≤

V_OUT

Output voltage accuracy ⁽¹⁾

1

%

V_IN≤6 V ⁽²⁾

,

–1

V_{CP_EN}= 1.8 V, 3 V ≤V_BIAS≤11 V, 0.7 V ≤V_IN≤6 V

(2)

,

V_{CP_EN}= 1.8 V, no BIAS, 1.1 V ≤V_IN≤6 V

V_IN= 1.1 V, V_{CP_EN}= 1.8 V, V_OUT= 0.5 V,

I_LOAD= 0 A, V_BIAS= 0 V

50

µA

V_{CP_EN}= 0 V (CP disabled),

0.7 V ≤V_IN≤6 V ^{(1) (2)}, 0.5 V ≤V_OUT≤5.2 V,

V_OUT+ 3.2 V ≤V_BIAS≤11 V,

0 A ≤I_OUT≤5 A

1

–1

I_REF

REF current pin

V_{CP_EN}= 1.8 V (CP enabled, V_BIAS= 0 V),

1.1 V ≤V_IN≤6 V ⁽¹⁾, 0.5 V ≤V_OUT≤5.2 V,

0 A ≤I_OUT≤5 A ⁽²⁾

%

1

2

–1

–2

V_{CP_EN}= 1.8 V (CP enabled),

0.7 V ≤V_IN≤6 V ⁽¹⁾, 0.5 V ≤V_OUT≤5.2 V,

3 V ≤V_BIAS≤11 V, 0 A ≤I_OUT≤5 A

V_IN= 0.7 V, V_OUT= 0.5 V, I_OUT= 0 A,

V_{CP_EN}= 1.8 V, 3 V ≤V_BIAS≤11 V,

V_{CP_EN}= 0 V, V_OUT+ 3.2 V ≤V_BIAS≤11 V

0.7 V ≤V_IN≤6 V ^{(1) (2)}, 0.5 V ≤V_OUT≤5.2 V,

V_{CP_EN}= 1.8 V, 3 V ≤V_BIAS≤11 V,

0 A ≤I_OUT≤5 A

Output offset voltage (V_NR/SS

-

V_OS

mV

V_OUT

)

1.1 V ≤V_IN≤6.0 V ^{(1) (2)}, 0.5 V ≤V_OUT≤5.2 V,

V_{CP_EN}= 1.8 V, V_BIAS= 0 V,

0 A ≤I_OUT≤5 A

0.7 V ≤V_IN≤6 V ^{(1) (2)}, 0.5 V ≤V_OUT≤5.2 V,

V_{CP_EN}= 0 V, V_OUT+ 3.2 V ≤V_BIAS≤11 V,

0 A ≤I_OUT≤5 A

V_OUT+ 3.2 V ≤V_BIAS≤11 V, V_IN= 0.7V, V_OUT= 0.5 V,

V_{CP_EN}= 0 V, I_OUT= 0 A

0.15

0.06

0.03

0.01

nA/V

µV/V

nA/V

µV/V

ΔI_REF(ΔVBIAS)

ΔV_OS(ΔVBIAS)

ΔI_REF(ΔVIN)

ΔV_OS(ΔVIN)

Line regulation: ΔI_REF

Line regulation: ΔV_OS

Line regulation: ΔI_REF

Line regulation: ΔV_OS

V_OUT+ 3.2 V ≤V_BIAS≤11 V, V_IN= 0.7 V, V_OUT= 0.5 V,

V_{CP_EN}= 0 V, I_OUT= 0 A

1.1 V ≤V_IN≤6 V, V_OUT= 0.5 V, V_{CP_EN}= 1.8 V,

I_OUT= 0 A, V_BIAS= 0 V

1.1 V ≤V_IN≤6 V, V_OUT= 0.5 V, V_{CP_EN}= 1.8 V,

I_OUT= 0 A, V_BIAS= 0 V

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6.5 Electrical Characteristics (continued)

over operating temperature range (T_J= –40 °C to +125 °C), V_IN(NOM)= V_OUT(NOM)+ 0.4 V, V_{CP_EN}= 1.8 V, V_BIAS= 0 V, I_OUT

= 0 A, V_EN= 1.8 V, C_IN= 10 µF, C_OUT= 22 μF, C_BIAS= 0 nF, C_NR/SS= 100 nF, SNS pin shorted to OUT pin, and PG pin

pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN= 0.7 V, V_OUT= 0.5 V, V_{CP_EN}= 0 V, 0 A ≤I_OUT≤5

A,

5

V_OUT+ 3.2 V ≤V_BIAS≤11 V

µV/A

ΔV_OS(ΔIOUT)

Load regulation: ΔV_OS

V_OUT= 5.2 V, V_{CP_EN}= 1.8 V, 0 A ≤I_OUT≤5 A,

V_BIAS= 0 V

175

Change in I_REFvs V_REF

Change in V_OSvs V_REF

4.4

nA

0.5 V ≤V_REF≤5.2 V, V_IN= 6 V, I_OUT= 0 A,

V_{CP_EN}= 1.8 V, V_BIAS= 0 V

0.25

mV

1.1 V ≤V_IN≤5.3 V, I_OUT= 5 A, V_{CP_EN}= 1.8 V,

–40°C ≤T_J≤+125°C

75

110

100

110

100

110

100

1.1 V ≤V_IN≤5.3 V, I_OUT= 5 A, V_{CP_EN}= 1.8 V,

–40°C ≤T_J≤+85°C

0.7 V ≤V_IN≤1.1 V, I_OUT= 5 A, V_{CP_EN}= 1.8 V,

V_BIAS= 3 V, –40°C ≤T_J≤+125°C

V_DO

Dropout voltage ⁽³⁾

mV

0.7 V ≤V_IN≤1.1 V, I_OUT= 5 A, V_{CP_EN}= 1.8 V,

V_BIAS= 3 V, –40 °C ≤T_J≤+85 °C

0.7 V ≤V_IN≤5.3 V, I_OUT= 5 A, V_{CP_EN}= 0 V,

V_BIAS= V_IN+ 3.2 V, –40°C ≤T_J≤+125°C

0.7 V ≤V_IN≤5.3 V, I_OUT= 5 A, V_{CP_EN}= 0 V,

V_BIAS= V_IN+ 3.2 V, –40°C ≤T_J≤+85°C

V_OUTforced at 0.9 × V_OUT(NOM)

,

V_OUT(NOM)= 5.2 V,

V_IN= V_OUT(NOM)+ 400 mV,

V_{CP_EN}= 0 V, V_BIAS= V_OUT+ 3.2 V

I_LIM

Output current limit

5.2

6.0

6.7

A

I_SC

Short circuit current limit

4

R_LOAD= 10 mΩ, under foldback operation

V_IN= 6 V, I_OUT= 0 A, V_{CP_EN}= 0 V, V_BIAS= V_OUT+ 3.2 V,

V_OUT= 5.2 V

1

8

1.5

2

15

I_BIAS

I_GND

I_SDN

BIAS pin current

mA

µA

V_IN= 0.7 V, I_OUT= 5 A, V_OUT= 0.5 V,

V_{CP_EN}= 1.8 V, 3.0 V ≤V_BIAS≤11 V

11

5

V_IN= 6 V, I_OUT= 0 A, V_{CP_EN}= 0 V, V_BIAS= V_OUT+ 3.2 V,

V_OUT= 5.2 V

3.5

6.5

V_IN= 5.6 V, I_OUT= 5 A, V_OUT= 5.2 V, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V

16.5

17.5

16.5

7

V_IN= 1.1 V, I_OUT= 5 A, V_OUT= 0.5 V,

V_{CP_EN}= 1.8 V, V_BIAS= 0 V

12

11

5

24

23

GND pin current

V_IN= 0.7 V, I_OUT= 5 A, V_OUT= 0.5 V,

V_{CP_EN}= 1.8 V, 3 V ≤V_BIAS≤11 V

V_IN= 0.7 V, I_OUT= 5 A, V_OUT= 0.5 V,

V_{CP_EN}= 0 V, V_OUT+ 3.2 V ≤V_BIAS≤11 V

9

PG = (open), V_IN= 6 V, V_EN= 0.4 V, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V

100

150

300

Shutdown GND pin current

PG = (open), V_IN= 6 V, V_EN= 0.4 V, V_{CP_EN}= 0.4 V,

V_BIAS= 11 V

450

5

I_EN

EN pin current

-5

µA

V

V_IN= 6 V, 0 V ≤V_EN≤6 V, V_{CP_EN}= 1.8 V, V_BIAS= 0 V

V_IN= 1.1 V (V_{CP_EN}= 1.8 V) or

V_IH(EN)

EN trip point rising (turn-on)

0.62

0.65

40

0.68

V

_BIAS≥3 V (V_{CP_EN}= 0 V)

V_IN= 1.1 V (V_{CP_EN}= 1.8 V) or

_BIAS≥3 V (V_{CP_EN}= 0 V)

V_HYS(EN)

I_{CP_EN}

EN trip point hysteresis

CP_EN pin current

mV

µA

V

5

V_IN= 6.0 V, 0 V ≤V_{CP_EN}≤6 V

–5

1.1 V ≤V_IN≤6 V, V_EN= 1.8 V, V_BIAS= 0 V,

0.7 V ≤V_IN≤1.1 V, V_EN= 1.8 V, V_BIAS= 3 V

V_{IH(CP_EN)}

CP_EN trip point rising (turn-on)

0.57

0.6

56

0.63

1.1 V ≤V_IN≤6 V, V_EN= 1.8 V, V_BIAS= 0 V,

0.7 V ≤V_IN≤1.1 V, V_EN= 1.8 V, V_BIAS= 3 V

V_{HYS(CP_EN)}

CP_EN trip point hysteresis

mV

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6.5 Electrical Characteristics (continued)

over operating temperature range (T_J= –40 °C to +125 °C), V_IN(NOM)= V_OUT(NOM)+ 0.4 V, V_{CP_EN}= 1.8 V, V_BIAS= 0 V, I_OUT

= 0 A, V_EN= 1.8 V, C_IN= 10 µF, C_OUT= 22 μF, C_BIAS= 0 nF, C_NR/SS= 100 nF, SNS pin shorted to OUT pin, and PG pin

pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

For PG transitioning low with falling V_OUT, V_IN= 1.1 V,

V_BIAS= 0 V, V_{CP_EN}= 1.8 V, V_OUT< V_IT(PG), I_PG= –1 mA

(current into device)

V_IT(PG)

PG pin threshold

87

90

93

%

V_IN= 1.1 V, V_BIAS= 0 V, V_{CP_EN}= 1.8 V, V_OUT< V_IT(PG)

I_PG= –1 mA (current into device)

,

V_HYS(PG)

V_OL(PG)

I_LKG(PG)

PG pin hysteresis

2

%

V

V_IN= 1.1 V, V_BIAS= 0 V, V_{CP_EN}= 1.8 V, V_OUT< V_IT(PG)

,

PG pin low-level output voltage

PG pin leakage current

0.4

1

I_PG= –1 mA (current into device)

V_PG= 6 V, V_OUT> V_IT(PG),V_IN= 1.1 V, V_BIAS= 0 V,

V_{CP_EN}= 1.8 V

µA

f = 1 MHz, V_IN= 0.8 V, V_OUT(NOM)= 0.5 V, V_{CP_EN}= 0 V,

V_BIAS= V_OUT+ 3.2 V, I_OUT= 5 A, C_NR/SS= 4.7 µF

40

36

f = 1 MHz, V_IN= 0.9 V, V_OUT(NOM)= 0.5 V, V_{CP_EN}= 0 V,

V_BIAS= V_OUT+ 3.2 V, I_OUT= 5 A, C_NR/SS= 4.7 µF

PSRR

Power-supply ripple rejection

dB

f = 1 MHz, V_IN= 5.3 V, V_OUT(NOM)= 5 V, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V, I_OUT= 5 A, C_NR/SS= 4.7 µF

f = 1 MHz, V_IN= 5.4 V, V_OUT(NOM)= 5 V, , V_{CP_EN}= 1.8 V,

V_BIAS= 0 V, I_OUT= 5 A, C_NR/SS= 4.7 µF

BW = 10 Hz to 100 kHz,

2.49

20

0.7V ≤V_IN≤6 V, 0.5 V ≤V_OUT≤5.2 V, I_OUT= 5 A,

C_NR/SS= 4.7 µF, V_{CP_EN}= 0 V, V_BIAS= V_OUT+ 3.2 V

V_n

Output noise voltage

µV_RMS

BW = 10 Hz to 100 kHz,

1.1 V ≤V_IN≤6 V, 0.5 V ≤V_OUT≤5.2 V,

I_OUT= 5 A, C_NR/SS= 4.7 µF, V_{CP_EN}= 1.8 V, V_BIAS= 0 V

f = 100 Hz, 0.7 V ≤V_IN≤6 V,

0.5 V ≤V_OUT≤5.2 V, I_OUT= 5 A, C_NR/SS= 4.7 µF,

V_{CP_EN}= 0 V, V_BIAS= V_OUT+ 3.2 V

f = 1 kHz, 0.7 V ≤V_IN≤6 V, 0.5 V ≤V_OUT≤5.2 V,

I_OUT= 5 A, C_NR/SS= 4.7 µF, V_{CP_EN}= 0 V,

V_BIAS= V_OUT+ 3.2 V

Noise spectral density

9

nV/√Hz

f = 10 kHz, 0.7 V ≤V_IN≤6 V, 0.5 V ≤V_OUT≤5.2 V,

I_OUT= 5 A, C_NR/SS= 4.7 µF, V_{CP_EN}= 0 V,

V_BIAS= V_OUT+ 3.2 V

6

Output pin active discharge

resistance

R_DIS

V_IN= 1.1 V, V_{CP_EN}= 1.8 V, V_BIAS= 0 V, V_EN= 0 V

110

Ω

NR/SS pin active discharge

resistance

R_{NR/SS_DIS}

T_SD(shutdown)

T_SD(reset)

100

165

150

Ω

°C

Thermal shutdown temperature Shutdown, temperature increasing

Thermal shutdown reset

Reset, temperature decreasing

temperature

(1) Max power dissipation of 2 W.

(2) Limited by pulse max power dissipation. For 0 mA ≤I_OUT≤2.5 A, V_IN= 6 V, 0 mA ≤I_OUT≤5 A, V_IN= 5.6 V.

(3) V_REF= V_IN, V_SNS= 97% × V_REF.

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6.6 Typical Characteristics

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= V_IN,

V_OUT= 0.9 V, V_BIAS= 0 V, I_OUT= 5 A

V_OUT= 0.5 V, V_BIAS= 3 V, I_OUT= 5 A

图6-1. PSRR vs Frequency and V_INfor CP Enabled,

图6-2. PSRR vs Frequency and V_INfor CP Enabled, Minimum

No Bias

Bias

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_OUT= 0.5 V, V_BIAS= 11 V, I_OUT= 5 A

V_OUT= 3.3 V, V_BIAS= 6.5 V, I_OUT= 5 A

图6-3. PSRR vs Frequency and V_INfor CP Disabled, Maximum

图6-4. PSRR vs Frequency and V_INfor CP Disabled, Minimum

Bias

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V, V_IN=

V_OUT= 5.2 V, V_BIAS= 11 V, I_OUT= 5 A

1.2 V, V_OUT= 0.9 V, V_BIAS= 0 V, I_OUT= 5 A

图6-5. PSRR vs Frequency and V_INfor CP Disabled, Maximum

图6-6. PSRR vs Frequency and I_OUTfor CP Enabled,

Bias

No Bias

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V, V_IN= 1.2 V,

V_IN= 1.2 V, V_OUT= 0.9 V, I_OUT= 5 A

V_OUT= 0.9 V, V_BIAS= 11 V, I_OUT= 5 A

图6-7. PSRR vs Frequency and V_BIASfor CP Enabled

图6-8. PSRR vs Frequency and C_NR/SSfor CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_IN= 1.2 V, V_OUT= 0.9 V, I_OUT= 5 A

V_IN= 0.8 V, V_OUT= 0.5 V, I_OUT= 5 A

图6-9. PSRR vs Frequency and V_BIASfor CP Disabled

图6-10. BIAS PSRR vs Frequency and V_BIASfor CP Enabled, V_IN

= 0.8 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, V_{CP_EN}= 0 V, V_IN= 1.2 V, V_OUT= 0.9

V_IN= 1.2 V, V_OUT= 0.9 V, I_OUT= 5 A

V, V_BIAS= 11 V, I_OUT= 5 A

图6-11. BIAS PSRR vs Frequency and V_BIASfor CP Disabled,

图6-12. PSRR vs Frequency and C_OUT

V_IN= 1.2 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_OUT= V_IN–300 mV, V_BIAS= 11 V, I_OUT= 5 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= V_IN,

V_IN= 0.8 V, V_OUT= 0.5 V, V_BIAS= 3.7 V

图6-14. Output Voltage Noise Density vs Frequency and I_OUTfor

图6-13. PSRR vs Frequency and V_IN

CP Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= V_IN, V_IN= 5.3 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 5.3 V, V_OUT= 5

V_OUT= 5 V, I_OUT= 5 A

V, V_BIAS= 11 V, I_OUT= 5 A

图6-15. Output Voltage Noise Density vs Frequency and C_NR/SS图6-16. Output Voltage Noise Density vs Frequency and I_OUTfor

for CP Enabled

CP Disabled

C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 5.3 V, V_OUT= 5 V,

C_NR/SS= C_IN= 4.7 μF, V_IN= 5.3 V, V_OUT= 5 V

图6-18. RMS Noise vs C_NR/SS

V_BIAS= 11 V

图6-17. Output Voltage Noise Density vs Frequency and C_NR/SS

for CP Disabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, CP_EN = GND, V_IN= 0.8 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 0.8 V,

V_OUT= 0.5 V, V_BIAS= 3.7 V

V_BIAS= 3.7 V, I_OUT= 5 A

图6-19. Output Voltage Noise Density vs Frequency and C_OUT

图6-20. Output Voltage Noise Density vs Frequency and V_{CP_EN}

for V_OUT= 0.5 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 1.2 V, I_OUT= 5 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 1.5 V, I_OUT= 5 A

图6-21. Output Voltage Noise Density vs Frequency and V_{CP_EN}图6-22. Output Voltage Noise Density vs Frequency and V_{CP_EN}

for V_OUT= 0.9 V

for V_OUT= 1.2 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 3.6 V, I_OUT= 5 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 2.1 V, I_OUT= 5 A

图6-24. Output Voltage Noise Density vs Frequency and V_{CP_EN}

图6-23. Output Voltage Noise Density vs Frequency and V_{CP_EN}

for V_OUT= 3.3 V

for V_OUT= 1.8 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 5.3 V, I_OUT= 5 A

C_NR/SS= C_IN= 4.7 μF, V_{CP_EN}= V_IN, C_OUT= 22 μF,

V_IN= 0.8 V, I_OUT= 5 A

图6-25. Output Voltage Noise Density vs Frequency and V_{CP_EN}图6-26. Output Voltage Noise Density vs Frequency and V_BIAS

for V_OUT= 5 V for V_OUT= 0.5 V, CP Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, V_{CP_EN}= 0 V, C_OUT= 22 μF,

C_NR/SS= C_IN= 4.7 μF, V_{CP_EN}= 1.8 V, C_OUT= 22 μF,

V_IN= 5.3 V, I_OUT= 5 A

I_OUT= 5 A

图6-27. Output Voltage Noise Density vs Frequency and V_BIAS

图6-28. RMS Noise vs V_OUTfor CP Enabled

for V_OUT= 5 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, V_{CP_EN}= 1.8 V, C_OUT= 22 μF,

C_NR/SS= C_IN= 4.7 μF, V_{CP_EN}= 0 V, C_OUT= 22 μF, I_OUT= 5

V_IN= V_OUT+ 0.3 V, I_OUT= 5 A

A

图6-29. Output Voltage Noise Density vs Frequency and V_OUT

for CP Enabled

图6-30. RMS Noise vs V_OUTfor CP Disabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, V_{CP_EN}= 0 V, C_OUT= 22 μF,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= V_OUT+ 0.3 V,

V_IN= V_OUT+ 0.3 V, I_OUT= 5 A

V_{CP_EN}= V_IN, V_BIAS= 0 V, V_OUT= 5 V

图6-31. Output Voltage Noise Density vs Frequency and V_OUT

图6-32. Charge Pump Output Voltage Noise Density vs

for CP Disabled

Frequency and I_OUT

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 3 V, V_IN= 0.8 V, SR = 1 A/μs

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V, V_IN= 1.1 V, SR = 1 A/μs

图6-33. Load Transient for V_OUT= 0.5 V, I_OUT= 100 mA to 5 A,

图6-34. Load Transient for V_OUT= 0.5 V, I_OUT= 100 mA to 5 A,

CP Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V, V_IN= 3.6 V, SR = 1 A/μs

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V, V_IN= 5.5 V, SR = 1 A/μs

图6-35. Load Transient for V_OUT= 3.3 V, I_OUT= 100 mA to 5 A,

图6-36. Load Transient for V_OUT= 5.2 V, I_OUT= 100 mA to 5 A,

CP Enabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 3.7 V, V_IN= 0.8 V

图6-37. Load Transient for V_OUT= 0.5 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 0.5 A/μs

图6-38. Load Transient for V_OUT= 0.5 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 1 A/μs

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 11 V, V_IN= 0.8 V

V_BIAS= 6.5 V, V_IN= 3.6 V

图6-39. Load Transient for V_OUT= 0.5 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 1 A/μs, V_BIAS= 11 V

图6-40. Load Transient for V_OUT= 3.3 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 0.5 A/μs, V_BIAS= 6.5 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 6.5 V, V_IN= 3.6 V

V_BIAS= 11 V, V_IN= 3.6 V

图6-41. Load Transient for V_OUT= 3.3 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 1 A/μs, V_BIAS= 6.5 V

图6-42. Load Transient for V_OUT= 3.3 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 1 A/μs, V_BIAS= 11 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 8.4 V, V_IN= 5.5 V

图6-43. Load Transient for V_OUT= 5.2 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 0.5 A/μs, V_BIAS= 8.4 V

图6-44. Load Transient for V_OUT= 5.2 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 1 A/μs, V_BIAS= 8.4 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 8.4 V, V_IN= 5.5 V

图6-45. Load Transient for V_OUT= 5.2 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 5 A/μs, V_BIAS= 8.4 V

图6-46. Load Transient for V_OUT= 5.2 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 10 A/μs, V_BIAS= 8.4 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V, V_BIAS

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

=

5 V, V_OUT= 0.5 V, I_OUT= 100 mA, SR = 1 V/μs

V_BIAS= 11 V, V_IN= 5.5 V

图6-48. IN Line Transient for V_IN= 0.9 V to 1.2 V

图6-47. Load Transient for V_OUT= 5.2 V, I_OUT= 100 mA to 5 A,

CP Disabled, SR = 1 A/μs, V_BIAS= 11 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V, V_BIAS

5 V, V_OUT= 0.5 V, I_OUT= 100 mA, SR = 1 V/μs

=

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_IN= 0.8 V, V_OUT= 0.5 V, SR = 1 V/μs

图6-49. IN Line Transient for V_IN= 0.9 V to 6 V

图6-50. BIAS Line Transient for V_IN= 0.9 V to 6 V,

I_OUT= 100 mA

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_IN= 0.8 V, V_OUT= 0.5 V, SR = 1 V/μs

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 9 V, V_IN= 5.5 V, V_OUT(nom)= 5.2 V

图6-52. Start-Up Under Current Limit

图6-51. BIAS Line Transient for V_IN= 0.9 V to 6 V, I_OUT= 5 A

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 5 V, V_IN= 0.8 V, V_OUT= 0.5 V

图6-53. Start-Up for BIAS-EN-IN Rail Sequence for CP Disabled 图6-54. Start-Up for EN-BIAS-IN Rail Sequence for CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 5 V, V_IN= 0.8 V, V_OUT= 0.5 V

图6-55. Start-Up for EN-IN-BIAS Rail Sequence for CP Disabled 图6-56. Start-Up for IN-BIAS-EN Rail Sequence for CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 3 V,

V_BIAS= 5 V, V_IN= 0.8 V, V_OUT= 0.5 V

V_BIAS= 5 V, V_IN= 0.7 V, V_OUT= 0.5 V, I_OUT= 5 A

图6-57. Start-Up for IN-EN-BIAS Rail Sequence for CP Disabled

图6-58. Start-Up for CP_EN-BIAS-IN Rail Sequence for CP

Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 3 V,

C_NR/SS= 100 nF, C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 3 V,

V_BIAS= 5 V, V_IN= 0.7 V, V_OUT= 0.5 V, I_OUT= 5 A

V_BIAS= 9 V, V_IN= 5.6 V, V_OUT= 5.2 V

图6-59. Start-Up for IN-CP_EN-EN Rail Sequence for CP

图6-60. Start-Up for IN-BIAS-EN Rail Sequence for CP Disabled,

Enabled

V_OUT= 5.2 V, C_NR/SS= 100 nF

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 3 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 9 V, V_IN= 5.6 V, V_OUT= 5.2 V, I_OUT= 5 A

V_BIAS= 5 V, V_IN= 0.7 V, V_OUT= 0.5 V

图6-61. Start-Up for IN-BIAS-EN-PG Rail Sequence for CP

Disabled, V_OUT= 5.2 V, C_NR/SS= 4.7 μF

图6-62. Inrush Current for CP Disabled, V_OUT= 0.5 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 5 V, V_IN= 0.7 V, V_OUT= 0.5 V

V_BIAS= 9 V, V_IN= 5.5 V, V_OUT= 5.2 V

图6-63. Inrush Current for CP Disabled, V_OUT= 0.5 V,

First 500 μs

图6-64. Inrush Current for CP Disabled, V_OUT= 5.2 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 9 V, V_IN= 5.5 V, V_OUT= 5.2 V

V_BIAS= 0 V, I_OUT= 5 A

图6-65. Inrush Current for CP Disabled, V_OUT= 5.2 V,

图6-66. Dropout Voltage vs V_INfor CP Enabled,

First 500 μs

No Bias Rail

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

I_OUT= 5 A

图6-67. Dropout Voltage vs V_INfor CP Enabled, V_BIAS= 3 V

图6-68. Dropout Voltage vs V_INfor CP Enabled,

V_BIAS= V_IN+ 3.2 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

I_OUT= 5 A

图6-69. Dropout Voltage vs V_BIASfor CP Enabled,

图6-70. Dropout Voltage vs V_BIASfor CP Disabled,

V_IN= 0.7 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V

图6-71. Dropout Voltage vs I_OUTfor CP Disabled,

图6-72. Dropout Voltage vs I_OUTfor CP Enabled, V_IN= 0.7 V,

V_IN= 0.7 V, V_BIAS= 3.9 V

V_BIAS= 3 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V

图6-73. Dropout Voltage vs I_OUTfor CP Enabled, V_IN= 1.1 V, No 图6-74. Dropout Voltage vs I_OUTfor CP Enabled, V_IN= 5.3 V, No

Bias

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V

V_BIAS= 0 V

图6-75. Dropout Voltage vs I_OUTfor CP Enabled, V_IN= 6 V, No

图6-76. Dropout Voltage vs I_OUTfor CP Enabled, V_IN= 5.3 V,

Bias

V_BIAS= 3 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V

图6-77. Dropout Voltage vs I_OUTfor CP Enabled, V_IN= 6 V, V_BIAS

图6-78. Dropout Voltage vs I_OUTfor CP Disabled,

= 3 V

V_IN= 5.3 V, V_BIAS= 9.2 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V

图6-80. Output Discharge Resistor vs V_IN

图6-79. Dropout Voltage vs I_OUTfor CP Disabled, V_IN= 6 V, V_BIAS

= 9.2 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V

V_BIAS= 0 V, V_IN= 1.1 V

图6-81. Fast Soft-Start Current vs Temperature and V_IN

图6-82. Reference Current vs Temperature

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V, V_IN= 1.1 V, V_OUT= 0.5 V

V_BIAS= 0 V, V_IN= 6 V, I_OUT= 0 A

图6-84. Reference Current Accuracy vs I_OUT

图6-83. Change in Reference Current vs V_REF

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 3 V, V_OUT= 0.5 V

V_BIAS= 3.7 V, V_OUT= 0.5 V

图6-85. Reference Current Accuracy vs V_INfor CP Enabled

图6-86. Reference Current Accuracy vs V_INfor CP Disabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_IN= 0.7 V, V_OUT= 0.5 V

图6-87. Reference Current Accuracy vs V_BIASfor CP Disabled,

图6-88. Reference Current Accuracy vs V_BIASfor CP Enabled,

I_OUT= 0 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-90. I_REFDistribution

V_IN= 0.7 V, V_OUT= 0.5 V

图6-89. Reference Current Accuracy vs V_BIASfor CP Disabled,

I_OUT= 5 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-91. V_OSDistribution

V_IN= 5.5 V, V_OUT= 5.2 V

图6-92. Offset Voltage vs I_OUT

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 3.7 V, V_OUT= 0.5 V, I_OUT= 0 A

V_BIAS= 0 V, V_IN= 6 V, I_OUT= 0 A

图6-93. Offset Voltage vs V_IN

图6-94. Offset Voltage vs V_OUT

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 11 V, V_OUT= 0.5 V, I_OUT= 0 A

V_BIAS= 3.7 V, V_OUT= 0.5 V, I_OUT= 0 A

图6-95. Output Voltage Accuracy vs V_INfor V_BIAS= 11 V,

图6-96. Output Voltage Accuracy vs V_INfor V_BIAS= 3.7 V, CP

CP Disabled

Disabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V, V_IN= 6

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V, V_OUT= 0.5 V, I_OUT= 0 A

V_IN= 0.7 V, V_OUT= 0.5 V, I_OUT= 0 A

图6-97. Output Voltage Accuracy vs V_BIASfor V_IN= 6 V,

图6-98. Output Voltage Accuracy vs V_BIASfor V_IN= 0.7 V, CP

CP Disabled

Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 11 V, V_IN= 0.7 V, V_OUT= 0.5 V, I_OUT= 0 A

图6-99. Output Voltage Accuracy vs I_OUTfor V_BIAS= 11 V, CP

图6-100. Output Voltage Accuracy vs I_OUTfor V_BIAS= 3.7 V, CP

Disabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 11 V, V_IN= 6 V, V_OUT= 5.2 V, I_OUT= 0 A

V_BIAS= 8.4 V, V_IN= 6 V, V_OUT= 5.2 V, I_OUT= 0 A

图6-101. Output Voltage Accuracy vs I_OUTfor V_IN= 6 V,

图6-102. Output Voltage Accuracy vs I_OUTfor V_IN= 6 V, V_BIAS=

V_BIAS= 11 V, CP Disabled

8.4 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 11 V, V_IN= 5.6 V, V_OUT= 5.2 V, I_OUT= 0 A

V_BIAS= 8.4 V, V_IN= 5.6 V, V_OUT= 5.2 V, I_OUT= 0 A

图6-103. Output Voltage Accuracy vs I_OUTfor V_IN= 5.6 V, V_BIAS= 图6-104. Output Voltage Accuracy vs I_OUTfor V_IN= 5.6 V, V_BIAS

11 V, CP Disabled 8.4 V, CP Disabled

=

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V, V_IN= 0.7 V, V_OUT= 0.5 V, I_OUT= 0 A

V_BIAS= 0 V, V_IN= 1.1 V, V_OUT= 0.5 V

图6-105. Output Voltage Accuracy vs V_INfor CP Enabled

图6-106. Output Voltage Accuracy vs I_OUTfor V_IN= 1.1 V, CP

Enabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 0 V, V_IN= 6 V, V_OUT= 5.2 V

V_BIAS= 0 V, V_IN= 5.6 V, V_OUT= 5.2 V

图6-107. Output Voltage Accuracy vs I_OUTfor V_IN= 6 V,

图6-108. Output Voltage Accuracy vs I_OUTfor V_IN= 5.6 V, CP

CP Enabled

Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 11 V, V_OUT= 0.5 V, I_OUT= 0 A

V_BIAS= 3 V, V_OUT= 0.5 V, I_OUT= 0 A

图6-109. Output Voltage Accuracy vs V_INfor V_BIAS= 11 V, CP

图6-110. Output Voltage Accuracy vs V_INfor V_BIAS= 3 V,

Enabled

CP Enabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_IN= 6 V, V_OUT= 0.5 V, I_OUT= 0 A

V_IN= 0.7 V, V_OUT= 0.5 V, I_OUT= 0 A

图6-111. Output Voltage Accuracy vs V_BIASfor V_IN= 6 V,

图6-112. Output Voltage Accuracy vs V_BIASfor V_IN= 0.7 V, CP

CP Enabled

Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 11 V, V_IN= 0.7 V, V_OUT= 0.5 V

图6-113. Output Voltage Accuracy vs I_OUTfor V_OUT= 0.5 V, V_BIAS图6-114. Output Voltage Accuracy vs I_OUTfor V_OUT= 0.5 V, V_BIAS

= 11 V, CP Enabled

= 3 V, CP Enabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 11 V, V_IN= 6 V, V_OUT= 5.2 V

V_BIAS= 3 V, V_IN= 6 V, V_OUT= 5.2 V

图6-115. Output Voltage Accuracy vs I_OUTfor V_IN= 6 V, V_BIAS= 图6-116. Output Voltage Accuracy vs I_OUTfor V_IN= 6 V, V_BIAS= 3

11 V, CP Enabled

V, CP Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_BIAS= 11 V, V_IN= 5.6 V, V_OUT= 5.2 V

V_BIAS= 3 V, V_IN= 5.6 V, V_OUT= 5.2 V

图6-117. Output Voltage Accuracy vs I_OUTfor V_IN= 5.6 V, V_BIAS= 图6-118. Output Voltage Accuracy vs I_OUTfor V_IN= 5.6 V, V_BIAS

=

11 V, CP Enabled

3 V, CP Enabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 3.7 V to 11 V, V_OUT= 0.5 V

图6-119. I_REFBIAS Rail Line Regulation

图6-120. V_OSBIAS Rail Line Regulation

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_BIAS= 3.7 V to 11 V, V_OUT= 0.5 V

V_IN= 0.7 V, V_OUT= 0.5 V

图6-121. V_OUTBIAS Rail Line Regulation

图6-122. V_OSLoad Regulation

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_IN= 1.1 V to 6 V, V_OUT= 0.5 V, I_OUT= 0 A

图6-123. I_REFIN Rail Line Regulation

图6-124. V_OSIN Rail Line Regulation

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_IN= 1.1 V to 6 V, V_OUT= 0.5 V, I_OUT= 0 A

V_BIAS= 0 V, V_OUT= 5.2 V, I_OUT= 0 A to 5 A

图6-125. V_OUTIN Rail Line Regulation

图6-126. V_OUTLoad Regulation

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-128. I_LIMITvs Temperature

V_BIAS= 8.4 V, V_IN= 5.6 V, V_OUT(nom)= 5.2 V

图6-127. I_LIMITvs V_OUT

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_OUT= 0.5 V

图6-129. UVLO_INThreshold vs Temperature With BIAS Rail

图6-130. UVLO_INThreshold vs Temperature Without BIAS Rail

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_OUT= 0.5 V

图6-131. UVLO_INHysteresis vs Temperature

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-132. UVLO_BIASThreshold vs Temperature for CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_OUT= 0.5 V

图6-134. UVLO_INHysteresis vs Temperature

图6-133. UVLO_BIASThreshold vs Temperature for CP Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-135. BIAS Pin Quiescent Current vs V_BIASfor

图6-136. BIAS Pin Quiescent Current vs V_BIASfor

V_OUT= 0.5 V, CP Enabled, I_OUT= 0 A

V_OUT= 0.5 V, CP Enabled, I_OUT= 5 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-137. BIAS Pin Quiescent Current vs V_INfor

图6-138. BIAS Pin Quiescent Current vs V_INfor

V_OUT= 5.2 V, V_BIAS= 11 V, CP Disabled

V_OUT= 5.2 V, V_BIAS= 8.4 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-139. Total BIAS Pin Quiescent Current vs V_INfor

图6-140. Total Quiescent Current vs V_INfor V_OUT= 5.2 V, V_BIAS=

V_OUT= 5.2 V, V_BIAS= 11 V, CP Disabled

8.4 V, CP Disabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-141. IN Pin Quiescent Current vs V_INfor V_OUT= 5.2 V, V_BIAS图6-142. IN Pin Quiescent Current vs V_INfor V_OUT= 5.2 V, V_BIAS

= 11 V, CP Disabled

= 8.4 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 6 V

图6-143. BIAS Pin Quiescent Current vs I_OUTfor

图6-144. Total Quiescent Current vs I_OUTfor V_OUT= 5.2 V, V_BIAS

V_OUT= 5.2 V, V_BIAS= 11 V, CP Disabled

= 11 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 6 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-145. IN Pin Quiescent Current vs I_OUTfor V_OUT= 5.2 V, V_BIAS

图6-146. BIAS Pin Current vs V_INfor V_OUT= 0.5 V,

= 11 V, CP Disabled

V_BIAS= 11 V, CP Disabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-147. Total Quiescent Current vs V_INfor V_OUT= 0.5 V, V_BIAS= 图6-148. IN Pin Quiescent Current vs V_INfor V_OUT= 0.5 V, V_BIAS

11 V, CP Disabled

= 11 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-149. BIAS Pin Quiescent Current vs V_INfor

图6-150. Total Pin Quiescent Current vs V_INfor

V_OUT= 0.5 V, V_BIAS= 3.7 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 6 V

图6-151. IN Pin Quiescent Current vs V_INfor V_OUT= 0.5 V, V_BIAS

图6-152. IN Pin Quiescent Current vs I_OUTfor V_OUT= 5.2 V, CP

= 3.7 V, CP Disabled

Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-153. BIAS Pin Quiescent Current vs V_INfor

图6-154. BIAS Pin Quiescent Current vs V_INfor

V_OUT= 0.5 V, No BIAS, CP Enabled, I_OUT= 0 A

V_OUT= 0.5 V, No BIAS, CP Enabled, I_OUT= 5 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 1.1 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-155. IN Pin Quiescent Current vs I_OUTfor V_OUT= 0.5 V, No

图6-156. BIAS Pin Quiescent Current vs V_INfor

BIAS, CP Enabled, I_OUT= 0 A

V_OUT= 0.5 V, V_BIAS= 3 V, CP Enabled, I_OUT= 0 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-157. Total Quiescent Current vs V_INfor V_OUT= 0.5 V, V_BIAS= 图6-158. IN Pin Quiescent Current vs V_INfor V_OUT= 0.5 V, V_BIAS

3 V, CP Enabled, I_OUT= 0 A = 3 V, CP Enabled, I_OUT= 0 A

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-159. BIAS Pin Quiescent Current vs V_INfor

图6-160. Total Quiescent Current vs V_INfor V_OUT= 0.5 V, V_BIAS=

V_OUT= 0.5 V, V_BIAS= 11 V, CP Enabled, I_OUT= 0 A

11 V, CP Enabled, I_OUT= 0 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-161. IN Pin Quiescent Current vs V_INfor V_OUT= 0.5 V, V_BIAS

图6-162. BIAS Pin Quiescent Current vs V_BIASfor

= 11 V, CP Enabled, I_OUT= 0 A

V_OUT= 0.5 V, V_IN= 0.7 V, CP Enabled, I_OUT= 0 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-163. Total Quiescent Current vs V_BIASfor V_OUT= 0.5 V, V_IN= 图6-164. IN Pin Quiescent Current vs V_BIASfor V_OUT= 0.5 V, V_IN

0.7 V, CP Enabled, I_OUT= 0 A

= 0.7 V, CP Enabled, I_OUT= 0 A

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-165. BIAS Pin Quiescent Current vs V_BIASfor

图6-166. Total Quiescent Current vs V_BIASfor V_OUT= 0.5 V, V_IN=

V_OUT= 0.5 V, V_IN= 0.7 V, CP Enabled, I_OUT= 5 A

0.7 V, CP Enabled, I_OUT= 5 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-167. IN Pin Quiescent Current vs V_BIASfor V_OUT= 0.5 V, V_IN

图6-168. BIAS Pin Quiescent Current vs V_BIASfor

= 0.7 V, CP Enabled, I_OUT= 5 A

V_OUT= 0.5 V, V_IN= 1.1 V, CP Enabled, I_OUT= 0 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-169. Total Quiescent Current vs V_BIASfor V_OUT= 0.5 V, V_IN

=

图6-170. IN Pin Quiescent Current vs Bias Voltage for

1.1 V, CP Enabled, I_OUT= 0 A

V_OUT= 0.5 V, V_IN= 1.1 V, CP Enabled, I_OUT= 0 A

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-171. BIAS Pin Quiescent Current vs I_OUTfor

图6-172. Total Quiescent Current vs I_OUTfor V_OUT= 0.5 V, V_IN=

V_OUT= 0.5 V, V_IN= 0.7 V, V_BIAS= 3.7 V, CP Enabled, I_OUT= 0 A

0.7 V, V_BIAS= 3.7 V, CP Enabled, I_OUT= 0 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-173. IN Pin Quiescent Current vs I_OUTfor V_OUT= 0.5 V, V_IN

=

图6-174. BIAS Pin Quiescent Current vs I_OUTfor

0.7 V, V_BIAS= 3.7 V, CP Enabled, I_OUT= 0 A

V_OUT= 0.5 V, V_IN= 0.7 V, V_BIAS= 11 V, CP Enabled, I_OUT= 0 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-175. Total Quiescent Current vs I_OUTfor V_OUT= 0.5 V, V_IN= 图6-176. IN Pin Quiescent Current vs I_OUTfor V_OUT= 0.5 V, V_IN

0.7 V, V_BIAS= 11 V, CP Enabled, I_OUT= 0 A 0.7 V, V_BIAS= 11 V, CP Enabled, I_OUT= 0 A

=

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-177. BIAS Pin Quiescent Current vs V_BIASfor

图6-178. Total Quiescent Current vs V_BIASfor V_OUT= 0.5 V, V_IN=

V_OUT= 0.5 V, V_IN= 0.7 V, CP Disabled, I_OUT= 0 A

0.7 V, CP Disabled, I_OUT= 0 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-179. IN Pin Quiescent Current vs V_BIASfor V_OUT= 0.5 V, V_IN

图6-180. BIAS Pin Quiescent Current vs V_BIASfor

= 0.7 V, CP Disabled, I_OUT= 0 A

V_OUT= 0.5 V, V_IN= 0.7 V, CP Disabled, I_OUT= 5 A

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-181. Total Quiescent Current vs V_BIASfor V_OUT= 0.5 V, V_IN= 图6-182. IN Pin Quiescent Current vs V_BIASfor V_OUT= 0.5 V, V_IN

0.7 V, CP Disabled, I_OUT= 5 A = 0.7 V, CP Disabled, I_OUT= 5 A

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-183. BIAS Pin Quiescent Current vs I_OUTfor

图6-184. Total Quiescent Current vs I_OUTfor V_OUT= 0.5 V, V_IN=

V_OUT= 0.5 V, V_IN= 0.7 V, V_BIAS= 3.7 V, CP Disabled

0.7 V, V_BIAS= 3.7 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-185. IN Pin Quiescent Current vs I_OUTfor V_OUT= 0.5 V, V_IN

=

图6-186. BIAS Pin Quiescent Current vs I_OUTfor

0.7 V, V_BIAS= 3.7 V, CP Disabled

V_OUT= 0.5 V, V_IN= 0.7 V, V_BIAS= 11 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-188. IN Pin Quiescent Current vs I_OUTfor V_OUT= 0.5 V, V_IN

=

图6-187. Total Quiescent Current vs I_OUTfor V_OUT= 0.5 V, V_IN

=

0.7 V, V_BIAS= 11 V, CP Disabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0.4 V,

V_EN= 0.4 V

图6-189. Shutdown Current vs V_INfor V_OUT= 0.5 V,

图6-190. BIAS Pin Shutdown Current vs V_INfor

V_BIAS= 0 V, CP Enabled

V_OUT= 0.5 V, V_BIAS= 11 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0.4 V,

V_EN= 0.4 V

图6-191. IN Pin Shutdown Current vs V_INfor V_OUT= 0.5 V, V_BIAS图6-192. Total Shutdown Current vs V_INfor V_OUT= 0.5 V, V_BIAS

= 11 V, CP Disabled 11 V, CP Disabled

=

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_EN= 0.4 V

图6-193. BIAS Pin Shutdown Current vs V_INfor

图6-194. IN Pin Shutdown Current vs V_INfor V_OUT= 0.5 V, V_BIAS

V_OUT= 0.5 V, V_BIAS= 3 V, CP Enabled

= 3 V, CP Enabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_EN= 0.4 V

图6-195. Total Shutdown Current vs V_INfor V_OUT= 0.5 V, V_BIAS

=

图6-196. BIAS Pin Shutdown Current vs V_BIASfor

3 V, CP Enabled

V_IN= 0.7 V, V_OUT= 0.5 V, CP Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_EN= 0.4 V

图6-197. IN Pin Shutdown Current vs V_BIASfor V_IN= 0.7 V, V_OUT图6-198. Total Shutdown Current vs V_BIASfor V_IN= 0.7 V, V_OUT

=

= 0.5 V, CP Enabled

0.5 V, CP Enabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

V_EN= 0.4 V

图6-199. BIAS Pin Shutdown Current vs V_BIASfor V_IN= 6 V,

图6-200. IN Pin Shutdown Current vs V_BIASfor V_IN= 6 V,

V_OUT(nom)= 0.5 V, CP Enabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 1.8 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_EN= 0.4 V

图6-201. Total Shutdown Current vs V_BIASfor V_IN= 6 V,

图6-202. BIAS Pin Shutdown Current vs V_BIASfor

V_OUT(nom)= 0.5 V, CP Enabled

V_IN= 0.7 V, V_OUT(nom)= 0.5 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_EN= 0.4 V

图6-203. IN Pin Shutdown Current vs V_BIASfor V_IN= 0.7 V,

图6-204. Total Shutdown Current vs V_BIASfor V_IN= 0.7 V,

V_OUT(nom)= 0.5 V, CP Disabled

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

V_EN= 0.4 V

图6-205. BIAS Pin Shutdown Current vs V_BIASfor V_IN= 6 V,

图6-206. IN Pin Shutdown Current vs V_BIASfor V_IN= 6 V,

V_OUT(nom)= 0.5 V, CP Disabled

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= 0 V,

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

V_EN= 0.4 V

图6-207. Total Shutdown Current vs V_BIASfor V_IN= 6 V,

图6-208. EN Threshold Voltage vs Temperature for

V_OUT(nom)= 0.5 V, CP Disabled

V_IN= 0.7 V and 1.1 V, V_OUT= 0.5 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-209. EN Threshold Voltage vs Temperature for

图6-210. EN Hysteresis vs Temperature for V_IN= 0.7 V and 1.1

V_IN= 6 V, V_OUT= 0.5 V

V, V_OUT= 0.5 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-211. EN Hysteresis vs Temperature for V_IN= 6 V,

图6-212. EN Pin Current vs Temperature

V_OUT= 0.5 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-213. CP_EN Threshold Voltage vs Temperature

图6-214. CP_EN Pin Current vs Temperature

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-215. CP_EN Hysteresis vs Temperature

图6-216. PG Threshold Voltage vs Temperature for

V_IN= 0.7 V and 1.1 V

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-217. PG Threshold Voltage vs Temperature for

图6-218. PG Hysteresis vs Temperature for V_IN= 0.7 V and 1.1 V

V_IN= 6 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF

图6-219. PG Hysteresis vs Temperature for V_IN= 6 V

图6-220. PG Leakage Current vs Temperature

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_BIAS= 0 V,

V_OUT= 0.5 V, V_{CP_EN}= 1.8 V

图6-221. PG Pin Low-Level Voltage vs PG Pin Current for V_IN

=

图6-222. PG Pin Low-Level Voltage vs PG Pin Current for V_IN=

1.1 V, No BIAS

6 V,

No BIAS

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6.6 Typical Characteristics (continued)

V_IN= V_OUT(NOM)+ 0.4 V, V_EN= 1.8 V, V_{CP_EN}= 1.8 V, C_IN= 10 µF, C_NR/SS= 4.7 μF, C_OUT= 22 μF, C_BIAS= 0 nF, SNS pin

shorted to OUT pin, and PG pin pulled up to V_INwith 100 kΩ(unless otherwise noted); typical values are at T_J= 25°C

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_OUT= 0.5 V

图6-223. PG Pin Low-Level Voltage vs PG Pin Current for V_IN

=

图6-224. PG Pin Low-Level Voltage vs PG Pin Current for V_IN=

0.7 V, V_BIAS= 3.7 V, V_{CP_EN}= 0 V

0.7 V, V_BIAS= 11 V, V_{CP_EN}= 0 V

C_NR/SS= C_IN= 4.7 μF, C_OUT= 22 μF, V_OUT= 0.5 V

图6-225. PG Pin Low-Level Voltage vs PG Pin Current for V_IN

=

图6-226. PG Pin Low-Level Voltage vs PG Pin Current for V_IN=

0.7 V, V_BIAS= 3 V, V_{CP_EN}= 1.8 V

0.7 V, V_BIAS= 11 V, V_{CP_EN}= 1.8 V

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7 Detailed Description

7.1 Overview

The TPS7A57 is a low-noise (2.45 μV_RMSover 10-Hz to 100-kHz bandwidth), ultra-high PSRR (> 36 dB to

1 MHz), high-accuracy (1%), ultra-low-dropout (LDO) linear voltage regulator with an input range of 0.7 V to 6.0

V and an output voltage range from 0.5 V to 5.2 V. This device uses innovative circuitry to achieve wide

bandwidth and high loop gain, resulting in ultra-high PSRR even with very low operational headroom [V_OpHr

=

(V_IN– V_OUT)]. At a high level, the device has two main primary features (the current reference and the unity-

gain LDO buffer) and a few secondary features (such as the adjustable soft-start inrush control, precision

enable, charge pump enable, and PG pin).

The current reference is controlled by the REF pin. This pin sets the output voltage with a single resistor.

The NR/SS pin sets the start-up time, and filters the noise generated by the reference and external set resistor.

The unity-gain LDO buffer controls the output voltage. The low noise does not increase with output voltage and

provides wideband PSRR. As such, the SNS pin is only used for remote sensing of the load.

The low-noise current reference, 50 μA typical, is used in conjunction with an external resistor (R_REF) to set the

output voltage. This process allows the output voltage range to be set from 0.5 V to 5.2 V. To achieve its low

noise and allow for a soft-start inrush, an external capacitor, C_NR/SS(typically 4.7 μF), is placed on the NR/SS

pin. When start-up is completed and the switch between REF and NR/SS is closed, the C_NR/SScapacitor is in

parallel with the R_REFresistor attenuating the band-gap noise. The R_REFresistor sets the output voltage. This

unity-gain LDO provides ultra-high PSRR over a wide frequency range without compromising load and line

transients.

The EN pin sets the precision enable feature; a resistor divider on this pin selects the optimal input voltage at

which the device starts. There are three independent undervoltage lockout (UVLO) voltages in this device: the

internal fixed UVLO thresholds for the IN and BIAS rails, and the externally adjustable UVLO threshold using the

EN pin.

The CP_EN pin enables or disables the internal charge pump. The TPS7A57 does not allow operation below

1.1 V without a BIAS rail. If the charge pump is disabled, a minimum operating headroom between OUT and

BIAS is required.

This regulator offers current limit, thermal protection, is fully specified from –40°C to +125°C, and is offered in a

16-pin WQFN, 3-mm × 3-mm thermally efficient package.

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7.2 Functional Block Diagram

Precision

CP_EN

V_NR/SS

Charge

Pump

SNS

+

œ

BIAS

Logic

UVLO_BIAS

UVLO_IN

Current

Limit

OUT

IN

Thermal

Shutdown

Band Gap

50µA

(1)

R_DIS

Logic

Fast soft-start

200µA

UVLO_IN/BIAS

REF

Current Limit

Thermal Shutdown

Logic

Output discharge

V_NR/SS

V_{CP_OU T}

NR/SS

(2)

Band Gap

R_{NR/SS_DIS}

PG

NR/SS discharge

Logic

90% . V_REF

+

V_{SN S}

œ

Precision

EN

GND

A. See the R_DIS(the output pin active discharge resistance) value in the Electrical Characteristics table.

B. See the R_{NR/SS_DIS}(the NR/SS pin active discharge resistance) value in the Electrical Characteristics table.

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7.3 Feature Description

7.3.1 Output Voltage Setting and Regulation

The simplified regulation circuit is shown in 图 7-1, in which the input signal (V_REF) is generated by the internal

current source (I_REF) and the external resistor (R_REF). The LDO output voltage is programmed by the V_REF

voltage because the error amplifier is always operating in unity-gain configuration. The V_REFreference voltage is

generated by an internal low-noise current source driving the R_REFresistor and is designed to have very low

bandwidth at the input to the error amplifier through the use of a low-pass filter (C_NR/SS|| R_REF).

The unity-gain configuration is achieved by connecting SNS to OUT. Minimize trace inductance on the output

and connect C_OUTas close to the output as possible.

V_IN

To Load

I_REF

I_SS

V_REF

V_SNS

V_NR/SS

C_NR/SS

R_REF

V_OUT= I_REF× R_REF

.

图7-1. Simplified Regulation Circuit

This unity-gain configuration, along with the highly accurate I_REFreference current, enables the device to

achieve excellent output voltage accuracy. The low dropout voltage (V_DO) enables reduced thermal dissipation

and achieves robust performance. This combination of features make this device an excellent voltage source for

powering sensitive analog low-voltage (≤5.5 V) devices.

7.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)

The device architecture features a highly accurate, high-precision, low-noise current reference followed by a

state-of-the-art, complementary metal oxide semiconductor (CMOS) error amplifier (6 nV/√Hz at 10-kHz noise

for V_OUT≥ 0.5 V). Unlike previous-generation LDOs, the unity-gain configuration of this device ensures low

noise over the entire output voltage range. Additional noise reduction and higher output current can be achieved

by placing multiple TPS7A57 LDOs in parallel, see the Paralleling for Higher Output Current and Lower Noise

section.

7.3.3 Programmable Soft-Start (NR/SS Pin)

The device features a programmable, monotonic, current-controlled, soft-start circuit that uses the C_NR/SS

capacitor to minimize inrush current into the output capacitor and load during start-up. This circuitry can also

reduce the start-up time for some applications that require the output voltage to reach at least 90% of its set

value for fast system start up. See the Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)

section for more details.

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7.3.4 Precision Enable and UVLO

Depending on the circuit implementation, up to three independent undervoltage lockout (UVLO) voltage circuits

can be active. An internally set UVLO on the input supply (IN pin) and the bias supply (BIAS pin) automatically

disables the LDO when the input voltage reaches the minimum threshold. A precision EN function (EN pin) can

also be used as a user-programmable UVLO.

1. The internal input supply voltage UVLO circuit prevents the regulator from turning on when the input voltage

is not high enough, see the Electrical Characteristics table for more details.

2. The internal bias supply voltage UVLO circuit prevents the regulator from turning on when the bias voltage is

not high enough, see the Electrical Characteristics table for more details.

3. The precision enable circuit allows a simple sequencing of multiple power supplies with a resistor divider

from another supply. This enable circuit can be used to set an external UVLO voltage at which the device is

enabled using a resistor divider on the EN pin; see the Precision Enable (External UVLO) section for more

details.

7.3.5 Charge Pump Enable and BIAS Rail

This device allows the internal charge pump to be disabled for systems that cannot tolerate any switching noise.

When V_INis less than 1.1 V, the BIAS rail is required because this rail sources the current needed by the internal

circuitry. The charge pump can be either enabled or disabled. Consider adequate operating headroom

requirements from OUT to BIAS if the charge pump is disabled. See the Undervoltage Lockout (UVLO)

Operation section for more details.

When V_INis greater than or equal to 1.1 V, the CP_EN pin connection determines how the internal circuitry is

powered. If CP_EN is connected to GND (CP disabled), the internal circuitry is powered from the BIAS rail; see

the Undervoltage Lockout (UVLO) Operation section for more details. If CP_EN is connected to the supply (CP

enabled), any current required to power the internal circuitry comes from the IN pin. As such, the BIAS pin can

be left open.

7.3.6 Power-Good Pin (PG Pin)

The PG pin is an output indicating if the LDO is ready to provide power. This pin is implemented using an open-

drain architecture. During the start-up phase, the PG voltage threshold is set by the REF voltage when the fast

soft-start is ongoing and is set by the NR/SS voltage when the fast soft-start is completed and the switch

between REF and NR/SS is closed.

As shown in the Functional Block Diagram, the PG pin is implemented by comparing the SNS pin voltage to an

internal reference voltage and, as such, is considered a voltage indicator reflecting the output voltage status.

For PG pin implementation, see the Power-Good Functionality section.

7.3.7 Active Discharge

To quickly discharge internal nodes, the device incorporates two internal pulldown metal-oxide semiconductor

field effect transistors (MOSFETs). The first pulldown MOSFET connects a resistor (R_DIS) from OUT to ground

when the device is disabled to actively discharge the output capacitor. The second pulldown MOSFET connects

a resistor from NR/SS (R_{NR/SS_DIS}) to ground when the device is disabled and discharges the NR/SS capacitor.

Both pulldown MOSFETs are activated by any of the following events:

• Driving the EN pin below the V_EN(LOW)threshold

• The IN pin voltage falling below the undervoltage lockout V_UVLO(IN)threshold

• The BIAS pin voltage falling below the undervoltage lockout V_UVLO(BIAS)threshold

备注

A brownout event on BIAS during a low-input, low-output (LILO) operation (< 1.1 V_IN) can result in

incomplete C_NR/SSdischarge. Consider the time constant on both the NR/SS and OUT pins for a

proper system shutdown procedure.

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7.3.8 Thermal Shutdown Protection (T_SD

)

A thermal shutdown protection circuit disables the LDO when the pass transistor junction temperature (T_J) rises

to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device resets (turns on) when the

temperature falls to T_SD(shutdown)(typical). The thermal time constant of the semiconductor die is fairly short, thus

the device may cycle off and on when thermal shutdown is reached until power dissipation is reduced. Power

dissipation during start up can be high from large V_IN– V_OUTvoltage drops across the device or from high

inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection

disables the device before start up completes. For reliable operation, limit the junction temperature to the

maximum listed in the Electrical Characteristics table. Operation above this maximum temperature causes the

device to exceed its operational specifications. Although the internal protection circuitry of the device is designed

to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking.

Continuously running the device into thermal shutdown or above the maximum recommended junction

temperature reduces long-term reliability.

7.4 Device Functional Modes

7.4.1 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

)

• The bias voltage is greater than the nominal output voltage plus the OUT-to-BIAS dropout voltage (V_OUT(nom)

+ V_DO(BIAS)) if the charge pump is disabled or if the input voltage is less than 1.1 V

• The output current is less than the current limit (I_OUT< I_LIM

)

• The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD(shutdown)

)

• The voltage on the EN pin has previously exceeded the V_IH(EN)threshold voltage and has not yet decreased

to less than the enable falling threshold

表7-1 summarizes all valid modes of operation and shows what rail is sourcing the internal biasing current.

表7-1. Valid Modes of Operation

RAIL SOURCING

BIASING CURRENT

V_INRANGE

V_OUTRANGE

V_BIASRANGE

CP MODE

On

3 V to 11 V

BIAS

< 1.1 V

≥0.5 V, ≤V_IN–V_DO

Max (V_OUT+ 2.1 V, 2.8 V)

to 11 V

Off

BIAS

Not present

3 V to 11 V

On

IN

≥0.5 V, ≤V_IN–V_DO≥

0.5 V, ≤V_IN–V_DO

BIAS

≥1.1 V, < 2 V

Max (V_OUT+ 2.1 V, 2.8 V)

to 11 V

Off

On

Off

BIAS

IN

Not required, does not

source current even if

present

≥2 V

≥0.5 V, ≤V_IN–V_DO

Max (V_OUT+ 2.1 V, 2.8 V)

to 11 V

BIAS

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7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. In dropout operation, the transient performance is significantly degraded because the

pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result

in large output voltage deviations.

备注

Unlike traditional n-type field effect transistor (NMOS) LDOs with two supply rails, BIAS and IN, the

TPS7A57 cannot enter an OUT-to-BIAS dropout mode. If the charge pump is disabled, a minimum

UVLO (BIAS) voltage above the REF voltage must be maintained. If the charge pump is enabled, and

if the IN voltage is less than 1.1 V, a voltage greater than or equal to the 3-V BIAS rail must be

present. If the charge pump is enabled and the IN voltage is greater than or equal to 1.1 V, a BIAS rail

is not required.

For additional information, see the Undervoltage Lockout (UVLO) Operation section.

7.4.3 Disabled

The output can be shutdown by forcing the voltage of the EN pin to less than the V_IH(EN)threshold (see the

Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown,

and both the NR/SS pin and OUT pin voltages are actively discharged to ground by internal discharge circuits to

ground when the IN pin voltage is higher than or equal to a diode-drop voltage.

7.4.4 Current-Limit Operation

If the output current is greater than or equal to the minimum current limit (I_LIM(Min)), then the device operates in

current-limit mode. Current limit is a foldback implementation. For additional information, see the Current Limit

and Foldback Behavior section.

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

Successfully implementing an LDO in an application depends on the application requirements. This section

discusses key device features and how to best implement them to achieve a reliable design.

8.1.1 Precision Enable (External UVLO)

The precision enable circuit (EN pin) turns the device on and off. This circuit can be used to set an external

undervoltage lockout (UVLO) voltage, as shown in 图 8-1, to turn on and off the device using a resistor divider

between IN (or BIAS when the charge pump is disabled), EN, and GND.

V_IN(or V_BIAS

C

)

IN (or BIAS)

R_(TOP)

GND

EN

TPS7A57

R_(BOTTOM)

GND

图8-1. Precision EN Used as an External UVLO

This external UVLO solution is used to prevent the device from turning on when the input supply voltage is not

high enough and can place the device in dropout operation. This solution also allows simple sequencing of

multiple power supplies with a resistor divider from another supply. Another benefit from using a resistor divider

to enable or disable the device is that the EN pin is never left floating because this pin does not have an internal

pulldown resistor. However, a zener diode may be needed between the EN pin and ground to comply with the

absolute maximum ratings on this pin.

Use 方程式1 and 方程式2 to determine the correct resistor values.

V_ON= V_OFF× [(V_IH(EN)+ V_HYS(EN)) / V_EN

]

(1)

(2)

R_(TOP)= R_(BOTTOM)× (V_OFF/ V_IH(EN)–1)

where:

• V_OFFis the input or bias voltage where the regulator turns off

• V_ONis the input or bias voltage where the regulator turns on

备注

For the EN pin input current, I_EN, effects are ignored.

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8.1.2 Undervoltage Lockout (UVLO) Operation

表8-1 lists the UVLO thresholds for different modes of operation.

表8-1. Relative Threshold for Different Modes of Operation

CHARGE PUMP ON

(With or Without a Bias Rail)

UVLO LOGIC: (a, c) || b

(Typ)

CHARGE PUMP OFF

(With Bias Rail)

(Typ)

UVLO THRESHOLD

NAME

a

b

c

0.67 V

1.07 V

2.8 V

0.67 V

N/A

V_UVLO(IN)rising

V_UVLO(BIAS)rising

Max (V_REF+ 2.1 V, 2.8 V)

8.1.2.1 IN Pin UVLO

The IN pin UVLO (UVLO(IN)) circuit makes sure that the device remains disabled before the input supply

reaches the minimum operational voltage range, and that the device shuts down when the input supply falls too

low.

The UVLO(IN) circuit has a minimum response time of several microseconds to fully assert. During this time, a

downward line transient below approximately 0.67 V causes the input supply UVLO(IN) to assert for a short time.

However, the UVLO(IN) circuit does not have enough stored energy to fully discharge the internal circuits inside

of the device and may result in incomplete discharge of OUT and NR/SS capacitors.

备注

The effect of the downward line transient can trigger the overshoot prevention circuit and can be easily

mitigated by using the solution proposed in the Precision Enable (External UVLO) section.

8.1.2.2 BIAS UVLO

The BIAS pin UVLO (UVLO(BIAS)) circuit makes sure that the device remains disabled before the input supply

reaches the minimum operational voltage range, and that the device shuts down when the input supply falls too

low.

The UVLO(BIAS) circuit has a minimum response time of several microseconds to fully assert. During this time,

a downward line transient below approximately 2.8 V (with the charge pump enabled) or V_REF+ 2.1 V (with the

charge pump disabled) causes the input supply UVLO(BIAS) to assert for a short time. However, the

UVLO(BIAS) circuit does not have enough stored energy to fully discharge the internal circuits inside of the

device and may result in incomplete discharge of the OUT and NR/SS capacitors.

备注

The effect of the downward line transient can trigger the overshoot prevention circuit and can be easily

mitigated by using the solution proposed in the Precision Enable (External UVLO) section.

8.1.2.3 Typical UVLO Operation

图 8-2 illustrates the UVLO (IN or BIAS) circuit response to various input voltage events. The diagram can be

separated into the following regions:

• Region A: The device does not turn on until the input reaches the UVLO rising threshold.

• Region B: Normal operation with a regulated output.

• Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold –UVLO hysteresis).

The output may fall out of regulation but the device is still enabled.

• Region D: Normal operation with a regulated output.

• Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising

threshold is reached by the input voltage and a normal start up then follows.

• Region F: Normal operation followed by the input falling to the UVLO falling threshold.

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• Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The

output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN

C

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

图8-2. Typical UVLO Operation

8.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction

When operating with IN between 1.07 V and 1.1 V with the internal charge pump on, a glitch can occur on the

output during the shutdown power-supply sequence if the BIAS rail falls prior to the IN rail.

When the BIAS rail falls below the V_{UVLO_BIAS}threshold, the output is disabled. When the IN rail is above the

minimum UVLO threshold to operate, the LDO restarts. 图8-3 shows this behavior.

To prevent this behavior, ensure the proper turn-off power-supply sequence is followed, or select an operating

mode (such as charge pump disabled).

V_BIAS

UVLO_BIAS

V_IN

V_OUT

UVLO_IN

Time

图8-3. UVLO_INand UVLO_BIASInteraction

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8.1.3 Dropout Voltage (V_DO

)

Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and

output voltage (V_DO= V_IN–V_OUT) that is required for regulation. When V_INdrops to or below the set V_DOfor the

given load current, the device functions as a resistive switch and does not regulate output voltage. When the

device is operating in dropout, the output voltage tracks the input voltage and the dropout voltage (V_DO) is

proportional to the output current because the device is operating as a resistive switch. Operating the device at

or near dropout significantly degrades the device transient performance and PSRR. Maintaining sufficient V_OpHr

significantly improves the device transient performance and PSRR.

备注

If the minimum BIAS rail is set 3.2 V above the REF pin voltage with the internal charge pump

disabled, the pass transistor cannot be in BIAS-to-OUT dropout, thus leaving only the IN-to-OUT

dropout conditions to be considered. For other operating conditions, see the Undervoltage Lockout

(UVLO) Operation section.

8.1.4 Input and Output Capacitor Requirements (C_INand C_OUT

)

The TPS7A57 is designed and characterized for operation with ceramic capacitors of 22 µF or greater (15 µF or

greater of capacitance) at the output and 10 µF or greater (5 µF or greater of capacitance) at the input. Use at

least a 10-µF capacitor at the input to minimize input impedance. Place the input and output capacitors as near

as practical to the respective input and output pins in order to minimize trace parasitics. If the trace inductance

from the input supply to the TPS7A57 is high, a fast current transient can cause V_INto ring above the absolute

maximum voltage rating and damage the device. This situation can be mitigated by adding additional input

capacitors to dampen the ringing, thereby keeping any voltage spike below the device absolute maximum

ratings.

备注

Because of its wide bandwidth, the LDO error amplifier may react faster than the output capacitor. In

such a case, the load behavior appears directly on the LDO supply, potentially dragging the supply

down. To avoid such behaviors, minimize both ESR and ESL present on the output; see the

Recommended Operating Conditions table.

8.1.5 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) and low equivalent series

inductance (ESL) ceramic capacitors at the input, output, and noise-reduction pin. Multilayer ceramic capacitors

have become the industry standard for these types of applications and are recommended, but must be used with

good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide

relatively good capacitive stability across temperature. The use of Y5V-rated capacitors is discouraged because

of large variations in capacitance.

Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and

temperature. Make sure to derate ceramic capacitors by at least 50%. The input and output capacitors

recommended herein account for a capacitance derating of approximately 50%, but at high V_INand V_OUT

conditions (V_IN= 5.5 V to V_OUT= 5.0 V) and temperature extremes, the derating can be greater than 50%, and

must be taken into consideration.

The device requires input, output, and noise-reduction capacitors for proper operation of the LDO. Use the

nominal or larger than nominal input and output capacitors as specified in the Recommended Operating

Conditions table. Place input and output capacitors as close as possible to the corresponding pin and make the

capacitor GND connections are as close as possible to the device GND pin to shorten transient currents on the

return path. Using a larger input capacitor or a bank of capacitors with various values is always good design

practice to counteract input trace inductance, improve transient response, and reduce input ripple and noise.

Similarly, multiple capacitors on the output reduce charge pump ripple and optimize PSRR; see the Optimizing

Noise and PSRR section.

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Use the nominal noise-reduction C_NR/SScapacitor because using a larger C_NRSScapacitor can lengthen the

start-up time as mentioned previously.

8.1.6 Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)

The NR/SS pin has the dual function of controlling the soft-start time and reducing the noise generated by the

internal band-gap reference and the external resistor R_REF. The NR/SS capacitor (C_NR/SS) reduces the output

noise to very low levels and sets the output ramp rate to limit inrush current.

The device features a programmable, monotonic, voltage-controlled, soft-start circuit that is set to work with an

external capacitor (C_NR/SS). In addition to the soft-start feature, the C_NR/SScapacitor also lowers the output

voltage noise of the LDO. The soft-start feature can be used to eliminate power-up initialization problems. The

controlled output voltage ramp also reduces peak inrush current during start up, minimizing start-up transients to

the input power bus.

To achieve a monotonic start up, the device output voltage tracks the V_NR/SSreference voltage until this

reference reaches its set value (the set output voltage). The V_NR/SSreference voltage is set by the R_REFresistor

and, during start up, the device uses a fast charging current (I_{FAST_SS}), as shown in 图 8-4, to charge the C_NR/SS

capacitor.

备注

Any leakage on the NR/SS and REF pins directly impacts the accuracy of the reference voltage.

To PG

+

SS_Ctrl

I_SS

50µA

REF

NR/SS

C_NR/SS

R_REF

SS_Ctrl

图8-4. Simplified Soft-Start Circuit

The 200-μA (typical) I_NR/SScurrent quickly charges C_NR/SSuntil its voltage reaches approximately 97% of the

set output voltage, then the I_SScurrent turns off, the switch between REF and NR/SS closes, and only the I_REF

current continues to charge C_NR/SSto its set output voltage level.

备注

The discharge pulldown resistor on NR/SS (see the Functional Block Diagram) is engaged when any

of the GND referenced UVLOs have been tripped, or when any faults occur (overtemp, PORs, IREF

bad, or OTP error) and the NRSS pin is above 50 mV.

The soft-start ramp time depends on the fast start-up (I_NR/SS) charging current, the reference current (I_REF),

C_NR/SScapacitor value, and the targeted output voltage (V_OUT(target)). 方程式 3 calculates the soft-start ramp

time.

Soft-start time (t_SS) = (V_OUT(target)× C_NR/SS) / ( I_SS

)

(3)

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The I_SScurrent is provided in the Typical Characteristics section and has a value of 200 μA (typical). The I_REF

current has a value of 50 μA (typical). The remaining 3% of the start-up time is determined by the R_REF

_NR/SStime constant. 图8-5 shows the PG threshold at start up.

×

C

97%

NR/SS Threshold

92%

Spec Table PG Threshold

Switch closes

Time

图8-5. PG Threshold During Start-Up

The output voltage noise can be lowered significantly by increasing the C_NR/SScapacitor. The C_NR/SScapacitor

and R_REFresistor form a low-pass filter (LPF) that filters out noise from the V_REFvoltage reference, thereby

reducing the device noise floor. The LPF is a single-pole filter and 方程式 4 calculates the LPF cutoff frequency.

Increasing the C_NR/SScapacitor can significantly lower output voltage noise, however, doing so lengthens start-

up time. For low-noise applications, use a 4.7-μF C_NR/SSfor optimal noise and start-up time trade off.

Cutoff Frequency (f_cutoff) = 1 / (2 × π× R_REF× C_NR/SS

)

(4)

备注

Current limit can be entered during start up with a small C_NR/SSand large C_OUTbecause V_OUTno

longer tracks the soft-start ramp.

图8-6 and 图8-7 show the impact of the C_NR/SScapacitor on the LDO output voltage noise.

C_IN= 4.7 μF, C_OUT= 22 μF, V_{CP_EN}= V_IN, V_IN= 5.3 V,

C_IN= 4.7 μF, C_OUT= 22 μF, V_IN= 5.3 V, V_OUT= 5 V,

V_OUT= 5 V, I_OUT= 5 A

V_BIAS= 11 V

图8-6. Output Voltage Noise Density vs C_NR/SS

图8-7. Output Voltage Noise Density vs C_NR/SS

With Charge Pump Enabled

With Charge Pump Disabled

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8.1.7 Optimizing Noise and PSRR

Noise can be generally defined as any unwanted signal combining with the desired signal (such as the regulated

LDO output) that results in degraded power-supply source quality. Noise can be easily noticed in audio as a

hissing or popping sound. Extrinsic and intrinsic are the two basic groups that noise can be categorized into.

Noise produced from an external circuit or natural phenomena such as 50 to 60 hertz power-line noise (spikes),

along with its harmonics, is an excellent representative of extrinsic noise. Intrinsic noise is produced by

components within the device circuitry such as resistors and transistors. For this device, the two dominating

sources of intrinsic noise are the error amplifier and the internal reference voltage (V_REF). Another term that

sometimes combines with extrinsic noise is PSRR, which refers to the ability of the circuit or device to reject or

filter out input supply noise and is expressed as a ratio of output voltage noise ripple to input voltage noise

ripple.

Optimize the device intrinsic noise and PSRR by carefully selecting:

• C_NR/SSfor the low-frequency range up to the device bandwidth

• C_OUTfor the high-frequency range close to and higher than the device bandwidth

• Operating headroom, V_IN–V_OUT(V_OpHr), mainly for the low-frequency range up to the device bandwidth, but

also for higher frequencies to a less effect

The device noise performance can be significantly improved by using a larger C_NR/SScapacitor to filter out noise

coupling from the input into the device V_REFreference. This coupling is especially apparent from low frequencies

up to the device bandwidth. The low-pass filter formed by C_NR/SSand R_REFcan be designed to target low-

frequency noise originating in the input supply. One downside of a larger C_NR/SScapacitor is a longer start-up

time. The device unity-gain configuration eliminates the noise performance degradation that other LDOs suffer

from because of their feedback network. Furthermore, increasing the device load current has little to no effect on

the device noise performance.

Further improvement to the device noise at a higher frequency range than the device bandwidth can be

achieved by using a larger C_OUTcapacitor. However, a larger C_OUTincreases inrush current and slows down the

device transient response.

These behaviors are described in the Typical Characteristics section. 图 6-17 and 图 6-19 list the measured 10-

Hz to 100-kHz RMS noise for a 5-V device and a 0.5-V output voltage with a 300-mV headroom for different

C_NR/SSand C_OUTconditions with a 5-A load current. 表 8-2 and 表 8-3 list the typical output noise for these

capacitors.

Increasing the operational headroom between V_INand V_OUThas little to no effect on improving noise

performance. However, this increase does improve PSRR significantly for frequency ranges up to the device

bandwidth. Higher headroom can also improve transient performance of the device as well. Although C_OUThas

little to no affect on improving PSRR at low frequency, C_OUTcan improve PSRR for higher frequencies beyond

the device bandwidth. A larger C_OUTcan also lengthen start-up time and increase start-up inrush current. A

combination of capacitors, such as 470 μF || 22 μF is more effective because a combination provides lower

ESR and ESL. This behavior is illustrated in 图6-12.

表8-2. Output Noise for 0.5-V_OUTvs C_OUT, and Typical Start-Up Time

C_NR/SS(µF)

C_OUT(µF)

START-UP TIME (ms)

V_n(μV_RMS), 10-Hz to 100-kHz BW

2.4

4.7

22

11.75

2.48

470

表8-3. Output Noise for 5-V_OUTvs C_NR/SS, C_OUT, and Typical Start-Up Time for V_{CP_EN}= 5.3 V

C_NR/SS(µF)

C_OUT(µF)

START-UP TIME (ms)

V_n(μV_RMS), 10-Hz to 100-kHz BW

16.68

3.38

2.51

0.1

1

22

2.5

25

4.7

117.5

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8.1.8 Adjustable Operation

As shown in 图8-8, the output voltage of the device can be set using a single external resistor (R_REF).

TPS7A57

0.9 V

IN

OUT

SNS

0.65 V

C_OUT

C_IN

V_OUT

EN

5 V

BIAS

REF

R_PG

C_BIAS

PG

R_REF

5 V

CP_EN

NR/SS

GND

C_NR/SS

图8-8. Typical Circuit

Use 方程式5 to calculate the R_REFvalue needed for the desirable output voltage.

V_OUT= I_REF(NOM)× R_REF

(5)

表 8-4 shows the recommended R_REFresistor values to achieve several common rails using a standard 1%-

tolerance resistor.

表8-4. Recommended R_REFValues

R_REF(kΩ)⁽¹⁾

TARGETED OUTPUT VOLTAGE (V)

CALCULATED OUTPUT VOLTAGE (V)

0.5

0.6

0.7

0.8

0.9

1.0

1.2

1.5

2.5

3.0

3.3

3.6

4.7

5.0

10.0

0.500

0.605

0.700

0.810

0.910

1.000

1.215

1.505

2.495

3.020

3.325

3.575

4.765

5.000

12.1

14.0

16.2

18.2

20.0

24.3

30.1

49.9

60.4

66.5

71.5

95.3

100.0

(1) 1% resistors.

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8.1.9 Load Transient Response

The load-step transient response is the LDO output voltage response to load current, whereby output voltage

regulation is maintained. There are two key transitions during a load transient response: the transition from a

light to a heavy load, and the transition from a heavy to a light load. The regions shown in 图 8-9 are broken

down in this section. Regions A, E, and H are where the output voltage is in steady-state regulation.

A

C

D

E

G

H

V_OUT

B

F

Time (µs)

Current slew rate (rise = fall)

Max output current

Minimum output current

I_OUT

Time (µs)

图8-9. Load Transient Waveform

During transitions from a light load to a heavy load:

• The initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to

the output capacitor (region B)

• Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage

regulation (region C)

During transitions from a heavy load to a light load:

• The initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge

to increase (region F)

• Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load

discharging the output capacitor (region G)

Transitions between current levels changes the internal power dissipation because the device is a high-current

device (region D). The change in power dissipation changes the die temperature during these transitions, and

leads to a slightly different voltage level. This temperature-dependent output voltage level shows up in the

various load transient responses.

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor.

备注

The TPS7A57, with its high bandwidth, may react faster than the output capacitors. Make sure that

there is sufficient capacitance at the input of the LDO.

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8.1.10 Current Limit and Foldback Behavior

图8-10 shows the foldback current limit behavior for output voltages ranging from 0.5 V to 5 V.

图8-10. Current Limit Foldback Behavior

8.1.11 Charge Pump Operation

As discussed in the Charge Pump Enable and BIAS Rail section, the internal charge pump can be enabled or

disabled using the CP_EN pin, allowing operation as low as 1.1 V without a BIAS rail.

The CP_EN pin voltage threshold and hysteresis are defined in the Electrical Characteristics table.

Depending on the circuit implementation, the internal charge pump is powered from either the IN or the BIAS

rails. This pin is not designed to be digitally controlled with a digital I/O pin, but is instead intended to be tied on

the printed circuit board (PCB) to an analog rail.

Although not intended to be controlled dynamically, the CP_EN pin can be controlled by using a low impedance

source and ensuring adequate sequencing between EN and CP_EN because the CP_EN pin is latched when

the EN pin is turned on and only an EN reset or a power cycle clears and resets the CP_EN latch.

图8-11 shows the switching frequency of the charge pump at no-load and full load.

图8-11. Charge Pump Noise

8.1.12 Sequencing

There is no sequencing requirement between IN, BIAS, and EN. CP_EN is an analog signal and must be

connected to either IN, BIAS, or GND.

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As with devices having an internal MUX and charge pump, a false PG can be triggered during shutdown if the

BIAS rail is faster than the IN rail to discharge.

As shown in 图 8-12, when the bias rail decreases below V_UVLO(BIAS), the internal MUX between IN and BIAS

switches over and the LDO is fully powered from the IN rail.

When the BIAS rail goes below UVLO(BIAS) with the IN rail greater than 1.1 V with the charge pump enabled,

the LDO may restart because IN is still a valid condition for operations.

图8-12. Total Quiescent Current vs BIAS

8.1.13 Power-Good Functionality

As described in the Functional Block Diagram, the PG pin is a open-drain MOSFET driven by a Schmitt trigger.

The Schmitt trigger compares the SNS pin voltage to a preselected voltage equal to 90% that of the reference

voltage.

As mentioned in the Recommended Operating Conditions table, the pullup resistance must be between 10 kΩ

and 100 kΩ for optimal performance. If the PG functionality is not desired, the PG pin can either be left floating

or connected to GND.

There are two UVLO circuits present on the BIAS rail, one referenced to GND (V_UVLO(BIAS)) and one referenced

to V_REF(V_UVLO(BIAS)– V_REF). A false PG event can occur as a result of logic priorities when the charge pump is

disabled.

To eliminate any false PG events, consider setting V_BIAS3.2 V above V_OUT

.

表8-5 describes the various UVLO behaviors.

表8-5. UVLO Triggered PG Events

V_IN

V_UVLO(BIAS)RISING

V_UVLO(BIAS)FALLING

V

_UVLO(BIAS)–V_REFRISING

V

_UVLO(BIAS)–V_REFFALLING

1.86 + 0.5 = 2.36 V

1.86 + 0.7 = 2.56 V

1.86 + 1.4 = 3.26 V

1.86 + 5.2 = 7.06 V

0.5 V

0.7 V

1.4 V

5.2 V

2.8 V

2.685 V

2.1 + 0.5 = 2.6 V

2.685 V

2.1 + 0.7 = 2.8 V

2.685 V

2.1 + 1.4 = 3.5 V

2.685 V

2.1 + 5.2 = 7.3 V

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8.1.14 Output Impedance

Output impedance can be modeled, as shown in 图 8-13, as an ideal voltage source followed by a series R

(R_OUT) and series L (L_OUT) output.

V_OUT

Ideal

Voltage

Source

R_OUT

L_OUT

+

œ

图8-13. Output Impedance Model

Output impedance curves were measured using the EVM and are provided for the following conditions:

1. 图8-14, 图8-15, and 图8-16 are provided for the 5.5-V_IN, 5-V_OUT, and I_OUT= 200-mA, 500-mA, and 5-A

conditions

2. 图8-17 is provided for the 0.9-V_IN, 0.5-V_OUT, and I_OUT= 4.6-A conditions

3. 图8-18 to 图8-21 are provided for the 0.75 -V_IN, 0.5-V_OUT, 3-V_BIAS, and I_OUT= 20-mA, 200-mA, 500-mA,

and 1-A conditions.

图8-14. V_IN= 5.5 V, V_OUT= 5 V, V_BIAS= 8 V, CP_EN 图8-15. V_IN= 5.5 V, V_OUT= 5 V, V_BIAS= 8 V, CP_EN

= 0, I_OUT= 200 mA

= 0, I_OUT= 500 mA

图8-16. V_IN= 5.5 V, V_OUT= 5 V, V_BIAS= 8 V, CP_EN

图8-17. V_IN= 0.9 V, V_BIAS= 3 V, V_OUT= 0.5 V ,

= 0, I_OUT= 5 A

CP_EN = 0, I_OUT= 4.6 A

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图8-18. V_IN= 0.75 V, V_BIAS= 3 V, V_OUT= 0.5 V ,

图8-19. V_IN= 0.75 V, V_BIAS= 3 V, V_OUT= 0.5 V,

CP_EN = 0, I_OUT= 20 mA

CP_EN = 0, I_OUT= 100 mA

图8-20. V_IN= 0.75 V, V_BIAS= 3 V, V_OUT= 0.5 V,

图8-21. V_IN= 0.75 V, V_BIAS= 3 V, V_OUT= 0.5 V,

CP_EN = 0, I_OUT= 500 mA

CP_EN = 0, I_OUT= 1 A

表8-6 provides a summary of the tested conditions described in this section.

表8-6. Model for Tested Conditions Summary

V_IN

V_OUT

0.5 V

5 V

V_BIAS

3 V

8 V

I_OUT

20 mA

200 mA

500 mA

1 A

CP_EN

R_OUT

L_OUT

0.75 V

0.9 V

5.5 V

Off

0.5 nH

200 μΩ

400 μΩ

300 μΩ

200 μΩ

Off

4.6 A

Off

200 mA

500 mA

5 A

Off

5 V

Off

5 V

Off

8.1.15 Paralleling for Higher Output Current and Lower Noise

Achieving higher output current and lower noise is achievable by paralleling two or more LDOs. Implementation

must be carefully planned out to optimize performance and minimize output current imbalance.

Because the TPS7A57 output voltage is set by a resistor driven by a current source, the REF resistor and

capacitor must be adjusted as per the following:

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R_REF= V_{OUT_TARGET}/ (n × I_REF

)

(6)

(7)

C_{NR/SS_parallel}= n × C_{NR/SS_single}

where:

• n is the number of LDOs in parallel

• I_REFis the REF current as provided in the Electrical Characteristics table

• C_NR/SS_single is the NR/SS capacitor for a single LDO. Note that each LDO must have its own C_NR/SS

capacitor.

When connecting the IN pins together, and with the LDO being a buffer, the current imbalance is only affected by

the error offset voltage of the error amplifier. As such, the current imbalance can be expressed as:

2

ε_I= V_OS× 2 × R_BALLAST/ (R_BALLAST²–ΔR_BALLAST

)

(8)

where:

• ε_Iis the current imbalance

• V_OSis the LDO error offset voltage

• R_BALLASTis the ballast resistor

• ΔR_BALLASTis the deviation of the ballast resistor value from the nominal value

With the typical offset voltage of 200 μV, the ballast resistor must be 2 mΩ or greater (as shown in 图 8-22),

considering no error from the design of the PCB ballast resistor (ΔR_BALLAST= 0 Ω) and a 100-mA maximum

current imbalance.

V_IN

PG

FB_PG

IN

R_{BALLAST = 2 mꢀ}

OUT

SNS

TPS7A57

V_{EN_UV}

EN

REF NR/SS GND

V_{OUT = 1 V}

REF

EN

NR/SS

GND

R_{BALLAST = 2 mꢀ}

TPS7A57

OUT

SNS

IN

C_{OUT = 22 µF}

C_{IN = 10 µF}

FB_PG

PG

图8-22. Paralleling Multiple TPS7A57 Devices

Using the configuration described, the LDO output noise is reduced by:

e_{O_parallel}= (1 / √n) × e_{O_single}

(9)

where:

• n is the numbers of LDOs in parallel

• e_{O_single}is the output noise density from a single LDO

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• e_{O_parallel}is the output noise density for the resulting parallel LDO

In 图8-22, the noise is reduced by 1/√2.

8.1.16 Current Mode Margining

Output voltage margining is a technique that allows a circuit to be evaluated for how well changes are tolerated

in the power supply. This test is typically performed by adjusting the supply voltage to a fixed percentage above

and below its nominal output voltage.

This section discusses the implementation of a voltage margining application using the TPS7A57. A margining

target of ±2.5% is used to demonstrate the chosen implementation.

图8-23 shows a simplified visualization of the TPS7A57 REF pin with a current DAC.

TPS7A57

50 µA

DAC63204

Range: ±25 µA

R_REF

LSB: 196 nA

图8-23. Simplified Margining Schematic

表8-7 summarizes the design requirements.

表8-7. Design Requirement

PARAMETER

Design Values

V_IN

2.5 V

V_OUT

1.8 V nominal with ±2.5% margining

C_NR/SS

4.7 μF

36 kΩ

R_REF

DAC I_OUTrange

±25 μA

In this example, the output voltage is set to a nominal 1.8 V using 36 kΩ at the REF pin to GND. 方程式 10

calculates the R_REFresistor value.

R_REF= V_OUT/ I_REF

(10)

The DAC63204, a 4-channel, 12-bit voltage and current output DAC with I²C, was selected and programmed

into the current-output mode with an output range set to ±25 μA. In conjunction with the 8-bit current DAC

resolution, this output range allows a minimum step size (or LSB) of approximately 196 nA. Into the 36-kΩ

resistor, the LSB translates into a 7-mV voltage resolution or 0.38% of the nominal 1.8-V targeted voltage. To

achieve the full ±2.5% swing around the nominal voltage, the DAC63204 must source or sink ±1.25 μA.

The current flowing through R_REFchanges to 51.25 μA and 48.75 μA and adjusts the output voltage to 1.845 V

and 1.75 V, respectively.

图8-24 and 图8-25 show the current margining results.

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图8-24. Margining Up

图8-25. Margining Down

When implementing voltage margining with this LDO, a time constant is associated with its response. This RC

time constant is a result of the parallel combination of R_REFand C_NR/SS, see 图 8-23. This RC effect is illustrated

in 图8-24 and 图8-25.

方程式11 calculates the time constant for this implementation:

τ= R_REF× C_NR/SS

(11)

where:

• R_REFis 36 kΩ

• C_NR/SSis 4.7 μF

• τ= 169 ms

8.1.17 Voltage Mode Margining

Output voltage margining is a technique that allows a circuit to be evaluated for how well changes are tolerated

in the power supply. This test is typically performed by adjusting the supply voltage to a fixed percentage above

and below its nominal output voltage.

This section discusses the implementation of a voltage mode margining application using the TPS7A57. A

margining target of ±5% is used to demonstrate the chosen implementation.

图8-26 shows a simplified visualization of the TPS7A57 REF pin with a voltage DAC.

TPS7A57

50 µA

R_V2I= 100 kΩ

DAC63204

Range: [0 t 5 V]

R_REF

LSB: 1.22 mV

图8-26. Simplified Voltage Mode Margining Schematic

表8-7 summarizes the design requirements.

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表8-8. Design Requirement

PARAMETER

V_IN

DESIGN VALUES

2.5 V

1.8 V nominal with ±5% margining

4.7 μF

V_OUT

C_NR/SS

R_REF

36 kΩ

DAC V_OUTrange

1.432 V to 2.108 V

In this example, the output voltage is set to a nominal 1.8-V using a 36-kΩ resistor at the REF pin to GND. 方程

式12 calculates the value for the R_REFresistor.

R_REF= V_OUT/ I_REF

(12)

The DAC63204, a 4-channel, 12-bit voltage and current output DAC with I²C, was selected and programmed

into the voltage-output mode with an output range set between 1.432 V and 2.108 V. In conjunction with the 12-

bit voltage DAC resolution, this output range allows a minimum step size (or LSB) of approximately 1.22 mV or

122 μA when the voltage-to-input (V2I) conversion or R_V2I(100 kΩ) is taken into consideration. Into the 36-kΩ

resistor, this LSB translates into a 0.44-mV voltage resolution or approximately 0.025% of the nominal 1.8-V

targeted voltage. To achieve the full ±5% swing around the nominal voltage, the DAC63204 must source 3.1 μA

or sink 3.7 μA.

The current flowing through R_REFchanges to 53.1 μA and 46.3 μA, thus adjusting the output voltage to 1.88 V

and 1.7 V respectively.

节8.1.17 and 图8-28 show the voltage margining results.

图8-27. Margining From –5% to +5%

图8-28. Margining from +5% to –5%

When implementing voltage margining with this LDO, there is a time constant associated with its response. This

RC time constant originates from the parallel combination of R_REFand C_NR/SS. 节 8.1.17 and 图 8-28 show this

RC effect.

方程式13 calculates the time constant for this implementation:

τ= R_REF× C_NR/SS

(13)

where:

• R_REFis 36 kΩ

• C_NR/SSis 4.7 μF

• τ= 169 ms

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8.1.18 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. 方程式14 calculates P_D:

P_D= (V_OUT- V_IN) ´ I_OUT

(14)

备注

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the

system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be

obtained. The low dropout of the device allows for maximum efficiency across a wide range of output

voltages.

The primary heat conduction path for the package is through the thermal pad to the PCB. Solder the thermal pad

to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any

inner plane areas or to a bottom-side copper plane.

The power dissipation through the device determines the junction temperature (T_J) for the device. Power

dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (R_θJA

)

of the combined PCB and device package and the temperature of the ambient air (T_A), according to 方程式 15.

The equation is rearranged for output current in 方程式16.

T_J= T_A= (R_θJA× P_D)

(15)

(16)

I_OUT= (T_J–T_A) / [R_θJA× (V_IN–V_OUT)]

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The R_θJArecorded in the Thermal Information table is determined by the JEDEC standard, PCB, and

copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-

designed thermal layout, R_θJAis actually the sum of the RTE package junction-to-case (bottom) thermal

resistance (R_θJCbot) plus the thermal resistance contribution by the PCB copper.

8.1.19 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with 方程式17 and are given in the Electrical Characteristics table.

Y_JT: T_J= T_T+ Y_JT´ P_D

Y_JB: T_J= T_B+ Y_JB´ P_D

(17)

where:

• P_Dis the power dissipated as explained in 方程式14

• T_Tis the temperature at the center-top of the device package

• T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

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8.1.20 TPS7A57EVM-081 Thermal Analysis

The TPS7A57EVM-081 was used to develop the TPS7A5701RTE thermal model. The RTE package is a 3-mm

× 3-mm, 16-pin WQFN with 25-µm plating on each via. The EVM is a 3.5-inch × 3.5-inch (89 mm × 89 mm) PCB

comprised of six layers. 表 8-9 lists the layer stackup for the EVM. 图 8-29 to 图 8-36 illustrate the various layer

details for the EVM.

表8-9. TPS7A57EVM-081 PCB Stackup

LAYER

NAME

Top overlay

Top solder

Top layer

MATERIAL

THICKNESS (mil)

1

2

—

0.4

Solder resist

Copper

3

2.756

9

4

Dielectric 1

Mid layer 1

Dielectric 2

Mid layer 2

Dielectric 3

Mid layer 3

Dielectric 4

Mid Layer 4

Dielectric 5

Bottom layer

Bottom solder

FR-4 high Tg

Copper

5

2.756

9

6

FR-4 high Tg

Copper

7

2.756

9

8

FR-4 high Tg

Copper

9

2.756

9

10

11

12

13

14

FR-4 high Tg

Copper

2.756

9

FR-4 high Tg

Copper

2.756

0.4

Solder resist

图8-29. Top Assembly Layer and Silkscreen

图8-30. Top Layer Routing

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图8-31. Layer 2 Routing

图8-32. Layer 3 Routing

图8-33. Layer 4 Routing

图8-34. Layer 5 Routing

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图8-35. Bottom Layer Routing

图8-36. Bottom Assembly Layer and Silkscreen

表 8-10 shows thermal simulation data for the TPS7A57EVM-056. 图 8-37 and 图 8-38 show the thermal

gradient on the PCB and device that results when a 1-W power dissipation is used through the pass transistor

with a 25°C ambient temperature.

表8-10. TPS7A57EVM-081 Thermal Simulation Data

DUT

R

_θJA(ͦ C/W)

⍦_JB(ͦ C/W)

⍦_JT(°C/W)

TPS7A57EVM-056

21.9

11.9

0.4

Precision

CP_EN

V_NR/SS

Charge

Pump

SNS

+

œ

BIAS

Logic

UVLO_BIAS

UVLO_IN

Current

Limit

OUT

IN

Thermal

Shutdown

Band Gap

50µA

(1)

R_DIS

Logic

Fast soft-start

200µA

UVLO_IN/BIAS

Current Limit

REF

Thermal Shutdown

Logic

Output discharge

V_NR/SS

V_{CP_OU}

T

NR/SS

(2)

Band Gap

R_{NR/SS_DIS}

NR/SS discharge

PG

PCB

Logic

90% . V_REF

+

temperature

test point

V_SN

S

œ

Precision

EN

GND

图8-37. TPS7A57EVM-081 3D View

图8-38. TPS7A57EVM-081 PCB Thermal Gradient

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8.2 Typical Application

TPS7A57

0.8 V

IN

OUT

SNS

0.5 V

22 µF

EN

V_EN

11 V

BIAS

REF

1 µF

PG

10 kΩ

CP_EN

NR/SS

GND

4.7 µF

图8-39. Typical Application Schematic

8.2.1 Design Requirements

表8-11 lists the required application parameters for this design example.

表8-11. Design Parameters

PARAMETER

Input voltage

DESIGN REQUIREMENT

0.8 V, ±3%, provided by the dc/dc converter switching at 1 MHz

Bias voltage

11 V

0.5 V, 1%

Output voltage

Charge pump

Disabled

Output current

Noise

4.2 A (maximum), 3.5 A (minimum)

Less than 5 μV_RMS

80 dB at max load current

> 35 dB at max load current

±5 mV, 100 mA to 3.5 A

Start-up time < 15 ms

PSRR at 10 kHz

PSRR at 1 MHz

Maximum load transient

Start-up environment

8.2.2 Detailed Design Procedure

In this design example, the device is powered by a dc/dc convertor switching at 1 MHz. The load requires a 0.5-

V clean rail with less than 5 μV_RMS. The typical 22-μF input and output capacitors and 4.7-μF NR/SS

capacitors are used to achieve a good balance between fast start-up time and excellent noise, and PSRR

performance and load transient.

The output voltage is set using a 10-kΩ, thin-film resistor value calculated as described in the Output Voltage

Setting and Regulation section. The PG pin is not used and is thus connected to ground to help with thermals.

The enable voltage is provided by a external I/O. 图 8-41 illustrates that the device meets all design noise

requirements. 图8-40 depicts adequate PSRR performance.

As illustrated in 图8-42, the load transient is adequate to the power-supply requirement.

图8-39 depicts the implementation of these components.

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8.2.3 Application Curves

图8-41. Noise vs Frequency

图8-40. PSRR vs Frequency

图8-43. Start-Up Rail Sequence

图8-42. Load Transient

8.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply ranging from 0.7 V to 6.0 V and a BIAS rail up to

11 V. Ensure that the input voltage range provides adequate operational headroom for the device to have a

regulated output. This input supply must be well regulated and low impedance. If the input supply is noisy, use

additional input capacitors with low ESR and increase the operating headroom to achieve the desired output

noise, PSRR, and load transient performance.

There is no sequencing requirement between IN, BIAS, and EN. CP_EN is an analog signal and must be

connected to either IN, BIAS, or GND.

8.4 Layout

8.4.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near as

practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,

copper surface. To avoid negative system performance, do not use vias and long traces to the input and output

capacitors. The grounding and layout scheme illustrated in 图 8-44 minimizes inductive parasitics, and thereby

reduces load-current transients, minimizes noise, and increases circuit stability.

Because of its wide bandwidth and high output current capability, inductance present on the output negatively

impacts load transient response. For best performance, minimize trace inductance between the output and load.

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A low ESL capacitor combined with low trace inductance limits the total inductance present on the output and

optimizes the high-frequency PSRR.

To improve performance, use a ground reference plane, either embedded in the PCB itself or placed on the

bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output

voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when

connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal

requirements.

8.4.2 Layout Example

R_PG

BIAS

16

15

14

13

1

2

3

4

IN

12

11

10

9

OUT

V_IN

V_OUT

OUT

IN

OUT

5

6

7

8

C_BIAS

Circles denote PCB via connections.

Power Ground

图8-44. Recommended Layout

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, TPS7A57EVM-056 Evaluation Module user guide

• Texas Instruments, High-Current, Low-Noise Parallel LDO Reference Design design guide

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 商标

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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10.1 Mechanical Data

PACKAGE OUTLINE

RTE0016C

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

6

0

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

B

A

PIN 1 INDEX AREA

3.1

2.9

C

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

1.68 0.07

(0.1) TYP

5

8

EXPOSED

THERMAL PAD

12X 0.5

4

9

4X

SYMM

17

1.5

1

12

0.30

16X

0.18

PIN 1 ID

(OPTIONAL)

16

13

0.1

C A B

SYMM

0.05

0.5

0.3

16X

4219117/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RTE0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.68)

SYMM

16

13

16X (0.6)

1

12

16X (0.24)

SYMM

(2.8)

17

(0.58)

TYP

12X (0.5)

9

4

(

0.2) TYP

VIA

5

8

(R0.05)

ALL PAD CORNERS

(0.58) TYP

(2.8)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219117/A 09/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RTE0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.55)

16

13

16X (0.6)

1

12

16X (0.24)

17

SYMM

(2.8)

12X (0.5)

9

4

METAL

ALL AROUND

5

8

SYMM

(2.8)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4219117/A 09/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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GENERIC PACKAGE VIEW

RTE 16

3 x 3, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225944/A

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PACKAGE OUTLINE

RTE0016C

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

6

0

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

B

A

PIN 1 INDEX AREA

3.1

2.9

SIDE WALL

METAL THICKNESS

DIM A

OPTION 1

0.1

OPTION 2

0.2

C

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

1.68 0.07

(DIM A) TYP

5

8

EXPOSED

THERMAL PAD

12X 0.5

4

9

4X

SYMM

17

1.5

1

12

0.30

16X

0.18

PIN 1 ID

(OPTIONAL)

13

16

0.1

C A B

SYMM

0.05

0.5

0.3

16X

4219117/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTE0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.68)

SYMM

13

16

16X (0.6)

1

12

16X (0.24)

SYMM

(2.8)

17

(0.58)

TYP

12X (0.5)

9

4

(

0.2) TYP

VIA

5

8

(R0.05)

ALL PAD CORNERS

(0.58) TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219117/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTE0016C

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.55)

16

13

16X (0.6)

1

12

16X (0.24)

17

SYMM

(2.8)

12X (0.5)

9

4

METAL

ALL AROUND

5

8

SYMM

(2.8)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4219117/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS7A57
厂家：	TEXAS INSTRUMENTS
描述：	5A、低输入电压、低噪声、高精度、低压降 (LDO) 稳压器稳压器
文件：	总93页 (文件大小：8394K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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