TPS7A20_V05 [TI]

TPS7A20 300-mA, Ultra-Low-Noise, Low-IQ, High PSRR LDO;


型号：	TPS7A20_V05
厂家：	TEXAS INSTRUMENTS
描述：	TPS7A20 300-mA, Ultra-Low-Noise, Low-IQ, High PSRR LDO
文件：	总31页 (文件大小：910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS7A20

SBVS338A –MARCH 2020–REVISED MARCH 2020

TPS7A20 300-mA, Ultra-Low-Noise, Low-I_Q, High PSRR LDO

1 Features

3 Description

The TPS7A20 is an ultra-small, low-dropout (LDO)

•

Low output voltage noise: 6 µV_RMS

No noise-bypass capacitor required

linear regulator that can source 300 mA of output

current. The TPS7A20 is designed to provide low

noise, high PSRR, and excellent load line transient

performance that can meet the requirements of RF

and other sensitive analog circuits. Using innovative

design techniques, the TPS7A20 offers an ultra-low

noise performance without the addition of a noise

bypass capacitor. The TPS7A20 also provides the

advantage of low quiescent current, which can be

ideal for any battery-powered applications. The

–

•

High PSRR: 85 dB at 1 kHz

Very low I_Q: 6.5 µA

Input voltage range: 1.6 V to 6.0 V

Output voltage range: 0.8 V to 5.5 V

Output voltage tolerance: ±1.5% (max)

Very low dropout:

–

140 mV (max) at 300 mA (V_OUT= 3.3 V)

TPS7A20 can be used for

a wide variety of

•

Low inrush current

applications by supporting an input voltage range

from 1.6 V to 6.0 V and a wide output range of 0.8 V

to 5.5 V. The device uses a precision reference circuit

to provide a maximum accuracy of 1.5% over load,

line, and temperature variations

Smart enable pulldown

Stable with 1-µF minimum ceramic output

capacitors

•

Packages:

The TPS7A20 features an internal soft-start to lower

the inrush current, thus minimizing the input voltage

drop during start up. The device is stable with small

ceramic capacitors, allowing for a small overall

solution size.

–

1-mm × 1-mm X2SON

0.603-mm × 0.603-mm DSBGA (preview)

2.90-mm × 1.60-mm SOT23-5 (preview)

2 Applications

The TPS7A20 has a smart enable input circuit with

an internally controlled pulldown resistor that keeps

the LDO disabled even when the EN pin is left

floating and helps eliminate the external components

used to pulldown the EN pin.

•

Smartphones and tablets

IP network cameras

Portable medical equipment

Smart meters and field transmitters

Motor drives

Device Information⁽¹⁾

PART

NUMBER

PACKAGE

BODY SIZE (NOM)

Wearables

X2SON (4)

1.00 mm × 1.00 mm

0.603 mm × 0.603 mm

2.90 mm × 1.60 mm

Simplified Schematic

TPS7A20

DSBGA (4)⁽²⁾

SOT-23 (5)⁽²⁾

V_OUT

V_IN

OUTPUT

INPUT

1 µF

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

1 µF

(2) Preview package.

TPS7A20

V_EN

ENABLE

GND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to

change without notice.

TPS7A20

SBVS338A –MARCH 2020–REVISED MARCH 2020

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Table of Contents

7.4 Device Functional Modes........................................ 12

Application and Implementation ........................ 13

8.1 Application Information............................................ 13

8.2 Typical Application .................................................. 17

Power Supply Recommendations...................... 17

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics.......................................... 7

6.7 Typical Characteristics.............................................. 8

Detailed Description .............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................. 10

10 Layout................................................................... 18

10.1 Layout Guidelines ................................................. 18

10.2 Layout Examples................................................... 18

11 Device and Documentation Support ................. 20

11.1 Device Support...................................................... 20

11.2 Receiving Notification of Documentation Updates 20

11.3 Community Resources.......................................... 20

11.4 Trademarks........................................................... 20

11.5 Electrostatic Discharge Caution............................ 20

11.6 Glossary................................................................ 20

12 Mechanical, Packaging, and Orderable

Information ........................................................... 20

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2020) to Revision A

Page

•

Changed low output voltage noise from 7 µV_RMSto 6 µV_RMSin Features section ................................................................. 1

Changed YEN package designator to YWD throughout document ...................................................................................... 3

Changed DQN pin out drawing from Bottom View to Top View ............................................................................................ 4

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SBVS338A –MARCH 2020–REVISED MARCH 2020

5 Pin Configuration and Functions

YWD Package (Preview)

4-Pin DSBGA

YWD Package (Preview)

4-Pin DSBGA

Top View

Bottom View

OUT

GND

OUT

Not to scale

Pin Functions: DSBGA

I/O

DESCRIPTION

NO.

NAME

Input voltage supply. For best transient response and to minimize input impedance, use the

recommended value or larger capacitor from IN to ground as listed in the Recommended

Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the

device as possible.

Regulated output voltage. A minimum 1-µF low equivalent series resistance (ESR) capacitor

is required from OUT to ground for stability. For best transient response, use the nominal

recommended value or larger capacitor from OUT to ground. Follow the recommended

capacitor value as listed in the Recommended Operating Conditions table. Place the output

capacitor as close to the OUT and GND pins of the device as possible. An internal 150-Ω

(typical) pulldown resistor prevents a charge from remaining on V_OUTwhen the regulator is

in shutdown mode (V_EN< V_IL).

OUT

Enable input. A low voltage (< V_IL) on this pin turns the regulator off and discharges the

output pin to GND. A high voltage (> V_IH) on this pin enables the regulator output. This pin

has an internal 500-kΩ pulldown resistor to hold the regulator off by default.

GND

—

Common ground.

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DQN Package

4-Pin X2SON

Top View

DBV Package (Preview)

5-Pin SOT-23

Top View

OUT

GND

OUT

Thermal Pad

N/C

GND

Not to scale

Pin Functions: X2SON, SOT-23

I/O

DESCRIPTION

NAME

X2SON

SOT-23

Input voltage supply. For best transient response and to minimize input

impedance, use the recommended value or larger capacitor from IN to ground as

listed in the Recommended Operating Conditions table. Place the input capacitor

as close to the IN and GND pins of the device as possible.

Regulated output voltage. A minimum 1-µF low ESR capacitor is required from

OUT to ground for stability. For best transient response, use the nominal

recommended value or larger capacitor from OUT to ground. Follow the

recommended capacitor value as listed in the Recommended Operating

Conditions table. Place the output capacitor as close to the OUT and GND pins of

the device as possible. An internal 150-Ω (typical) pulldown resistor prevents a

OUT

charge from remaining on V_OUTwhen the regulator is in shutdown mode (V_EN

V_IL).

Enable input. A low voltage (< V_IL) on this pin turns the regulator off and

discharges the output pin to GND. A high voltage (> V_IH) on this pin enables the

regulator output. This pin has an internal 500-kΩ pulldown resistor to hold the

regulator off by default.

GND

N/C

—

Common ground.

—

No internal electrical connection.

Thermal pad for the X2SON package. Connect this pad to GND or leave floating.

Do not connect to any potential other than GND. Connect the thermal pad to a

large-area ground plane for best thermal performance.

Thermal Pad

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_IN

–0.3

6.5

V_IN+ 0.3 or

6.0V⁽²⁾

Voltage

Current

V_OUT

–0.3

V_EN

–0.3

Internally limited

-40

6.5

Maximum output current

Operating junction temperature, T_J

Storage temperature, T_stg

125

150

°C

Temperatu

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings

only, and functional operation of the device at these or any other conditionsbeyond those indicated underRecommended Operating

Conditionsis not implied. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability.

(2) Maximum is V_IN+ 0.3 V, or 6.0 V, whichever is smaller

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.6

NOM

MAX

6.0

UNIT

V_IN

Input supply voltage

Enable input voltage

Output voltage

V_EN

V_OUT

I_OUT

C_IN

6.0

0.8

5.5

Output current

300

µF

mΩ

°C

Input capacitor

(2)

C_OUT

ESR

T_J

Output capacitor⁽¹⁾

200

Output Capacitor

Operating junction temperature

–40

125

(1) Effective output capacitance of 0.5 µF minimum is required for stability

(2) 200 µF is the maximum derated capacitance that can be used for stability

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6.4 Thermal Information

TPS7A20

(2)

YWD⁽²⁾

(DSBGA)

DBV

DQN

(X2SON)

THERMAL METRIC⁽¹⁾

UNIT

(SOT-23)

5 PINS

TBD

4 PINS

179.1

137.6

116.3

6.1

4 PINS

TBD

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

TBD

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

TBD

ψ_JB

TBD

116.3

112.3

R_θJC(bot)

TBD

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Preview Package

6.5 Electrical Characteristics

at operating temperature range (T_J= –40℃ to +125℃), V_IN= V_OUT(NOM)+ 0.3 V or 1.6V, whichever is greater, V_EN= 1.0 V,

I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted); all typical values are at T_J= 25℃

PARAMETER

TEST CONDITIONS

V_IN= (V_OUT(NOM)+ 0.3 V) to 6.0 V,

I_OUT= 1 mA to 300 mA,

_OUT≥ 1.5 V

MIN

TYP

MAX

UNIT

–1.5

1.5

ΔV_OUT

Output voltage tolerance

V_IN= (V_OUT(NOM)+ 0.5 V) to 6.0 V,

I_OUT= 1 mA to 300 mA

V_OUT< 1.5 V

–30

V_IN= (V_OUT(NOM)+ 0.3 V) to 6.0 V,

I_OUT= 1 mA

ΔV_OUT

(ΔV_IN

Line regulation

Load regulation

0.03

%/V

)

ΔV_OUT(ΔI_O

I_OUT= 1 mA to 300 mA

0.003

6.5

%/mA

)

T_J= 25°C

V_EN= V_IN, V_IN= 6.0

V, I_OUT= 0 mA

T_J= –40°C to 85°C

T_J= –40°C to 125°C

I_GND

Ground current

µA

V_EN= V_IN, V_IN= 6.0 V, I_OUT= 300 mA

2000

0.15

6.5

I_SHTDWN

I_GND(DO)

Shutdown current

V_EN= 0 V (disabled), V_IN= 6.0 V, T_J= 25°C

0.5

µA

Ground current in dropout

V_IN≤ V_OUT(NOM), I_OUT= 0 mA

0.8 V ≤ VOUT < 1.0 V

690

490

355

240

140

730

1.0 V ≤ VOUT < 1.2 V

1.2 V ≤ VOUT < 1.5 V

1.5 V ≤ VOUT < 2.5 V

2.5 V ≤ VOUT < 3.3 V

3.3 V ≤ VOUT ≤ 5.5 V

I_OUT= 300 mA,

V_OUT= 95% x

V_OUT(NOM)

V_DO

Dropout voltage

I_CL

I_SC

Output current limit

V_OUT= 0.9 x V_OUT(NOM), V_IN= V_OUT(NOM)+ V_DO

360

520

160

Short-circuit current limit

V_OUT= 0 V

f = 1 kHz

f = 10 kHz

f = 100 kHz

f = 1 MHz

I_OUT= 20 mA,

V_IN= V_OUT+ 1.0 V

PSRR

Power-supply rejection ratio

f = 1 kHz

f = 10 kHz

f = 100 kHz

f = 1 MHz

I_OUT= 300 mA,

V_IN= V_OUT+ 1.0 V

Power-supply rejection ratio

Output noise voltage

BW = 10 Hz to 100

kHz

V_OUT= 2.8V

I_OUT= 300 mA

V_N

µV_RMS

I_OUT= 1 mA

Output automatic discharge

pulldown resistance

R_PULLDOWN

V_EN< V_EN(LOW)(output disabled)

150

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Electrical Characteristics (continued)

at operating temperature range (T_J= –40℃ to +125℃), V_IN= V_OUT(NOM)+ 0.3 V or 1.6V, whichever is greater, V_EN= 1.0 V,

I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted); all typical values are at T_J= 25℃

PARAMETER

TEST CONDITIONS

MIN

TYP

165

140

MAX

UNIT

Thermal shutdown rising

Thermal shutdown falling

T_Jrising

T_SD

°C

T_Jfalling

V_IN= 1.6 V to 6.0 V,

V_ENfalling until the output is disabled

V_EN(LOW)

V_EN(HI)

EN pin logic low threshold

EN pin logic high threshold

0.25

V_IN= 1.6 V to 6.0 V

V_ENrising until the output is enabled

0.92

V_INrising

V_INfalling

1.21

1.17

1.35

1.3

1.55

1.5

V_UVLO

UVLO threshold

V_UVLO(HYST

UVLO hysteresis

120

500

)

I_EN

EN Pin leakage current

Smart enable pulldown resistor

V_EN= 6.0 V and V_IN= 6.0 V

V_EN= 0.25 V

250

R_EN(PULL-

KΩ

DOWN)

6.6 Switching Characteristics

at operating temperature range (T_J= –40℃ to +125℃), V_IN= V_OUT(NOM)+ 0.3 V or 1.6V, whichever is greater, V_EN= 1.0 V,

I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF (unless otherwise noted); all typical values are at T_J= 25℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

From V_EN> V_IHto V_OUT= 95% of V_OUT(NOM)

t_ON

Turnon time

750

1500

µs

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6.7 Typical Characteristics

V_IN= V_OUT(NOM)+ 0.3 V or 1.6 V (whichever is greater), V_OUT= 2.8 V, I_OUT= 1 mA, C_IN= 1 µF, C_OUT= 1 µF, and T_A= 25°C

(unless otherwise noted)

100

120

110

100

V_IN

3.3 V

V_IN

3.3 V

3.1 V

3.8 V

3.1 V

3.8 V

10k

100k

Frequency (Hz)

10M

10k

100k

Frequency (Hz)

10M

D001

V_OUT= 2.8 V, I_OUT= 20 mA, C_OUT= 1 µF

V_OUT= 2.8 V, I_OUT= 300 mA, C_OUT= 1 µF

Figure 1. PSRR at 20-mA Loads

Figure 2. PSRR at 300-mA Loads

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7 Detailed Description

7.1 Overview

Designed to meet the needs of sensitive RF and analog circuits, the TPS7A20 provides low noise, high PSRR,

low quiescent current, as well as low line and load transient response figures. Using innovative design

techniques, the TPS7A20 offers class-leading noise performance without the need for a separate noise filter

capacitor.

The TPS7A20 is designed to perform with a single 1-µF input capacitor and a single 1-µF ceramic output

capacitor.

7.2 Functional Block Diagram

Current

Limit

OUT

Bandgap

Active Discharge

P-Version Only

Error

Amp

UVLO

Internal

Controller

Thermal

Shutdown

GND

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7.3 Feature Description

7.3.1 Low Output Noise

Any internal noise at the TPS7A20 reference voltage is reduced by a first-order, low-pass RC filter before being

passed to the output buffer stage. The low-pass RC filter has a –3-dB cut-off frequency of approximately 0.1 Hz.

7.3.2 Smart Enable

The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable

pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than

the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the

enable pin to the input of the device.

This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven

above V_EN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable internal

pulldown resistor (R_EN(PULLDOWN)) is disconnected. When the enable pin is floating, the R_EN(PULLDOWN)is

connected and pulls the enable pin low to disable the device. The R_EN(PULLDOWN)value is listed in the Electrical

Characteristics table.

This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the

output voltage.

7.3.3 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.

The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output

voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the

nominal output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. Use Equation 1 to calculate the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(1)

7.3.4 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a

brickwall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK). In a high-load current fault with the

output voltage above V_FOLDBACK, the brickwall scheme limits the output current to the current limit (I_CL). When the

voltage drops below V_FOLDBACK, a foldback current limit activates that scales back the current as the output

voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-

circuit current limit (I_SC). I_CLand I_SCare listed in the Electrical Characteristics table.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. When the device output is shorted and the output

is below V_FOLDBACK, the pass transistor dissipates power [(V_IN– V_OUT) × I_SC]. If thermal shutdown is triggered, the

device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If

the output current fault condition continues, the device cycles between current limit and thermal shutdown. For

more information on current limits, see the Know Your Limits application report.

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Feature Description (continued)

Figure 3 shows a diagram of the foldback current limit.

V_OUT

Brickwall

V_OUT(NOM)

V_FOLDBACK

Foldback

0 V

I_OUT

I_RATED

0 mA

I_SC

I_CL

Figure 3. Foldback Current Limit

7.3.5 Undervoltage Lockout (UVLO)

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a

controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input

drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.6 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(T_J) of the pass transistor rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when

thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high

from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before startup

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

7.3.7 Active Discharge

The device has an internal pulldown MOSFET that connects an R_PULLDOWNresistor to ground when the device is

disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin or by

the undervoltage lockout (UVLO).

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Feature Description (continued)

Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input

supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current

flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a

short period of time.

7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

The Device Functional Mode Comparison table shows the conditions that lead to the different modes of

operation. See the Electrical Characteristics table for parameter values.

Table 1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

The output current is less than the current limit (I_OUT< I_CL

The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to

less than the enable falling threshold

)

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN

pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned

off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal

discharge circuit from the output to ground.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input

and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and

are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and

C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of

Y5V-rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and

temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input

and output capacitors recommended in the Recommended Operating Conditions table account for an effective

capacitance of approximately 50% of the nominal value.

8.1.2 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor

from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,

and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value

capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located

several inches from the input power source.

Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor

within the range specified in the Recommended Operating Conditions table for stability.

8.1.3 Load Transient Response

The load-step transient response is the output voltage response by the LDO to a step in load current, whereby

output voltage regulation is maintained. There are two key transitions during a load transient response: the

transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in

Figure 4 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.

tAt

tCt

tDt

tEt

tGt

tHt

Figure 4. Load Transient Waveform

During transitions from a light load to a heavy load, the:

•

Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the

output capacitor (region B)

•

Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage

regulation (region C)

During transitions from a heavy load to a light load, the:

•

Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to

increase (region F)

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Application Information (continued)

•

Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load

discharging the output capacitor (region G)

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor.

8.1.4 Undervoltage Lockout (UVLO) Operation

The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational

voltage range, and ensures that the device shuts down when the input supply collapses. Figure 5 shows the

UVLO circuit response to various input voltage events. The diagram can be separated into the following parts:

•

Region A: The device does not start until the input reaches the UVLO rising threshold.

Region B: Normal operation, regulating device.

Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The

output may fall out of regulation but the device remains enabled.

•

Region D: Normal operation, regulating device.

Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising

threshold is reached by the input voltage and a normal start-up follows.

•

Region F: Normal operation followed by the input falling to the UVLO falling threshold.

Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The

output falls because of the load and active discharge circuit.

UVLO Rising Threshold

UVLO Hysteresis

V_IN

V_OUT

tAt

tBt

tDt

tEt

tFt

tGt

Figure 5. Typical UVLO Operation

8.1.5 Power Dissipation (P_D)

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

difference and load conditions. Use Equation 2 to approximate P_D:

P_D= (V_IN– V_OUT) × I_OUT

(2)

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system

voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low

dropout of the TPS7A20 allows for maximum efficiency across a wide range of output voltages.

The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal

pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that

conduct heat to any inner plane areas or to a bottom-side copper plane.

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Application Information (continued)

The maximum power dissipation determines the maximum allowable junction temperature (T_J) for the device.

According to Equation 3, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the ambient

air (T_A). Equation 4 rearranges Equation 3 for output current.

T_J= T_A+ (R_θJA× P_D)

(3)

(4)

I_OUT= (T_J– T_A) / [R_θJA× (V_IN– V_OUT)]

Unfortunately, this thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the

particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the

planes. The R_θJArecorded in the Thermal Information table is determined by the JEDEC standard, PCB, and

copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-

designed thermal layout, R_θJAis actually the sum of the X2SON package junction-to-case (bottom) thermal

resistance (R_θJC(bot)) plus the thermal resistance contribution by the PCB copper.

8.1.5.1 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal

resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics

are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JTand

Ψ_JB) are used in accordance with Equation 5 and are given in the Thermal Information table.

Ψ_JT: T_J= T_T+ Ψ_JT× P_Dand Ψ_JB: T_J= T_B+ Ψ_JB× P_D

where:

•

P_Dis the power dissipated as explained in Equation 2

T_Tis the temperature at the center-top of the device package

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(5)

8.1.5.2 Recommended Area for Continuous Operation

The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input

voltage. The recommended area for continuous operation for a linear regulator is given in Figure 6 and can be

separated into the following parts:

•

Dropout voltage limits the minimum differential voltage between the input and the output (V_IN– V_OUT) at a

given output current level. See the Dropout Operation section for more details.

The rated output currents limits the maximum recommended output current level. Exceeding this rating

causes the device to fall out of specification.

The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating

causes the device to fall out of specification and reduces long-term reliability.

–

The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum-rated

junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when V_IN

V_OUTincreases the output current must decrease.

–

•

The rated input voltage range governs both the minimum and maximum of V_IN– V_OUT

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Application Information (continued)

Figure 6 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a

_θJAas given in the Thermal Information table.

Output current limited by

dropout

Rated output

current

Output current limited by thermals

Limited by

minimum V_IN

Limited by

maximum V_IN

V_INœ V_OUT(V)

Figure 6. Region Description of Continuous Operation Regime

The TPS7A20 is designed to meet the requirements of RF and analog circuits, by providing low noise, high

PSRR, low quiescent current, and low line or load transient response figures. The device offers excellent noise

performance without the need for a noise bypass capacitor and is stable with input and output capacitors with a

value of 1 µF. The TPS7A20 delivers this performance in industry-standard packages such as DSBGA, X2SON,

and SOT-23 which, for this device, are specified with an operating junction temperature (T_J) of –40°C to +125°C.

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8.2 Typical Application

Figure 7 shows the typical application circuit for the TPS7A20. Input and output capacitances may need to be

increased above the 1 µF minimum for some applications.

V_OUT

V_IN

OUTPUT

1.0 µF

INPUT

1.0 µF

TPS7A20

V_EN

ENABLE

GND

SVA-30180501

Figure 7. TPS7A20 Typical Application

8.2.1 Design Requirements

Table 2 summaries the design requirements for Figure 7.

Table 2. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

3.1 V to 6.0 V

2.8 V

Output current

200 mA

Output capacitor range

Output capacitor ESR range

0.7 µF to 10 µF

5 mΩ to 80 mΩ

8.2.2 Detailed Design Procedure

The TPS7A20 is designed to meet the requirements of RF and analog circuits, by providing low noise, high

PSRR, low quiescent current, and low line or load transient response figures. The device offers excellent noise

performance without the need for a noise bypass capacitor and is stable with input and output capacitors with a

value of 1 µF. The TPS7A20 delivers this performance in industry standard packages such as DSBGA, X2SON,

and SOT-23 which, for this device, are specified with an operating junction temperature (T_J) of –40°C to 125°C.

9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 1.6 V to 6.0 V. The input supply must

be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic

performance is optimum, the input supply must be at least V_OUT(nom)+ 0.3 V or 1.6 V, whichever is greater. TI

highly recommends using a 1-µF or greater input capacitor to reduce the impedance of the input supply,

especially during transients.

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10 Layout

10.1 Layout Guidelines

•

Place input and output capacitors as close to the device as possible.

Use copper planes for device connections to optimize thermal performance.

Place thermal vias around the device to distribute the heat.

Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or

solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder

joint on the thermal pad.

10.2 Layout Examples

OUT

GND

Enable

N/C

Figure 8. DBV Package (SOT-23) Typical Layout

TPS7A20

V_OUT

V_IN

C_OUT

C_IN

Power Ground

V_EN

Figure 9. DQN Package (X2SON) Typical Layout

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Layout Examples (continued)

V_IN

V_OUT

TPS7A20

C_OUT

C_IN

Power Ground

V_EN

Figure 10. YWD Package (DSBGA) Typical Layout

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 3. Device Nomenclature⁽¹⁾⁽²⁾

PRODUCT

V_OUT

XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used

in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).

P indicates an active output discharge feature. All members of the TPS7A20 family actively discharge

the output when the device is disabled.

TPS7A20xx(x)Pyyyz

YYY is the package designator.

Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder on www.ti.com.

(2) Output voltages from 0.8 V to 5.5 V in 25-mV increments are available. Contact the factory for details and availability.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

4-Sep-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTPS7A2012PDBVR

PTPS7A2012PDQNR

PTPS7A2015PDQNR

PTPS7A201825PDQNR

PTPS7A20185PDQNR

PTPS7A2018PDBVR

PTPS7A2018PDQNR

PTPS7A2025PDBVR

PTPS7A2025PDQNR

PTPS7A2028PDBVR

PTPS7A2028PDQNR

PTPS7A2029PDQNR

PTPS7A2030PDBVR

PTPS7A2030PDQNR

PTPS7A2033PDBVR

PTPS7A2033PDQNR

PTPS7A2045PDQNR

PTPS7A2050PDBVR

ACTIVE

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

SOT-23

X2SON

SOT-23

DBV

DQN

DBV

DQN

DBV

DQN

DBV

DQN

DBV

DQN

DBV

DQN

DBV

3000

TBD

Call TI

-40 to 125

Call TI

TPS7A2012PDQNR

TPS7A2015PDBVR

PREVIEW

X2SON

SOT-23

DQN

DBV

3000

TBD

Call TI

-40 to 125

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

4-Sep-2020

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A2015PDQNR

PREVIEW

X2SON

DQN

3000

Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

-40 to 125

TPS7A20185PDBVR

TPS7A20185PDQNR

PREVIEW

SOT-23

X2SON

DBV

DQN

3000

TBD

Call TI

-40 to 125

Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

TPS7A2018PDBVR

TPS7A2024PDBVR

TPS7A2025PDBVR

TPS7A2025PDQNR

TPS7A2028PDBVR

TPS7A2028PDQNR

PREVIEW

SOT-23

X2SON

SOT-23

X2SON

DBV

DQN

DBV

DQN

3000

TBD

Call TI

-40 to 125

Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

TPS7A2029PDQNR

TPS7A2030PDBVR

TPS7A2030PDQNR

TPS7A2033PDBVR

TPS7A2033PDQNR

PREVIEW

X2SON

SOT-23

X2SON

SOT-23

X2SON

DQN

DBV

DQN

DBV

DQN

3000

TBD

Call TI

-40 to 125

Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM

& no Sb/Br)

TPS7A2045PDQNR

TPS7A2050PDBVR

PREVIEW

X2SON

SOT-23

DQN

DBV

3000

TBD

Call TI

-40 to 125

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

4-Sep-2020

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE OUTLINE

X2SON - 0.4 mm max height

DQN0004A

PLASTIC SMALL OUTLINE - NO LEAD

1.05

0.95

1.05

0.95

PIN 1

INDEX AREA

0.4 MAX

SEATING PLANE

0.08

NOTE 6

+0.12

-0.1

0.05

0.00

0.48

(0.05) TYP

NOTE 6

EXPOSED

THERMAL PAD

2X 0.65

(0.07) TYP

NOTE 5

0.28

PIN 1 ID

(OPTIONAL)

NOTE 4

0.15

(0.11)

0.3

0.2

0.1

C A B

0.05

0.30

0.15

4215302/E 12/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.

5. Shape of exposed side leads may differ.

6. Number and location of exposed tie bars may vary.

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EXAMPLE BOARD LAYOUT

X2SON - 0.4 mm max height

DQN0004A

PLASTIC SMALL OUTLINE - NO LEAD

(0.86)

SYMM

SEE DETAIL

4X (0.36)

(0.03)

4X (0.21)

SYMM

(0.65)

4X (0.18)

(

0.48)

(0.22) TYP

EXPOSED METAL

CLEARANCE

LAND PATTERN EXAMPLE

SCALE: 40X

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

DEFINED

SOLDER MASK DETAIL

4215302/E 12/2016

NOTES: (continued)

7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

X2SON - 0.4 mm max height

DQN0004A

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

SYMM

4X (0.4)

4X (0.03)

4X (0.21)

SYMM

(0.65)

SOLDER MASK

EDGE

4X (0.22)

(

0.45)

4X (0.235)

SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1mm THICK STENCIL

EXPOSED PAD

88% PRINTED SOLDER COVERAGE BY AREA

SCALE: 60X

4215302/E 12/2016

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

0.90

PIN 1

INDEX AREA

2X 0.95

1.9

3.05

2.75

1.9

0.5

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/E 09/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

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