TPS73132DBVRG4 [TI]
Single Output LDO, 150mA, Fixed(3.2V), Cap free, Low Noise, Fast Transient Response 5-SOT-23 -40 to 85;
| 型号： | TPS73132DBVRG4 |
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TEXAS INSTRUMENTS |
| 描述： | Single Output LDO, 150mA, Fixed(3.2V), Cap free, Low Noise, Fast Transient Response 5-SOT-23 -40 to 85 信息通信管理 光电二极管 输出元件 调节器 |
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TPS731xx
www.ti.com .......................................................................................................................................... SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009
Cap-Free, NMOS, 150mA Low Dropout Regulator
with Reverse Current Protection
1
FEATURES
DESCRIPTION
2
•
Stable with No Output Capacitor or Any Value
or Type of Capacitor
The TPS731xx family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly constant
over all values of output current.
•
•
•
Input Voltage Range of 1.7V to 5.5V
Ultralow Dropout Voltage: 30mV Typ
Excellent Load Transient Response—with or
without Optional Output Capacitor
•
New NMOS Topology Provides Low Reverse
Leakage Current
The TPS731xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1μA and
ideal for portable applications. The extremely low
output noise (30μVRMS with 0.1μF CNR) is ideal for
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
•
•
•
Low Noise: 30μVRMS Typ (10kHz to 100kHz)
0.5% Initial Accuracy
1% Overall Accuracy over Line, Load, and
Temperature
•
•
Less Than 1μA Max IQ in Shutdown Mode
Thermal Shutdown and Specified Min/Max
Current Limit Protection
•
Available in Multiple Output Voltage Versions
–
–
–
Fixed Outputs of 1.20V to 5.0V
Adjustable Outputs from 1.20V to 5.5V
Custom Outputs Available
APPLICATIONS
•
•
•
•
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
space
DBV PACKAGE
SOT23
(TOP VIEW)
Optional
Optional
VIN
VOUT
IN
OUT
TPS731xx
GND
1
2
3
IN
GND
EN
OUT
5
4
EN
NR
ON
OFF
NR/FB
Optional
Typical Application Circuit for Fixed-Voltage Versions
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2009, Texas Instruments Incorporated
TPS731xx
SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009.......................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS731xx yy yz
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Z is package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM
programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
PARAMETER
TPS731xx
–0.3 to 6.0
–0.3 to 6.0
–0.3 to 5.5
–0.3 to 6.0
Internally limited
Indefinite
UNIT
VIN range
V
V
V
V
VEN range
VOUT range
VNR, VFB range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
See Dissipation Ratings Table
–55 to +150
–65 to +150
2
°C
°C
kV
V
ESD rating, CDM
500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = 25°C
T
A ≤ 25°C
TA = 70°C
TA = 85°C
BOARD
PACKAGE
RΘJC
RΘJA
POWER RATING POWER RATING POWER RATING
(2)
Low-K
DBV
DBV
64°C/W
64°C/W
255°C/W
180°C/W
3.9mW/°C
5.6mW/°C
390mW
560mW
215mW
310mW
155mW
225mW
(3)
High-K
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
2
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TPS731xx
www.ti.com .......................................................................................................................................... SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = -40°C to +125°C), VIN = VOUT(nom) + 0.5V(1), IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1μF, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN
1.7
TYP
MAX UNIT
VIN
Input voltage range(1)
Internal reference (TPS73101)
Output voltage range (TPS73101)(2)
Nominal
5.5
1.210
V
V
V
VFB
TJ = +25°C
TJ = +25°C
1.198
VFB
1.20
5.5 – VDO
+0.5
–0.5
VOUT
Accuracy(1) (3)
%
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10 mA ≤ IOUT ≤ 150mA
VIN, IOUT, and T
–1.0
±0.5
+1.0
ΔVOUT%/ΔVIN
Line regulation(1)
VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V
1mA ≤ IOUT ≤ 150mA
0.01
0.002
%/V
ΔVOUT%/ΔIOUT Load regulation
%/mA
10mA ≤ IOUT ≤ 150mA
0.0005
Dropout voltage(4)
VDO
IOUT = 150mA
30
100
500
mV
(VIN = VOUT (nom) – 0.1V)
ZO(DO)
ICL
Output impedance in dropout
Output current limit
1.7 V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0V
0.25
360
200
0.1
Ω
150
mA
mA
μA
ISC
Short-circuit current
IREV
Reverse leakage current(5) (–IIN
)
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT
10
550
750
IOUT = 10mA (IQ)
IOUT = 150mA
400
550
IGND
GND pin current
μA
V
EN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5,
ISHDN
IFB
Shutdown current (IGND
)
0.02
1
μA
μA
–40°C ≤ TJ ≤ +100°C
FB pin current (TPS73101)
0.1
58
37
0.3
f = 100Hz, IOUT = 150 mA
f = 10kHz, IOUT = 150 mA
COUT = 10μF, No CNR
Power-supply rejection ratio
(ripple rejection)
PSRR
dB
27 × VOUT
8.5 × VOUT
Output noise voltage
BW = 10Hz - 100kHz
VN
μVRMS
μs
COUT = 10μF, CNR = 0.01μF
VOUT = 3V, RL = 30Ω
COUT = 1μF, CNR = 0.01μF
tSTR
Startup time
600
VEN(HI)
VEN(LO)
IEN(HI)
EN pin high (enabled)
EN pin low (shutdown)
EN pin current (enabled)
1.7
0
VIN
0.5
0.1
V
V
VEN = 5.5V
0.02
+160
+140
μA
Shutdown
Reset
Temp increasing
Temp decreasing
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
–40
+125
(1) Minimum VIN = VOUT + VDO or 1.7V, whichever is greater.
(2) TPS73101 is tested at VOUT = 2.5V.
(3) Tolerance of external resistors not included in this specification.
(4) VDO is not measured for fixed output versions with VOUT(nom) < 1.8V since minimum VIN = 1.7V.
(5) Fixed-voltage versions only; refer to the Applications section for more information.
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TPS731xx
SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009.......................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
R2
Ω
R1 + R2 = 80k
NR
Figure 1. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
V
O
R
1
R
2
4MHz
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
Short
Open
Charge Pump
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
OUT
FB
Current
Limit
R
R
19kΩ for best
1
2
accuracy.
GND
Ω
80k
Ω
8k
R1
R2
Figure 2. Adjustable Voltage Version
4
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TPS731xx
www.ti.com .......................................................................................................................................... SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009
PIN CONFIGURATION
DBV PACKAGE
SOT23
(TOP VIEW)
5
4
IN
GND
EN
1
2
3
OUT
NR/FB
PIN DESCRIPTIONS
SOT23
(DBV)
NAME
IN
PIN NO.
DESCRIPTION
1
2
Input supply
Ground
GND
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to
IN if not used.
EN
NR
3
4
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the
internal bandgap, reducing output noise to very low levels.
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the
output voltage of the device.
FB
4
5
OUT
Output of the regulator. There are no output capacitor requirements for stability.
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TPS731xx
SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009.......................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.5
0.4
0.3
0.2
0.1
0
0.20
0.15
0.10
0.05
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
_
+25 C
_
+125 C
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
0.05
0.10
0.15
0.20
−
_
40 C
−
−
−
0
15
30 45
60
75
90 105 120 135 150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
−
VIN VOUT (V)
IOUT (mA)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
50
40
30
20
10
0
50
40
30
20
10
0
TPS73125DBV
IOUT = 150mA
TPS73125DBV
_
+125 C
_
+25 C
−
_
40 C
−
−
25
0
30
60
IOUT (mA)
90
120
150
50
0
25
50
75
100
125
_
Temperature ( C)
Figure 5.
Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
16
14
12
10
8
IOUT = 10mA
All Voltage Versions
IOUT = 10mA
25
20
15
10
5
6
4
2
0
0
_
VOUT Error (%)
Worst Case dVOUT/dT (ppm/ C)
Figure 7.
Figure 8.
6
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TPS731xx
www.ti.com .......................................................................................................................................... SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
700
700
600
500
400
300
200
100
0
IOUT = 150mA
600
500
400
300
200
100
0
VIN = 5.5V
VIN = 4V
VIN = 2V
VIN = 5.5V
VIN = 4V
VIN = 2V
−
−
25
0
30
60
IOUT (mA)
90
120
150
50
0
25
50
75
100
125
_
Temperature ( C)
Figure 9.
Figure 10.
GROUND PIN CURRENT in SHUTDOWN vs TEMPERATURE
CURRENT LIMIT vs VOUT (FOLDBACK)
1
400
350
300
250
200
150
100
50
TPS73133
VENABLE = 0.5V
VIN = VO + 0.5V
ICL
ISC
0.1
0.01
0
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−
−
25
50
0
25
50
75
100
125
Output Voltage (V)
_
Temperature ( C)
Figure 11.
Figure 12.
CURRENT LIMIT vs VIN
CURRENT LIMIT vs TEMPERATURE
500
500
450
400
350
300
250
200
150
450
400
350
300
250
200
150
−
−
25
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
0
25
50
75
100
125
VIN (V)
_
Temperature ( C)
Figure 13.
Figure 14.
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TPS731xx
SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009.......................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
IOUT = 100mA
COUT = Any
IOUT = 1mA
COUT = 1mF
IOUT = 1mA
COUT = 10mF
IO = 100mA
CO = 1mF
IOUT = 1mA
COUT = Any
Frequency = 10kHz
COUT = 10mF
IOUT = 100mA
COUT = 10mF
IOUT = Any
VOUT = 2.5V
VIN = VOUT + 1V
COUT = 0mF
IOUT = 100mA
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
VIN - VOUT (V)
Frequency (Hz)
Figure 15.
Figure 16.
NOISE SPECTRAL DENSITY
NOISE SPECTRAL DENSITY
CNR = 0μF
CNR = 0.01μF
1
1
µ
COUT = 1 F
µ
COUT = 1 F
µ
COUT = 0 F
0.1
0.1
µ
COUT = 10 F
µ
COUT = 0 F
µ
COUT = 10 F
IOUT = 150mA
10 100
IOUT = 150mA
10 100
0.01
0.01
1k
10k
100k
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 17.
Figure 18.
RMS NOISE VOLTAGE vs COUT
RMS NOISE VOLTAGE vs CNR
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
VOUT = 3.3V
VOUT = 1.5V
60
40
20
µ
CNR = 0.01 F
µ
COUT = 0 F
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p
10p
100p
1n
10n
µ
COUT ( F)
CNR (F)
Figure 19.
Figure 20.
8
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TPS731xx
www.ti.com .......................................................................................................................................... SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
TPS73133
TPS73133
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
µ
COUT = 0 F
VIN = 3.8V
IOUT = 150mA
40mV/tick
40mV/tick
40mV/tick
25mA/tick
VOUT
VOUT
VOUT
IOUT
µ
COUT = 0 F
50mV/div
VOUT
µ
COUT = 1 F
µ
COUT = 100 F
µ
COUT = 10 F
50mV/div
1V/div
VOUT
dVIN
dt
5.5V
µ
= 0.5V/
s
150mA
4.5V
VIN
10mA
10 s/div
µ
µ
10 s/div
Figure 21.
Figure 22.
TPS73133
TPS73133
TURN-ON RESPONSE
TURN-OFF RESPONSE
RL = 1kΩ
RL = 20Ω
COUT = 10
VOUT
µ
COUT = 0
F
µ
F
Ω
RL = 20
Ω
RL = 20
1V/div
1V/div
1V/div
1V/div
µ
COUT = 1
F
µ
COUT = 1
F
Ω
RL = 1k
Ω
RL = 20
COUT = 0µF
COUT = 10µF
VOUT
2V
2V
VEN
0V
0V
VEN
100µs/div
100µs/div
Figure 23.
Figure 24.
TPS73133
POWER UP / POWER DOWN
IENABLE vs TEMPERATURE
10
1
6
5
4
3
2
1
0
VIN
VOUT
0.1
0.01
−
−
1
2
−
−
25
50
0
25
50
75
100
125
50ms/div
_
Temperature ( C)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise
noted.
TPS73101
TPS73101
RMS NOISE VOLTAGE vs CFB
IFB vs TEMPERATURE
60
55
50
45
40
35
30
25
20
160
140
120
100
80
60
VOUT = 2.5V
40
µ
COUT = 0 F
Ω
R1 = 39.2k
20
10Hz < Frequency < 100kHz
0
10p
100p
1n
10n
−
−
25
50
0
25
50
75
100
125
CFB (F)
_
Temperature ( C)
Figure 27.
Figure 28.
TPS73101
TPS73101
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10nF
VOUT = 2.5V
CFB = 10nF
Ω
R1 = 39.2k
µ
COUT = 0 F
µ
COUT = 0 F
VOUT
VOUT
50mV/div
50mV/div
100mV/div
100mV/div
µ
COUT = 10 F
VOUT
µ
COUT = 10 F
VOUT
4.5V
150mA
3.5V
VIN
10mA
IOUT
µ
µ
25 s/div
5 s/div
Figure 29.
Figure 30.
10
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TPS731xx
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APPLICATION INFORMATION
For best accuracy, make the parallel combination of
The TPS731xx belongs to a family of new generation
R1 and R2 approximately equal to 19kΩ. This 19kΩ,
LDO regulators that use an NMOS pass transistor to
in addition to the internal 8kΩ resistor, presents the
achieve ultra-low-dropout performance, reverse
same impedance to the error amp as the 27kΩ
current blockage, and freedom from output capacitor
bandgap reference output. This impedance helps
constraints. These features, combined with low noise
compensate for leakages into the error amp
and an enable input, make the TPS731xx ideal for
terminals.
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and an
INPUT AND OUTPUT CAPACITOR
adjustable output version. All versions have thermal
REQUIREMENTS
and over-current protection, including foldback
current limit.
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1μF to 1μF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response, noise
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the connections
for the adjustable output version (TPS73101).
rejection, and ripple rejection.
A
higher-value
Optional input capacitor.
May improve source
Optional output capacitor.
May improve load transient,
noise, or PSRR.
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
impedance, noise, or PSRR.
VIN
VOUT
IN
OUT
TPS731xx
The TPS731xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
multiple low ESR capacitors are in parallel, ringing
may occur when the product of COUT and total ESR
drops below 50nΩF. Total ESR includes all parasitic
resistances, including capacitor ESR and board,
socket, and solder joint resistance. In most
applications, the sum of capacitor ESR and trace
resistance will meet this requirement.
EN
GND
NR
ON
OFF
Optional bypass
capacitor to reduce
output noise.
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
OUTPUT NOISE
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS731xx and
it generates approximately 32μVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
VIN
VOUT
IN
OUT
TPS73101
R1
CFB
EN
GND
FB
ON
R2
OFF
Optional capacitor
reduces output noise
and improves
(R1 + R2)
R2
VOUT
=
x 1.204
VOUT
VREF
(R1 ) R2)
VN + 32mVRMS
+ 32mVRMS
transient response.
R2
(1)
Since the value of VREF is 1.2V, this relationship
reduces to:
Figure 32. Typical Application Circuit for
Adjustable-Voltage Version
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 32. Sample
resistor values for common output voltages are
shown in Figure 2.
(2)
for the case of no CNR
.
Copyright © 2003–2009, Texas Instruments Incorporated
Submit Documentation Feedback
11
TPS731xx
SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009.......................................................................................................................................... www.ti.com
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
ENABLE PIN AND SHUTDOWN
The enable pin (EN) is active high and is compatible
with standard TTL-CMOS levels. A VEN below 0.5V
(max) turns the regulator off and drops the GND pin
current to approximately 10nA. When EN is used to
shutdown the regulator, all charge is removed from
the pass transistor gate, and the output ramps back
up to a regulated VOUT (see Figure 23).
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 8.5
VOUT(V)
(3)
When shutdown capability is not required, EN can be
connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass
transistor may be left on (enhanced) for a significant
time after VIN has been removed. This scenario can
result in reverse current flow (if the IN pin is low
impedance) and faster ramp times upon power-up. In
addition, for VIN ramp times slower than a few
milliseconds, the output may overshoot upon
power-up.
for CNR = 10nF.
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in the Typical Characteristics section.
The TPS73101 adjustable version does not have the
NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin
(FB) reduces output noise and improves load
transient performance.
Note that current limit foldback can prevent device
start-up under some conditions. See the Internal
Current Limit section.
The TPS731xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250μV of switching noise at
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
DROPOUT VOLTAGE
The TPS731xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
values of IOUT and COUT
.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the PCB be designed with separate ground planes for
VIN and VOUT, with each ground plane connected only
at the ground pin (GND) of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
For large step changes in load current, the TPS731xx
requires a larger voltage drop from VIN to VOUT to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of VIN – VOUT above this line
insure normal transient response.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
INTERNAL CURRENT LIMIT
The TPS731xx internal current limit helps protect the
regulator during fault conditions. Foldback current
limit helps to protect the regulator from damage
during output short-circuit conditions by reducing
current limit when VOUT drops below 0.5V. See
Figure 12 in the Typical Characteristics section.
the TPS731xx can take
a couple of hundred
Note from Figure 12 that approximately –0.2V of VOUT
results in a current limit of 0mA. Therefore, if OUT is
forced below –0.2V before EN goes high, the device
may not start up. In applications that work with both a
positive and negative voltage supply, the TPS731xx
should be enabled first.
microseconds to return to the specified regulation
accuracy.
12
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Copyright © 2003–2009, Texas Instruments Incorporated
TPS731xx
www.ti.com .......................................................................................................................................... SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009
TRANSIENT RESPONSE
After the EN pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current flowing
out of the IN pin due to voltage applied on the OUT
pin. There will be additional current flowing into the
OUT pin due to the 80kΩ internal resistor divider to
ground (see Figure 1 and Figure 2).
The low open-loop output impedance provided by the
NMOS pass element in
a
voltage follower
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1μF) from the output pin (OUT) to ground will reduce
undershoot magnitude but increase its duration. In
the adjustable version, the addition of a capacitor,
CFB, from the OUT pin to the FB pin will also improve
the transient response.
For the TPS73101, reverse current may flow when
VFB is more than 1.0V above VIN.
THERMAL PROTECTION
The TPS731xx does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as
alternate power supplies, to the output. This also
results in an output overshoot of several percent if the
load current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor COUT and the internal/external load
resistance. The rate of decay is given by:
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(Fixed voltage version)
VOUT
dVńdt +
COUT 80kW ø RLOAD
(4)
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
(Adjustable voltage version)
VOUT
dVńdt +
(
)
COUT 80kW ø R1 ) R2 ø RLOAD
(5)
condition of your application. This produces
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
a
REVERSE CURRENT
The NMOS pass element of the TPS731xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
the EN pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the
gate.
The internal protection circuitry of the TPS731xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS731xx into thermal
shutdown degrades device reliability.
Copyright © 2003–2009, Texas Instruments Incorporated
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13
TPS731xx
SBVS034M –SEPTEMBER 2003–REVISED AUGUST 2009.......................................................................................................................................... www.ti.com
PD + (VIN * VOUT) IOUT
POWER DISSIPATION
(6)
The ability to remove heat from the die is different for
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Power Dissipation Ratings table.
Using heavier copper will increase the effectiveness
in removing heat from the device. The addition of
plated through-holes to heat-dissipating layers also
improves the heat-sink effectiveness.
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TPS731xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
space
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (May, 2009) to Revision M ..................................................................................................... Page
•
•
•
Changed Figure 12 ............................................................................................................................................................... 7
Added paragraph about recommended start-up sequence to Internal Current Limit section ............................................. 12
Added paragraph about current foldback and device start-up to Enable Pin and Shutdown section ................................ 12
14
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Copyright © 2003–2009, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2013
PACKAGING INFORMATION
Orderable Device
TPS73101DBVR
TPS73101DBVRG4
TPS73101DBVT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
PWYQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
3000
250
Green (RoHS
& no Sb/Br)
PWYQ
PWYQ
PWYQ
BYX
BYX
BYX
BYX
T31
Green (RoHS
& no Sb/Br)
TPS73101DBVTG4
TPS731125DBVR
TPS731125DBVRG4
TPS731125DBVT
TPS731125DBVTG4
TPS73115DBVR
TPS73115DBVRG4
TPS73115DBVT
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
T31
Green (RoHS
& no Sb/Br)
T31
TPS73115DBVTG4
TPS73118DBVR
TPS73118DBVRG4
TPS73118DBVT
250
Green (RoHS
& no Sb/Br)
T31
3000
3000
250
Green (RoHS
& no Sb/Br)
T32
Green (RoHS
& no Sb/Br)
T32
Green (RoHS
& no Sb/Br)
T32
TPS73118DBVTG4
TPS73125DBVR
250
Green (RoHS
& no Sb/Br)
T32
3000
Green (RoHS
& no Sb/Br)
PHWI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS73125DBVRG4
TPS73125DBVT
TPS73125DBVTG4
TPS73130DBVR
TPS73130DBVRG4
TPS73130DBVT
TPS73130DBVTG4
TPS73131DBVR
TPS73131DBVRG4
TPS73131DBVT
TPS73131DBVTG4
TPS73132DBVR
TPS73132DBVRG4
TPS73132DBVT
TPS73132DBVTG4
TPS73133DBVR
TPS73133DBVRG4
TPS73133DBVT
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
PHWI
PHWI
PHWI
T33
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
250
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
T33
Green (RoHS
& no Sb/Br)
T33
250
Green (RoHS
& no Sb/Br)
T33
3000
3000
250
Green (RoHS
& no Sb/Br)
BYS
BYS
BYS
BYS
T52
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
T52
Green (RoHS
& no Sb/Br)
T52
250
Green (RoHS
& no Sb/Br)
T52
3000
3000
250
Green (RoHS
& no Sb/Br)
T34
Green (RoHS
& no Sb/Br)
T34
Green (RoHS
& no Sb/Br)
T34
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS73133DBVTG4
TPS73150DBVR
TPS73150DBVRG4
TPS73150DBVT
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
5
5
5
5
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
T34
T35
T35
T35
T35
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
DBV
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS73150DBVTG4
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73101, TPS731125, TPS73115, TPS73118, TPS73125, TPS73130, TPS73132, TPS73133, TPS73150 :
Enhanced Product: TPS73101-EP, TPS731125-EP, TPS73115-EP, TPS73118-EP, TPS73125-EP, TPS73130-EP, TPS73132-EP, TPS73133-EP, TPS73150-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73101DBVR
TPS73101DBVT
TPS731125DBVR
TPS731125DBVT
TPS73115DBVR
TPS73115DBVT
TPS73118DBVR
TPS73118DBVT
TPS73125DBVR
TPS73125DBVT
TPS73130DBVR
TPS73130DBVT
TPS73131DBVR
TPS73131DBVT
TPS73132DBVR
TPS73132DBVT
TPS73133DBVR
TPS73133DBVT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000
250
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
179.0
179.0
178.0
178.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
8.4
8.4
9.0
9.0
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.2
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.2
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3.2
3.2
1.4
3000
250
3.23
3.23
3.17
3.17
1.37
1.37
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2011
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73150DBVR
TPS73150DBVT
SOT-23
SOT-23
DBV
DBV
5
5
3000
250
178.0
178.0
9.0
9.0
3.23
3.23
3.17
3.17
1.37
1.37
4.0
4.0
8.0
8.0
Q3
Q3
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS73101DBVR
TPS73101DBVT
TPS731125DBVR
TPS731125DBVT
TPS73115DBVR
TPS73115DBVT
TPS73118DBVR
TPS73118DBVT
TPS73125DBVR
TPS73125DBVT
TPS73130DBVR
TPS73130DBVT
TPS73131DBVR
TPS73131DBVT
TPS73132DBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
203.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
203.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
35.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2011
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS73132DBVT
TPS73133DBVR
TPS73133DBVT
TPS73150DBVR
TPS73150DBVT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
250
3000
250
203.0
180.0
180.0
180.0
180.0
203.0
180.0
180.0
180.0
180.0
35.0
18.0
18.0
18.0
18.0
3000
250
Pack Materials-Page 3
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