TPS70630DRVR [TI]
具有反向电流保护和使能功能的 150mA、超低 IQ、低压降稳压器 | DRV | 6 | -40 to 125;型号: | TPS70630DRVR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有反向电流保护和使能功能的 150mA、超低 IQ、低压降稳压器 | DRV | 6 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
文件: | 总34页 (文件大小:1694K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS706
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
TPS706 具有使能功能的 150mA、6.5V、1μA IQ 稳压器
1 特性
3 说明
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输入电压范围:2.7V 至 6.5V
TPS706 系列线性稳压器是针对功耗敏感型应用而设计
的超低静态电流器件。 一个精密带隙和误差放大器在
温度范围内的精度为 2%。 只有 1µA 的静态电流使得
此器件成为由电池供电、要求非常小闲置状态功率耗散
的常开系统的理想解决方案。 该系列器件还具有热关
断、电流限制和反向电流保护功能,提升了器件安全
性。
超低 IQ:1μA
反向电流保护
低 ISHDN:150nA
支持 200mA 峰值输出
低压降:50mA 时为 245mV
在温度范围内精度为 2%
可提供固定输出电压:1.2V 至 5V
热关断及过流保护
通过将 EN 引脚拉为低电平,可将该系列稳压器置于关
断模式。 这个模式的关断电流低至 150nA(典型
值)。
封装:小外形尺寸晶体管 (SOT)-23-5 封装、晶圆
级小外形无引线 (WSON)
TPS706 系列采用 WSON-6 和 SOT-23-5 封装。
2 应用
器件信息(1)
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智能手机和平板电脑
器件型号
TPS706
封装
SOT-23 (5)
WSON (6)
封装尺寸(标称值)
2.90mm x 1.60mm
2.00mm x 2.00mm
便携式和电池供电类应用
摄像机模块
机顶盒
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
可穿戴产品
固态硬盘
空白
医疗设备
空白
空白
典型应用电路
接地电流与 VIN 和温度间的关系
3
VOUT
VIN
IN
OUT
TJ = -40°C
TJ = +25°C
2.8
1 mF
2.2 mF
TJ = +85°C
2.6
GND
EN
TJ = +125°C
2.4
TPS706
NC
2.2
2
1.8
1.6
1.4
1.2
1
4
4.25 4.5 4.75
5
5.25 5.5 5.75
6
6.25 6.5
Input Voltage (V)
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBVS245
TPS706
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com.cn
目录
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 15
Power Supply Recommendations...................... 15
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 5
6.7 Typical Characteristics.............................................. 6
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
8
9
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Examples................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 器件支持................................................................ 19
11.2 文档支持................................................................ 19
11.3 商标....................................................................... 19
11.4 静电放电警告......................................................... 19
11.5 术语表 ................................................................... 19
12 机械封装和可订购信息 .......................................... 19
7
4 修订历史记录
Changes from Original (October 2014) to Revision A
Page
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已更改产品预览数据表;以量产数据状态发布........................................................................................................................ 1
2
Copyright © 2014–2015, Texas Instruments Incorporated
TPS706
www.ti.com.cn
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
5 Pin Configuration and Functions
DBV Package
SOT-23-5
(Top View)
DRV Package
WSON-6
(Top View)
IN
GND
EN
1
2
3
5
4
OUT
NC
OUT
NC
1
2
3
6
5
4
IN
NC
EN
GND
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
DRV
DBV
Enable pin. Driving this pin high enables the device. Driving this pin low puts the
device into low current shutdown. This pin can be left floating to enable the device.
The maximum voltage must remain below 6.5 V.
EN
4
3
I
GND
IN
3
6
2
1
4
—
I
Ground
Unregulated input to the device
No internal connection
NC
2, 5
—
Regulated output voltage. Connect a small 2.2-µF or greater ceramic capacitor
from this pin to ground to assure stability.
OUT
1
5
O
The thermal pad is electrically connected to the GND node.
Connect to the GND plane for improved thermal performance.
Thermal pad
—
—
Copyright © 2014–2015, Texas Instruments Incorporated
3
TPS706
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
specified at TJ = –40°C to 125°C, unless otherwise noted; all voltages are with respect to GND(1)
MIN
MAX
UNIT
VIN
–0.3
–0.3
–0.3
7
V
V
V
Voltage
VEN
VOUT
IOUT
7
7
Internally limited
Indefinite
Maximum output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature, TJ
PDISS
See Thermal Information
150
–55
–55
°C
°C
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
2.7
1.2
0
NOM
MAX
6.5
5
UNIT
VIN
Input voltage
V
V
VOUT
IOUT
VEN
CIN
Output voltage
Output current
150
6.5
mA
V
Enable voltage
0
Input capacitor
0
1
µF
µF
°C
COUT
TJ
Output capacitor
Operating junction temperature
2
2.2
47
–40
125
6.4 Thermal Information
TPS706
THERMAL METRIC(1)
DBV
DRV
UNIT
5 PINS
212.1
78.5
6 PINS
73.1
97.0
42.6
2.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
39.5
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.86
ψJB
38.7
42.9
12.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014–2015, Texas Instruments Incorporated
TPS706
www.ti.com.cn
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
6.5 Electrical Characteristics
At TJ = –40°C to 125°C, VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), IOUT = 1 mA, VEN = 2 V, and CIN = COUT = 2.2-μF
ceramic, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
2.7
TYP
MAX
6.5
5.0
2%
1%
10
UNIT
V
VIN
Input voltage range
Output voltage range
VOUT
1.2
V
VOUT < 3.3 V
OUT ≥ 3.3 V, TJ = –40°C to 85°C
–2%
–1%
VOUT(accuracy)
DC output accuracy
V
Line regulation
Load regulation
(VOUT(nom) + 1 V, 2.7 V) ≤ VIN ≤ 6.5 V
3
mV
mV
ΔVOUT
VIN = VOUT(nom) + 1.5 V or 3 V (whichever is
greater), 100 µA ≤ IOUT ≤ 150 mA
20
50
2.8 V ≤ VOUT ≤ 3.3 V, IOUT = 50 mA
2.8 V ≤ VOUT ≤ 3.3 V, IOUT = 150 mA
VOUT = 0.9 × VOUT(nom)
295
975
320
1.3
350
150
80
650
1540
500
mV
mV
mA
µA
µA
nA
dB
dB
dB
VDO
I(CL)
IGND
ISHDN
Dropout voltage(1)(2)
Output current limit(3)
Ground pin current
Shutdown current
200
IOUT = 0 mA, VOUT ≤ 3.3 V
IOUT = 150 mA
2.55
VEN ≤ 0.4 V, VIN = 2.7 V
f = 10 Hz
PSRR
Vn
Power-supply rejection ratio f = 100 Hz
f = 1 kHz
62
52
BW = 10 Hz to 100 kHz, IOUT = 10 mA,
VIN = 2.7 V, VOUT = 1.2 V
Output noise voltage
190
μVRMS
Enable pin high (enabled)
Enable pin high (disabled)
EN pin current
0.9
0
V
V
VEN(HI)
IEN
0.4
EN = 1.0 V, VIN = 5.5 V
300
10
nA
Reverse current
(flowing out of IN pin)
VOUT = 3 V, VIN = VEN = 0 V
nA
nA
IREV
Reverse current
(flowing into OUT pin)
VOUT = 3 V, VIN = VEN = 0 V
100
Shutdown, temperature increasing
Reset, temperature decreasing
158
140
°C
°C
Thermal shutdown
temperature
TSD
TJ
Operating junction
temperature
–40
125
°C
(1) VDO is measured with VIN = 0.98 × VOUT(nom)
.
(2) Dropout is only valid when VOUT ≥ 2.8 V because of the minimum input voltage limits.
(3) Measured with VIN = VOUT + 3 V for VOUT ≤ 2.5 V. Measured with VIN = VOUT + 2.5 V for VOUT > 2.5 V.
6.6 Timing Requirements
At TJ = –40°C to 125°C, VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), RL = 47 Ω, VEN = 2 V, and CIN = COUT = 2.2-μF
ceramic, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
MIN
TYP
200
500
MAX
600
UNIT
µs
V
OUT(nom) ≤ 3.3 V
tSTR
Start-up time(1)
VOUT > 3.3 V
1500
µs
(1) Startup time = time from EN assertion to 0.95 × VOUT(nom) and load = 47 Ω.
Copyright © 2014–2015, Texas Instruments Incorporated
5
TPS706
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com.cn
6.7 Typical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
1.205
1.204
1.203
1.202
1.201
1.2
3.31
3.308
3.306
3.304
3.302
3.3
TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
1.199
1.198
1.197
1.196
1.195
3.298
3.296
3.294
3.292
3.29
2.5
3
3.5
4
4.5
5
5.5
6
6.5
4.25 4.5 4.75
5
5.25 5.5 5.75
Input Voltage (V)
6
6.25 6.5
Input Voltage (V)
TPS70612
TPS70633
Figure 1. 1.2-V Line Regulation vs VIN and Temperature
Figure 2. 3.3-V Line Regulation vs VIN and Temperature
1.205
3.308
TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TJ = -40°C
1.2025
3.304
3.3
TJ = +25°C
TJ = +85°C
TJ = +125°C
1.2
1.1975
3.296
3.292
3.288
3.284
3.28
1.195
1.1925
1.19
1.1875
1.185
1.1825
1.18
3.276
3.272
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
Output Current (mA)
Input Current (mA)
TPS70612
TPS70633
Figure 3. 1.2-V Load Regulation vs IOUT and Temperature
Figure 4. 3.3-V Load Regulation vs IOUT and Temperature
1.205
500
IOUT = 10 mA
IOUT = 150 mA
TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
480
460
440
420
400
380
360
340
320
300
280
260
240
220
200
1.2025
1.2
1.1975
1.195
1.1925
1.19
1.1875
1.185
1.1825
1.18
-40
-20
0
20
40
60
80
100 120 140
3.5
4
4.5
5
5.5
6
6.5
Junction Temperature (qC)
Input Voltage (V)
TPS70612
TPS70612
Figure 5. VOUT vs Temperature
Figure 6. 1.2-V Current Limit vs VIN and Temperature
6
Copyright © 2014–2015, Texas Instruments Incorporated
TPS706
www.ti.com.cn
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
440
430
420
410
400
390
380
370
360
350
340
330
320
310
300
3
2.5
2
TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TJ = +125 qC
TJ = +85 qC
TJ = +25 qC
TJ = -40 qC
1.5
1
0.5
5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9
6
6.1 6.2 6.3 6.4 6.5
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Input Voltage (V)
Input Voltage (V)
TPS70633
TPS70612
Figure 7. 3.3-V Current Limit vs VIN and Temperature
Figure 8. GND Current vs VIN and Temperature
800
700
600
500
400
300
200
100
0
3
TJ = +125 qC
TJ = +85 qC
TJ = +25 qC
TJ = -40 qC
TJ = -40°C
2.8
TJ = +25°C
TJ = +85°C
TJ = +125°C
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
4
4.25 4.5 4.75
5
5.25 5.5 5.75
6
6.25 6.5
0
25
50
75
100
125
150
Input Voltage (V)
Output Current (mA)
TPS70633, EN = open
TPS70612
Figure 9. GND Current vs VIN and Temperature
Figure 10. GND Current vs IOUT and Temperature
90
80
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0
TJ = +125 qC
TJ = +85 qC
TJ = +25 qC
TJ = -40 qC
2.5
3
3.5
4
4.5
5
5.5
6
6.5
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Input Voltage (V)
Frequency (Hz)
Shutdown current, TPS70612
VOUT = 2.8 V, VIN = 3.8 V, COUT = 2.2 µF
Figure 11. Shutdown Current vs VIN and Temperature
Figure 12. Power-Supply Rejection Ratio vs Frequency
Copyright © 2014–2015, Texas Instruments Incorporated
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TPS706
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com.cn
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
7
6.5
6
140
130
120
110
100
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
10 25 40 55 70 85 100 115 130
±50 ±35 ±20 ±5
1E+1
1E+2
1E+3
Frequency (Hz)
1E+4
1E+5
Temperature (C)
C019
TPS70612
VOUT = 2.8 V
Figure 14. Start-Up Time vs Temperature
Figure 13. Noise
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 4
(50 mA / div)
Channel 4
(100 mA / div)
Time (100 ms / div)
Time (500 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Figure 15. TPS70612 Load Transient (0 mA to 50 mA)
Figure 16. TPS70612 Load Transient (1 mA to 150 mA)
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 4
(50 mA / div)
Channel 4
(100 mA / div)
Time (10 ms / div)
Time (100 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Figure 17. TPS70612 Load Transient (50 mA to 0 mA)
Figure 18. TPS70612 Load Transient (50 mA to 150 mA)
8
Copyright © 2014–2015, Texas Instruments Incorporated
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ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 4
(50 mA / div)
Channel 4
(100 mA / div)
Time (100 ms / div)
Time (500 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Figure 19. TPS70633 Load Transient (0 mA to 50 mA)
Figure 20. TPS70633 Load Transient (1 mA to 150 mA)
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 4
(50 mA / div)
Channel 4
(50 mA / div)
Time (10 ms / div)
Time (500 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Figure 21. TPS70633 Load Transient (50 mA to 0 mA)
Figure 22. TPS70633 Load Transient (50 mA to 150 mA)
Channel 2
(50 mV / div)
Channel 2
(50 mV / div)
Channel 4
(2 V / div)
Channel 4
(2 V / div)
Time (50 ms / div)
Time (50 ms / div)
Channel 2 = VOUT, channel 4 = VIN, IOUT = 10 mA
Channel 2 = VOUT, channel 4 = VIN, IOUT = 50 mA
Figure 23. TPS70612 Line Transient (2.7 V to 3.7 V)
Figure 24. TPS70612 Line Transient (2.7 V to 3.7 V)
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ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
Channel 2
(50 mV / div)
Channel 2
(50 mV / div)
Channel 4
(2 V / div)
Channel 4
(2 V / div)
Time (50 ms / div)
Time (50 ms / div)
Channel 2 = VOUT, channel 4 = VIN, IOUT = 10 mA
Channel 2 = VOUT, channel 4 = VIN, IOUT = 50 mA
Figure 25. TPS70633 Line Transient (4.3 V to 5.3 V)
Figure 26. TPS70633 Line Transient (4.3 V to 5.3 V)
Channel 2
(1 V / div)
Channel 2
(1 V / div)
Channel 1
(500 mV / div)
Channel 1
(1 V / div)
Time (50 ms / div)
Time (500 ms / div)
Channel 1 = EN, channel 2 = VOUT, VIN = 4.3 V, COUT = 2.2 µF,
TPS70633
Channel 1 = VIN, channel 2 = VOUT, IOUT = 3 mA, TPS70633
Figure 27. Power-Up with Enable
Figure 28. Power-Up and Power-Down Response
Channel 2
(1 V / div)
Channel 1
(1 V / div)
Time (500 ms / div)
Channel 1 = VIN, channel 2 = VOUT, IOUT = 150 mA, TPS70633
Figure 29. Power-Up and Power-Down Response
10
Copyright © 2014–2015, Texas Instruments Incorporated
TPS706
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ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
7 Detailed Description
7.1 Overview
The TPS706 series are ultralow quiescent current, low-dropout (LDO) linear regulators. The TPS706 offers
reverse current protection to block any discharge current from the output into the input. The TPS706 also
features current limit and thermal shutdown for reliable operation.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
Bandgap
EN
Logic
Device
GND
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TPS706 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry
operates properly.
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI) (0.9 V, minimum).
Turn off the device by forcing the EN pin to drop below 0.4 V. If shutdown capability is not required, connect EN
to IN.
7.3.3 Reverse Current Protection
The TPS706 has integrated reverse current protection. Reverse current protection prevents the flow of current
from the OUT pin to the IN pin when output voltage is higher than input voltage. The reverse current protection
circuitry places the power path in high impedance when the output voltage is higher than the input voltage. This
setting reduces leakage current from the output to the input to 10 nA, typical. The reverse current protection is
always active regardless of the enable pin logic state or if the OUT pin voltage is greater than 1.8 V. Reverse
current can flow if the output voltage is less than 1.8 V and if input voltage is less than the output voltage.
If voltage is applied to the input pin, then the maximum voltage that can be applied to the OUT pin is the lower of
three times the nominal output voltage or 6.5 V. For example, if the 1.2-V output voltage version is used, then the
maximum reverse bias voltage that can be applied to the OUT pin is 3.6 V. If the 3.3-V output voltage version is
used, then the maximum reverse bias voltage that can be applied to the OUT pin is 6.5 V.
Copyright © 2014–2015, Texas Instruments Incorporated
11
TPS706
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com.cn
Feature Description (continued)
7.3.4 Internal Current Limit
The TPS706 internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output
voltage is not regulated, and can be measured as (VOUT = ILIMIT × RLOAD). The PMOS pass transistor dissipates
[(VIN – VOUT) × ILIMIT] until a thermal shutdown is triggered and the device turns off. When cool, the device is
turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between
current limit and thermal shutdown; see the Thermal Information section for more details.
The TPS706 is characterized over the recommended operating output current range up to 150 mA. The internal
current limit begins to limit the output current at a minimum of 200 mA of output current.
7.3.5 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 158°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 125°C, maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least
35°C above the maximum expected ambient condition of the particular application. This configuration produces a
worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The TPS706 internal protection circuitry is designed to protect against overload conditions. This circuitry is not
intended to replace proper heatsinking. Continuously running the TPS706 into thermal shutdown degrades
device reliability.
12
Copyright © 2014–2015, Texas Instruments Incorporated
TPS706
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ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
The input voltage is at least as high as VIN(min).
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
•
•
The output current is less than the current limit.
The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
•
The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
•
The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
IOUT < ILIM
—
TJ
VIN > VOUT(nom) + VDO and
VIN > VIN(min)
Normal mode
Dropout mode
VEN > VEN(HI)
VEN > VEN(HI)
TJ < 125°C
TJ < 125°C
VIN(min) < VIN < VOUT(nom) + VDO
Disabled mode
(any true condition disables the
device)
—
VEN < VEN(low)
—
TJ > 158°C
Copyright © 2014–2015, Texas Instruments Incorporated
13
TPS706
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS706 consumes low quiescent current and delivers excellent line and load transient performance. This
performance, combined with low noise and good PSRR with little (VIN – VOUT) headroom, makes these devices
ideal for RF portable applications, current limit, and thermal protection. The TPS706 devices are specified from
–40°C to 125°C.
8.1.1 Input and Output Capacitor Considerations
The TPS706 devices are stable with output capacitors with an effective capacitance of 2.0 μF or greater for
output voltages below 1.5 V. For output voltages equal or greater than 1.5 V, the minimum effective capacitance
for stability is 1.5 µF. The maximum capacitance for stability is 47 µF. The equivalent series resistance (ESR) of
the output capacitor must be between 0 Ω and 0.2 Ω for stability.
The effective capacitance is the minimum capacitance value of a capacitor after taking into account variations
resulting from tolerances, temperature, and dc bias effects. X5R- and X7R-type ceramic capacitors are
recommended because these capacitors have minimal variation in value and ESR over temperature.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to
2.2-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple rejection, and PSRR.
8.1.2 Dropout Voltage
The TPS706 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO approximately scales with the output current because the PMOS device
functions like a resistor in dropout.
The ground pin current of many linear voltage regulators increases substantially when the device is operated in
dropout. This increase in ground pin current while operating in dropout can be several orders of magnitude larger
than when the device is not in dropout. The TPS706 employs a special control loop that limits the increase in
ground pin current while operating in dropout. This functionality allows for the most efficient operation while in
dropout conditions that can greatly increase battery run times.
8.1.3 Transient Response
As with any regulator, increasing the output capacitor size reduces over- and undershoot magnitude, but
increases transient response duration.
14
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TPS706
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ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
8.2 Typical Application
VIN
VOUT
IN
OUT
1 mF
2.2 mF
GND
EN
TPS70633
NC
Figure 30. 3.3-V, Low-IQ Rail
8.2.1 Design Requirements
Table 2 summarizes the design requirements for Figure 30.
Table 2. Design Requirements for a 3.3-V, Low-IQ Rail Application
PARAMETER
VIN
DESIGN SPECIFICATION
4.3 V
3.3 V
VOUT
I(IN) (no load)
IOUT (max)
< 5 µA
150 mA
8.2.2 Detailed Design Procedure
Select a 2.2-µF, 10-V X7R output capacitor to satisfy the minimum output capacitance requirement with a 3.3-V
dc bias.
Select a 1.0-µF, 6.3-V X7R input capacitor to provide input noise filtering and eliminate high-frequency voltage
transients.
8.2.3 Application Curves
Channel 2
(200 mV / div)
Channel 2
(1 V / div)
Channel 1
(500 mV / div)
Channel 4
(50 mA / div)
Time (500 ms / div)
Time (50 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Channel 1 = EN, channel 2 = VOUT, VIN = 4.3 V, COUT = 2.2 µF,
TPS70633
Figure 32. Power-Up with Enable
Figure 31. TPS70633 Load Transient (50 mA to 150 mA)
9 Power Supply Recommendations
This device is designed to operate with an input supply range of 2.7 V to 6.5 V. The input voltage range must
provide adequate headroom in order for the device to have a regulated output. This input supply must be well-
regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
Copyright © 2014–2015, Texas Instruments Incorporated
15
TPS706
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
Input and output capacitors must be placed as close to the device pins as possible. To improve ac performance
(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate
ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the
output capacitor ground connection must be connected directly to the device GND pin.
10.1.2 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by
the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown
in Equation 1.
PD = (VIN – VOUT) × IOUT
(1)
Figure 33 shows the maximum ambient temperature versus the power dissipation of the TPS706. This figure
assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board
thermal impedances vary widely. If the application requires high power dissipation, having a thorough
understanding of the board temperature and thermal impedances is helpful to ensure the TPS706 does not
operate above a junction temperature of 125°C.
125
TPS706, DBV Package
TPS706, DRV Package
100
75
50
0
0.2
0.4
0.6
0.8
1
Power Dissipation (W)
Figure 33. Maximum Ambient Temperature vs Device Power Dissipation
16
Copyright © 2014–2015, Texas Instruments Incorporated
TPS706
www.ti.com.cn
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
Layout Guidelines (continued)
Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB, shown in the
Thermal Information. These metrics are a more accurate representation of the heat transfer characteristics of the
die and the package than RθJA. The junction temperature can be estimated with Equation 2.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where:
•
•
•
PD is the power dissipation shown by Equation 1,
TT is the temperature at the center-top of the IC package,
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface.
(2)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
Copyright © 2014–2015, Texas Instruments Incorporated
17
TPS706
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
www.ti.com.cn
10.2 Layout Examples
Input Capacitor
Input
Trace
Enable
Trace
Grounded
Thermal Plane
NC
EN
Input Ground
Plane
IN
Thermal Pad
GND
NC
Output Trace
OUT
Grounded
Thermal Plane
Output Ground
Plane
Output Capacitor
Designates thermal vias.
Figure 34. WSON Layout Example
VOUT
VIN
OUT
IN
CIN
COUT
GND
EN
NC
GND PLANE
Represents via used for application-specific connections.
Figure 35. SOT23-5 Layout Example
18
版权 © 2014–2015, Texas Instruments Incorporated
TPS706
www.ti.com.cn
ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 Spice 模型
分析模拟电路和系统的性能时,使用 SPICE 模型对电路性能进行计算机仿真非常有用。 您可以从产品文件夹中的
仿真模型下获取 TPS706 的 SPICE 模型。
11.1.2 器件命名规则
表 3. 器件命名规则(1)
产品
VOUT
TPS706xx yyy z
xx 为标称输出电压。 对于分辨率为 100mV 的输出电压,订货编号中使用两位数字;否则,
使用三位数字(例如,28 = 2.8V)。
yyy 为封装标识符。
z 为卷带数量(R = 3000,T = 250)。
(1) 要获得最新的封装和订货信息,请参阅本文档末尾的封装选项附录,或者登录 TI 的网站 www.ti.com.cn进行查询。
11.2 文档支持
11.2.1 相关文档
SBVU002 — DEM-SOT23LDO 演示固定装置
SBVA025 — 《使用新的热指标》
11.3 商标
All trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 ,
可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2014–2015, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS70612DBVR
TPS70612DBVT
TPS70612DRVR
TPS70612DRVT
TPS70615DBVR
TPS70615DBVT
TPS70615DRVR
TPS70615DRVT
TPS70618DBVR
TPS70618DBVT
TPS70618DRVR
TPS70618DRVT
TPS70625DBVR
TPS70625DBVT
TPS70625DRVR
TPS70625DRVT
TPS70628DBVR
TPS70628DBVT
TPS70628DRVR
TPS70628DRVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
5
5
6
6
5
5
6
6
5
5
6
6
5
5
6
6
5
5
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
SJC
SJC
SJC
SJC
SIW
SIW
SIW
SIW
SIX
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SIX
SIX
SIX
SIY
SIY
SIY
SIY
SJU
SJU
SJU
SJU
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS70630DBVR
TPS70630DBVT
TPS70630DRVR
TPS70630DRVT
TPS70633DBVR
TPS70633DBVT
TPS70633DRVR
TPS70633DRVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
5
5
6
6
5
5
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
SIZ
SIZ
SIZ
SIZ
SJA
SJA
SJA
SJA
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS70612DBVR
TPS70612DBVT
TPS70612DRVR
TPS70612DRVT
TPS70615DBVR
TPS70615DBVT
TPS70615DRVR
TPS70615DRVT
TPS70618DBVR
TPS70618DBVT
TPS70618DRVR
TPS70618DRVR
TPS70618DRVT
TPS70618DRVT
TPS70625DBVR
TPS70625DBVT
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
WSON
WSON
SOT-23
SOT-23
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
DRV
DRV
DBV
DBV
5
5
6
6
5
5
6
6
5
5
6
6
6
6
5
5
3000
250
178.0
178.0
180.0
180.0
178.0
178.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
180.0
178.0
178.0
9.0
9.0
8.4
8.4
9.0
9.0
8.4
8.4
9.0
9.0
8.4
8.4
8.4
8.4
9.0
9.0
3.3
3.3
2.3
2.3
3.3
3.3
2.3
2.3
3.3
3.3
2.3
2.3
2.3
2.3
3.3
3.3
3.2
3.2
2.3
2.3
3.2
3.2
2.3
2.3
3.2
3.2
2.3
2.3
2.3
2.3
3.2
3.2
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q2
Q2
Q2
Q3
Q3
3000
250
1.15
1.15
1.4
3000
250
1.4
3000
250
1.15
1.15
1.4
3000
250
1.4
3000
3000
250
1.15
1.15
1.15
1.15
1.4
250
3000
250
1.4
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS70625DRVR
TPS70625DRVR
TPS70625DRVT
TPS70625DRVT
TPS70628DBVR
TPS70628DBVT
TPS70628DRVR
TPS70628DRVR
TPS70628DRVT
TPS70628DRVT
TPS70630DBVR
TPS70630DBVT
TPS70630DRVR
TPS70630DRVR
TPS70630DRVT
TPS70630DRVT
TPS70633DBVR
TPS70633DBVT
TPS70633DRVR
TPS70633DRVR
TPS70633DRVT
TPS70633DRVT
WSON
WSON
WSON
WSON
SOT-23
SOT-23
WSON
WSON
WSON
WSON
SOT-23
SOT-23
WSON
WSON
WSON
WSON
SOT-23
SOT-23
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DBV
DBV
DRV
DRV
DRV
DRV
DBV
DBV
DRV
DRV
DRV
DRV
DBV
DBV
DRV
DRV
DRV
DRV
6
6
6
6
5
5
6
6
6
6
5
5
6
6
6
6
5
5
6
6
6
6
3000
3000
250
180.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
9.0
9.0
8.4
8.4
8.4
8.4
9.0
9.0
8.4
8.4
8.4
8.4
9.0
9.0
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
3.3
3.3
2.3
2.3
2.3
2.3
3.3
3.3
2.3
2.3
2.3
2.3
3.3
3.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
3.2
3.2
2.3
2.3
2.3
2.3
3.2
3.2
2.3
2.3
2.3
2.3
3.2
3.2
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q3
Q3
Q2
Q2
Q2
Q2
Q3
Q3
Q2
Q2
Q2
Q2
Q3
Q3
Q2
Q2
Q2
Q2
250
3000
250
1.4
3000
3000
250
1.15
1.15
1.15
1.15
1.4
250
3000
250
1.4
3000
3000
250
1.15
1.15
1.15
1.15
1.4
250
3000
250
1.4
3000
3000
250
1.15
1.15
1.15
1.15
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS70612DBVR
TPS70612DBVT
TPS70612DRVR
TPS70612DRVT
TPS70615DBVR
TPS70615DBVT
TPS70615DRVR
TPS70615DRVT
TPS70618DBVR
TPS70618DBVT
TPS70618DRVR
TPS70618DRVR
TPS70618DRVT
TPS70618DRVT
TPS70625DBVR
TPS70625DBVT
TPS70625DRVR
TPS70625DRVR
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
WSON
WSON
SOT-23
SOT-23
WSON
WSON
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
DRV
DRV
DBV
DBV
DRV
DRV
5
5
6
6
5
5
6
6
5
5
6
6
6
6
5
5
6
6
3000
250
180.0
180.0
182.0
182.0
180.0
180.0
182.0
182.0
180.0
180.0
182.0
210.0
210.0
182.0
180.0
180.0
210.0
182.0
180.0
180.0
182.0
182.0
180.0
180.0
182.0
182.0
180.0
180.0
182.0
185.0
185.0
182.0
180.0
180.0
185.0
182.0
18.0
18.0
20.0
20.0
18.0
18.0
20.0
20.0
18.0
18.0
20.0
35.0
35.0
20.0
18.0
18.0
35.0
20.0
3000
250
3000
250
3000
250
3000
250
3000
3000
250
250
3000
250
3000
3000
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS70625DRVT
TPS70625DRVT
TPS70628DBVR
TPS70628DBVT
TPS70628DRVR
TPS70628DRVR
TPS70628DRVT
TPS70628DRVT
TPS70630DBVR
TPS70630DBVT
TPS70630DRVR
TPS70630DRVR
TPS70630DRVT
TPS70630DRVT
TPS70633DBVR
TPS70633DBVT
TPS70633DRVR
TPS70633DRVR
TPS70633DRVT
TPS70633DRVT
WSON
WSON
SOT-23
SOT-23
WSON
WSON
WSON
WSON
SOT-23
SOT-23
WSON
WSON
WSON
WSON
SOT-23
SOT-23
WSON
WSON
WSON
WSON
DRV
DRV
DBV
DBV
DRV
DRV
DRV
DRV
DBV
DBV
DRV
DRV
DRV
DRV
DBV
DBV
DRV
DRV
DRV
DRV
6
6
5
5
6
6
6
6
5
5
6
6
6
6
5
5
6
6
6
6
250
250
210.0
182.0
180.0
180.0
210.0
182.0
182.0
210.0
180.0
180.0
182.0
210.0
182.0
210.0
180.0
180.0
210.0
182.0
182.0
210.0
185.0
182.0
180.0
180.0
185.0
182.0
182.0
185.0
180.0
180.0
182.0
185.0
182.0
185.0
180.0
180.0
185.0
182.0
182.0
185.0
35.0
20.0
18.0
18.0
35.0
20.0
20.0
35.0
18.0
18.0
20.0
35.0
20.0
35.0
18.0
18.0
35.0
20.0
20.0
35.0
3000
250
3000
3000
250
250
3000
250
3000
3000
250
250
3000
250
3000
3000
250
250
Pack Materials-Page 4
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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