TPS65150QPWPRQ1 [TI]
具有集成 VCOM 缓冲器的汽车类、紧凑型 LCD 偏置电源 | PWP | 24 | -40 to 125;
| 型号： | TPS65150QPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成 VCOM 缓冲器的汽车类、紧凑型 LCD 偏置电源 | PWP | 24 | -40 to 125 CD 光电二极管 |
| 文件： | 总42页 (文件大小：2571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS65150-Q1
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
TPS65150-Q1 具备栅极电压整形功能和 VCOM 缓冲器的汽车 LCD 电源，
适用于源极和栅极驱动器
1 特性
2 应用
1
•
符合 AEC-Q100 标准：的顶部
•
4" 至 17"液晶 (LCD) 显示屏
–
–
器件温度 1 级：–40°C 至 125°C 结温范围
–
–
–
–
汽车信息娱乐系统和仪表板
汽车导航系统
器件人体放电模型 (HBM) 静电防护 (ESD) 分类
符合 AEC - Q100-002
后座娱乐系统
–
器件带电器件模型 (CDM) ESD 分类符合 AEC-
Q100-011
智能车镜
•
•
输入电压范围：1.8V 至 6V
V(VS) 升压转换器
3 说明
TPS65150-Q1 是一款电源，适用于汽车 LCD 应用。
该器件集成了一个针对源极电压的升压转换器以及两个
针对栅极电压并经过稳压的可调节电荷泵驱动器。为了
削减外部成本、改善图像质量并减少影像残留，该器件
采用 VCOM 缓冲器并具备栅极电压整形功能。
–
–
–
V
–
–
V
–
输出电压高达 15V
输出电压精度 < 1%
2A 开关电流限值
•
•
(VGH) 正向稳压电荷泵驱动器
输出电压高达 30 V
栅极电压整形
该器件经设计可由 1.8V 至 6V 的电源供电运行，非常
适合 使用 3.3V 或 5V 固定输入电压轨的 汽车 LCD 应
用。
(VGL) 负向稳压电荷泵驱动器
输出电压低至 -15V
VGL 和 VGH 的可调上电序列允许该器件针对各种显
示屏进行优化。
•
•
集成 VCOM 缓冲器
可调上电序列
–
外部隔离 MOSFET 的栅极驱动信号，针对
V(VS)
为了防止系统发生故障，TPS65150-Q1 集成了可调节
关断锁存功能。该器件监测输出（V(VS)、V(VGL) 和 V
(VGH)）。当其中一个输出低于其电源正常阈值的时间超
过可调节故障延迟时间后，该器件进入关断模式。
•
DRV8303 中的 特性
–
–
–
–
超出稳压范围保护
过压保护
器件信息(1)
可调故障检测时序
热关断
器件型号
封装
封装尺寸（标称值）
TPS65150-Q1
TSSOP (24)
6.40mm x 7.80mm
•
带有外露散热焊盘的 24 引脚 TSSOP 封装
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
框图
Boost
Converter
V(VS)
VI
Up to 15 V / 300 mA
1.8 V to 6.0 V
Negative
Charge Pump
V(VGL)
Down to œ15 V / 50 mA
Positive
Charge Pump
V(CPI)
Gate-Voltage
Shaping
V(VGH)
Up to 30 V / 50 mA
VCOM
Buffer
V(VCCM)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSBX4
TPS65150-Q1
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 20
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
8.3 System Examples ................................................... 30
Power Supply Recommendations...................... 33
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 34
11 器件和文档支持 ..................................................... 35
11.1 器件支持 ............................................................... 35
11.2 接收文档更新通知 ................................................. 35
11.3 社区资源................................................................ 35
11.4 商标....................................................................... 35
11.5 静电放电警告......................................................... 35
11.6 Glossary................................................................ 35
12 机械、封装和可订购信息....................................... 35
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (December 2016) to Revision C
Page
•
•
已将“符合 AEC-Q100 标准”移动到特性列表 ........................................................................................................................... 1
Changed the Electrical Characteristics conditions From: TA = –40°C to 85°C To: TA = –40°C to 125°C.............................. 6
Changes from Revision A (September 2013) to Revision B
Page
•
已添加 ESD 额定值表，特性 说明部分、器件功能模式、应用和实施部分、电源相关建议部分、布局部分、器件和文
档支持部分以及机械、封装和可订购信息部分........................................................................................................................ 1
Added specifications to the Absolute Maximum Ratings table............................................................................................... 5
已添加 Switching Characteristics ........................................................................................................................................... 7
已更改 typical characteristics graphs ..................................................................................................................................... 8
已更改 Functional Block Diagram for clarity ........................................................................................................................ 11
•
•
•
•
Changes from Original (June 2013) to Revision A
Page
•
已更改 文档状态“产品预览”至“量产数据” ................................................................................................................................ 1
2
Copyright © 2013–2017, Texas Instruments Incorporated
TPS65150-Q1
www.ti.com.cn
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
5 Pin Configuration and Functions
PWP Package
24-Pin TSSOP
Top View
FB
1
24
23
22
21
20
19
18
17
16
15
14
13
FDLY
GD
DLY1
DLY2
VIN
2
3
COMP
FBN
4
SW
5
REF
SW
6
GND
DRVN
DRVP
CPI
PGND
PGND
SUP
VCOM
IN
7
8
9
10
11
12
VGH
ADJ
FBP
CTRL
Pin Functions
PIN
I/O
DESCRIPTION
NAME
HTSSOP
Gate voltage shaping circuit. Connecting a capacitor to this pin sets the fall time of the
positive gate voltage V(VGH)
ADJ
14
I/O
.
This is the compensation pin for the main boost converter. A small capacitor and if
required a series resistor is connected to this pin.
COMP
CPI
22
16
O
I
Input of the VGH isolation switch and gate voltage shaping circuit.
Control signal for the gate voltage shaping signal. Apply the control signal for the gate
voltage control. Usually the timing controller of the LCD panel generates this signal. If this
function is not required, this pin must be connected to VI. By doing this, the internal switch
CTRL
13
I
between CPI and VGH provides isolation for the positive charge pump output V(VGH)
DLY2 sets the delay time for V(VGH) to come up.
.
Power-on sequencing adjust. Connecting a capacitor from this pin to ground allows to set
the delay time between the boost converter output V(VS) and the negative charge pump
V(VGL) during start-up.
DLY1
DLY2
2
3
I/O
I/O
Power-on sequencing adjust. Connecting a capacitor from this pin to ground allows to set
the delay time between the negative charge pump V(VGL) and the positive charge pump
during start-up. Note that Q5 in the gate voltage shaping block only turns on when the
positive charge pump is within regulation. (This provides input-output isolation of V(VGH)).
DRVN
DRVP
FB
18
17
1
I/O
Negative charge pump driver.
I/O
Positive charge pump driver.
I
I
I
Boost converter feedback sense input.
Negative charge pump feedback sense input.
Positive charge pump feedback sense input.
FBN
FBP
21
12
Fault delay. Connecting a capacitor from this pin to VI sets the delay time from the point
when one or more of the of the outputs V(VS), V(VGH), V(VGL) drops below its power good
threshold until the device shuts down. To restart the device, the input voltage must be
cycled to ground. This feature can be disabled by connecting the FDLY pin to VI.
FDLY
24
I/O
Active-low, open-drain output. This output is latched low when the boost converter output
is in regulation. This signal can be used to drive an external MOSFET to provide isolation
GD
23
I
I
for V(VS)
.
GND
IN
19
11
Analog ground.
Input of the VCOM buffer. If this pin is connected to ground, the VCOM buffer is disabled.
Power ground.
PGND
REF
7, 8
20
O
Internal reference output, typically 1.213 V.
Supply pin of the positive, negative charge pump and boost converter gate drive circuit.
This pin must be connected to the output of the main boost converter and cannot be
connected to any other voltage rail.
SUP
9
I/O
Copyright © 2013–2017, Texas Instruments Incorporated
3
TPS65150-Q1
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
SW
HTSSOP
5, 6
I
Switch pin of the boost converter.
VCOM
10
O
VCOM buffer output. Typically a 1-µF output capacitor is required on this pin.
Positive output voltage to drive the TFT gates with an adjustable fall time. This pin is
internally connected with a MOSFET switch to the positive charge pump input CPI.
VGH
15
O
I
VIN
4
This is the input voltage pin of the device.
The thermal pad must to be soldered to GND
Thermal Pad
—
4
Copyright © 2013–2017, Texas Instruments Incorporated
TPS65150-Q1
www.ti.com.cn
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
7
UNIT
V
VIN, CTRL
ADJ
22
V
VCOM, IN, DRVP, DRVN
FBN, COMP, FBP, FB, DLY1, DLY2
15
V
5.5
4
V
REF
V
Voltages on pin
VGH
30
V
FDLY
6
V
GD, SUP
15.5
20
V
SW
CPI
V
32
V
Operating junction temperature, TJ
Storage temperature, Tstg
125
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC-Q100-02
Charged-device model (CDM), per AEC-Q100-011
V(ESD)
Electrostatic discharge
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
6
UNIT
VI
Input voltage range
1.8
V
V
V(VS)
L
Output voltage range of the boost converter V(VS)
Inductor(1)
15
4.7
µH
°C
TA
Operating ambient temperature
–40
125
(1) See Typical Application for further information.
6.4 Thermal Information
TPS65150-Q1
THERMAL METRIC(1)
PWP (TSSOP)
24 PINS
40.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
20.8
18.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJB
18.2
RθJC(bot)
1.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2013–2017, Texas Instruments Incorporated
5
TPS65150-Q1
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
www.ti.com.cn
6.5 Electrical Characteristics
VI = 3.3 V, V(VS) = 10 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
Input voltage (VIN)
1.8
6
25
V
Supply current (VIN)
Device not switching
14
1.9
750
1.6
1.6
1.7
1.7
155
10
µA
mA
µA
Supply current (SUP)
Device not switching
3
Supply current (VCOM buffer)
1500
1.8
–40 °C < TA < 85 °C
–40 °C < TA < 125 °C
–40 °C < TA < 85 °C
–40 °C < TA < 125 °C
VIT–
Undervoltage lockout threshold (VIN)
Undervoltage lockout threshold (VIN)
VI falling
V
V
1.85
1.9
VIT+
VI rising
TJ rising
1.95
Thermal shutdown temperature threshold
Thermal shutdown temperature hysteresis
°C
°C
LOGIC SIGNALS
VIH
High-level input voltage (CTRL)
1.6
V
V
VIL
Low-level input voltage (CTRL)
Input current (CTRL)
0.4
0.2
IIH, IIL
CTRL = VI or GND
0.01
µA
BOOST CONVERTER
VO
Output voltage
15
1.154
1.160
100
V
V
–40 °C < TA < 85 °C
–40 °C < TA < 125 °C
1.136
1.132
1.146
1.146
10
Vref
IIB
Boost converter reference voltage (FB)
Input bias current (FB)
nA
mΩ
VO = 10 V
VO = 5 V
VO = 10 V
VO = 5 V
200
305
8
300
rDS(on)
Drain-source on-state resistance (Q1)
IDS = 500 mA
IDS = 500 mA
450
15
rDS(on)
IDS
Drain-source on-state resistance (Q2)
Ω
12
22
Drain-source current rating (Q2)
Current limit (Q1)
1
2
A
A
2.5
1
3.4
10
20
I(SW)(off)
VIT+
Off-state current (SW)
Overvoltage protection threshold (SUP)
Line regulation
V(SW) = 15 V
V(SUP) rising
VI = 1.8 V to 5 V
VI = 5 V
µA
V
16
ΔVO(ΔVI)
ΔVO(ΔIO)
IO = 1 mA
0.007
0.16
%/V
%/A
Load regulation
IO = 0 A to 400 mA
–12% of
Vref
–4% of
Vref
VIT+
Gate drive threshold (FB)(1)
V
NEGATIVE CHARGE PUMP
VO
Output voltage
–2
1.219
1.223
36
V
V
–40 °C < TA < 85 °C
–40 °C < TA < 125 °C
1.205
1.203
–36
1.213
1.213
0
V(REF)
Reference output voltage (REF)
Vref
Feedback regulation voltage (FBN)
Input bias current (FBN)
mV
nA
Ω
IIB
10
100
rDS(on)
Drain-source on-state resistance (Q4)
IDS = 20 mA
4.4
I(DRVN) = 50 mA
130
280
0.016
300
450
V(FBN) = 5% above nominal
voltage
V(DRVN)
Current sink voltage drop(2)
Load regulation
mV
I(DRVN) = 100 mA
IO = 0 mA to 20 mA
ΔVO(ΔIO)
VO = –5 V
%/mA
(1) The GD signal is latched low when the main boost converter output is within regulation. The GD signal is reset when the voltage on the
VIN pin goes below the UVLO threshold voltage.
(2) The maximum charge pump output current is half the drive current of the internal current source or sink.
6
版权 © 2013–2017, Texas Instruments Incorporated
TPS65150-Q1
www.ti.com.cn
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
Electrical Characteristics (接下页)
VI = 3.3 V, V(VS) = 10 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POSITIVE CHARGE PUMP
VO
Output voltage
CTRL = GND
CTRL = GND
CTRL = GND
IDS = 20 mA
VGH = open
30
1.238
100
V
V
Vref
IIB
Feedback regulation voltage (FBP)
Input bias current (FBP)
VGH = open
VGH = open
1.187
1.214
10
nA
Ω
rDS(on)
Drain-source on-state resistance (Q3)
1.1
I(DRVP) = 50 mA
420
900
0.07
650
V(SUP)
V(DRVP)
–
V(FBP) = 5% below nominal
voltage
Current sink voltage drop(2)
mV
I(DRVP)= 100 mA
IO = 0 mA to 20 mA
1400
ΔVO(ΔIO)
Load regulation
VO = 24 V
%/mA
GATE-VOLTAGE SHAPING
rDS(on)
I(ADJ)
VOmin
IOM
Drain-source on-state resistance (Q5)
IO = –20 mA
V(ADJ) = 20 V
V(ADJ) = 0 V
12
200
2
30
Ω
µA
V
Capacitor charge current
Minimum output voltage
Maximum output current
V(CPI) = 30 V
IO = –10 mA
160
20
240
mA
TIMING CIRCUITS DLY1, DLY2, FDLY
I(DLY1)
I(DLY2)
R(FDLY)
Drive current into delay capacitor (DLY1)
V(DLY1) = 1.213 V
V(DLY2) = 1.213 V
3
3
5
5
7
7
µA
µA
kΩ
Drive current into delay capacitor (DLY2)
Fault time delay resistor
250
450
650
GATE DRIVE (GD)
–12% of
V(SUP)
–4% of
V(SUP)
V(GD_VS)
Gate Drive Threshold
V(VS) rising
VOL
IOH
Low-level output voltage (GD)
Off-state current (GD)
IOL = 500 µA
VOH = 15 V
0.5
1
V
0.001
µA
VCOM BUFFER
V(SUP)
–
VISR
VIO
Single-ended input voltage (IN)
2.25
V
2 V
Input offset voltage (IN)
IO = 0 mA
–25
–37
25
mV
IO = ±25 mA
IO = ±50 mA
IO = ±100 mA
IO = ±150 mA
37
–77
55
ΔVO(ΔIO)
Load regulation
mV
–85
85
–110
–300
1.2
110
300
IIB
Input bias current (IN)
–30
nA
A
V(SUP) = 15 V
V(SUP) = 10 V
V(SUP) = 5 V
IOM
Maximum output current (VCOM)
0.65
0.15
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Oscillator frequency
TEST CONDITIONS
MIN
TYP
MAX
1.38
UNIT
MHz
1.02
1.2
50%
50%
Duty cycle (DRVN)
Duty cycle (DRVP)
版权 © 2013–2017, Texas Instruments Incorporated
7
TPS65150-Q1
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
www.ti.com.cn
6.7 Typical Characteristics
The typical characteristics are measured at 3.3 V
表 1. Table Of Graphs
FIGURE
图 1
Boost converter switch (Q1) current limit
Boost converter switch (Q1) rDS(on)
Boost converter rectifier (Q2) rDS(on)
Boost converter reference Voltage
Positive charge pump reference voltage
REF pin voltage
vs temperature
vs temperature
vs temperature
vs temperature
vs temperature
vs temperature
vs temperature
图 2
图 3
图 4
图 5
图 6
Oscillator frequency
图 7
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
0.30
0.25
0.20
0.15
0.10
0.05
0.00
−40
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
120
Junction Temperature (°C)
Junction Temperature (°C)
G000
G000
图 1. Boost Converter Switch (Q1) Current Limit vs
图 2. Boost Converter Switch (Q1) rDS(on) vs Temperature
Temperature
25
1.155
1.150
1.145
1.140
1.135
20
15
10
5
0
−40
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
120
Junction Temperature (°C)
Junction Temperature (°C)
G000
G000
图 3. Boost Converter Rectifier (Q2) rDS(on) vs Temperature
图 4. Boost Converter Reference Voltage vs Temperature
8
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TPS65150-Q1
www.ti.com.cn
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
1.24
1.220
1.215
1.210
1.205
1.200
1.23
1.22
1.21
1.20
1.19
1.18
−40
−20
0
20
40
60
80
100
120
−40
−20
0
20
40
60
80
100
120
Junction Temperature (°C)
Junction Temperature (°C)
G000
G000
图 5. Positive Charge Pump Reference Voltage vs
图 6. REF Pin Voltage vs Temperature
Temperature
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
−40
−20
0
20
40
60
80
100
120
Junction Temperature (°C)
G000
图 7. Oscillator Frequency vs Temperature
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TPS65150-Q1
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS65150-Q1 device is a complete bias supply for LCD displays. The device generates supply voltages for
the source driver and gate driver ICs in the display as well as generating the common plane voltage of the
display (VCOM). The device also features a gate-voltage shaping function that can be used to reduce image
sticking and improve picture quality. The use of external components to control power-up sequencing, fault
detection time, and boost converter compensation allows the device to be optimized for a variety of displays.
The device has been designed to work from input supply voltages as low as 1.8 V and is therefore ideal for use
in applications where it is supplied from fixed 2.5-V, 3.3-V, or 5-V supplies.
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7.2 Functional Block Diagram
SW
SUP
FB
œ
Sawtooth
Generator
Q2
1.146 V
+
V(VIN)
Current
Limit
&
Soft
Start
COMP
FBP
Control
Logic
&
Gate
Drivers
1.2 MHz
V(SUP)
Q1
œ
I(DRVP)
Current
Control
&
+
1.214 V
PGND
DRVP
Soft
Start
1.2 MHz
Q3
CPI
Q5
Control
Logic
FBN
Q7
VGH
V(SUP)
œ
Q6
Current
Control
&
Soft
Start
Q4
+
V(FBP) power good
UVLO
&
200 µA
DRVN
1.2 MHz
I(DRVN)
ADJ
CTRL
Boost converter soft start completed
V(FB) power good
&
VIN
GD
5 µA
5 µA
1.213 V
delay 1
DLY1
REF
References,
Control Logic,
Oscillator,
Sequencing,
Fault Detection &
Thermal Shutdown
1.213 V
1.146 V
1.2 MHz
1.213 V
delay 2
DLY2
GND
V(SUP)
Soft Start
Q11
0.69 V(VIN)
fault
œ
FDLY
VCOM
+
450 kꢀ
Q12
Disable
IN
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7.3 Feature Description
7.3.1 Boost Converter
图 8 shows a simplified block diagram of the boost converter.
L
VI
VO
CI
CO
VIN
SW
SUP
Q2
Feed-forward
signal
Current Limit
& Soft Start
To charge
pumps,
VCOM
I(SW)
buffer, etc.
Q1
Gate
Drive
1.2 MHz
Sawtooth
Generator
CFF
R1
R2
FB
œ
+
Vref = 1.146 V
COMP
RCOMP
CCOMP
Copyright © 2016, Texas Instruments Incorporated
图 8. Boost Converter Block Diagram
The boost converter uses a unique fast-response voltage-mode controller scheme with input feedforward to
achieve excellent line and load regulation, while still allowing the use of small external components. The use of
external compensation adds flexibility and allows the response of the boost converter to be optimized for a wide
range of external components.
The TPS65150-Q1 device uses a virtual-synchronous topology that allows the boost converter to operate in
continuous conduction mode (CCM) even at light loads. This is achieved by including a small MOSFET (Q2) in
parallel with the external rectifier diode. Under light-load conditions, Q2 allows the inductor current to become
negative, maintaining operation in CCM. By operating always in CCM, boost converter compensation is
simplified, ringing on the SW pin at low loads is avoided, and additional charge pump stages can be driven by
the SW pin. The boost converter duty cycle is given by 公式 1.
ꢀVI
D = 1 œ
VO
where
•
η is the boost converter efficiency (either taken from data in Application Curves or a worst-case assumption of
75%),
•
•
VI is the boost converter input supply voltage, and
VO is the boost converter output voltage.
(1)
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Feature Description (接下页)
Use 公式 2 to calculate the boost converter peak switch current.
DVI
IO
I:
=
+
;
SW M
where
•
•
•
f = 1.2 MHz (the boost converter switching frequency),
IO is the boost converter output current, and
L is the boost converter inductance.
(2)
7.3.1.1 Setting the Boost Converter Output Voltage
The boost converter output voltage is set by the R1/R2 resistor divider, and is calculated using 公式 3.
R1
VO = l1 +
p Vref
R2
where
•
Vref = 1.146 V (the boost converter internal reference voltage).
(3)
To minimize quiescent current consumption, the value of R1 should be in the range of 100 kΩ to 1 MΩ.
7.3.1.2 Boost Converter Rectifier Diode
The reverse voltage rating of the diode must be higher than the maximum output voltage of the converter, and its
average forward current rating must be higher than the output current of the boost converter. Use 公式 4 to
calculate the rectifier diode repetitive peak forward current.
IFRM = I:
;
SW M
(4)
Use 公式 5 to calculate the power dissipated in the rectifier diode.
PD = VFIO
where
•
VF is the rectifier diode forward voltage.
(5)
The main diode parameters affecting converter efficiency are its forward voltage and reverse leakage current,
and both should be as low as possible.
7.3.1.3 Choosing the Boost Converter Output Capacitance
The output capacitance of the boost converter smooths the output voltage and supplies transient output current
demands that are outside the loop bandwidth of the converter. Generally speaking, larger output currents or
smaller input supply voltages require larger output capacitances. Use 公式 6 to calculate the output voltage ripple
of the boost converter.
DIO
VO PP
=
;
:
fCO
where
•
CO is the boost converter output capacitance.
(6)
7.3.1.4 Compensation
The boost converter requires a series R-C network connected between the COMP pin and ground to
compensate its feedback loop. The COMP pin is the output of the boost converter's error amplifier, and the
compensation capacitor determines the amplifier's low-frequency gain and the resistor its high-frequency gain.
Because the converter gain changes with the input voltage, different compensation capacitors may be required:
lower input voltages require a higher gain, and therefore a smaller compensation capacitor value. If an input
supply voltage of the application changes (for example, if the TPS65150-Q1 device is supplied from a battery),
choose compensation components suitable for a supply voltage midway between the minimum and maximum
values. In all cases, verify that the values selected are suitable by performing transient tests over the full range of
operating conditions.
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Feature Description (接下页)
表 2. Recommended Compensation Components for Different Input Supply Voltages
FEED-FORWARD ZERO
CUT-OFF FREQUENCY
VI
CCOMP
RCOMP
2.5 V
3.3 V
5 V
470 pF
470 pF
2.2 nF
68 kΩ
33 kΩ
0 kΩ
8.8 kHz
7.8 kHz
11.2 kHz
A feed-forward capacitor CFF in parallel with the upper feedback resistor R1 adds an additional zero to the loop
response, which improves transient performance. 表 2 suggests suitable values for the cut-off frequency of the
feedforward zero; however, these are only guidelines. In any application, variations in input supply voltage,
inductance, and output capacitance all affect circuit operation, and the optimum value must be verified with
transient tests before being finalized.
The cut-off frequency of the feed-forward zero is determined using 公式 7.
1
fco
=
:
;
2ΠR1 CFF
where
•
fco is the cutoff frequency of the feedforward zero formed by R1 and CFF
.
(7)
7.3.1.5 Soft Start
The boost converter features a soft-start function that limits the current drawn from the input supply during start-
up. During the first 2048 switching cycles, the switch current of the boost converter is limited to 40% of its
maximum value; during the next 2048 cycles, it is limited to 60% of its maximum value; and after that it is as high
as it must be to regulate the output voltage (up to 100% of the maximum). In typical applications, this results in a
start-up time of about 5 ms (see 图 9).
100%
60%
40%
0%
t2048 cyclest
t2048 cyclest
t
图 9. Boost Converter Switch Current Limit During Soft-Start
7.3.1.6 Gate Drive Signal
The GD pin provides a signal to control an external P-channel enhancement MOSFET, allowing the output of the
boost converter to be isolated from its input when disabled (see 图 36). The GD pin is an open-drain type whose
output is latched low as soon as the output voltage of the boost converter reaches its power-good threshold. The
GD pin goes high impedance whenever the input voltage falls below the undervoltage lockout threshold or the
device shuts down as the result of a fault condition (see Adjustable Fault Delay).
7.3.2 Negative Charge Pump
图 10 shows a simplified block diagram of the negative charge pump.
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SUP
Q4
Current
Control
&
CFLY
D1
1.2 MHz
DRVN
VO
Soft
Start
D2
CO
I(DRVN)
R1
FBN
REF
+
œ
R2
+
1.213 V
œ
Copyright © 2016, Texas Instruments Incorporated
图 10. Negative Charge Pump Block Diagram
The negative charge pump operates with a fixed frequency of 1.2 MHz and a 50% duty cycle in two distinct
phases. During the charge phase, transistor Q4 is turned on, controlled current source I(DRVN) is turned off, and
flying capacitance CFLY charges up to approximately V(SUP). During the discharge phase, Q4 is turned off, I(DRVN)
is turned on, and a negative current of I(DRVN) flows through D1 to the output. The output voltage is fed back
through R1 and R2 to an error amplifier that controls I(DRVN) so that the output voltage is regulated at the correct
value.
7.3.2.1 Negative Charge Pump Output Voltage
The negative charge pump output voltage is set by resistors R1 and R2 and is given by 公式 8.
R1
VO = œ l p V(REF)
R2
where
•
V(REF) = 1.213 V (the voltage on the REF pin).
(8)
Resistor R2 should be in the range 39 kΩ to 150 kΩ. Smaller values load the REF pin too heavily and larger
values may cause stability problems.
7.3.2.2 Negative Charge Pump Flying Capacitance
The flying capacitance transfers charge from the SUP pin to the negative charge pump output. TI recommends a
flying capacitor of at least 100 nF for output currents up to 20 mA. Smaller values can be used with smaller
output currents.
7.3.2.3 Negative Charge Pump Output Capacitance
The output capacitor smooths the discontinuous current delivered by the flying capacitor to generate a DC output
voltage. In general, higher output currents require larger output capacitances. Use 公式 9 to calculate the
negative charge pump output voltage ripple.
IO
VO(PP)
=
2fCO
where
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•
•
•
IO is the negative charge pump output current,
CO is the negative charge pump output capacitance, and
f = 1.2 MHz (the negative charge pump switching frequency).
(9)
7.3.2.4 Negative Charge Pump Diodes
The average forward current of both diodes is equal to the negative charge pump output current. If the
recommended flying capacitor (or larger) is used, the repetitive peak forward current in D1 and D2 is equal to
twice the output current.
7.3.3 Positive Charge Pump
图 11 shows a simplified block diagram of the positive charge pump, which works in a similar way to the negative
charge pump except that the positions of the current source IDRVP and the MOSFET Q3 are reversed.
SUP
V(VS)
I(DRVP)
D2
Current
Control
&
CFLY
1.2 MHz
DRVP
VO
Soft
Start
D1
CO
Q3
R1
R2
FBP
œ
+
Vref = 1.214 V
Copyright © 2016, Texas Instruments Incorporated
图 11. Positive Charge Pump Block Diagram
If higher output voltages are required another charge pump stage can be added to the output, as shown in 图 34
at the end of the data sheet.
7.3.3.1 Positive Charge Pump Output Voltage
The positive charge pump output voltage is set by resistors R1 and R2 and is calculated using 公式 10.
R1
VO = l1 +
p Vref
R2
where
•
Vref = 1.214 V (the positive charge pump reference voltage).
(10)
TI recommends choosing a value for R2 not greater than 1 MΩ.
7.3.3.2 Positive Charge Pump Flying Capacitance
The flying capacitance transfers charge from the SUP pin to the charge pump output. TI recommends a flying
(1)
capacitor of at least 330 nF
currents.
for output currents up to 20 mA. Smaller values can be used with smaller output
(1) The minimum recommended flying capacitance for the positive charge pump is larger than for the negative charge pump because the
rDS(on) of Q3 is smaller than the rDS(on) of Q4.
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7.3.3.3 Positive Charge Pump Output Capacitance
The output voltage ripple of the positive charge pump is given by 公式 11.
IO
VO(PP)
=
2fCO
where
•
•
•
IO is the output current of the positive charge pump,
CO is the output capacitance of the positive charge pump, and
f = 1.2 MHz (the switching frequency of the positive charge pump).
(11)
7.3.3.4 Positive Charge Pump Diodes
The average forward current of both diodes is equal to the positive charge pump output current. If the
recommended flying capacitance (or larger) is used, the repetitive peak forward current in D1 and D2 equal to
twice the output current.
7.3.4 Power-On Sequencing, DLY1, DLY2
The boost converter starts as soon as the input supply voltage exceeds the rising UVLO threshold. The negative
charge pump starts td(DLY1) seconds after the boost converter output voltage has reached its final value, and the
positive charge pump starts td(DLY2) seconds after the output of the negative charge pump has reached its final
value. The VCOM buffer starts up as soon as the output voltage of the positive charge pump (V(CPI)) has reached
its final value.
VI
VIT+
VITœ
V(VS)
ttd(DLY1)
t
V(VGL)
See note 1
V(CPI)
ttd(DLY2)t
V(VCOM)
V(GD)
Notes
1. The fall times of V(VS), V(VGL), V(CPI) depend on their respective load currents and feedback resistances.
图 12. Start-Up Sequencing With CTRL = High
The delay times td(DLY1) and td(DLY2) are set by the capacitors connected to the DLY1 and DLY2 pins respectively.
Each of these pins is connected to its own 5-µA current source (I(DLY1) and I(DLY2)) that causes the voltage on the
external capacitor to ramp up linearly. The delay time is defined by how long it takes the voltage on the external
capacitor to reach the reference voltage, and is given by 公式 12.
CDLY2Vref
CDLY1Vref
td(DLY1)
=
and td(DLY2) =
I(DLY1)
I(DLY2)
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where
•
•
•
Vref = 1.213 V (the internal reference voltage),
I(DLY1) = 5 µA (the DLY1 pin output current), and
I(DLY2) = 5 µA (the DLY2 pin output current).
(12)
7.3.5 Gate Voltage Shaping
The gate voltage shaping function can be used to reduce crosstalk between LCD pixels by reducing the gate
drivers’ input supply voltage between lines. 图 13 shows a simplified block diagram of the gate voltage shaping
function. Gate voltage shaping is controlled by a logic-level signal applied to the CTRL pin. When CTRL is high,
Q5 and Q7 are on and Q6 is off, and the output of the positive charge pump is connected to the VGH pin. When
CTRL is low, Q5 and Q7 are off and Q6 is on. Q6 operates as a source follower and tracks the voltage on the
ADJ pin, which ramps down linearly as the current sink I(ADJ) discharges the external capacitor CADJ (see 图 14).
The peak-to-peak voltage on the VGH pin is determined by the value of CADJ and the duration of the low level
applied to the CTRL pin, and is calculated using 公式 13.
I(ADJ) w(CTRL)
t
V(VGH)(PP)
=
CADJ
where
•
•
•
I(ADJ) = 200 µA (ADJ pin output current),
tw(CTRL) is the duration of the low-level signal connected to the CTRL pin, and
CADJ is the capacitance connected to the ADJ pin.
(13)
When the input supply voltage is below the UVLO threshold or the device enters a shutdown condition because
of a fault on one or more of its outputs, Q5 and Q6 turn off and the VGH pin is high impedance.
CPI
Q5
Q7
VGH
Control
Logic
I(ADJ) = 200 µA
Q6
&
V(VIN) > VIT
V(FBP) power good
CTRL
ADJ
CADJ
Copyright © 2016, Texas Instruments Incorporated
图 13. Gate Voltage Shaping Block Diagram
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ttw(CTRL)
t
CTRL
V(CPI)
V(VGH)
V(VGH)(PP)
图 14. Gate Voltage Shaping Timing
7.3.6 VCOM Buffer
The VCOM Buffer is a transconductance amplifier designed to drive capacitive loads. The IN pin is the input of
the VCOM buffer. The VCOM buffer features a soft-start function that reduces the current drawn from the SUP
pin when the amplifier starts up.
If the VCOM buffer is not required for certain applications, it is possible to shut down the VCOM buffer by
connecting IN to ground, reducing the overall quiescent current. The IN pin cannot be pulled dynamically to
ground during operation.
7.3.7 Protection
7.3.7.1 Boost Converter Overvoltage Protection
The boost converter features an overvoltage protection function that monitors the voltage on the SUP pin and
forces the TPS65150-Q1 device to enter fault mode if the boost converter output voltage exceeds the
overvoltage threshold.
7.3.7.2 Adjustable Fault Delay
The TPS65150-Q1 device detects a fault condition and shuts down if the boost converter output or either of the
charge pump outputs falls out of regulation for longer than the fault delay time td(FDLY). Fault conditions are
detected by comparing the voltage on the feedback pins with the internal power-good thresholds. Outputs that
fall below their power-good threshold but recover within less than td(FDLY) seconds are not detected as faults and
the device does not shut down in such cases. The output fault detection function is active during start-up, so the
device shuts down if any of its outputs fails to reach its power-good threshold during start-up. Shut-down
following an output voltage fault is a latched condition, and the input supply voltage must be cycled to recover
normal operation after it occurs.
The fault detection delay time is set by the capacitor connected between the FDLY and VIN pins and is given by
公式 14.
td(FDLY) = R(FDLY)CFDLY
where
•
•
R(FDLY) = 450 kΩ (the internal resistance connected to the FDLY pin) and
CFDLY is the external capacitance connected to the FDLY pin.
(14)
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1
100m
10m
1m
Minimum
Typical
Maximum
100u
1n
10n
100n
1u
Capacitance Connected to FDLY Pin (F)
G000
图 15. Adjustable Fault Delay Time
7.3.7.3 Thermal Shutdown
A thermal shutdown is implemented to prevent damage because of excessive heat and power dissipation.
Typically, the thermal shutdown threshold is 155°C. When this threshold is reached, the device enters shutdown.
The device can be enabled again by cycling the input supply voltage.
7.3.7.4 Undervoltage Lockout
The TPS65150-Q1 device has an undervoltage lockout (UVLO) function. The UVLO function stops device
operation if the voltage on the VIN pin is less than the UVLO threshold voltage. This makes sure that the device
only operates when the supply voltage is high enough for correct operation.
7.4 Device Functional Modes
图 16 shows the functional modes of the TPS65150-Q1.
7.4.1 VI > VIT+
When the input supply voltage is above the undervoltage lockout threshold, the device is on and all its functions
are enabled. Note that full performance may not be available until the input supply voltage exceeds the minimum
value specified in Recommended Operating Conditions.
7.4.2 VI < VIT–
When the input supply voltage is below the undervoltage lockout threshold, the TPS65150-Q1 device is off and
all its functions are disabled.
7.4.3 Fault Mode
The TPS65150-Q1 device immediately enters fault mode when any of the following is detected:
•
•
boost converter overvoltage
overtemperature
The TPS65150-Q1 device also enters fault mode if any of the following conditions is detected and persists for
longer than td(FDLY)
:
•
•
•
boost converter output out of regulation
negative charge pump output out of regulation
positive charge pump output out of regulation
The TPS65150-Q1 device does not function during fault mode. Cycle the input supply voltage to exit fault mode
and recover normal operation.
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Device Functional Modes (接下页)
VI < VITœ
!bò
{Ç!Ç9
hCC
VI > VIT+
hb
Boost converter out of regulation
Negative charge pump out of regulation
Positive charge pump out of regulation
Thermal shutdown
Boost converter over-voltage
Fault condition duration
less than td(FDLY)
Fault condition duration
longer than td(FDLY)
C!Ü[Ç
59Ç9/ÇLhb
C!Ü[Ç
图 16. Functional Modes
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS65150-Q1 device has been designed to provide the input supply voltages for the source drivers and
gate drivers plus the voltage for the common plane in LCD display applications. In addition, the device provides a
gate voltage shaping function that can be used to modulate the gate drivers' positive supply to reduce image
sticking.
8.2 Typical Application
图 17 shows a typical application circuit for a monitor display powered from a 5-V supply. It generates up to
450 mA at 13.5 V to power the source drivers, and 20 mA at 23 V and –5 V to power the gate drivers.
L1
3.9 µH
C2
22 µF
C15
22 pF
D1
VI
V(VS)
5 V
13.5 V, 450 mA
C1
22 µF
R1
820 kꢀ
VIN
SW
SUP
FB
C7
330 nF
C14
1 µF
D2
R2
75 kꢀ
DRVN
V(VGL)
œ5 V, 20 mA
C3
330 nF
D3
C16
330 nF
R3
620 kꢀ
D4
D5
C4
330 nF
DRVP
FBP
FBN
R4
150 kꢀ
R5
1 Mꢀ
REF
C8
220 nF
C13 100 nF
C9 2.2 nF
C10 22 pF
C11 10 nF
C12 10 nF
VI
FDLY
COMP
R6
56 kꢀ
CPI
GD
ADJ
DLY1
DLY2
FLK
CTRL
IN
VGH
V(VGH)
23 V, 20 mA
R7
500 kꢀ
V(VS)
VCOM
V(VCOM)
R8
500 kꢀ
C6
1 nF
C5
1 µF
PGND
GND
Copyright © 2016, Texas Instruments Incorporated
图 17. Monitor LCD Supply Powered from a 5-V Rail
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Typical Application (接下页)
8.2.1 Design Requirements
表 3 shows the parameters for this example.
表 3. Design Parameters
PARAMETER
Input supply voltage
VALUE
5 V
VI
V(VS)
V(VS)(PP)
V(CPI)
Boost converter output voltage and current
13.5 V at 450 mA
10 mV
Boost converter peak-to-peak output voltage ripple
Positive charge pump output voltage and current
23 V at 20 mA
100 mV
V(VGH)(PP) Positive charge pump peak-to-peak output voltage ripple
V(VGL)
V(VGL)(PP)
td1
Negative charge pump output voltage and current
Negative charge pump peak-to-peak output voltage ripple
Negative charge pump start-up delay time
Positive charge pump start-up delay time
Fault delay time
–5 V at 20 mA
100 mV
1 ms
td2
1 ms
td(fault)
45 ms
Gate voltage shaping slope
10 V/µs
8.2.2 Detailed Design Procedure
8.2.2.1 Boost Converter Design Procedure
8.2.2.1.1 Inductor Selection
Several inductors work with the TPS65150-Q1, and with external compensation the performance can be adjusted
to the specific application requirements.
The main parameter for the inductor selection is the inductor saturation current, which must be higher than the
peak switch current as calculated in 公式 2 with additional margin to cover for heavy load transients. The
alternative, more conservative approach, is to choose the inductor with a saturation current at least as high as
the maximum switch current limit of 3.4 A.
The second important parameter is the inductor DC resistance. Usually, the lower the DC resistance the higher
the efficiency. It is important to note that the inductor DC resistance is not the only parameter determining the
efficiency. For a boost converter, where the inductor is the energy storage element, the type and material of the
inductor influences the efficiency as well. Especially at a switching frequency of 1.2 MHz, inductor core losses,
proximity effects, and skin effects become more important. Usually, an inductor with a larger form factor gives
higher efficiency. The efficiency difference between different inductors can vary from 2% to 10%. For the
TPS65150-Q1, inductor values from 3.3 µH and 6.8 µH are a good choice, but other values can be used as well.
Possible inductors are shown in 表 4. Equivalent parts can also be used.
表 4. Inductor Selection(1)
INDUCTANCE
4.7 µH
ISAT
DCR
MANUFACTURER
Coilcraft
PART NUMBER
DO1813P-472HC
CDRH5D28-4R2
CDC5D23-4R7
DIMENSIONS
2.6 A
2.2 A
1.6 A
1.8 A
2.6 A
1.9 A
54 mΩ
23 mΩ
48 mΩ
60 mΩ
20 mΩ
50 mΩ
8.89 mm × 6.1 mm × 5 mm
5.7 mm × 5.7 mm × 3 mm
6 mm × 6 mm × 2.5 mm
6.5 mm × 6.5 mm × 1.5 mm
7 mm × 7 mm × 3 mm
4.2 µH
Sumida
4.7 µH
Sumida
4.2 µH
Sumida
CDRH6D12-4R2
CDRH6D28-3R9
CDRH6D12-3R3
3.9 µH
Sumida
3.3 µH
Sumida
6.5 mm × 6.5 mm × 1.5 mm
(1) See Third-party Products disclaimer
版权 © 2013–2017, Texas Instruments Incorporated
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The first step in the design procedure is to verify whether the maximum possible output current of the boost
converter supports the specific application requirements. A simple approach is to estimate the converter
efficiency, by taking the efficiency numbers from the provided efficiency curves, or use a worst case assumption
for the expected efficiency, for example, 75%.
From 图 19, it can be seen that the boost converter efficiency is about 85% when operating under the target
application conditions. Inserting these values into 公式 1 yields 公式 15.
:
;:
;
0.85 5 V
D = 1 œ
= 0.69
13.5 V
(15)
and from 公式 2, the peak switch current can be calculated as 公式 16.
;:
:
;
:
;
0.69 5 V
0.45 A
I(SW)M
=
+
= 1.8 A
:
;:
;
2 1.2 MHz 3.9 ꢀH
1 œ 0.69
(16)
The peak switch current is the peak current that the integrated switch, inductor, and rectifier diode must be able
to handle. The calculation must be done for the minimum input voltage where the peak switch current is highest.
For the calculation of the maximum current delivered by the boost converter, it must be considered that the
positive and negative charge pumps as well as the VCOM buffer run from the output of the boost converter as
well.
8.2.2.2 Rectifier Diode Selection
The rectifier diode reverse voltage rating must be higher than the maximum output voltage of the converter
(13.5 V in this application); its average forward current rating must be higher than the maximum boost converter
output current of 450 mA, and its repetitive peak forward current must be greater than or equal to the peak
switch current of 1.8 A. Not all diode manufacturers specify repetitive peak forward current; however, a diode
with an average forward current rating of 1 A or higher is suitable for most practical applications.
From 公式 5, the power dissipated in the rectifier diode is calculated with 公式 17.
:
;:
;
PD = IOVF = 0.45 A 0.5 V = 0.225 W
(17)
表 5 lists a number of suitable rectifier diodes, any of which would be suitable for this application. Equivalent
parts can also be used.
表 5. Rectifier Diode Selection(1)
IF(AV)
2 A
2 A
1 A
1 A
1 A
VR
VF
MANUFACTURER
Vishay Semiconductor
Fairchild Semiconductor
Fairchild Semiconductor
Microsemi
PART NUMBER
SL22
20 V
20 V
30 V
20 V
20 V
0.44 V at 2 A
0.5 V at 2 A
0.44 V at 2 A
0.45 V at 1 A
0.45 V at 1 A
SS22
MBRS130L
UPS120
ON Semiconductor
MBRM120
(1) See Third-party Products disclaimer.
8.2.2.3 Setting the Output Voltage
Rearranging 公式 3 and inserting the application parameters yields 公式 18.
R1 13.5 V
=
œ 1 = 10.78
R2 1.146 V
(18)
Standard values of R1 = 820 kΩ and R2 = 75 kΩ result in a nominal output voltage of 13.68 V and satisfy the
recommendation that the value R1 be lower than 1 MΩ.
8.2.2.4 Output Capacitor Selection
For best output voltage filtering, a low ESR output capacitor is recommended. Ceramic capacitors have a low
ESR value, but tantalum capacitors can be used as well, depending on the application. A 22-µF ceramic output
capacitor works for most applications. Higher capacitor values can be used to improve the load transient
regulation. See 表 6 for the selection of the output capacitor.
24
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TPS65150-Q1
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ZHCSBL3C –JUNE 2013–REVISED MAY 2017
Rearranging 公式 6 and inserting the application parameters, the minimum value of output capacitance is given
by 公式 19.
1 œ 0.69
;:
13.5 V œ 5 V 1 œ 0.69
m1.8 A œ 0.45 A œ l p l
;
1.2 MHz
CO =
pq = 20.3 ꢀF
:
1.2 MHz 10 mV
3.9 ꢀH
(19)
The closest standard value is 22 µF. In practice, TI recommends connecting an additional 1-µF capacitor directly
to the SUP pin to ensure a clean supply to the internal circuitry that runs from this supply voltage.
8.2.2.5 Input Capacitor Selection
For good input voltage filtering, low ESR ceramic capacitors are recommended. A 22-µF ceramic input capacitor
is sufficient for most applications. For better input voltage filtering, this value can be increased. See 表 6 for input
capacitor recommendations. Equivalent parts can also be used.
表 6. Input and Output Capacitance Selection
CAPACITANCE
22 µF
VOLTAGE RATING
MANUFACTURER
Taiyo Yuden
PART NUMBER
EMK325BY226MM
JMK316BJ226
SIZE
1206
1206
16 V
22 µF
6.3 V
Taiyo Yuden
8.2.2.6 Compensation
From 表 2, it can be seen that the recommended values for C9 and R9 when VI = 5 V are 2.2 nF and 0 Ω
respectively, and that a feedforward zero at 11.2 kHz must be added.
Rearranging 公式 7 yields 公式 20.
1
C15 =
:
;
2Œfco R1
(20)
Inserting fco = 11.2 kHz and R1 = 820 kΩ yields .
1
C15 =
= 17 pF
:
;: ;
2Œ 11.2 kHz 820 kꢀ
In this case, a standard value of 22 pF was used.
8.2.2.7 Negative Charge Pump
8.2.2.7.1 Choosing the Output Capacitance
Rearranging 公式 9 and inserting the application parameters, the minimum recommended value of C3 is given by
公式 21.
IO
20 mA
: ;: ;
2 1.2 MHz 100 mV
C3 =
=
= 83 nF
2fVO PP
:
;
(21)
In this application, a capacitor of 330 nF was used to allow the same value to be used for all charge pump
capacitors.
8.2.2.7.2 Choosing the Flying Capacitance
A minimum flying capacitance of 100 nF is recommended. In this application, a capacitor of 330 nF was used to
allow the same value to be used for all charge pump capacitors.
8.2.2.7.3 Choosing the Feedback Resistors
The ratio of R3 to R4 required to generate an output voltage of –5 V is given by 公式 22.
VO
œ5 V
: ;
p R4 = 4.122 R4
R3 = œ F
G R4 = œ l
V(REF)
1.213 V
(22)
Values of R3 = 620 kΩ and R4 = 150 kΩ generate a nominal output voltage of –5.014 V and load the REF pin
with only 8 µA.
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8.2.2.7.4 Choosing the Diodes
The average forward current in D2 and D3 is equal to the output current and therefore a maximum of 20 mA. The
peak repetitive forward current in D2 and D3 is equal to twice the output current and therefore less than 40 mA.
The BAT54S comprises two Schottky diodes in a small SOT-23 package and easily meets the current
requirements of this application.
8.2.2.8 Positive Charge Pump
8.2.2.8.1 Choosing the Flying Capacitance
A minimum flying capacitor of 330 nF is recommended.
8.2.2.8.2 Choosing the Output Capacitance
Rearranging 公式 10 and inserting the application parameters yields 公式 23.
:
;
20 mA
C4 =
= 83 nF
:
;:
;
2 1.2 MHz 100 mV
(23)
In this application, a nominal value of 330 nF was used to allow the same value to be used for all charge pump
capacitors.
8.2.2.8.3 Choosing the Feedback Resistors
Rearranging 公式 8 and inserting the application parameters yields 公式 24.
R5
23 V
=
œ 1 = 17.95
R6 1.214 V
(24)
Standard values of 1 MΩ and 56 kΩ result in a nominal output voltage of 22.89 V.
8.2.2.8.4 Choosing the Diodes
The average forward current in D4 and D5 is equal to the output current and therefore a maximum of 20 mA. The
peak repetitive forward current in D4 and D5 is equal to twice the output current and therefore less than 40 mA.
8.2.2.9 Gate Voltage Shaping
Rearranging 公式 13 and inserting I(ADJ) = 200 µA and slope = 10 V/µs yields 公式 25.
I:
200 ꢀA
;
ADJ
C10 =
=
= 20 pF
slope 10 V/ꢀs
(25)
(26)
The closest standard value for C10 is 22 pF.
8.2.2.10 Power-On Sequencing
Rearranging 公式 12 and inserting td1 = td2 = 1 ms and Vref2 = 1.213 V, yields 公式 26.
:
;:
;
5 ꢀA 2.5 ms
C11 = C12 =
= 10.31 nF
1.213 V
10 nF is the closest standard value.
8.2.2.11 Fault Delay
Rearranging 公式 14 and inserting td(FDLY) = 45 ms yields 公式 27.
45 ms
CFDLY
=
= 100 nF
450 kꢀ
(27)
100 nF is a standard value.
26
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8.2.3 Application Curves
100
100
90
80
70
60
50
40
30
20
10
0
V
(VS)
= 10 V
V
(VS)
= 13.5 V
90
80
70
60
50
40
30
20
10
0
VI = 2.5 V
VI = 3.3 V
VI = 5 V
VI = 2.5 V
VI = 3.3 V
VI = 5 V
0
100m 200m 300m 400m 500m 600m 700m
0
100m
200m
300m
400m
500m
Output Current (A)
Output Current (A)
G000
G000
I(VGH) = 0 mA
I(VGL) = 0 mA
I(VGH) = 0 mA
I(VGL) = 0 mA
图 18. Boost Converter Efficiency (V(VS) = 10 V, I(VGH)
=
图 19. Boost Converter Efficiency (V(VS) = 13.5 V, I(VGH)
=
I(VGL) = 0 mA)
I(VGL) = 0 mA)
100
90
80
70
60
50
40
30
20
10
0
1.155M
1.15M
V
(VS)
= 15 V
V
(VS)
= 13.5 V
1.145M
1.14M
1.135M
1.13M
VI = 2.5 V
VI = 3.3 V
VI = 5 V
1.125M
1.12M
VI = 1.8 V
VI = 3.6 V
−40
−20
0
20
40
60
80
100
120
0
50m
100m
150m
200m
250m
300m
Free−Air Temperature (°C)
Output Current (A)
G000
G000
I(VGH) = 0 mA
I(VGL) = 0 mA
图 21. Boost Converter Switching Frequency
图 20. Boost Converter Efficiency (V(VS) = 15 V, I(VGH)
=
I(VGL) = 0 mA)
V(SW)
V(SW)
10 V/div
10 V/div
V(VS)
V(VS)
50 mV/div
50 mV/div
VI = 5 V
V(VS) = 13.5 V / 10 mA
IL
1 A/div
IL
VI = 5 V
1 A/div
V(VS) = 13.5 V / 300 mA
250 ns/div
250 ns/div
图 23. Boost Converter Operation (Light Load)
图 22. Boost Converter Operation (Nominal Load)
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ZHCSBL3C –JUNE 2013–REVISED MAY 2017
www.ti.com.cn
V(VS)
VI
100 mV/div
5 V/div
VI = 3.3 V
V(VS) = 10 V, CO = 22 µF
V(VS)
5 V/div
I(VS)
30 mA to 330 mA
VI = 5 V
I
IN
V(VS) = 13.5 V
I(VS) = 200 mA
500 mA/div
100 µs/div
图 24. Boost Converter Load Transient Response
2.5 ms/div
图 25. Boost Converter Soft Start
V(VS)
V(VS)
5 V/div
5 V/div
V(VGH)
V(VGH)
10 V/div
10 V/div
V(VGL)
V(VGL)
5 V/div
5 V/div
VI = 5 V
V(VCOM)
5 V/div
V(VCOM)
2 V/div
V(VS) = 13.6 V / 300 mA
C(IN) = 1 nF
1 ms/div
图 26. Power-On Sequencing
2.5 ms/div
图 27. Power-On Sequencing With External Isolation
MOSFET
V(VS)
5 V/div
V(VGH)
CTRL
2 V/div
10 V/div
td(FDLY)
V(VGH)
10 V/div
Fault
(Heavy load on V(VS)
)
V(VGL)
5 V/div
CADJ = 68 pF
I(VGH) = No Load
CFDLY = 10 nF
2.5 µs/div
图 28. Gate Voltage Shaping
10 ms/div
图 29. Adjustable Fault Detection Time
28
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TPS65150-Q1
www.ti.com.cn
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
−4.86
−4.88
−4.90
−4.92
−4.94
−4.96
−4.98
−5.00
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
V
V
= 10 V
= –5 V
V
V
= 15 V
= 24 V
(VGH)
(VS)
(VS)
(VGL)
TA = –40°C
TA = 25°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = 85°C
−5.02
0
20m
40m
60m
80m
100m
0
20m
40m
60m
80m
100m
Output Current (A)
Output Current (A)
G000
G000
图 30. Negative Charge Pump Load Regulation
图 31. Positive Charge Pump Load Regulation (×2)
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
80m
60m
40m
20m
0
V
V
= 10 V
= 24 V
V
V
= 10 V
= 5 V
(VS)
(VS)
(VCOM)
(VGH)
−20m
−40m
−60m
−80m
TA = –40°C
TA = 25°C
TA = 85°C
0
20m
40m
60m
80m
100m
−160m −120m −80m −40m
0
40m 80m 120m 160m
Output Current (A)
Output Current (A)
G000
G000
图 32. Positive Charge Pump Load Regulation (×3)
图 33. VCOM Buffer Load Regulation
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TPS65150-Q1
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
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8.3 System Examples
V(SW)
L1
C2
22 µF
C15
47 pF
3.9 µH
D1
VI
V(VS)
2.5 V
10 V, 280 mA
C1
22 µF
R1
430 kꢀ
VIN
SW
SUP
FB
C14
1 µF
C7
330 nF
D2
R2
56 kꢀ
V(VGL)
œ5 V, 20 mA
DRVN
C3
D3
330 nF
C16
330 nF
R3
620 kꢀ
D4
D5
C17
330 nF
DRVP
FBP
FBN
D6
D7
C18
C4
R4
150 kꢀ
R5
1 Mꢀ
330 nF
330 nF
V(SW)
REF
C8
220 nF
C13 100 nF
C9 470 pF
C10 22 pF
C11 10 nF
C12 10 nF
VI
FDLY
COMP
R6
56 kꢀ
R9
68 kꢀ
CPI
GD
ADJ
DLY1
DLY2
V(VGH)
23 V, 20 mA
FLK
V(VS)
CTRL
IN
VGH
R7
500 kꢀ
VCOM
V(VCOM)
R8
500 kꢀ
C6
1 nF
C5
1 µF
PGND
GND
Copyright © 2016, Texas Instruments Incorporated
图 34. Notebook LCD Supply Powered from a 2.5-V Rail
30
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TPS65150-Q1
www.ti.com.cn
ZHCSBL3C –JUNE 2013–REVISED MAY 2017
System Examples (接下页)
L1
3.9 µH
C2
22 µF
C15
22 pF
D1
VI
V(VS)
5 V
13.5 V, 450 mA
C1
22 µF
R1
820 kꢀ
VIN
SW
SUP
FB
C7
330 nF
C14
1 µF
D2
R2
75 kꢀ
DRVN
V(VGL)
œ5 V, 20 mA
C3
D3
330 nF
C16
330 nF
R3
620 kꢀ
D4
D5
DRVP
FBP
FBN
C4
R4
150 kꢀ
R5
1 Mꢀ
330 nF
REF
C8
220 nF
C13 100 nF
C9 2.2 nF
C10 22 pF
C11 10 nF
C12 10 nF
VI
FDLY
COMP
R6
56 kꢀ
CPI
GD
ADJ
DLY1
DLY2
FLK
CTRL
IN
VGH
V(VGH)
23 V, 20 mA
R7
500 kꢀ
V(VS)
VCOM
V(VCOM)
R8
500 kꢀ
C6
1 nF
C5
1 µF
PGND
GND
Copyright © 2016, Texas Instruments Incorporated
图 35. Monitor LCD Supply Powered from a 5-V Rail
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31
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ZHCSBL3C –JUNE 2013–REVISED MAY 2017
www.ti.com.cn
System Examples (接下页)
Q1
Si2343
L1
3.9 µH
C2
22 µF
C15
22 pF
C17
220 nF
C13
1 µF
D1
VI
V(VS)
5 V
13.5 V, 450 mA
C1
22 µF
R1
820 kꢀ
R7
510 kꢀ
VIN
SW
SUP
FB
R8
100 kꢀ
C7
330 nF
C14
1 µF
D2
R2
75 kꢀ
V(VGL)
DRVN
œ5 V, 20 mA
C3
D3
330 nF
C16
330 nF
R3
620 kꢀ
D4
D5
DRVP
FBP
FBN
C4
R4
150 kꢀ
R5
1 Mꢀ
330 nF
REF
C8
220 nF
C13 100 nF
C9 2.2 nF
C10 22 pF
C11 10 nF
C12 10 nF
VI
FDLY
COMP
R6
56 kꢀ
CPI
GD
ADJ
DLY1
DLY2
V(VGH)
23 V, 20 mA
FLK
CTRL
IN
VGH
R7
500 kꢀ
V(VS)
VCOM
V(VCOM)
R8
500 kꢀ
C6
1 nF
C5
1 µF
PGND
GND
Copyright © 2016, Texas Instruments Incorporated
图 36. Typical Isolation and Short Circuit Protection Switch for V(VS) Using Q1 and Gate Drive Signal (GD)
32
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TPS65150-Q1
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ZHCSBL3C –JUNE 2013–REVISED MAY 2017
9 Power Supply Recommendations
The TPS65150-Q1 device is designed to operate with input supplies from 1.8 V to 6 V. Like most integrated
circuits, the input supply must be stable and free of noise if the full performance of the device is to be achieved. If
the input is placed more than a few centimeters away from the device, additional bulk capacitance may be
required. The input capacitance shown in the application schematics in this data sheet is sufficient for typical
applications.
10 Layout
10.1 Layout Guidelines
The PCB layout is an important step in the power supply design. An incorrect layout could cause converter
instability, load regulation problems, noise, and EMI issues. Especially with a switching DC-DC converter at high
load currents, too-thin PCB traces can cause significant voltage spikes. Good grounding is also important. If
possible, TI recommends using a common ground plane to minimize ground shifts between analog ground
(GND) and power ground (PGND). Additionally, the following PCB design layout guidelines are recommended for
the TPS65150-Q1 device:
1. Boost converter output capacitor, input capacitor and Power ground (PGND) must form a star ground or must
be directly connected together on a common power ground plane.
2. Place the input capacitor directly from the input pin (VIN) to ground.
3. Use a bold PCB trace to connect SUP to the output Vs.
4. Place a small bypass capacitor from the SUP pin to ground.
5. Use short traces for the charge-pump drive pins (DRVN, DRVP) of VGH and VGL because these traces
carry switching currents.
6. Place the charge pump flying capacitors as close as possible to the DRVP and DRVN pin, avoiding a high
voltage spikes at these pins.
7. Place the Schottky diodes as close as possible to the device and to the flying capacitors connected to DRVP
and DRVN.
8. Carefully route the charge pump traces to avoid interference with other circuits because they carry high
voltage switching currents .
9. Place the output capacitor of the VCOM buffer as close as possible to the output pin (VCOM).
10. The thermal pad must be soldered to the PCB for correct thermal performance.
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ZHCSBL3C –JUNE 2013–REVISED MAY 2017
www.ti.com.cn
10.2 Layout Example
VI
GND
FB
FDLY
GD
DLY1
DLY2 COMP
VIN
SW
SW
FBN
REF
GND
PGND DRVN
PGND DRVP
V(VGL)
SUP
VCOM
IN
CPI
VGH
ADJ
V(VGH)
GND
FBP
CTRL
V(CPI)
V(VCOM)
V(VS)
GND
Via to inner / bottom signal layer
Thermal via to copper pour on inner / bottom signal layer
图 37. PCB Layout Example
34
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ZHCSBL3C –JUNE 2013–REVISED MAY 2017
11 器件和文档支持
11.1 器件支持
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 接收文档更新通知
要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可
收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
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35
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65150QPWPRQ1
ACTIVE
HTSSOP
PWP
24
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS65150Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65150QPWPRQ1 HTSSOP PWP
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 24
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPS65150QPWPRQ1
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
PWP 24
4.4 x 7.6, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224742/B
www.ti.com
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