TPS62861 [TI]
具有 I2C/VSEL 接口的 1.75V 至 5.5V 输入、1A 超低 IQ 降压转换器;
| 型号： | TPS62861 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C/VSEL 接口的 1.75V 至 5.5V 输入、1A 超低 IQ 降压转换器 转换器 |
| 文件： | 总35页 (文件大小：2217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS62860, TPS62861
ZHCSL99E –SEPTEMBER 2019 –REVISED APRIL 2023
TPS6286x 具有I2C/VSEL 接口的
1.75V 至5.5V 输入、0.6A/1A 同步降压转换器
1 特性
3 说明
• 2.3μA 工作静态电流
TPS6286x 器件是具有 I2C 接口和 VSEL 接口的高频
• 开关频率高达4MHz
• 1% 的输出电压精度
同步降压转换器。这些器件提供了高效、灵活和具有高
功率密度的负载点直流/直流解决方案。该转换器在中
高负载条件下以PWM 模式运行，并在轻负载时自动进
入省电运行模式，从而在整个负载电流范围内保持高效
率。该器件还可强制进入PWM 运行模式，以实现最小
输出电压纹波。凭借其 DCS-Control 架构，这些器件
可实现出色的负载瞬态性能并符合严格的输出电压精度
要求。通过 I2C 接口和专用 VSEL 引脚，可快速调整
输出电压，使负载的功耗适应相关应用不断变化的性能
需求。该器件系列提供两个 VSEL 引脚和四个出厂预
设电压，支持在没有I2C 接口的情况下使用。
• DVS 输出为0.4V 至1.9875V（阶跃为12.5mV）
• 通过I2C 用户接口进行调节
– 输出电压预设
– 斜坡速度
• 在运行期间通过VSEL 引脚来切换VOUT
• 电源正常指示
• 支持小于6mm² 的解决方案尺寸
• 支持小于0.6mm 的解决方案高度
• 微型8 引脚0.35mm 间距WCSP 封装
• 经过优化的引脚排列，可支持0201 元件
器件信息
封装尺寸（标称
封装(1)
2 应用
器件型号
电流
值）
• 可穿戴电子产品
• 便携式电子产品
• 手机
TPS628610
TPS628601
TPS628600
TPS628602
TPS628603
1A
0.6A
0.6A
0.6A
0.6A
YCH
（DSBGA，8）
0.70mm × 1.40mm
× 0.40mm
• 医疗传感器贴片和患者监护仪
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
TPS628610
100
VIN
1.75V – 5.5V
0.47µH
VOUT
VIN
SW
95
90
85
80
75
70
65
60
55
50
10
F
4.7
F
GND
VOS
EN
SDA
SCL
VSEL
TPS628601/2
VIN
1.75V – 5.5V
1.0µH
VOUT
VIN
SW
10
F
4.7
F
GND
VOS
EN
PG
VSEL-1
VSEL-2
TPS628601
TPS628610
45
40
10m
100m
1m
10m
100m
1
Load Current [A]
典型应用
效率与IOUT（1.1VOUT、3.8VIN）间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDU8
TPS62860, TPS62861
ZHCSL99E –SEPTEMBER 2019 –REVISED APRIL 2023
www.ti.com.cn
Table of Contents
8.4 Programming............................................................ 15
8.5 Register Map.............................................................18
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Application, TPS628610............................... 21
9.3 Typical Application, TPS628600, TPS62860x.......... 27
9.4 Power Supply Recommendations.............................28
9.5 Layout....................................................................... 28
10 Device and Documentation Support..........................29
10.1 Device Support....................................................... 29
10.2 接收文档更新通知................................................... 29
10.3 支持资源..................................................................29
10.4 Trademarks.............................................................29
10.5 静电放电警告.......................................................... 29
10.6 术语表..................................................................... 29
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................7
7.6 I2C Interface Timing Characteristics........................... 8
7.7 Typical Characteristics..............................................10
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (May 2022) to Revision E (April 2023)
Page
• 向数据表添加了 TPS628603.............................................................................................................................. 1
• 更新了商标信息.................................................................................................................................................. 1
• Updated the ESD Ratings CDM row to show testing was per JS-002................................................................5
• Added table note to the Thermal Information table.............................................................................................5
Changes from Revision C (March 2022) to Revision D (May 2022)
Page
• Corrected the internal fixed soft-start time test condition....................................................................................5
Changes from Revision B (September 2020) to Revision C (March 2022)
Page
• 向数据表添加了 TPS628602.............................................................................................................................. 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSDU8
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ZHCSL99E –SEPTEMBER 2019 –REVISED APRIL 2023
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5 Device Comparison Table
ORDERABLE PART NUMBER OUTPUT CURRENT
DEFAULT VO SETTING
0.6 V, 1.1 V
fSW
USER INTERFACE
EN, I2C, VSEL
TPS628600YCH
TPS628601YCH
TPS628610YCH
TPS628602YCH
TPS628603YCH
0.6 A
0.6 A
1 A
1.5 MHz
1.5 MHz
4 MHz
0.6 V, 0.7 V, 0.8 V, 1.0 V
0.6 V, 1.1 V
2x VSEL, EN, PG
EN, I2C, VSEL
0.6 A
0.6 A
1.05 V, 0.9 V, 0.875 V, 0.625 V
1.5 MHz
2x VSEL, EN, PG
1.05 V, 0.65 V
1.5 MHz
EN, I2C, VSEL
6 Pin Configuration and Functions
1
2
A
B
C
D
图6-1. 8-Pin DSBGA YCH Package (Top View)
表6-1. Pin Functions, TPS628610 and TPS628600/03
PIN
I/O
DESCRIPTION
NAME
NO.
GND
D2
PWR
GND supply pin. Connect this pin close to the GND terminal of the input and output capacitor.
Output voltage sense pin for the internal feedback divider network and regulation loop. This pin also
discharges VOUT by an internal MOSFET when the converter is disabled. Connect this pin directly to the
output capacitor with a short trace.
VOS
D1
IN
VIN power supply pin. Connect the input capacitor close to this pin for best noise and voltage spike
suppression. A ceramic capacitor is required.
VIN
SW
C2
C1
PWR
PWR
The switch pin is connected to the internal MOSFET switches. Connect the inductor to this terminal.
Voltage Selection Pin. Can be toggled during operation. LOW = 0.6 V(TPS628600/10), 1.05
V(TPS628603), HIGH = 1.1 V(TPS628600/10), 0.65 V(TPS628603)
VSEL
EN
B2
B1
IN
IN
A high level enables the devices and a low level turns the device off. The pin features an internal
pulldown resistor, which is disabled after the device has started up.
SDA
SCL
A2
A1
IN
IN
I2C serial data pin. Do not leave floating.
I2C serial clock pin. Do not leave floating.
表6-2. Pin Functions, TPS628601, TPS628602
DESCRIPTION
PIN
I/O
NAME
NO.
GND
D2
PWR
GND supply pin. Connect this pin close to the GND terminal of the input and output capacitor.
Output voltage sense pin for the internal feedback divider network and regulation loop. This pin also
discharges VOUT by an internal MOSFET when the converter is disabled. Connect this pin directly to
the output capacitor with a short trace.
VOS
VIN
D1
C2
IN
VIN power supply pin. Connect the input capacitor close to this pin for best noise and voltage spike
suppression. A ceramic capacitor is required.
PWR
SW
PG
C1
B2
PWR
OUT
The switch pin is connected to the internal MOSFET switches. Connect the inductor to this terminal.
Open-drain power-good output
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Product Folder Links: TPS62860 TPS62861
English Data Sheet: SLUSDU8
TPS62860, TPS62861
ZHCSL99E –SEPTEMBER 2019 –REVISED APRIL 2023
www.ti.com.cn
表6-2. Pin Functions, TPS628601, TPS628602 (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
A high level enables the devices and a low level turns the device off. The pin features an internal
pulldown resistor, which is disabled after the device has started up.
EN
B1
IN
VSEL-1
VSEL-2
A2
A1
IN
IN
Voltage Selection Pin. Can be toggled during operation.
Voltage Selection Pin. Can be toggled during operation.
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English Data Sheet: SLUSDU8
TPS62860, TPS62861
ZHCSL99E –SEPTEMBER 2019 –REVISED APRIL 2023
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–2.5
–0.3
–0.3
–40
–55
MAX
UNIT
V
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
TJ
VIN
6
SW, DC
VIN +0.3V
V
SW, transient < 10 ns, while switching
EN, VSEL, SDA, SCL, PG
VOS
9
6
V
V
5
V
Operating junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001 (1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002 (2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
1.75
0.4
0
NOM
MAX
5.5
UNIT
V
VIN
Input supply voltage range
Output voltage range
VOUT
1.9875
5.5
V
Pin voltage
SW
V
Pin voltage
EN, SDA, SCL, VSEL, PG
TPS628610, VIN > 2.3V
TPS628610, VIN <= 2.3V
TPS628601
0
5.5
V
IOUT
IOUT
IOUT
IPG
Output current range
1
A
Output current range
0.7
A
Output current range
0.6
A
Power Good input current capability
Operating junction temperature
Effective Input Capacitance
Effective Inductance
1
mA
°C
µF
µH
µF
µH
µF
TJ
-40
2
125
CIN
L
4.7
0.33
2
0.47
0.82
26
TPS628610
TPS628601
COUT
L
Effective Output Capacitance
Effective Inductance
0.7
3
1.0
1.2
26
COUT
Effective Output Capacitance
7.4 Thermal Information
DEVICE
THERMAL METRIC(1)
YCH (DSBGA)
8 PINs
121.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
1.1
33.7
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English Data Sheet: SLUSDU8
TPS62860, TPS62861
ZHCSL99E –SEPTEMBER 2019 –REVISED APRIL 2023
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UNIT
DEVICE
YCH (DSBGA)
8 PINs
THERMAL METRIC(1)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.7
°C/W
°C/W
ψJT
ψJB
33.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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English Data Sheet: SLUSDU8
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7.5 Electrical Characteristics
TJ = –40°C to +125°C, VIN = 3.6 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
EN = VIN, IOUT = 0μA, VOUT = 1.2 V
device not switching, TJ = -40°C to +85°C
IQ(VIN)
VIN quiescent current
2.3
2.5
4
µA
µA
nA
EN = VIN, IOUT = 0μA, VOUT = 1.2 V,
device switching
EN = GND, shutdown current into VIN
VSEL/MODE = GND, TJ = -40°C to +85°C
ISD(VIN)
VIN shutdown supply current
120
250
UVLO
VUVLO(R)
VUVLO(F)
VUVLO(H)
LOGIC PINs
VIH
VIN UVLO rising threshold
VIN UVLO falling threshold
VIN UVLO hysteresis
VIN rising
VIN falling
1.65
1.56
100
1.75
1.7
V
V
mV
High-level input voltage threshold
Low-level input voltage threshold
0.8
V
V
VIL
0.4
25
ILKG
Input leakage current into SDA, SCL, VSEL Pin connected to VIN
10
0.5
10
nA
MΩ
nA
EN internal pull-down resistance
Input Leakage into EN
EN pin to GND
ILKG
Pin connected to VIN
25
VOUT VOLTAGE
VOUT
Output Voltage Accuracy
Output Voltage Accuracy
PWM Mode, no load, TJ = 25°C to 85°C
PWM Mode, no load, TJ = -40°C to 125°C
-1
-2
+1
%
%
VOUT
+1.7
EN = VIN, VOUT = 1.2 V (internal 12MΩ
resistor divider),
IVOS(LKG)
VOS input leakage current
100
400
nA
TJ = -40°C to +85°C
SWITCHING FREQUENCY
fSW(FCCM)
fSW(FCCM)
STARTUP
Switching frequency, TPS62861x
VIN = 3.6V, VOUT =1.2V, PWM operation
VIN = 3.6V, VOUT =1.2V, PWM operation
4
MHz
MHz
Switching frequency, TPS62860x
1.5
Internal fixed soft-start time
from VOUT = 0V to 95% of VOUT nominal
0.125
500
0.2
ms
µs
EN HIGH to start of switching delay
1000
POWER STAGE
RDSON(HS)
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
IOUT = 500 mA
IOUT = 500 mA
120
80
170
115
mΩ
mΩ
RDSON(LS)
OVERCURRENT PROTECTION
IHS(OC)
High-side peak current limit
TPS628610
1.3
1.2
1.45
1.35
1.1
1.55
1.45
1.2
A
A
A
A
A
ILS(OC)
Low-side valley current limit
High-side peak current limit
Low-side valley current limit
Low-side negative current limit
TPS628610
IHS(OC)
TPS628601
0.95
0.85
ILS(OC)
TPS628601
1.0
1.1
ILS(NOC)
POWER GOOD
VPGTH
Sinking current limit on LS FET
0.8
Power Good threshold
PGOOD low, VOS falling
PGOOD high, VOS rising
PG rising edge
93%
96%
16
VPGTH
Power Good threshold
tPG:DLY
Power good deglitch delay
Input leakage current into PG-pin
PG-pin output low-level voltage
µs
nA
mV
IPG;LKG
VPG = 5.0V
10
100
400
IPG = 1mA
OUTPUT DISCHARGE
EN = GND, IVOS = –10 mA into VOS pin
TJ = -40°C to +85°C
Output discharge resistor on VOS pin
7
11
Ω
THERMAL SHUTDOWN
TJ(SD)
Thermal shutdown threshold (1)
Temperature rising, PWM Mode
160
°C
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English Data Sheet: SLUSDU8
TPS62860, TPS62861
ZHCSL99E –SEPTEMBER 2019 –REVISED APRIL 2023
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TJ = –40°C to +125°C, VIN = 3.6 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TJ(HYS)
Thermal shutdown hysteresis (1)
20
°C
(1) Specified by design. Not production tested.
7.6 I2C Interface Timing Characteristics
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
100
400
1
UNIT
kHz
kHz
MHz
µs
Standard mode
fSCL
SCL Clock Frequency
Fast mode
Fast mode plus
Standard mode
Fast mode
4.7
1.3
0.5
4
Bus Free Time Between a STOP and
START Condition
tBUF
µs
Fast mode plus
Standard mode
Fast mode
µs
µs
tHD, tSTA Hold Time (Repeated) START condition
600
260
4.7
1.3
0.5
4
ns
Fast mode plus
Standard mode
Fast mode
ns
µs
tLOW
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
µs
Fast mode plus
Standard mode
Fast mode
µs
µs
tHIGH
600
260
4.7
600
260
250
100
50
ns
Fast mode plus
Standard mode
Fast mode
ns
µs
Setup Time for a Repeated START
Condition
tSU, tSTA
ns
Fast mode plus
Standard mode
Fast mode
ns
ns
tSU, tDAT Data Setup Time
tHD, tDAT Data Hold Time
ns
Fast mode plus
Standard mode
Fast mode
ns
0
3.45
0.9
µs
0
µs
Fast mode plus
Standard mode
0
µs
1000
300
ns
20+0.1C
B
tRCL
Rise Time of SCL Signal
Fast mode
ns
ns
ns
Fast mode plus
Standard mode
120
20+0.1C
B
1000
Rise Time of SCL Signal After a
Repeated START Condition and After an
Acknowledge BIT
tRCL1
20+0.1C
B
Fast mode
300
120
300
ns
ns
ns
Fast mode plus
Standard mode
20+0.1C
B
tFCL
Fall Time of SCL Signal
Rise Time of SDA Signal
Fast mode
300
120
ns
ns
ns
Fast mode plus
Standard mode
1000
20+0.1C
B
tRDA
Fast mode
300
120
ns
ns
Fast mode plus
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English Data Sheet: SLUSDU8
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PARAMETER(1)
TEST CONDITIONS
Standard mode
MIN
TYP
MAX
UNIT
300
ns
20+0.1C
B
tFDA
Fall Time of SDA Signal
Fast mode
300
120
ns
Fast mode plus
Standard mode
Fast mode
ns
µs
ns
ns
pF
pF
pF
4
600
260
tSU, tSTO Setup Time of STOP Condition
Fast mode plus
Standard mode
Fast mode
400
400
550
CB
Capacitive Load for SDA and SCL
Fast mode plus
(1) All values referred to VIL MAX and VIH MIN levels in ELECTRICAL CHARACTERISTICS table.
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English Data Sheet: SLUSDU8
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7.7 Typical Characteristics
400
5
4.5
4
TJ = -40°C
375
TJ = 0°C
350
TJ = +25°C
TJ = +85°C
325
300
275
250
225
200
175
150
125
100
75
TJ = +125°C
3.5
3
2.5
2
1.5
1
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
50
0.5
0
25
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Input Voltage [V]
Input Voltage [V]
Device not switching
EN = GND
EN = VIN
图7-1. Shutdown Current ISD
图7-2. Quiescent Current IQ
350
200
TJ = -40°C
TJ = -10°C
TJ = 30°C
TJ = 85°C
TJ = 125°C
TJ = -40°C
TJ = -10°C
TJ = 30°C
TJ = 85°C
TJ = 125°C
325
300
275
250
225
200
175
150
125
100
75
175
150
125
100
75
50
50
25
25
0
0
1.5
2
2.5
3
3.5
VIN [V]
4
4.5
5
5.5
1.5
2
2.5
3
3.5
VIN [V]
4
4.5
5
5.5
图7-3. High-side Switch Drain Source Resistance 图7-4. Low-side Switch Drain Source Resistance
RDS(ON)
RDS(ON)
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8 Detailed Description
8.1 Overview
The TPS6286x is a high-frequency synchronous step-down converter with ultra-low quiescent current
consumption and flexible output voltage by I²C or VSEL interface. Using TI's DCS-Control topology, the device
extends the high efficiency operation area down to microamperes of load current during Power Save Mode
Operation. TI's DCS-Control (direct control with seamless transition into power save mode) is an advanced
regulation topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of
DCS-Control are excellent AC load regulation and transient response, low output ripple voltage, and a seamless
transition between PFM and PWM mode operation. DCS-Control includes an AC loop which senses the output
voltage (VOS pin) and directly feeds the information to a fast comparator stage. This comparator sets the
switching frequency, which is constant for steady state operating conditions, and provides immediate response
to dynamic load changes. To achieve accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
8.2 Functional Block Diagram
VIN
PG
VI
HS Limit
Device Control
& Logic
Power Control
EN
SW
Power Save Mode
Forced PWM
Gate
Driver
Smart-Enable
Ref-System
100% Mode
UVLO
Start-up Handling
PG-Control
Thermal Shutdown
User Interface
DVS
SDA
/VSEL-1
SCL
/VSEL-2
LS Limit
VO
Direct
Control
VI
VOS
TON mer
VFB
–
VO
+
Device
Control
VREF
DCS-Control
GND
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device enters Power Save Mode (PSM) operation. PSM occurs when the
inductor current becomes discontinuous, which is when it reaches 0 A during a switching cycle. In Power Save
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Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized by increasing
the output capacitor or inductor value.
8.3.2 Forced PWM Operation
Through I2C, set the device in forced PWM (FPWM) mode by the CONTROL register. The device switches
continuously, even with a light load. This reduces the output voltage ripple and allows simple filtering of the
switching frequency for noise-sensitive applications. Efficiency at light load is lower in FPWM mode.
8.3.3 Smart Enable and Shutdown (EN)
An internal 500-kΩ resistor pulls the EN pin to GND and avoids the pin to be floating. This prevents an
uncontrolled start-up of the device in case the EN pin cannot be driven to low level safely. With EN low, the
device is in shutdown mode. The device is turned on with EN set to a high level. The pulldown control circuit
disconnects the pulldown resistor on the EN pin after the internal control logic and the reference have been
powered up. With EN set to a low level, the device enters shutdown mode and the pulldown resistor is activated
again.
8.3.4 Soft Start
After the device has been enabled with EN high, it initializes and powers up its internal circuits. This occurs
during the regulator start-up delay time, tDelay. After tDelay expires, the internal soft-start circuitry ramps up the
output voltage within the soft-start time, tRamp. See 图8-1.
VIN
EN
VOUT
ttDelay
t
ttRamp
ttStartupt
t
图8-1. Start-up Sequence
8.3.5 Output Voltage Selection (VSEL) for TPS62860x
The optional VSEL Interface allows setting the output voltage by a 2-pin HIGH/LOW setting. Using and applying
a digital pattern to the "VSEL-1" and "VSEL-2" pins sets the output voltage according to 表8-1.
表8-1. Target Output Voltage Setting by VSEL Interface
VSEL-2
VSEL-1
TPS628601
TPS628602
OPERATION MODE
PFM Mode
0
0
1
1
0
1
0
1
0.6 V
1.05 V
0.7 V
0.9 V
PFM Mode
0.8 V
0.875 V
0.625 V
PFM Mode
1.0 V
PFM Mode
8.3.6 Output Voltage Selection (VSEL and I2C) for TPS628610
The TPS628610 has two options to select the output voltage.
It can be changed by the VSEL pin. Putting this pin "HIGH" selects the output voltage according to VOUT register
2. Putting this pin "LOW" selects the voltage according to VOUT Register 1. The pin can be toggled during
operation.
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It can also be selected by the value in the VOUT register that is chosen by VSEL at the moment. The voltage
changes right after the I2C command is received.
8.3.7 Forced PWM Mode During Output Voltage Change
In normal operation, the device does not force PWM operation during VOUT change after VSEL toggle or I2C
command. For ramping down, this mode provides the remaining energy, stored in the output capacitor to the
load of the DC/DC and save battery charge. See 图9-14.
Through I2C, the device can be set to forced PWM (FPWM) switching during output voltage change. This allows
a controlled ramp of VOUT up and especially down, regardless of the load condition. See 图9-15.
This feature follows the internal I2C ramp and is only recommended for the setting 1 mV/µs and 0.1 mV/µs.
During the faster slopes (10 mV/µs and 5 mV/µs), the mode is likely to be left before the voltage reached the
new target value.
8.3.8 Undervoltage Lockout (UVLO)
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) comparator monitors
the supply voltage. The UVLO comparator shuts down the device at an input voltage of 1.7 V (max) with falling
VIN. The device starts at an input voltage of 1.8 V (max) rising VIN. After the device re-enters operation out of an
undervoltage lockout condition, it behaves like being enabled.
8.3.9 Power Good (PG)
The TPS6286x has a built-in Power-Good (PG) feature to indicate whether the output voltage has reached its
target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails or to indicate
any overload behavior on the output. The PG pin is an open-drain output that requires a pullup resistor to any
voltage up to the recommended input voltage level. PG is low when the device is turned off due to EN or thermal
shutdown. VIN must remain present for the PG pin to stay LOW. When applying VIN the first time, PG stays
HIGH until the first enabling of the device.
If the power-good output is not used, it is recommended to tie to GND or leave open.
表8-2. Power Good Indicator Functional Table
LOGIC SIGNALS
PG STATUS
THERMAL
SHUTDOWN
DVS TRANSITION
ACTIVE
VI
EN-PIN
VO
NO
High Impedance
LOW
VO on target
NO
YES
HIGH
VI > UVLO
VI < UVLO
VO < target
x
x
x
x
LOW
YES
x
x
x
LOW
LOW
x
x
x
LOW
Undefined
The PG indicator triggers immediately (after internal comparator delay) when Vo crosses the lower VPGTH to
indicate that the voltage has left the target setting. It features a delay after crossing the upper VPGTH when going
high to make sure Vo has reached the target again. 图8-2 sketches the behavior.
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VO
VPGTH
VPGTH
PG-delay
PG
图8-2. Power Good Transient and De-glitch Behavior
The PG Indicator is by default pulled low during DVS transition of the output voltage without any blanking or
delay time. 图 8-2 shows an example of this behavior. After Vo has reached the new target, the PG is again
active as shown in 图8-2.
8.3.10 Switch Current Limit and Short Circuit Protection
The TPS6286x integrates a current limit on the high-side and low-side MOSFETs to protect the converter against
overload or short-circuit conditions. The current in the switches is monitored cycle by cycle. If the high-side
MOSFET current limit, ILIMF, trips, the high-side MOSFET is turned off and the low-side MOSFET is turned on to
ramp down the inductor current. After the inductor current through the low-side switch decreases below the low-
side MOSFET current limit, ILIMF, the low-side MOSFET is turned off and the high-side MOSFET turns on again.
8.3.11 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds the
thermal shutdown temperature TSD of 160°C (typ), the device enters thermal shutdown. Both the high-side and
low-side power FETs are turned off. When TJ decreases below the hysteresis amount of typically 20°C, the
converter resumes operation, beginning with a soft start to the originally set VOUT. The thermal shutdown is not
active in Power Save Mode.
8.3.12 Output Voltage Discharge
The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage when the
device is disabled and to keep the output voltage close to 0 V. The output discharge feature is only active once
the device has been enabled at least once since the supply voltage was applied. The output discharge function
is not active if the device is disabled and the supply voltage is applied the first time. The internal discharge
resistor is connected to the VOS pin. The discharge function is enabled as soon as the device is disabled. The
minimum supply voltage required to keep the discharge function active is VI > VTH_UVLO-
.
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8.4 Programming
8.4.1 Serial Interface Description
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification, Version .6, 2014). The bus consists of a data line (SDA) and a clock line (SCL) with pullup
structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect
to the I2C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital
signal processor, controls the bus. The master is responsible for generating the SCL signal and device
addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A
slave device receives, transmits data, or both on the bus under control of the master device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1 Mbps). The interface
adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending
on the instantaneous application requirements. Register contents remain intact as long as the input voltage
remains above 1.8 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different and must not be used.
It is recommended that the I2C master initiates a STOP condition on the I2C bus after the initial power up of SDA
and SCL pullup voltages to ensure reset of the I2C engine.
8.4.2 Standard- and Fast-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图 8-3. All I2C-compatible devices recognize a
start condition.
DATA
CLK
S
P
START Condition
STOP Condition
图8-3. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see 图 8-4). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see 图 8-5) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with
a slave has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
图8-4. Bit Transfer on the Serial Interface
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver must acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see 图 8-3). This action releases the bus and stops the communication link with
the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and the devices wait for a start condition followed by a
matching address.
Attempting to read data from register addresses not listed in this section results in 00h being read out.
图8-5. Acknowledge on the I2C Bus
图8-6. Bus Protocol
8.4.3 I2C Update Sequence
The requires the following:
• A start condition
• A valid I2C address
• A register address byte
• A data byte for a single update
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After the receipt of each byte, the device acknowledges by pulling the SDA line low during the high period of a
single clock pulse. A valid I2C address selects the device. The device performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
8
1
7
1
1
8
1
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A/A
P
—0“ Write
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
From Master to Slave
From Slave to Master
Sr = REPEATED START condition
P = STOP condition
图8-7. “Write”Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
8
1
7
1
1
8
1
1
7
1
1
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
—0“ Write
—1“ Read
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
From Master to Slave
From Slave to Master
Sr = REPEATED START condition
P = STOP condition
图8-8. “Read”Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
8.4.4 I2C Register Reset
The I2C registers can be reset by the following:
• Pull the input voltage below 1.8 V (typ).
• A high to low transition on EN. The previous value of the "Enable Output Discharge" bit is latched until the
next EN rising edge or pulling the input voltage below 1.0 V (typ).
• Set the Reset bit in the CONTROL register. When Reset is set to 1, all registers are reset to the default
values and a new start-up begins immediately. After tDelay, the I2C registers can be programmed again.
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8.5 Register Map
表8-3. Register Map
REGISTER ADDRESS
REGISTER NAME
(HEX)
FACTORY DEFAULT
(HEX)
DESCRIPTION
Sets the target output voltage
0x01
0x02
0x03
0x05
VOUT Register 1
VOUT Register 2
0x10
0x38
Sets the target output voltage
CONTROL Register
STATUS Register
Sets miscellaneous configuration bits
Returns status flags, cleared on read-out
0x00
8.5.1 Slave Address Byte
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
R/W
The slave address byte is the first byte received following the START condition from the master device. The 7-bit
slave address is 0x40 and internally set.
8.5.2 Register Address Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master sends a byte to the device,
which contains the address of the register to be accessed.
8.5.3 VOUT Register 1
表8-4. VOUT Register 1 Description
REGISTER ADDRESS 0X01 READ/WRITE
BIT
FIELD
VALUE (HEX)
OUTPUT VOLTAGE (TYP)
6:0
VO1_SET
0x00
0x01
...
0.400 V
0.4125 V
0x10
0.600 V (default value for TPS628600/
TPS628610)
...
0x34
...
1.05 V (default value for TPS628603)
0x7E
0x7F
1.975 V
1.9875 V
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8.5.4 VOUT Register 2
表8-5. VOUT Register 2 Description
REGISTER ADDRESS 0X02 READ/WRITE
BIT
FIELD
VALUE (HEX)
OUTPUT VOLTAGE (TYP)
7
Operation Mode
VO2_SET
0x00
0 - Keep PFM/PWM selection as in
CONTROL-Register
1 - sets the device in PWM operation for this
Voltage selection
6:0
0x00
0x01
...
0.400 V
0.4125 V
0x14
...
0.65 V (default value for TPS628603)
0x38
1.10 V (default value for TPS628600 and
TPS628610)
...
0x7E
0x7F
1.975 V
1.9875 V
8.5.5 CONTROL Register
表8-6. CONTROL Register Description
REGISTER ADDRESS 0X03 READ/WRITE
BIT
FIELD
TYPE
DEFAULT DESCRIPTION
7
Reset
W
0
1 - Reset all registers to default.
This bit triggers a shutdown followed by a re-reading of the
internal OTP settings and a new soft start.
6
5
Enable FPWM Mode during Output
Voltage Change
R/W
R/W
1
1
0 - Keep the current mode status during output voltage change.
1 - Force the device in FPWM during output voltage change.
Software Enable Device
0 - Disable the device. All registers values are still kept.
1 - Re-enable the device with a new start-up without the tDelay
period.
4
3
Enable FPWM Mode
R/W
R/W
0
1
0 - Set the device in power save mode at light loads.
1 - Set the device in forced PWM mode at light loads.
Enable Output Discharge
0 - Disable output discharge.
1 - Enable output discharge.
This setting is used for the next disable cycle (Software or
Hardware).
2
Reserved
0:1
Voltage Ramp Speed
R/W
11(1)
00 - 10mV/µs
01 - 5 mV/µs
10 - 1 mV/µs
11 - 0.1 mV/µs
(1) The default value is programmed with 00 for TPS628603
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8.5.6 STATUS Register
表8-7. STATUS Register Description
REGISTER ADDRESS 0X05 READ ONLY(1)
BIT
7:5
4
FIELD
TYPE
DEFAULT DESCRIPTION
Reserved
Thermal Shutdown Tripped
R
0
0
1: Thermal Shutdown has tripped since the last reading.
0: No Thermal Shutdown event occurred during the last reading.
3
2
Reserved
Power Bad
R
1: Output voltage is or was below 0.95xVO
0: No Power Bad event occurred since last reading
1:0
Reserved
(1) All bit values are latched until the device is reset, or the STATUS register is read. Then, the STATUS register is reset to its default
values.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application, TPS628610
TPS628610
VIN
1.75V – 5.5V
VOUT
0.47µH
0.4V – 1.9V
VIN
SW
10
F
4.7
F
GND
VOS
EN
SDA
SCL
VSEL
图9-1. TPS628610, Typical Application
9.2.1 Design Requirements
表9-1 shows the list of components for the application circuit and the characteristic application curves.
表9-1. Components for Application Characteristic Curves
REFERENCE
DESCRIPTION
VALUE
SIZE [L x W X T]
MANUFACTURER(1)
TPS628610
Step down converter, 1 A
1.4 mm × 0.70 mm × 0.4 mm max.
Texas Instruments
Ceramic capacitor,
GRM155R60J475ME47D
CIN
4.7 µF
0402 (1 mm × 0.5 mm × 0.6 mm max.)
Murata
Ceramic capacitor,
GRM155R60J106ME15D
COUT
L
10 µF
0402 (1 mm × 0.5 mm × 0.65 mm max.)
0603 (1.6 mm × 0.8 mm × 1.0 mm max.)
Murata
Murata
Inductor DFE18SANR47MG0L
0.47 µH
(1) See Third-party Products Disclaimer.
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9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage
ripple, and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The
inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN or VOUT and can be
estimated according to 方程式1.
方程式 2 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor must be rated higher than the maximum inductor current, as calculated with 方程式 2. This is
recommended because during a heavy load transient the inductor current rises above the calculated value. A
more conservative way is to select the inductor saturation current according to the high side MOSFET switch
current limit, ILIMF
.
Vout
Vin
1-
DIL = Vout ´
L ´ ¦
(1)
(2)
DI
L
I
= I
+
Lmax
outmax
2
where
• f = Switching frequency
• L = Inductor value
• ΔIL= Peak-to-peak inductor ripple current
• ILmax = Maximum inductor current
表9-2 shows a list of possible inductors.
表9-2. List of Possible Inductors
SIZE IMPERIAL
(METRIC)
INDUCTANCE [µH]
INDUCTOR SERIES
DIMENSIONS L × W × T
SUPPLIER(1)
0.47
0.47
0.47
0.47
DFE18SAN_G0
HTEB16080F
0603 (1608)
0603 (1608)
0402 (1005)
0603 (1608)
1.6 mm × 0.8 mm × 1.0 mm max
1.6 mm × 0.8 mm × 0.6 mm max.
1.0 mm × 0.5 mm × 0.65 mm max.
1.6 mm × 0.8 mm × 0.8 mm max.
Murata
Cyntec
Cyntec
TDK
HTET1005FE
TFM160808ALC
(1) See Third-party Products Disclaimer
9.2.2.2 Output Capacitor Selection
The DCS-Control scheme of the TPS6286x allows the use of tiny ceramic capacitors. Ceramic capacitors with
low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires
either an X7R or X5R dielectric. At light-load currents, the converter operates in power save mode and the
output voltage ripple is dependent on the output capacitor value. A larger output capacitors can be used
reducing the output voltage ripple.
The inductor and output capacitor together provide a low-pass filter. 表 9-3 outlines possible inductor and
capacitor value combinations to simplify this process.
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DEVICE
表9-3. Recommended LC Output Filter Combinations
NOMINAL OUTPUT CAPACITOR VALUE (µF)
NOMINAL INDUCTOR VALUE
(µH)
4.7 µF
√
10 µF
2 x 10 µF
22 µF
√
0.47(1)
1.0(2)
(3)
TPS628610
TPS62860x
√
√
√
(3)
√
√
√
(1) An effective inductance range of 0.33 µH to 0.82 µH is recommended. An effective capacitance range of 2 µF to 26 µF is
recommended.
(2) An effective inductance range of 0.7 µH to 1.2 µH is recommended. An effective capacitance range of 3 µF to 26 µF is recommended.
(3) Typical application configuration. Other check marks indicate alternative filter combinations.
9.2.2.3 Input Capacitor Selection
Because the buck converter has a pulsating input current, a low ESR ceramic input capacitor is required for best
input voltage filtering to minimize input voltage spikes. For most applications, a 4.7-µF input capacitor is
sufficient. When operating from a high-impedance source (such as a coin cell) a larger input buffer capacitor
≥10 µF is recommended to avoid voltage drops during start-up and load transients. The input capacitance can
be increased without any limit for better input voltage filtering. The leakage current of the input capacitor adds to
the overall current consumption.
表9-4 shows a selection of input and output capacitors.
表9-4. Capacitor Options
SIZE IMPERIAL
(METRIC)
SUPPLIER(1)
CAPACITOR PART NUMBER
DIMENSIONS L × W × T
CAPACITANCE [μF]
4.7
4.7
10
GRM155R60J475ME47D
GRM035R60J475ME15
GRM155R60J106ME15D
0402 (1005)
0201 (0603)
0402 (1005)
1.0 mm × 0.5 mm × 0.6 mm max.
0.6 mm × 0.3 mm × 0.55 mm max
1.0 mm × 0.5 mm × 0.65 mm max.
Murata
Murata
Murata
(1) See Third-party Products Disclaimer
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9.2.3 Application Curves
VIN = 3.8 V, VOUT = 1.1 V, TA = 25°C, unless otherwise noted
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
55
50
45
40
55
VIN = 1.8V
VIN = 1.8V
50
45
40
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
10m
100m
1m
10m
100m
1
10m
100m
1m
10m
100m
1
Load Current [A]
Auto Power Save Mode
Load Current [A]
VOUT = 1.1 V
VOUT = 0.6 V Auto Power Save Mode
图9-2. Efficiency
图9-3. Efficiency
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
60
55
50
45
40
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
10m
100m
1m
10m
100m
1
10m
100m
1m
10m
100m
1
Load Current [A]
Load Current [A]
Auto Power Save Mode
VOUT = 1.9875 V
Auto Power Save Mode
VOUT = 0.4 V
图9-4. Efficiency
图9-5. Efficiency
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
0
0
1m
10m
100m
1
1m
10m
100m
1
Load Current [A]
Load Current [A]
VOUT = 1.1 V
Forced PWM Operation
VOUT = 0.6 V
Forced PWM operation
图9-6. Efficiency, Inductor Comparison
图9-7. Efficiency
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4
1M
100k
10k
1k
3
2
1
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
100
1m
10m
100m
1m
10m
100m
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
Load Current [A]
Load Current [A]
Auto Power Save Mode
VOUT = 1.1 V
VOUT = 1.1 V
图9-9. Switching Frequency
图9-8. Switching Frequency
IOUT = 500 mA
VSEL = HIGH
VSEL = HIGH
图9-11. PWM-Mode Operation
图9-10. PFM Mode Operation
5mV/µs
5mV/µs
10mV/µs
10mV/µs
1mV/µs
1mV/µs
0.1mV/µs
Default voltage setting
Default voltage setting
图9-13. DVS by VSEL, Different Ramp Speed
图9-12. DVS by VSEL, Different Ramp Speed
Settings
Settings
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IL
IL
Power Save Mode is active
Power Save Mode is active
图9-15. FPWM-Mode During VOUT Change Enabled
图9-14. Standard Operation: VOUT Change
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9.3 Typical Application, TPS628600, TPS62860x
TPS628600
VIN
1.75V – 5.5V
VOUT
0.4V – 1.9V
1µH
VIN
SW
10
F
4.7
F
GND
VOS
EN
SDA
SCL
VSEL
图9-16. TPS628600, Typical Application
TPS628601/2
1.0µH
VIN
1.75V – 5.5V
VOUT
VIN
SW
10
F
4.7
F
GND
VOS
EN
PG
VSEL-1
VSEL-2
图9-17. TPS62860x, Typical Application
9.3.1 Design Requirements
表9-5 shows the list of components for the application circuit and the characteristic application curves.
表9-5. Components for Application Characteristic Curves
REFERENCE
DESCRIPTION
VALUE
SIZE [L × W × T]
MANUFACTURER(1)
TPS628610
Step down converter, 1 A
1.4 mm × 0.70 mm × 0.4 mm max.
Texas Instruments
Ceramic capacitor,
GRM155R60J475ME47D
CIN
4.7 µF
0402 (1 mm × 0.5 mm × 0.6 mm max.)
Murata
Ceramic capacitor,
GRM155R60J106ME15D
COUT
L
10 µF
1 µH
0402 (1 mm × 0.5 mm × 0.65 mm max.)
0805 (2.0 mm × 1.6 mm × 1.0 mm max.)
Murata
Murata
Inductor DFE201610E
(1) See Third-party Products Disclaimer.
9.3.2 Detailed Design Procedure
See 节9.2.2.
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9.3.3 Application Curves
95
90
85
80
75
70
65
60
55
50
45
40
95
90
85
80
75
70
65
60
55
50
45
40
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
VIN = 1.8V
VIN = 2.5V
VIN = 3.3V
VIN = 3.8V
VIN = 5.0V
10m
100m
1m
10m
100m
1
10m
100m
1m
10m
100m
1
Load Current [A]
Auto Power Save Mode
Load Current [A]
Auto Power Save Mode
VOUT = 1.1 V
VOUT = 0.7 V
图9-18. Efficiency
图9-19. Efficiency
9.4 Power Supply Recommendations
The power supply must provide a current rating according to the supply voltage, output voltage, and output
current of the TPS6286x.
9.5 Layout
9.5.1 Layout Guidelines
The pinout of the TPS6286x converter has been optimized to enable a single top layer PCB routing of the
converter and its critical passive components such as CIN, COUT, and L. This pinout allows the connection of
tiny components such as 0201 (0603) size capacitors and 0402 (1005) size inductor. A solution size smaller than
5 mm2 can be achieved with a fixed output voltage.
• As for all switching power supplies, the layout is an important step in the design. A specified performance
requires the correct on board layout.
• It is critical to provide a low inductance, low impedance ground path. Therefore, use wide and short traces for
the main current paths.
• The input capacitor must be placed as close as possible to the VIN and GND pins of the converter. This is the
most critical component placement.
• The VOS line is a sensitive, high impedance line and must be connected to the output capacitor and routed
away from noisy components and traces (for example, SW line) or other noise sources.
9.5.2 Layout Example
VOUT
GND
VIN
图9-20. PCB Layout Example
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
I2C™ is a trademark of NXP Semiconductors.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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2-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS628600YCHR
TPS628601YCHR
TPS628603YCHR
TPS628610YCHR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
DSBGA
YCH
YCH
YCH
YCH
8
8
8
8
12000 RoHS & Green
12000 RoHS & Green
12000 RoHS & Green
12000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
S
T
Samples
Samples
Samples
Samples
SNAGCU
SNAGCU
SNAGCU
Q
U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS628600YCHR
TPS628601YCHR
TPS628603YCHR
TPS628610YCHR
DSBGA
DSBGA
DSBGA
DSBGA
YCH
YCH
YCH
YCH
8
8
8
8
12000
12000
12000
12000
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
0.8
0.8
1.5
1.5
0.47
0.47
0.43
0.47
2.0
2.0
2.0
2.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
0.84
0.8
1.62
1.5
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS628600YCHR
TPS628601YCHR
TPS628603YCHR
TPS628610YCHR
DSBGA
DSBGA
DSBGA
DSBGA
YCH
YCH
YCH
YCH
8
8
8
8
12000
12000
12000
12000
182.0
182.0
182.0
182.0
182.0
182.0
182.0
182.0
20.0
20.0
20.0
20.0
Pack Materials-Page 2
重要声明和免责声明
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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