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TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

TPS6281x-Q1 2.75-V to 6-V Adjustable-Frequency Step-Down Converter

1 Features

3 Description

The TPS6281x-Q1 is family of pin-to-pin 1-A, 2-A, 3-

1

•

AEC-Q100 qualified for automotive applications

A

and 4-A synchronous step-down DC/DC

–

Device temperature grade 1:

–40°C to +125°C T_A

converters. All devices offer high efficiency and ease

of use. The TPS6281x-Q1 family is based on a peak

current mode control topology. TPS6281x-Q1 is

designed for automotive applications such as

Infotainment and advanced driver assistance

systems. Low resistive switches allow up to 4-A

continuous output current at high ambient

temperature. The switching frequency is externally

adjustable from 1.8 MHz to 4 MHz and can also be

synchronized to an external clock in the same

frequency range. In PWM/PFM mode, the TPS6281x-

Q1 automatically enter Power Save Mode at light

loads to maintain high efficiency across the whole

load range. The TPS6281x-Q1 provide 1% output

voltage accuracy in PWM mode which helps design a

power supply with high output voltage accuracy. The

SS/TR pin allows setting the start-up time or forming

tracking of the output voltage to an external source.

This allows external sequencing of different supply

rails and limiting the inrush current during start-up.

•

Functional safety capable

–

Documentation available to aid functional

safety system design

•

Input voltage range: 2.75 V to 6 V

Family of 1 A, 2 A, 3 A and 4 A

Quiescent current 15-µA typical

Output voltage from 0.6 V to 5.5 V

Output voltage accuracy ±1% (PWM operation)

Adjustable soft-start

Forced PWM or PWM and PFM operation

Adjustable switching frequency of

1.8 MHz to 4 MHz

•

Precise ENABLE input allows

–

User-defined undervoltage lockout

Exact sequencing

The TPS6281x-Q1 is available in a 3-mm x 2-mm

VQFN package with wettable flanks.

•

100% duty cycle mode

Active output discharge

Device Information⁽¹⁾

Spread spectrum clocking - optional

Power good output with window comparator

Package with wettable flanks

PART NUMBER

TPS62810-Q1

TPS62811-Q1

TPS62812-Q1

TPS62813-Q1

PACKAGE

BODY SIZE (NOM)

3 mm x 2 mm

VQFN

2 Applications

VQFN

•

Infotainment head unit

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Hybrid and reconfigurable cluster

Telematics control unit

Surround view ECU, ADAS sensor fusion

External amplifier

Simplified Schematic

Efficiency vs Output Current; V_OUT= 3.3 V;

PWM/PFM; f_S= 2.25 MHz

L

0.47mH

V_IN

2.75V - 6V

TPS62810-Q1

V_OUT

VIN

SW

FB

100

95

90

85

80

75

70

65

C_IN

22mF

R₁

C_FF

EN

C_OUT

47mF

MODE/SYNC

R₂

R₃

COMP/FSET

SS/TR

C_SS

PG

GND

60

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

55

50

100m

1m

10m 100m

Output Current (A)

1

4

D002

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

www.ti.com

Table of Contents

9.4 Device Functional Modes........................................ 15

10 Application and Implementation........................ 18

10.1 Application Information.......................................... 18

10.2 Typical Application ............................................... 20

10.3 System Examples ................................................. 31

11 Power Supply Recommendations ..................... 34

12 Layout................................................................... 34

12.1 Layout Guidelines ................................................. 34

12.2 Layout Example .................................................... 34

13 Device and Documentation Support ................. 35

13.1 Device Support...................................................... 35

13.2 Documentation Support ........................................ 35

13.3 Related Links ........................................................ 35

13.4 Receiving Notification of Documentation Updates 35

13.5 Support Resources ............................................... 35

13.6 Trademarks........................................................... 35

13.7 Electrostatic Discharge Caution............................ 35

13.8 Glossary................................................................ 35

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 5

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings ............................................................ 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information ................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 10

8.1 Schematic ............................................................... 10

Detailed Description ............................................ 12

9.1 Overview ................................................................. 12

9.2 Functional Block Diagram ....................................... 12

9.3 Feature Description................................................. 13

8

9

14 Mechanical, Packaging, and Orderable

Information ........................................................... 36

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (December 2019) to Revision E

Page

•

Added TPS628122GQWRWYRQ1 into Device Comparison Table ...................................................................................... 4

Added feedback voltage for fixed voltage version TPS628122G........................................................................................... 8

Changes from Revision C (August 2019) to Revision D

Page

•

Added Functional safety capable information and link .......................................................................................................... 1

Added new voltage spins to Device Comparison Table ........................................................................................................ 4

Changed duty cycle for external synchronization to allow a wider range .............................................................................. 7

Added feedback voltage for fixed voltage versions TPS6281206, TPS628110A, TPS628112A, TPS6281008,

TPS628112M, TPS628120M ................................................................................................................................................. 8

•

Changed description for Power Save Mode Operation........................................................................................................ 16

Changes from Revision B (June 2019) to Revision C

Page

•

Changed marketing status from Advance Information to initial release for the TPS62811-Q1 and TPS62812-Q1. ............. 1

Changed Test Condition for Tracking Gain............................................................................................................................ 7

Changed Test Condition for Tracking Offset.......................................................................................................................... 7

Added feedback voltage for fixed voltage version TPS6281208QWRWYRQ1...................................................................... 8

Added FB input current for fixed voltage versions ................................................................................................................. 8

Added feedback voltage accuracy for fixed voltage versions................................................................................................. 8

Deleted Preview label for Systems Example ....................................................................................................................... 31

2

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Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

www.ti.com

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

Changes from Revision A (March 2019) to Revision B

Page

•

Changed marketing status from Advance Information to initial release for the TPS62810-Q1 and TPS62813-Q1. ............. 1

Changed parameter name from R_FSETto R_CF...................................................................................................................... 6

Changed minimum value for UVLO threshold for falling input voltage ................................................................................ 7

Deleted high-side MOSFET leakage current at T_J= 85°C..................................................................................................... 7

Deleted low-side MOSFET leakage current at T_J= 85°C ...................................................................................................... 8

Changed max value for high-side MOSFET current limit of TPS62810 and TPS62813........................................................ 8

Changed min / max value for high-side MOSFET current limit of TPS62812 and TPS62811............................................... 8

Changed min / max value for switching frequency tolerance for f_S= 1.8 MHz to 4 MHz....................................................... 8

Changed min / max value for feedback voltage accuracy with voltage tracking.................................................................... 8

Changes from Original (August 2018) to Revision A

Page

•

Added planned device spins to Device Comparison Table ................................................................................................... 4

Changed max inductance in Recommended Operating Conditions for the frequency range up to 3.5 MHz ....................... 6

Changed max inductance in Recommended Operating Conditions for the frequency range above 3.5 MHz....................... 6

Deleted min/max value for Thermal Shutdown Temperature ................................................................................................ 7

Changed max value for high-side MOSFET leakage current................................................................................................. 7

Changed max value for low-side MOSFET leakage current .................................................................................................. 8

Added spec for SW leakage................................................................................................................................................... 8

Changed load regulation from 0.025%/V to 0.05%/V............................................................................................................ 8

Changed equation for compensation setting 2 .................................................................................................................... 13

Changed R_CFrange for comp setting 2 in Table 3 ............................................................................................................... 14

Changed R_CFrange for comp setting 2 in Table 4 ............................................................................................................... 14

Changed C_FFfrom 22 pF to 10 pF in Table 7 and all schematics ....................................................................................... 20

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3

Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

www.ti.com

5 Device Comparison Table

DEVICE NUMBER

OUTPUT

CURRENT

Vout

DISCHARGE

FOLD-BACK

CURRENT LIMIT

SPREAD SPECTRUM

CLOCKING (SSC)

OUTPUT VOLTAGE

TPS62811QWRWYRQ1

TPS6281120QWRWYRQ1

TPS628110AQWRWYRQ1

TPS628112AQWRWYRQ1

TPS628112MQWRWYRQ1

TPS62812QWRWYRQ1

TPS6281220QWRWYRQ1

TPS6281206QWRWYRQ1

TPS6281208QWRWYRQ1

TPS628122GQWRWYRQ1

TPS628120MQWRWYRQ1

TPS62813QWRWYRQ1

TPS6281320QWRWYRQ1

TPS62810QWRWYRQ1

TPS6281020QWRWYRQ1

TPS6281008QWRWYRQ1

1 A

2 A

3 A

4 A

ON

OFF

ON

adjustable

fixed 1.2 V

fixed 1.8 V

adjustable

fixed 1.0 V

fixed 1.1 V

fixed 1.5 V

fixed 1.8 V

adjustable

fixed 1.1 V

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

4

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Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

www.ti.com

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

6 Pin Configuration and Functions

RWY Package

9 Pin (VQFN)

Top View

bottom view

top view

8

7

8

COMP/

FSET

COMP/

FSET

EN

9

6

9

PG

SS/TR

PG

GND

SW

VIN

GND

SW

VIN

FB

MODE/SYNC

FB

MODE/SYNC

5

3

4

2

3

2

4

1

Pin Functions

I/O

DESCRIPTION

NAME

NO.

This is the enable pin of the device. Connect to logic low to disable the device. Pull high to

enable the device. Do not leave this pin unconnected.

EN

8

I

Voltage feedback input, connect the resistive output voltage divider to this pin. For the fixed

voltage versions, connect the FB pin directly to the output voltage.

FB

5

4

GND

Ground pin

The device runs in PFM/PWM mode when this pin is pulled low. If the pin is pulled high, the

device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can also

be used to synchronize the device to an external frequency. See the Specifications for the

detailed specification of the digital signal applied to this pin for external synchronization.

MODE/SYNC

COMP/FSET

1

7

I

Device compensation and frequency set input. A resistor from this pin to GND defines the

compensation of the control loop as well as the switching frequency if not externally

synchronized. If the pin is tied to GND or VIN, the switching frequency is set to 2.25 MHz. Do

not leave this pin unconnected.

Open drain power good output. Low impedance when not "power good", high impedance

when "power good". This pin can be left open or be tied to GND when not used.

PG

9

6

O

I

Soft-Start / Tracking pin. A capacitor connected from this pin to GND defines the rise time for

the internal reference voltage. The pin can also be used as an input for tracking and

sequencing - see the Soft Start / Tracking (SS/TR) section.

SS/TR

SW

VIN

3

2

This is the switch pin of the converter and is connected to the internal Power MOSFETs.

Power supply input. Connect the input capacitor as close as possible between pin VIN and

GND.

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5

Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.3

-3

MAX

6.5

UNIT

V

VIN

SW

V_IN+0.3

10

V

Pin voltage range⁽¹⁾

SW (transient for less than 10 ns)⁽²⁾

V

FB

-0.3

-65

4

V

PG, SS/TR, COMP/FSET

EN, MODE/SYNC

V_IN+0.3

6.5

V

Pin voltage range⁽¹⁾

V

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) While switching

7.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

MIN

2.75

0.6

0.32

0.25

15

NOM

MAX

6

UNIT

V_IN

V_OUT

L

Supply voltage range

V

Output voltage range

5.5

0.9

470

V

Effective inductance for a switching frequency of 1.8 MHz to 3.5 MHz

Effective inductance for a switching frequency of 3.5 MHz to 4 MHz

Effective output capacitance for 1A and 2A version⁽¹⁾

0.47

0.33

22

µH

µF

kΩ

°C

L

C_OUT

C_IN

R_CF

T_J

(1)

Effective output capacitance for 3A and 4A version

27

47

Effective input capacitance⁽¹⁾

5

10

4.5

-40

100

Operating junction temperature

+150

(1) The values given for the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias effect of

ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the

manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see the

feature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.

7.4 Thermal Information

TPS6281x-Q1

THERMAL METRIC⁽¹⁾

RWY

9 PINS

71.1

37.2

16.4

0.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

16.1

n/a

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6

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Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

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SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

7.5 Electrical Characteristics

over operating junction temperature (T_J= -40 °C to +150 °C) and V_IN= 2.75 V to 6 V. Typical values at V_IN= 5 V and T_J= 25

°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

EN = high, I_OUT= 0 mA, Device not switching,

T_J= 125 °C

I_Q

Operating Quiescent Current

21

µA

I_Q

Operating Quiescent Current EN = high, I_OUT= 0 mA, Device not switching

15

30

18

µA

I_SD

Shutdown Current

EN = 0 V, at T_J= 125 °C

EN = 0 V, Nominal value at T_J= 25 °C,

Max value at T_J= 150 °C

I_SD

Shutdown Current

1.5

26

µA

Rising Input Voltage

Falling Input Voltage

2.5

2.6

2.5

2.75

2.6

V

Undervoltage Lockout

Threshold

V_UVLO

2.25

Thermal Shutdown

Temperature

Rising Junction Temperature

170

15

T_SD

°C

Thermal Shutdown Hysteresis

CONTROL (EN, SS/TR, PG, MODE/SYNC)

High Level Input Voltage for

MODE/SYNC Pin

V_IH

1.1

V

Low Level Input Voltage for

MODE/SYNC Pin

V_IL

0.3

4

Frequency Range on

MODE/SYNC Pin for

Synchronization

requires a resistor from COMP/FSET to GND, see

application section

f_SYNC

1.8

MHz

Duty Cycle of

Synchronization Signal at

MODE/SYNC Pin

20%

50%

80%

Time to Lock to External

Frequency

50

1.1

1.0

µs

V

Input Threshold Voltage for

EN pin; Rising Edge

V_IH

V_IL

1.06

0.96

1.15

1.05

150

2.5

Input Threshold Voltage for

EN pin; Falling Edge

V

Input Leakage Current for

EN, MODE/SYNC

I_LKG

V_IH= V_INor V_IL= GND

nA

kΩ

V

Resistance from COMP/FSET

to GND for Logic Low

internal frequency setting with f = 2.25 MHz

0

voltage on COMP/FSET for

logic high

VIN

95%

UVP Power Good Threshold

Voltage; dc Level

Rising (%V_FB

)

92%

87%

98%

93%

UVP Power Good Threshold

Voltage; dc Level

Falling (%V_FB

)

90%

V_{TH_PG}

OVP Power Good Threshold;

dc Level

Rising (%V_FB

)

107%

104%

110%

113%

111%

OVP Power Good Threshold;

dc Level

Falling (%V_FB

)

107%

40

Power Good De-glitch Time

for a high level to low level transition on power good

µs

V

Power Good Output Low

Voltage

V_{OL_PG}

I_PG= 2 mA

V_PG= 5 V

0.07

0.3

I_{LKG_PG}

I_SS/TR

Input Leakage Current (PG)

SS/TR Pin Source Current

Tracking Gain

100

2.8

nA

µA

2.1

2.5

1

V_FB/ V_SS/TRfor nominal V_FB= 0.6 V

Tracking Offset

feedback voltage with V_SS/TR= 0 V for nominal V_FB= 0.6 V

17

mV

POWER SWITCH

High-Side MOSFET ON-

R_DS(ON)

V_IN≥ 5 V

37

15

60

35

30

mΩ

µA

Resistance

Low-Side MOSFET ON-

Resistance

R_DS(ON)

V_IN≥ 5 V

High-Side MOSFET leakage

current

V_IN= 6 V; V(SW) = 0 V

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Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

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Electrical Characteristics (continued)

over operating junction temperature (T_J= -40 °C to +150 °C) and V_IN= 2.75 V to 6 V. Typical values at V_IN= 5 V and T_J= 25

°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low-Side MOSFET leakage

current

V(SW) = 6 V

55

µA

SW leakage

V(SW) = 0.6 V; current into SW pin

-0.025

4.8

30

µA

High-Side MOSFET Current

Limit

I_LIMH

dc value, for TPS62810; V_IN= 3 V to 6 V

5.6

4.5

3.4

6.55

A

High-Side MOSFET Current

Limit

dc value, for TPS62813; V_IN= 3V to 6 V

dc value, for TPS62812; V_IN= 3V to 6 V

dc value, for TPS62811; V_IN= 3V to 6 V

3.9

2.8

2.0

5.25

4.2

A

High-Side MOSFET Current

Limit

High-Side MOSFET Current

Limit

I_LIMH

I_LIMNEG

f_S

2.6

-1.8

2.25

3.25

A

Negative Valley Current Limit dc value

PWM Switching Frequency

Range

1.8

2.025

-19%

4

MHz

PWM Switching Frequency

f_S

with COMP/FSET tied to VIN or GND

2.25

2.475

MHz

PWM Switching Frequency

Tolerance

using a resistor from COMP/FSET to GND, fs = 1.8 MHz to

4 MHz

18%

75

t_on,min

OUTPUT

V_FB

Minimum on-time of HS FET

Minimum on-time of LS FET

T_J= -40 °C to 125 °C, V_IN= 3.3 V

V_IN= 3.3 V

50

30

ns

Feedback Voltage

adjustable output voltage versions

0.6

1.0

V

fixed output voltage

TPS6281206

V_FB

fixed output voltage

TPS6281208, TPS6281008

V_FB

Feedback Voltage

1.1

1.2

1.5

1.8

1

V

fixed output voltage

TPS628110A, TPS628112A

V_FB

fixed output voltage

TPS628122G

V_FB

V

fixed output voltage

TPS628112M, TPS628120M

V_FB

V

FB Input Leakage Current for

Adjustable Voltage Versions

I_{LKG_FB}

V_FB= 0.6 V

70

nA

µA

FB Input Current for Fixed

Voltage Versions

V_FBvoltage at target output

voltage

1

Feedback Voltage Accuracy

for Adjustable Voltage

Versions

V_FB

V_IN≥ V_OUT+ 1 V

PWM mode

-1%

1%

Feedback Voltage Accuracy

for Fixed Voltage Versions

PWM mode, Tj = -40°C to

125°C

V_FB

V_IN≥ V_OUT+ 1 V

V_IN≥ V_OUT+ 1 V;

-1%

1%

Feedback Voltage Accuracy

for Fixed Voltage Versions

PWM mode

1.3%

PFM mode;

Co,eff ≥ 22 µF,

L = 0.47 µH

V_FB

Feedback Voltage Accuracy

-1%

2%

V_OUT≥ 1.5 V

PFM mode;

Co,eff ≥ 47 µF,

L = 0.47 µH

V_FB

1 V ≤ V_OUT< 1.5 V

-1%

2.5%

7%

V_IN≥ V_OUT+ 1 V;

V_SS/TR= 0.3 V

Feedback Voltage Accuracy

with Voltage Tracking

V_FB

PWM mode

Load Regulation

PWM mode operation

0.05

0.02

%/A

%/V

Ω

Line Regulation

PWM mode operation, I_OUT= 1 A, V_IN≥ V_OUT+ 1 V

Output Discharge Resistance

50

I_OUT= 0 mA, Time from EN=high to start switching; V_IN

applied already

t_delay

Start-up Delay Time

135

250

470

µs

8

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Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

www.ti.com

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

Electrical Characteristics (continued)

over operating junction temperature (T_J= -40 °C to +150 °C) and V_IN= 2.75 V to 6 V. Typical values at V_IN= 5 V and T_J= 25

°C. (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_OUT= 0 mA, Time from first switching pulse until 95% of

nominal output voltage; device not in current limit

t_ramp

Ramp time; SS/TR Pin Open

100

150

200

µs

7.6 Typical Characteristics

80

50

V_IN= 2.7V

V_IN= 3.3V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

V_IN= 2.7V

76

72

68

64

60

56

52

48

44

40

36

32

28

24

20

46

42

38

34

30

26

22

18

14

10

V_IN= 3.3V

V_IN= 4.0V

V_IN= 5.0V

V_IN= 6.0V

-40

25 85

Junction Temperature (°C)

125

150

-40

25 85

Junction Temperature (°C)

125

150

D002

Figure 1. R_ds(on)of High-side Switch

Figure 2. R_ds(on)of Low-side Switch

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8 Parameter Measurement Information

8.1 Schematic

L

0.47 mH

V_IN

2.75 V - 6 V

TPS62810-Q1

V_OUT

VIN

SW

C_IN

R₁

R₂

22 mF

C_FF

EN

FB

C_OUT

R₃2 x 22 mF

+ 10 mF

MODE/SYNC

COMP/FSET

SS/TR

C_SS

PG

GND

Figure 3. Measurement Setup for TPS62810-Q1 and TPS62813-Q1

Table 1. List of Components

(1)

REFERENCE

DESCRIPTION

MANUFACTURER

Texas Instruments

IC

L

TPS62810-Q1 or TPS62813-Q1

0.47 µH inductor; XEL4030-471MEB

22 µF / 10 V; GCM31CR71A226KE02L

Coilcraft

Murata

C_IN

2 x 22 µF / 10 V; GCM31CR71A226KE02L

+ 1 x 10 µF 6.3 V; GCM188D70J106ME36

C_OUT

Murata

C_SS

R_CF

C_FF

R₁

4.7 nF (equal to 1-ms start-up ramp)

Any

8,06 kΩ

10 pF

Depending on VOUT

100 kΩ

R₂

R₃

(1) See the Third-party Products Disclaimer.

L

0.47 mH

V_IN

2.75 V - 6 V

TPS62812-Q1

V_OUT

VIN

SW

C_IN

R₁

R₂

22 mF

C_FF

EN

FB

C_OUT

R₃1 x 22 mF

+ 10 mF

MODE/SYNC

COMP/FSET

SS/TR

C_SS

PG

GND

Figure 4. Measurement Setup for TPS62812-Q1 and TPS62811-Q1

10

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Table 2. List of Components

(1)

REFERENCE

DESCRIPTION

MANUFACTURER

IC

L

TPS62812-Q1 or TPS62811-Q1

Texas Instruments

Coilcraft

0.56 µH inductor; XEL4020-561MEB

22 µF / 10 V; GCM31CR71A226KE02L

C_IN

Murata

1 x 22 µF / 10 V; GCM31CR71A226KE02L

+ 1 x 10 µF 6.3 V; GCM188D70J106ME36

C_OUT

Murata

C_SS

R_CF

C_FF

R₁

4.7 nF (equal to 1-ms start-up ramp)

Any

8,06 kΩ

10 pF

Depending on VOUT

100 kΩ

R₂

R₃

(1) See the Third-party Products Disclaimer.

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9 Detailed Description

9.1 Overview

The TPS6281x-Q1 synchronous switch mode DC/DC converters are based on a peak current mode control

topology. The control loop is internally compensated. To optimize the bandwidth of the control loop to the wide

range of output capacitance that can be used with TPS6281x-Q1, one of three internal compensation settings

can be selected. See the COMP/FSET section. The compensation setting is selected either by a resistor from

COMP/FSET to GND, or by the logic state of this pin. The regulation network achieves fast and stable operation

with small external components and low ESR ceramic output capacitors. The device can be operated without a

feedforward capacitor on the output voltage divider, however, using a typically 10-pF feedforward capacitor

improves transient response.

The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The

frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN, or in a range

of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be

synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no

need for additional passive components. External synchronization is only possible if a resistor from COMP/FSET

to GND is used. If COMP/FSET is directly tied to GND or VIN, the TPS6281x-Q1 cannot be synchronized

externally. An internal PLL allows to change from internal clock to external clock during operation. The

synchronization to the external clock is done on a falling edge of the clock applied at MODE to the rising edge on

the SW pin. This allows a roughly 180° phase shift when the SW pin is used to generate the synchronization

signal for a second converter. When the MODE pin is set to a logic low level, the device operates in power save

mode (PFM) at low output current and automatically transfers to fixed frequency PWM mode at higher output

current. In PFM mode, the switching frequency decreases linearly based on the load to sustain high efficiency

down to very low output current.

9.2 Functional Block Diagram

VIN

SW

Bias

Regulator

Gate Drive and Control

Oscillator

Ipeak

Izero

EN

MODE

gm

GND

FB

_

+

PG

Device

Control

+

-

Bandgap

SS/TR

Thermal

Shutdown

COMP/FSET

12

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9.3 Feature Description

9.3.1 Precise Enable

The voltage applied at the Enable pin of the TPS6281x-Q1 is compared to a fixed threshold of 1.1 V for a rising

voltage. This allows to drive the pin by a slowly changing voltage and enables the use of an external RC network

to achieve a power-up delay.

The Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the

input of the Enable pin.

The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The

TPS6281x-Q1 starts operation when the rising threshold is exceeded. For proper operation, the EN pin must be

terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown

current of typically 1 μA. In this mode, the internal high-side and low-side MOSFETs are turned off and the entire

internal control circuitry is switched off.

9.3.2 COMP/FSET

This pin allows to set two different parameters independently:

•

Internal compensation settings for the control loop

The switching frequency in PWM mode from 1.8 MHz to 4 MHz

A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change

in compensation allows you to adapt the device to different values of output capacitance. The resistor must be

placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting is

sampled at start-up of the converter, so a change in the resistor during operation only has an effect on the

switching frequency but not on the compensation.

To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined switching

frequency / compensation. Do not leave the pin floating.

The switching frequency has to be selected based on the input voltage and the output voltage to meet the

specifications for the minimum on-time and minimum off-time.

For example: V_IN= 5 V, V_OUT= 1 V --> duty cycle (DC) = 1 V / 5 V = 0.2

•

with t_on= DC × T --> t_on,min= 1 / f_s,max× DC

--> f_s,max= 1 / t_on,min× DC = 1 / 0.075 µs · 0.2 = 2.67 MHz

The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be

increased from the minimum value as given in Table 3 and Table 4, up to the maximum of 470 µF in all of the

three compensation ranges. If the capacitance of an output changes during operation, for example, when load

switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for the

minimum capacitance on the output. With large output capacitance, the compensation must be done based on

that large capacitance to get the best load transient response. Compensating for large output capacitance but

placing less capacitance on the output can lead to instability.

The switching frequency for the different compensation setting is determined by the following equations.

For compensation (comp) setting 1:

Space

18MHz ×kW

RCF(kW) =

fS(MHz)

(1)

For compensation (comp) setting 2:

Space

60MHz ×kW

RCF(kW) =

fS(MHz)

(2)

13

Space

For compensation (comp) setting 3:

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Feature Description (continued)

Space

180MHz ×kW

RCF(kW) =

fS(MHz)

(3)

Table 3. Switching Frequency and Compensation for TPS62810-Q1 (4 A) and TPS62813-Q1 (3 A)

MINIMUM OUTPUT

CAPACITANCE

MINIMUM OUTPUT

CAPACITANCE

MINIMUM OUTPUT

CAPACITANCE

COMPENSATION

R_CF

SWITCHING FREQUENCY

FOR VOUT < 1 V

FOR 1 V ≤ VOUT < 3.3 V

FOR VOUT ≥ 3.3 V

for smallest output

capacitance

(comp setting 1)

1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)

10 kΩ ... 4.5 kΩ

33 kΩ ... 15 kΩ

100 kΩ ... 45 kΩ

tied to GND

53 µF

100 µF

200 µF

53 µF

32 µF

60 µF

27 µF

50 µF

according to Equation 1

for medium output

capacitance

(comp setting 2)

1.8 MHz (33 kΩ) ... 4 MHz (15 kΩ)

according to Equation 2

for large output

capacitance

(comp setting 3)

1.8 MHz (100 kΩ) ... 4 MHz (45 kΩ)

120 µF

32 µF

100 µF

27 µF

according to Equation 3

for smallest output

capacitance

(comp setting 1)

internally fixed 2.25 MHz

for large output

capacitance

tied to V_IN

200 µF

120 µF

100 µF

(comp setting 3)

Table 4. Switching Frequency and Compensation for TPS62812-Q1 (2 A) and TPS62811-Q1 (1 A)

MINIMUM OUTPUT

CAPACITANCE

MINIMUM OUTPUT

CAPACITANCE

MINIMUM OUTPUT

CAPACITANCE

COMPENSATION

R_CF

SWITCHING FREQUENCY

FOR VOUT < 1 V

FOR 1 V ≤ VOUT < 3.3 V

FOR VOUT ≥ 3.3 V

for smallest output

capacitance

(comp setting 1)

1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)

10 kΩ ... 4.5 kΩ

33 kΩ ... 15 kΩ

100 kΩ ... 45 kΩ

tied to GND

30 µF

60 µF

18 µF

36 µF

80 µF

18 µF

80 µF

15 µF

30 µF

68 µF

15 µF

68 µF

according to Equation 1

for medium output

capacitance

(comp setting 2)

1.8 MHz (33 kΩ) ... 4 MHz (15 kΩ)

according to Equation 2

for large output

capacitance

(comp setting 3)

1.8MHz (100 kΩ) ...4 MHz (45 kΩ)

130 µF

30 µF

according to Equation 3

for smallest output

capacitance

(comp setting 1)

internally fixed 2.25 MHz

for large output

capacitance

tied to V_IN

130 µF

(comp setting 3)

Refer to the Output Capacitor section for further details on the output capacitance required depending on the

output voltage.

A too high resistor value for R_CFis decoded as "tied to V_IN", a value below the lowest range is decoded as "tied

to GND". The minimum output capacitance in Table 3 and Table 4 is for capacitors close to the output of the

device. If the capacitance is distributed, a lower compensation setting can be required. All values are effective

capacitance, including all tolerances, aging, dc bias effect, and so forth.

14

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9.3.3 MODE / SYNC

When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current. The

MODE/SYNC pin allows to force PWM mode when set high. The pin also allows you to apply an external clock in

a frequency range from 1.8 MHz to 4 MHz for external synchronization. Similar to COMP/FSET, the

specifications for the minimum on-time and minimum off-time have to be taken into account when setting the

external frequency. For use with external synchronization on the MODE/SYNC pin, the internal switching

frequency must be set by R_CFto a similar value than the externally applied clock. This ensures a fast settling to

the external clock and, if the external clock fails, the switching frequency stays in the same range and the

compensation settings are still valid. When there is no resistor from COMP/FSET to GND but the pin is pulled

high or low, external synchronization is not possible.

9.3.4 Spread Spectrum Clocking (SSC)

For device versions with SSC enabled, the switching frequency is randomly changed in PWM mode when the

internal clock is used. The frequency variation is typically between the nominal switching frequency and up to

288 kHz above the nominal switching frequency. When the device is externally synchronized by applying a clock

signal to the MODE/SYNC pin, the TPS6281x-Q1 follows the external clock and the internal spread spectrum

block is turned off. SSC is also disabled during soft start.

9.3.5 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the

power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the

input voltage trips below the threshold for a falling supply voltage.

9.3.6 Power Good Output (PG)

Power good is an open-drain output driven by a window comparator. PG is held low when the device is disabled,

in undervoltage lockout, and in thermal shutdown. When the output voltage is in regulation hence, within the

window defined in the electrical characteristics, the output is high impedance.

Table 5. PG Status

EN

X

DEVICE STATUS

V_IN< 2 V

PG STATE

undefined

low

V_IN≥ 2 V

2 V ≤ V_IN≤ UVLO OR in thermal shutdown OR V_OUTnot in

high

low

regulation

V_OUTin regulation

high impedance

9.3.7 Thermal Shutdown

The junction temperature (T_J) of the device is monitored by an internal temperature sensor. If T_Jexceeds 170°C

(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG

goes low. When T_Jdecreases by the hysteresis amount of typically 15°C, the converter resumes normal

operation, beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause,

the device needs up to 9 µs to detect a too high junction temperature. If the PFM burst is shorter than this delay,

the device does not detect a too high junction temperature.

9.4 Device Functional Modes

9.4.1 Pulse Width Modulation (PWM) Operation

TPS6281x-Q1 has two operating modes: Forced PWM mode (discussed in this section) and PWM/PFM

(discussed in the Power Save Mode Operation (PWM/PFM) section).

With the MODE/SYNC pin set to high, the TPS6281x-Q1 operates with pulse width modulation in continuous

conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND or

by an external clock signal applied to the MODE/SYNC pin. With an external clock is applied to MODE/SYNC,

the TPS6281x-Q1 follows the frequency applied to the pin. To maintain regulation, the frequency needs to be in

a range the TPS6281x-Q1 can operate at, taking the minimum on-time into account.

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Device Functional Modes (continued)

9.4.2 Power Save Mode Operation (PWM/PFM)

When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as

the peak inductor current is above the PFM threshold of about 1.2 A. When the peak inductor current drops

below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching

frequency decreases with the load current maintaining high efficiency.

9.4.3 100% Duty-Cycle Operation

The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle

increases as the input voltage comes close to the output voltage and the off-time gets smaller. When the

minimum off-time of typically 30 ns is reached, the TPS6281x-Q1 skips switching cycles while it approaches

100% mode. In 100% mode, it keeps the high-side switch on continuously. The high-side switch stays turned on

as long as the output voltage is below the target. In 100% mode, the low-side switch is turned off. The maximum

dropout voltage in 100% mode is the product of the on-resistance of the high-side switch plus the series

resistance of the inductor and the load current.

9.4.4 Current Limit and Short Circuit Protection

The TPS6281x-Q1 is protected against overload and short circuit events. If the inductor current exceeds the

current limit I_LIMH, the high-side switch is turned off and the low-side switch is turned on to ramp down the

inductor current. The high-side switch turns on again only if the current in the low-side switch has decreased

below the low-side current limit. Due to internal propagation delay, the actual current can exceed the static

current limit. The dynamic current limit is given as:

V

L

Ipeak(typ) = ILIMH

+

×tPD

L

where

•

I_LIMHis the static current limit as specified in the electrical characteristics

L is the effective inductance at the peak current

V_Lis the voltage across the inductor (V_IN- V_OUT

)

t_PDis the internal propagation delay of typically 50 ns

(4)

The current limit can exceed static values, especially if the input voltage is high and very small inductances are

used. The dynamic high-side switch peak current can be calculated as follows:

V

IN -VOUT

Ipeak(typ) = ILIMH

+

×50ns

L

(5)

9.4.5 Foldback Current Limit and Short Circuit Protection

This is valid for devices where foldback current limit is enabled.

When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the current limit

from its nominal value to typically 1.8 A. Foldback current limit is left when the current limit indication goes away.

For the case that device operation continues in current limit, it would, after 3072 switching cycles, try again full

current limit for again 1024 switching cycles.

9.4.6 Output Discharge

The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is

being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge

feature is only active once TPS6281x-Q1 has been enabled at least once since the supply voltage was applied.

The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage

lockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V. Output

discharge is not activated during a current limit or foldback current limit event.

16

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Device Functional Modes (continued)

9.4.7 Soft Start / Tracking (SS/TR)

The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush

current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high

impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a

delay of about 200 μs then the internal reference and hence V_OUTrises with a slope controlled by an external

capacitor connected to the SS/TR pin.

Leaving the SS/TR pin un-connected provides the fastest startup ramp with 150 µs typically. A capacitor

connected from SS/TR to GND is charged with 2.5 µA by an internal current source during soft start until it

reaches the reference voltage of 0.6 V. The capacitance required to set a certain ramp-time (t_ramp) therefore is:

(6)

If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor pulls

the SS/TR pin to GND to ensure a proper low level. Returning from those states causes a new start-up

sequence.

A voltage applied at SS/TR can be used to track a master voltage. The output voltage follows this voltage in both

directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load

current. The SS/TR pin must not be connected to the SS/TR pin of other devices. An external voltage applied on

SS/TR is internally clamped to the feedback voltage (0.6 V). It is recommended to set the target for the external

voltage on SS/TR slightly above the feedback voltage. Given the tolerances of the resistor divider R₅and R₆on

SS/TR, this ensures the device "switches" to the internal reference voltage when the power-up sequencing is

finished. See Figure 62.

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

10.1.1 Programming the Output Voltage

The output voltage of the TPS6281x-Q1 is adjustable. It can be programmed for output voltages from 0.6 V to

5.5 V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of

the output voltage is set by the selection of the resistor divider from Equation 7. It is recommended to choose

resistor values which allow a current of at least 2 µA, meaning the value of R₂must not exceed 400 kΩ. Lower

resistor values are recommended for highest accuracy and most robust design.

V

OUT

æ

ö

R1

= R

-1

FB

^{2 ×}ç

è

÷

V

ø

(7)

10.1.2 External Component Selection

10.1.2.1 Inductor Selection

The TPS6281x-Q1 is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25 MHz.

Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact on

efficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple which

causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower

nominal switching frequency, the inductance must be changed accordingly. See the Recommended Operating

Conditions for details.

The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-

PFM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturation

current and DC resistance (DCR). Equation 8 calculates the maximum inductor current.

DI_L(max)

I_L(max)= I_OUT(max)

+

2

(8)

V

OUT

æ

ö

V

1-

^{OUT ×}ç

÷

IN

1

V

è

Lmin

ø

DIL(max)

=

×

f

SW

where

•

I_L(max)is the maximum inductor current

ΔI_L(max)is the peak-to-peak inductor ripple current

Lmin is the minimum inductance at the operating point

(9)

Table 6. Typical Inductors

NOMINAL

SWITCHING

FREQUENCY

INDUCTANCE

[µH]

CURRENT

[A]⁽¹⁾

DIMENSIONS

[LxBxH] mm

TYPE

FOR DEVICE

MANUFACTURER⁽²⁾

XFL4015-471ME

XEL4020-561ME

0.47 µH, ±20%

0.56 µH, ±20%

3.5

9.9

TPS62813-Q1 / 12-Q1

2.25 MHz

4 x 4 x 1.6

4 x 4 x 2.1

Coilcraft

TPS62810-Q1 / 13-Q1 /

12-Q1

(1) Lower of I_RMSat 20°C rise or I_SATat 20% drop.

(2) See the Third-party Products Disclaimer.

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Application Information (continued)

Table 6. Typical Inductors (continued)

NOMINAL

SWITCHING

FREQUENCY

INDUCTANCE

[µH]

CURRENT

[A]⁽¹⁾

DIMENSIONS

[LxBxH] mm

TYPE

FOR DEVICE

MANUFACTURER⁽²⁾

TPS62810-Q1 / 13-Q1 /

12-Q1

XEL4030-471ME

0.47 µH, ±20%

12.3

2.25 MHz

4 x 4 x 3.1

Coilcraft

XEL3515-561ME

XFL3012-331MEB

XPL2010-681ML

0.56 µH, ±20%

0.33 µH, ±20%

0.68 µH, ±20%

4.5

2.6

1.5

TPS62813-Q1 / 12-Q1

TPS62811-Q1 / 12-Q1

TPS62811-Q1

2.25 MHz

≥ 3.5 MHz

2.25 MHz

3.5 x 3.2 x 1.5

3 x 3 x 1.3

Coilcraft

2 x 1.9 x 1

TPS62813-Q1 / 12-Q1 /

11-Q1

DFE252012PD-R47M

0.47 µH, ±20%

see data sheet

2.25 MHz

2.5 x 2 x 1.2

Murata

Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation

current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also

useful to get lower ripple current, but increases the transient response time and size as well.

10.1.3 Capacitor Selection

10.1.3.1 Input Capacitor

For most applications, 22 µF nominal is sufficient and is recommended. The input capacitor buffers the input

voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic

capacitor (MLCC) is recommended for best filtering and must be placed between VIN and GND as close as

possible to those pins.

10.1.3.2 Output Capacitor

The architecture of the TPS6281x-Q1 allows the use of tiny ceramic output capacitors with low equivalent series

resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low

resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to

use dielectric X7R, X7T, or an equivalent. Using a higher value has advantages like smaller voltage ripple and a

tighter DC output accuracy in power save mode. By changing the device compensation with a resistor from

COMP/FSET to GND, the device can be compensated in three steps based on the minimum capacitance used

on the output. The maximum capacitance is 470 µF in any of the compensation settings.

The minimum capacitance required on the output depends on the compensation setting as well as on the current

rating of the device. TPS62810-Q1 and TPS62813-Q1 require a minimum output capacitance of 27 µF while the

lower current versions TPS62812-Q1 and TPS62811-Q1 require 15 µF at minimum. The required output

capacitance also changes with the output voltage.

For output voltages below 1 V, the minimum increases linearly from 32 µF at 1 V to 53 µF at 0.6 V for the

TPS62810-Q1, the TPS62813-Q1 with the compensation setting for smallest output capacitance. Other

compensation ranges, ranges for TPS62811-Q1 and TPS62812-Q1, or both are equivalent. See Table 3 and

Table 4 for details.

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10.2 Typical Application

L

0.47 mH

V_IN

2.75 V - 6 V

TPS62810-Q1

V_OUT

VIN

SW

C_IN

R₁

R₂

22 mF

C_FF

EN

FB

C_OUT

R₃2 x 22 mF

+ 10 mF

MODE/SYNC

COMP/FSET

SS/TR

C_SS

PG

GND

Figure 5. Typical Application

10.2.1 Design Requirements

The design guidelines provide a component selection to operate the device within the recommended operating

conditions.

10.2.2 Detailed Design Procedure

V

OUT

æ

ö

R1

= R

-1

FB

^{2 ×}ç

è

÷

V

ø

(10)

With V_FB= 0.6 V:

Table 7. Setting the Output Voltage

NOMINAL OUTPUT VOLTAGE

V_OUT

R₁

R₂

C_FF

EXACT OUTPUT VOLTAGE

0.8 V

1.0 V

1.1 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

16.9 kΩ

20 kΩ

51 kΩ

30 kΩ

47 kΩ

68 kΩ

51 kΩ

40.2 kΩ

15 kΩ

19.6 kΩ

10 pF

0.7988 V

1.0 V

39.2 kΩ

68 kΩ

1.101 V

1.2 V

76.8 kΩ

80.6 kΩ

47.5 kΩ

88.7 kΩ

1.5 V

1.803 V

2.5 V

3.315 V

20

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10.2.3 Application Curves

All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless

otherwise noted. The BOM is according to Table 1.

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 3.3 V

PFM

T_A= 25°C

V_OUT= 3.3 V

PWM

T_A= 25°C

Figure 6. Efficiency versus Output Current

Figure 7. Efficiency versus Output Current

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 1.8 V

PFM

T_A= 25°C

V_OUT= 1.8 V

PWM

T_A= 25°C

Figure 8. Efficiency versus Output Current

Figure 9. Efficiency versus Output Current

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 1.2 V

PFM

T_A= 25°C

V_OUT= 1.2 V

PWM

T_A= 25°C

Figure 10. Efficiency versus Output Current

Figure 11. Efficiency versus Output Current

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100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 1.0 V

PFM

T_A= 25°C

V_OUT= 1.0 V

PWM

T_A= 25°C

Figure 12. Efficiency versus Output Current

Figure 13. Efficiency versus Output Current

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

100m

1m

10m 100m

Output Current (A)

1

4

0

1

2

Output Current (A)

3

4

D002

V_OUT= 0.6 V

PFM

T_A= 25°C

V_OUT= 0.6 V

PWM

T_A= 25°C

Figure 14. Efficiency versus Output Current

Figure 15. Efficiency versus Output Current

3,32

3,315

3,31

3,32

3,316

3,312

3,308

3,304

3,3

3,305

3,3

3,295

3,29

3,296

3,292

3,288

3,284

3,28

3,285

3,28

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

3,275

3,27

3,276

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 3.3 V

PFM

T_A= 25°C

V_OUT= 3.3 V

PWM

T_A= 25°C

Figure 16. Output Voltage versus Output Current

Figure 17. Output Voltage versus Output Current

22

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1,82

1,816

1,812

1,808

1,804

1,8

1,82

1,816

1,812

1,808

1,804

1,8

1,796

1,792

1,788

1,784

1,78

1,796

1,792

1,788

1,784

1,78

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 1.8 V

PFM

T_A= 25°C

V_OUT= 1.8 V

PWM

T_A= 25°C

Figure 18. Output Voltage versus Output Current

Figure 19. Output Voltage versus Output Current

1,2125

1,21

1,2125

1,21

1,2075

1,205

1,2025

1,2

1,2075

1,205

1,2025

1,2

1,1975

1,195

1,1925

1,19

1,1975

1,195

1,1925

1,19

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

1,1875

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 1.2 V

PFM

T_A= 25°C

V_OUT= 1.2 V

PWM

T_A= 25°C

Figure 20. Output Voltage versus Output Current

Figure 21. Output Voltage versus Output Current

1,01

1,008

1,006

1,004

1,002

1

1,01

1,008

1,006

1,004

1,002

1

0,998

0,996

0,994

0,992

0,99

0,998

0,996

0,994

0,992

0,99

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 6.0 V

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 1.0 V

PFM

T_A= 25°C

V_OUT= 1.0 V

PWM

T_A= 25°C

Figure 22. Output Voltage versus Output Current

Figure 23. Output Voltage versus Output Current

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0,612

0,61

0,606

0,6045

0,603

0,6015

0,6

0,608

0,606

0,604

0,602

0,6

0,5985

0,597

0,5955

0,594

V_IN= 2.7 V

0,598

V_IN= 3.3 V

V_IN= 4.0 V

V_IN= 5.0 V

V_IN= 2.7 V

V_IN= 3.3 V

V_IN= 4.0 V

0,596

0,594

100m

1m

10m 100m

Output Current (A)

1

4

100m

1m

10m 100m

Output Current (A)

1

4

D002

V_OUT= 0.6 V

PWM

T_A= 25°C

V_OUT= 0.6 V

PFM

T_A= 25°C

Figure 25. Output Voltage versus Output Current

Figure 24. Output Voltage versus Output Current

V_OUT= 3.3 V

V_IN= 5.0 V

PWM

T_A= 25°C

V_OUT= 3.3 V

V_IN= 5.0 V

PFM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 27. Load Transient Response

Figure 26. Load Transient Response

V_OUT= 1.8 V

V_IN= 5.0 V

PFM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

V_OUT= 1.8 V

V_IN= 5.0 V

PWM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 28. Load Transient Response

Figure 29. Load Transient Response

24

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V_OUT= 1.2 V

PFM

T_A= 25°C

V_OUT= 1.2 V

V_IN= 5.0 V

PWM

T_A= 25°C

V_IN= 5.0 V

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 30. Load Transient Response

Figure 31. Load Transient Response

V_OUT= 1.0 V

V_IN= 5.0 V

PWM

T_A= 25°C

V_OUT= 1.0 V

V_IN= 5.0 V

PFM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 33. Load Transient Response

Figure 32. Load Transient Response

V_OUT= 0.6 V

V_IN= 3.3 V

PFM

T_A= 25°C

V_OUT= 0.6 V

V_IN= 3.3 V

PWM

T_A= 25°C

I_OUT= 0.4 A to 3.6 A to 0.4 A

Figure 34. Load Transient Response

Figure 35. Load Transient Response

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V_OUT= 3.3 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 3.3 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 37. Line Transient Response

Figure 36. Line Transient Response

V_OUT= 1.8 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 1.8 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 39. Line Transient Response

Figure 38. Line Transient Response

V_OUT= 1.2 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 1.2 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 41. Line Transient Response

Figure 40. Line Transient Response

26

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V_OUT= 1.0 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 1.0 V

PFM

T_A= 25°C

V_IN= 4.5 V to 5.5 V to 4.5 V

I_OUT= 0.5 A

V_IN= 4.5 V to 5.5 V to 4.5 V

Figure 43. Line Transient Response

Figure 42. Line Transient Response

V_OUT= 0.6 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 0.6 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_IN= 3.0 V to 3.6 V to 3.0 V

Figure 45. Line Transient Response

Figure 44. Line Transient Response

V_OUT= 3.3 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_OUT= 3.3 V

I_OUT= 4 A

PWM

T_A= 25°C

V_IN= 5.0 V

BW = 20 MHz

V_IN= 5.0 V

BW = 20 MHz

Figure 46. Output Voltage Ripple

Figure 47. Output Voltage Ripple

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V_OUT= 1.8 V

I_OUT= 0.5 A

PFM

T_A= 25°C

V_OUT= 1.8 V

I_OUT= 4 A

PWM

T_A= 25°C

BW = 20 MHz

V_IN= 5.0 V

BW = 20 MHz

V_IN= 5.0 V

Figure 48. Output Voltage Ripple

Figure 49. Output Voltage Ripple

V_OUT= 1.2 V

I_OUT= 4 A

PWM

T_A= 25°C

BW = 20 MHz

V_OUT= 1.2 V

I_OUT= 0.5 A

PFM

T_A= 25°C

BW = 20 MHz

V_IN= 5.0 V

Figure 51. Output Voltage Ripple

Figure 50. Output Voltage Ripple

V_OUT= 1.0 V

I_OUT= 0.5 A

PFM

T_A= 25°C

BW = 20 MHz

V_OUT= 1.0 V

I_OUT= 4 A

PWM

T_A= 25°C

BW = 20 MHz

V_IN= 5.0 V

Figure 52. Output Voltage Ripple

Figure 53. Output Voltage Ripple

28

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V_OUT= 0.6 V

PFM

T_A= 25°C

V_OUT= 0.6 V

I_OUT= 4 A

PWM

T_A= 25°C

I_OUT= 0.5 A

V_IN= 3.3 V

BW = 20 MHz

V_IN= 3.3 V

BW = 20 MHz

Figure 54. Output Voltage Ripple

Figure 55. Output Voltage Ripple

V_OUT= 1.8 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 3.3 V

I_OUT= 4 A

PWM

T_A= 25°C

V_IN= 5 V

C_SS= 4.7 nF

V_IN= 5 V

C_SS= 4.7 nF

Figure 57. Start-Up Timing

Figure 56. Start-Up Timing

V_OUT= 1.2 V

I_OUT= 4 A

PWM

T_A= 25°C

V_OUT= 1.0 V

I_OUT= 4 A

PWM

T_A= 25°C

V_IN= 5 V

C_SS= 4.7 nF

V_IN= 5 V

C_SS= 4.7 nF

Figure 58. Start-Up Timing

Figure 59. Start-Up Timing

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V_OUT= 0.6 V

I_OUT= 4 A

PWM

T_A= 25°C

V_IN= 3.3 V

C_SS= 4.7 nF

Figure 60. Start-up Timing

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10.3 System Examples

10.3.1 Fixed Output Voltage Versions

Versions with an internally fixed output voltage allow you to remove the external feedback voltage divider. This

not only allows you to reduce the total solution size but also provides higher accuracy as there is no additional

error caused by the external resistor divider. The FB pin needs to be tied to the output voltage directly as shown

in Figure 61. Independent of that, the application shown runs with an internally defined switching frequency of

2.25 MHz by connecting COMP/FSET to GND.

L

0.56 mH

V_IN

2.75 V - 6 V

TPS62812x-Q1

V_OUT

VIN

SW

C_IN

22 mF

EN

FB

C_OUT

MODE/SYNC

R₃

1 x 22 mF

+ 10 mF

COMP/FSET

SS/TR

C_SS

PG

GND

Figure 61. Schematic for Fixed Output Voltage Versions

10.3.2 Voltage Tracking

The TPS6281x-Q1 follows the voltage applied to the SS/TR pin. A voltage ramp on SS/TR to 0.6 V ramps the

output voltage according to the 0.6 V feedback voltage.

Tracking the 3.3 V of device 1, such that both rails reach their target voltage at the same time, requires a resistor

divider on SS/TR of device 2 equal to the output voltage divider of device 1. The output current of 2.5 µA on the

SS/TR pin causes an offset voltage on the resistor divider formed by R₅and R₆. The equivalent resistance of R₅

// R₆, so it must be kept below 15 kΩ. The current from SS/TR causes a slightly higher voltage across R6 than

0.6 V, which is desired because device 2 switches to its internal reference as soon as the voltage at SS/TR is

higher than 0.6 V.

In case both devices need to run in forced PWM mode, it is recommended to tie the MODE pin of device 2 to the

output voltage or the power good signal of device 1, the master device. The TPS6281x-Q1 has a duty cycle

limitation defined by the minimum on-time. For tracking down to low output voltages, device 2 cannot follow once

the minimum duty cycle is reached. Enabling PFM mode while tracking is in progress allows you to ramp down

the output voltage close to 0 V.

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System Examples (continued)

Device 1 (master)

TPS62810-Q1

L

0.47 mH

V_IN

2.75 V - 6 V

3.3 V

VIN

SW

10 pF

C_IN

MODE/SYNC

22 mF

FB

C_OUT

47 mF

EN

SS/TR

COMP/FSET

4.7 nF

PG

GND

Device 2 (slave)

TPS62810-Q1

L

0.47 mH

1.8 V

VIN

SW

10 pF

C_IN

22 mF

EN

FB

R₅

C_OUT

MODE/SYNC

SS/TR

47 mF

COMP/FSET

PG

R₆

GND

Figure 62. Schematic for Output Voltage Tracking

Figure 63. Scope Plot for Output Voltage Tracking

10.3.3 Synchronizing to an External Clock

The TPS6281x-Q1 can be externally synchronized by applying an external clock on the MODE/SYNC pin. There

is no need for any additional circuitry as long as the input signal meets the requirements given in the electrical

specifications. The clock can be applied / removed during operation, allowing you to switch from an externally-

defined fixed frequency to power-save mode or to internal fixed frequency operation. The value of the R_CF

resistor must be chosen so that the internally defined frequency and the externally applied frequency are close to

each other. This ensures a smooth transition from internal to external frequency and vice versa.

32

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TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

www.ti.com

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

System Examples (continued)

L

0.47 mH

V_IN

2.75 V - 6 V

TPS62810-Q1

V_OUT

VIN

SW

C_IN

R₁

R₂

22 mF

C_FF

EN

FB

C_OUT

MODE/SYNC

47 mF

R₃

COMP/FSET

SS/TR

f_EXT

C_SS

PG

GND

Figure 64. Schematic Using External Synchronization

V_IN= 5 V

R_CF= 8.06 kΩ

I_OUT= 0.1 A

V_IN= 5 V

R_CF= 8.06 kΩ

I_OUT= 1 A

V_OUT= 1.8 V

f_EXT= 2.5 MHz

V_OUT= 1.8 V

f_EXT= 2.5 MHz

Figure 65. Switching from External Syncronization to

Power-Save Mode (PFM)

Figure 66. Switching from External Synchronization to

Internal Fixed Frequency

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Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

www.ti.com

11 Power Supply Recommendations

The TPS6281x-Q1 device family has no special requirements for its input power supply. The output current of the

input power supply needs to be rated according to the supply voltage, output voltage, and output current of the

TPS6281x-Q1.

12 Layout

12.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more at high switching

frequencies. Therefore, the PCB layout of the TPS6281x-Q1 demands careful attention to ensure operation and

to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load),

stability and accuracy weaknesses increased EMI radiation and noise sensitivity.

See the Layout Example for the recommended layout of the TPS6281x-Q1, which is designed for common

external ground connections. The input capacitor must be placed as close as possible between the VIN and GND

pin.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load

current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for

wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC

pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops that conduct an

alternating current must outline an area as small as possible, as this area is proportional to the energy radiated.

Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example

SW). Since they carry information about the output voltage, they must be connected as close as possible to the

actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R₁

and R₂, must be kept close to the IC and connect directly to those pins and the system ground plane.

The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help spread the heat

into the pcb.

The recommended layout is implemented on the EVM and shown in the TPS62810EVM-015 Evaluation Module

User's Guide.

12.2 Layout Example

GND

VIN

VOUT

Figure 67. Example Layout

34

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TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

www.ti.com

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

13 Device and Documentation Support

13.1 Device Support

13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Documentation Support

13.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, TPS62810EVM-015 Evaluation Module, SLVUBG0

13.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 8. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

TPS62810-Q1

TPS62811-Q1

TPS62812-Q1

TPS62813-Q1

Click here

13.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

13.5 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.6 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.8 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

www.ti.com

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

36

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TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

www.ti.com

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

PACKAGE OUTLINE

RWY0009A

VQFN-HR - 1 mm max height

SCALE 5.000

PLASTIC QUAD FLATPACK - NO LEAD

2.1

1.9

A

B

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.05)

S

C

A

L

E

3

0

.

0

SECTION A-A

TYPICAL

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

1.1

0.55

0.675

0.575

(0.2) TYP

6

0.55

0.45

5

7

A

4

SYMM

3

2

0.2 0.05

(0.9)

0.3

9X

0.2

0.1

0.05

0.5 TYP

C A B

C

8

1

9

0.4

0.3

4X

SYMM

0.675

0.575

0.1

C A B

C

0.05

4224015/B 01/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

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TPS62810-Q1, TPS62811-Q1

TPS62812-Q1, TPS62813-Q1

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

www.ti.com

EXAMPLE BOARD LAYOUT

RWY0009A

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.65)

(0.55)

(0.35)

9

SEE SOLDER MASK DETAIL

(0.25)

(0.5)

1

8

3X (0.25)

2

(0.5)

SYMM

(2.65)

3

4

3X (2.3)

(R0.05) TYP

(0.775)

5

7

6

(0.775)

0.25

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

0.05 MAX

ALL AROUND

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAIL

4224015/B 01/2018

NOTES: (continued)

3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be ﬁlled, plugged or tented.

www.ti.com

38

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TPS62812-Q1, TPS62813-Q1

www.ti.com

SLVSDU1E –AUGUST 2018–REVISED APRIL 2020

EXAMPLE STENCIL DESIGN

RWY0009A

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.25)

(0.65)

(0.775)

(0.31)

9

EXPOSED METAL

TYP

(0.775)

1

(0.21)

8

2

(0.5)

6X (1.05)

(2.65)

SYMM

3

4

6X (0.25)

(R0.05) TYP

5

7

6

SYMM

(1.25)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

PADS 1, 5, 7 & 8:

90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE: 25X

4224015/B 01/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

Submit Documentation Feedback

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Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Apr-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS6281008QWRWYRQ VQFN-

HR

RWY

9

3000

180.0

12.4

2.25

3.25

1.15

4.0

12.0

Q1

1

TPS6281020QWRWYRQ VQFN-

HR

1

TPS62810QWRWYRQ1 VQFN-

HR

TPS628110AQWRWYRQ VQFN-

1

HR

TPS6281120QWRWYRQ VQFN-

HR

TPS628112AQWRWYRQ VQFN-

HR

TPS628112MQWRWYRQ VQFN-

HR

1

TPS62811QWRWYRQ1 VQFN-

HR

TPS6281206QWRWYRQ VQFN-

1

HR

TPS6281208QWRWYRQ VQFN-

HR

TPS628120MQWRWYRQ VQFN-

1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Apr-2020

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

1

HR

TPS6281220QWRWYRQ VQFN-

HR

RWY

9

3000

180.0

12.4

2.25

3.25

1.15

4.0

12.0

Q1

1

TPS628122GQWRWYRQ VQFN-

HR

1

TPS62812QWRWYRQ1 VQFN-

HR

TPS6281320QWRWYRQ VQFN-

1

HR

TPS62813QWRWYRQ1 VQFN-

HR

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS6281008QWRWYRQ1

TPS6281020QWRWYRQ1

TPS62810QWRWYRQ1

TPS628110AQWRWYRQ1

TPS6281120QWRWYRQ1

TPS628112AQWRWYRQ1

TPS628112MQWRWYRQ1

VQFN-HR

RWY

9

3000

195.0

200.0

45.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Apr-2020

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS62811QWRWYRQ1

TPS6281206QWRWYRQ1

TPS6281208QWRWYRQ1

TPS628120MQWRWYRQ1

TPS6281220QWRWYRQ1

TPS628122GQWRWYRQ1

TPS62812QWRWYRQ1

TPS6281320QWRWYRQ1

TPS62813QWRWYRQ1

VQFN-HR

RWY

9

3000

195.0

200.0

45.0

Pack Materials-Page 3

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS62810-Q1_V04
厂家：	TEXAS INSTRUMENTS
描述：	TPS6281x-Q1 2.75-V to 6-V Adjustable-Frequency Step-Down Converter
文件：	总46页 (文件大小：3313K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS62810-Q1_V04 [TI]

相关型号：

TPS62810-Q1_V05

TPS6281006QWRWYRQ1

TPS6281008QWRWYRQ1

TPS628100MQWRWYRQ1

TPS6281020QWRWYRQ1

TPS62810M

TPS62810MWRWYR

TPS62810QWRWYRQ1

TPS62811-Q1

TPS6281109QWRWYRQ1

TPS628110AQWRWYRQ1

TPS6281120QWRWYRQ1